1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tfa9879.h -- driver for NXP Semiconductors TFA9879 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Axentia Technologies AB 6*4882a593Smuzhiyun * Author: Peter Rosin <peda@axentia.se> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _TFA9879_H 10*4882a593Smuzhiyun #define _TFA9879_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define TFA9879_DEVICE_CONTROL 0x00 13*4882a593Smuzhiyun #define TFA9879_SERIAL_INTERFACE_1 0x01 14*4882a593Smuzhiyun #define TFA9879_PCM_IOM2_FORMAT_1 0x02 15*4882a593Smuzhiyun #define TFA9879_SERIAL_INTERFACE_2 0x03 16*4882a593Smuzhiyun #define TFA9879_PCM_IOM2_FORMAT_2 0x04 17*4882a593Smuzhiyun #define TFA9879_EQUALIZER_A1 0x05 18*4882a593Smuzhiyun #define TFA9879_EQUALIZER_A2 0x06 19*4882a593Smuzhiyun #define TFA9879_EQUALIZER_B1 0x07 20*4882a593Smuzhiyun #define TFA9879_EQUALIZER_B2 0x08 21*4882a593Smuzhiyun #define TFA9879_EQUALIZER_C1 0x09 22*4882a593Smuzhiyun #define TFA9879_EQUALIZER_C2 0x0a 23*4882a593Smuzhiyun #define TFA9879_EQUALIZER_D1 0x0b 24*4882a593Smuzhiyun #define TFA9879_EQUALIZER_D2 0x0c 25*4882a593Smuzhiyun #define TFA9879_EQUALIZER_E1 0x0d 26*4882a593Smuzhiyun #define TFA9879_EQUALIZER_E2 0x0e 27*4882a593Smuzhiyun #define TFA9879_BYPASS_CONTROL 0x0f 28*4882a593Smuzhiyun #define TFA9879_DYNAMIC_RANGE_COMPR 0x10 29*4882a593Smuzhiyun #define TFA9879_BASS_TREBLE 0x11 30*4882a593Smuzhiyun #define TFA9879_HIGH_PASS_FILTER 0x12 31*4882a593Smuzhiyun #define TFA9879_VOLUME_CONTROL 0x13 32*4882a593Smuzhiyun #define TFA9879_MISC_CONTROL 0x14 33*4882a593Smuzhiyun #define TFA9879_MISC_STATUS 0x15 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* TFA9879_DEVICE_CONTROL */ 36*4882a593Smuzhiyun #define TFA9879_INPUT_SEL_MASK 0x0010 37*4882a593Smuzhiyun #define TFA9879_INPUT_SEL_SHIFT 4 38*4882a593Smuzhiyun #define TFA9879_OPMODE_MASK 0x0008 39*4882a593Smuzhiyun #define TFA9879_OPMODE_SHIFT 3 40*4882a593Smuzhiyun #define TFA9879_RESET_MASK 0x0002 41*4882a593Smuzhiyun #define TFA9879_RESET_SHIFT 1 42*4882a593Smuzhiyun #define TFA9879_POWERUP_MASK 0x0001 43*4882a593Smuzhiyun #define TFA9879_POWERUP_SHIFT 0 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* TFA9879_SERIAL_INTERFACE */ 46*4882a593Smuzhiyun #define TFA9879_MONO_SEL_MASK 0x0c00 47*4882a593Smuzhiyun #define TFA9879_MONO_SEL_SHIFT 10 48*4882a593Smuzhiyun #define TFA9879_MONO_SEL_LEFT 0 49*4882a593Smuzhiyun #define TFA9879_MONO_SEL_RIGHT 1 50*4882a593Smuzhiyun #define TFA9879_MONO_SEL_BOTH 2 51*4882a593Smuzhiyun #define TFA9879_I2S_FS_MASK 0x03c0 52*4882a593Smuzhiyun #define TFA9879_I2S_FS_SHIFT 6 53*4882a593Smuzhiyun #define TFA9879_I2S_FS_8000 0 54*4882a593Smuzhiyun #define TFA9879_I2S_FS_11025 1 55*4882a593Smuzhiyun #define TFA9879_I2S_FS_12000 2 56*4882a593Smuzhiyun #define TFA9879_I2S_FS_16000 3 57*4882a593Smuzhiyun #define TFA9879_I2S_FS_22050 4 58*4882a593Smuzhiyun #define TFA9879_I2S_FS_24000 5 59*4882a593Smuzhiyun #define TFA9879_I2S_FS_32000 6 60*4882a593Smuzhiyun #define TFA9879_I2S_FS_44100 7 61*4882a593Smuzhiyun #define TFA9879_I2S_FS_48000 8 62*4882a593Smuzhiyun #define TFA9879_I2S_FS_64000 9 63*4882a593Smuzhiyun #define TFA9879_I2S_FS_88200 10 64*4882a593Smuzhiyun #define TFA9879_I2S_FS_96000 11 65*4882a593Smuzhiyun #define TFA9879_I2S_SET_MASK 0x0038 66*4882a593Smuzhiyun #define TFA9879_I2S_SET_SHIFT 3 67*4882a593Smuzhiyun #define TFA9879_I2S_SET_MSB_J_24 2 68*4882a593Smuzhiyun #define TFA9879_I2S_SET_I2S_24 3 69*4882a593Smuzhiyun #define TFA9879_I2S_SET_LSB_J_16 4 70*4882a593Smuzhiyun #define TFA9879_I2S_SET_LSB_J_18 5 71*4882a593Smuzhiyun #define TFA9879_I2S_SET_LSB_J_20 6 72*4882a593Smuzhiyun #define TFA9879_I2S_SET_LSB_J_24 7 73*4882a593Smuzhiyun #define TFA9879_SCK_POL_MASK 0x0004 74*4882a593Smuzhiyun #define TFA9879_SCK_POL_SHIFT 2 75*4882a593Smuzhiyun #define TFA9879_SCK_POL_NORMAL 0 76*4882a593Smuzhiyun #define TFA9879_SCK_POL_INVERSE 1 77*4882a593Smuzhiyun #define TFA9879_I_MODE_MASK 0x0003 78*4882a593Smuzhiyun #define TFA9879_I_MODE_SHIFT 0 79*4882a593Smuzhiyun #define TFA9879_I_MODE_I2S 0 80*4882a593Smuzhiyun #define TFA9879_I_MODE_PCM_IOM2_SHORT 1 81*4882a593Smuzhiyun #define TFA9879_I_MODE_PCM_IOM2_LONG 2 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* TFA9879_PCM_IOM2_FORMAT */ 84*4882a593Smuzhiyun #define TFA9879_PCM_FS_MASK 0x0800 85*4882a593Smuzhiyun #define TFA9879_PCM_FS_SHIFT 11 86*4882a593Smuzhiyun #define TFA9879_A_LAW_MASK 0x0400 87*4882a593Smuzhiyun #define TFA9879_A_LAW_SHIFT 10 88*4882a593Smuzhiyun #define TFA9879_PCM_COMP_MASK 0x0200 89*4882a593Smuzhiyun #define TFA9879_PCM_COMP_SHIFT 9 90*4882a593Smuzhiyun #define TFA9879_PCM_DL_MASK 0x0100 91*4882a593Smuzhiyun #define TFA9879_PCM_DL_SHIFT 8 92*4882a593Smuzhiyun #define TFA9879_D1_SLOT_MASK 0x00f0 93*4882a593Smuzhiyun #define TFA9879_D1_SLOT_SHIFT 4 94*4882a593Smuzhiyun #define TFA9879_D2_SLOT_MASK 0x000f 95*4882a593Smuzhiyun #define TFA9879_D2_SLOT_SHIFT 0 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* TFA9879_EQUALIZER_X1 */ 98*4882a593Smuzhiyun #define TFA9879_T1_MASK 0x8000 99*4882a593Smuzhiyun #define TFA9879_T1_SHIFT 15 100*4882a593Smuzhiyun #define TFA9879_K1M_MASK 0x7ff0 101*4882a593Smuzhiyun #define TFA9879_K1M_SHIFT 4 102*4882a593Smuzhiyun #define TFA9879_K1E_MASK 0x000f 103*4882a593Smuzhiyun #define TFA9879_K1E_SHIFT 0 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* TFA9879_EQUALIZER_X2 */ 106*4882a593Smuzhiyun #define TFA9879_T2_MASK 0x8000 107*4882a593Smuzhiyun #define TFA9879_T2_SHIFT 15 108*4882a593Smuzhiyun #define TFA9879_K2M_MASK 0x7800 109*4882a593Smuzhiyun #define TFA9879_K2M_SHIFT 11 110*4882a593Smuzhiyun #define TFA9879_K2E_MASK 0x0700 111*4882a593Smuzhiyun #define TFA9879_K2E_SHIFT 8 112*4882a593Smuzhiyun #define TFA9879_K0_MASK 0x00fe 113*4882a593Smuzhiyun #define TFA9879_K0_SHIFT 1 114*4882a593Smuzhiyun #define TFA9879_S_MASK 0x0001 115*4882a593Smuzhiyun #define TFA9879_S_SHIFT 0 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* TFA9879_BYPASS_CONTROL */ 118*4882a593Smuzhiyun #define TFA9879_L_OCP_MASK 0x00c0 119*4882a593Smuzhiyun #define TFA9879_L_OCP_SHIFT 6 120*4882a593Smuzhiyun #define TFA9879_L_OTP_MASK 0x0030 121*4882a593Smuzhiyun #define TFA9879_L_OTP_SHIFT 4 122*4882a593Smuzhiyun #define TFA9879_CLIPCTRL_MASK 0x0008 123*4882a593Smuzhiyun #define TFA9879_CLIPCTRL_SHIFT 3 124*4882a593Smuzhiyun #define TFA9879_HPF_BP_MASK 0x0004 125*4882a593Smuzhiyun #define TFA9879_HPF_BP_SHIFT 2 126*4882a593Smuzhiyun #define TFA9879_DRC_BP_MASK 0x0002 127*4882a593Smuzhiyun #define TFA9879_DRC_BP_SHIFT 1 128*4882a593Smuzhiyun #define TFA9879_EQ_BP_MASK 0x0001 129*4882a593Smuzhiyun #define TFA9879_EQ_BP_SHIFT 0 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* TFA9879_DYNAMIC_RANGE_COMPR */ 132*4882a593Smuzhiyun #define TFA9879_AT_LVL_MASK 0xf000 133*4882a593Smuzhiyun #define TFA9879_AT_LVL_SHIFT 12 134*4882a593Smuzhiyun #define TFA9879_AT_RATE_MASK 0x0f00 135*4882a593Smuzhiyun #define TFA9879_AT_RATE_SHIFT 8 136*4882a593Smuzhiyun #define TFA9879_RL_LVL_MASK 0x00f0 137*4882a593Smuzhiyun #define TFA9879_RL_LVL_SHIFT 4 138*4882a593Smuzhiyun #define TFA9879_RL_RATE_MASK 0x000f 139*4882a593Smuzhiyun #define TFA9879_RL_RATE_SHIFT 0 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* TFA9879_BASS_TREBLE */ 142*4882a593Smuzhiyun #define TFA9879_G_TRBLE_MASK 0x3e00 143*4882a593Smuzhiyun #define TFA9879_G_TRBLE_SHIFT 9 144*4882a593Smuzhiyun #define TFA9879_F_TRBLE_MASK 0x0180 145*4882a593Smuzhiyun #define TFA9879_F_TRBLE_SHIFT 7 146*4882a593Smuzhiyun #define TFA9879_G_BASS_MASK 0x007c 147*4882a593Smuzhiyun #define TFA9879_G_BASS_SHIFT 2 148*4882a593Smuzhiyun #define TFA9879_F_BASS_MASK 0x0003 149*4882a593Smuzhiyun #define TFA9879_F_BASS_SHIFT 0 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* TFA9879_HIGH_PASS_FILTER */ 152*4882a593Smuzhiyun #define TFA9879_HP_CTRL_MASK 0x00ff 153*4882a593Smuzhiyun #define TFA9879_HP_CTRL_SHIFT 0 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* TFA9879_VOLUME_CONTROL */ 156*4882a593Smuzhiyun #define TFA9879_ZR_CRSS_MASK 0x1000 157*4882a593Smuzhiyun #define TFA9879_ZR_CRSS_SHIFT 12 158*4882a593Smuzhiyun #define TFA9879_VOL_MASK 0x00ff 159*4882a593Smuzhiyun #define TFA9879_VOL_SHIFT 0 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* TFA9879_MISC_CONTROL */ 162*4882a593Smuzhiyun #define TFA9879_DE_PHAS_MASK 0x0c00 163*4882a593Smuzhiyun #define TFA9879_DE_PHAS_SHIFT 10 164*4882a593Smuzhiyun #define TFA9879_H_MUTE_MASK 0x0200 165*4882a593Smuzhiyun #define TFA9879_H_MUTE_SHIFT 9 166*4882a593Smuzhiyun #define TFA9879_S_MUTE_MASK 0x0100 167*4882a593Smuzhiyun #define TFA9879_S_MUTE_SHIFT 8 168*4882a593Smuzhiyun #define TFA9879_P_LIM_MASK 0x00ff 169*4882a593Smuzhiyun #define TFA9879_P_LIM_SHIFT 0 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* TFA9879_MISC_STATUS */ 172*4882a593Smuzhiyun #define TFA9879_PS_MASK 0x4000 173*4882a593Smuzhiyun #define TFA9879_PS_SHIFT 14 174*4882a593Smuzhiyun #define TFA9879_PORA_MASK 0x2000 175*4882a593Smuzhiyun #define TFA9879_PORA_SHIFT 13 176*4882a593Smuzhiyun #define TFA9879_AMP_MASK 0x0600 177*4882a593Smuzhiyun #define TFA9879_AMP_SHIFT 9 178*4882a593Smuzhiyun #define TFA9879_IBP_2_MASK 0x0100 179*4882a593Smuzhiyun #define TFA9879_IBP_2_SHIFT 8 180*4882a593Smuzhiyun #define TFA9879_OFP_2_MASK 0x0080 181*4882a593Smuzhiyun #define TFA9879_OFP_2_SHIFT 7 182*4882a593Smuzhiyun #define TFA9879_UFP_2_MASK 0x0040 183*4882a593Smuzhiyun #define TFA9879_UFP_2_SHIFT 6 184*4882a593Smuzhiyun #define TFA9879_IBP_1_MASK 0x0020 185*4882a593Smuzhiyun #define TFA9879_IBP_1_SHIFT 5 186*4882a593Smuzhiyun #define TFA9879_OFP_1_MASK 0x0010 187*4882a593Smuzhiyun #define TFA9879_OFP_1_SHIFT 4 188*4882a593Smuzhiyun #define TFA9879_UFP_1_MASK 0x0008 189*4882a593Smuzhiyun #define TFA9879_UFP_1_SHIFT 3 190*4882a593Smuzhiyun #define TFA9879_OCPOKA_MASK 0x0004 191*4882a593Smuzhiyun #define TFA9879_OCPOKA_SHIFT 2 192*4882a593Smuzhiyun #define TFA9879_OCPOKB_MASK 0x0002 193*4882a593Smuzhiyun #define TFA9879_OCPOKB_SHIFT 1 194*4882a593Smuzhiyun #define TFA9879_OTPOK_MASK 0x0001 195*4882a593Smuzhiyun #define TFA9879_OTPOK_SHIFT 0 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun #endif 198