1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tas2764.h - ALSA SoC Texas Instruments TAS2764 Mono Audio Amplifier 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Dan Murphy <dmurphy@ti.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __TAS2764__ 11*4882a593Smuzhiyun #define __TAS2764__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Book Control Register */ 14*4882a593Smuzhiyun #define TAS2764_BOOKCTL_PAGE 0 15*4882a593Smuzhiyun #define TAS2764_BOOKCTL_REG 127 16*4882a593Smuzhiyun #define TAS2764_REG(page, reg) ((page * 128) + reg) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Page */ 19*4882a593Smuzhiyun #define TAS2764_PAGE TAS2764_REG(0X0, 0x00) 20*4882a593Smuzhiyun #define TAS2764_PAGE_PAGE_MASK 255 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Software Reset */ 23*4882a593Smuzhiyun #define TAS2764_SW_RST TAS2764_REG(0X0, 0x01) 24*4882a593Smuzhiyun #define TAS2764_RST BIT(0) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Power Control */ 27*4882a593Smuzhiyun #define TAS2764_PWR_CTRL TAS2764_REG(0X0, 0x02) 28*4882a593Smuzhiyun #define TAS2764_PWR_CTRL_MASK GENMASK(1, 0) 29*4882a593Smuzhiyun #define TAS2764_PWR_CTRL_ACTIVE 0x0 30*4882a593Smuzhiyun #define TAS2764_PWR_CTRL_MUTE BIT(0) 31*4882a593Smuzhiyun #define TAS2764_PWR_CTRL_SHUTDOWN BIT(1) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define TAS2764_VSENSE_POWER_EN 3 34*4882a593Smuzhiyun #define TAS2764_ISENSE_POWER_EN 4 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Digital Volume Control */ 37*4882a593Smuzhiyun #define TAS2764_DVC TAS2764_REG(0X0, 0x1a) 38*4882a593Smuzhiyun #define TAS2764_DVC_MAX 0xc9 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define TAS2764_CHNL_0 TAS2764_REG(0X0, 0x03) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* TDM Configuration Reg0 */ 43*4882a593Smuzhiyun #define TAS2764_TDM_CFG0 TAS2764_REG(0X0, 0x08) 44*4882a593Smuzhiyun #define TAS2764_TDM_CFG0_SMP_MASK BIT(5) 45*4882a593Smuzhiyun #define TAS2764_TDM_CFG0_SMP_48KHZ 0x0 46*4882a593Smuzhiyun #define TAS2764_TDM_CFG0_SMP_44_1KHZ BIT(5) 47*4882a593Smuzhiyun #define TAS2764_TDM_CFG0_MASK GENMASK(3, 1) 48*4882a593Smuzhiyun #define TAS2764_TDM_CFG0_44_1_48KHZ BIT(3) 49*4882a593Smuzhiyun #define TAS2764_TDM_CFG0_88_2_96KHZ (BIT(3) | BIT(1)) 50*4882a593Smuzhiyun #define TAS2764_TDM_CFG0_FRAME_START BIT(0) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* TDM Configuration Reg1 */ 53*4882a593Smuzhiyun #define TAS2764_TDM_CFG1 TAS2764_REG(0X0, 0x09) 54*4882a593Smuzhiyun #define TAS2764_TDM_CFG1_MASK GENMASK(5, 1) 55*4882a593Smuzhiyun #define TAS2764_TDM_CFG1_51_SHIFT 1 56*4882a593Smuzhiyun #define TAS2764_TDM_CFG1_RX_MASK BIT(0) 57*4882a593Smuzhiyun #define TAS2764_TDM_CFG1_RX_RISING 0x0 58*4882a593Smuzhiyun #define TAS2764_TDM_CFG1_RX_FALLING BIT(0) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* TDM Configuration Reg2 */ 61*4882a593Smuzhiyun #define TAS2764_TDM_CFG2 TAS2764_REG(0X0, 0x0a) 62*4882a593Smuzhiyun #define TAS2764_TDM_CFG2_RXW_MASK GENMASK(3, 2) 63*4882a593Smuzhiyun #define TAS2764_TDM_CFG2_RXW_16BITS 0x0 64*4882a593Smuzhiyun #define TAS2764_TDM_CFG2_RXW_24BITS BIT(3) 65*4882a593Smuzhiyun #define TAS2764_TDM_CFG2_RXW_32BITS (BIT(3) | BIT(2)) 66*4882a593Smuzhiyun #define TAS2764_TDM_CFG2_RXS_MASK GENMASK(1, 0) 67*4882a593Smuzhiyun #define TAS2764_TDM_CFG2_RXS_16BITS 0x0 68*4882a593Smuzhiyun #define TAS2764_TDM_CFG2_RXS_24BITS BIT(0) 69*4882a593Smuzhiyun #define TAS2764_TDM_CFG2_RXS_32BITS BIT(1) 70*4882a593Smuzhiyun #define TAS2764_TDM_CFG2_SCFG_SHIFT 4 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* TDM Configuration Reg3 */ 73*4882a593Smuzhiyun #define TAS2764_TDM_CFG3 TAS2764_REG(0X0, 0x0c) 74*4882a593Smuzhiyun #define TAS2764_TDM_CFG3_RXS_MASK GENMASK(7, 4) 75*4882a593Smuzhiyun #define TAS2764_TDM_CFG3_RXS_SHIFT 0x4 76*4882a593Smuzhiyun #define TAS2764_TDM_CFG3_MASK GENMASK(3, 0) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* TDM Configuration Reg5 */ 79*4882a593Smuzhiyun #define TAS2764_TDM_CFG5 TAS2764_REG(0X0, 0x0e) 80*4882a593Smuzhiyun #define TAS2764_TDM_CFG5_VSNS_MASK BIT(6) 81*4882a593Smuzhiyun #define TAS2764_TDM_CFG5_VSNS_ENABLE BIT(6) 82*4882a593Smuzhiyun #define TAS2764_TDM_CFG5_50_MASK GENMASK(5, 0) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* TDM Configuration Reg6 */ 85*4882a593Smuzhiyun #define TAS2764_TDM_CFG6 TAS2764_REG(0X0, 0x0f) 86*4882a593Smuzhiyun #define TAS2764_TDM_CFG6_ISNS_MASK BIT(6) 87*4882a593Smuzhiyun #define TAS2764_TDM_CFG6_ISNS_ENABLE BIT(6) 88*4882a593Smuzhiyun #define TAS2764_TDM_CFG6_50_MASK GENMASK(5, 0) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* __TAS2764__ */ 91