1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tas2552.h - ALSA SoC Texas Instruments TAS2552 Mono Audio Amplifier 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Dan Murphy <dmurphy@ti.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __TAS2552_H__ 11*4882a593Smuzhiyun #define __TAS2552_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Register Address Map */ 14*4882a593Smuzhiyun #define TAS2552_DEVICE_STATUS 0x00 15*4882a593Smuzhiyun #define TAS2552_CFG_1 0x01 16*4882a593Smuzhiyun #define TAS2552_CFG_2 0x02 17*4882a593Smuzhiyun #define TAS2552_CFG_3 0x03 18*4882a593Smuzhiyun #define TAS2552_DOUT 0x04 19*4882a593Smuzhiyun #define TAS2552_SER_CTRL_1 0x05 20*4882a593Smuzhiyun #define TAS2552_SER_CTRL_2 0x06 21*4882a593Smuzhiyun #define TAS2552_OUTPUT_DATA 0x07 22*4882a593Smuzhiyun #define TAS2552_PLL_CTRL_1 0x08 23*4882a593Smuzhiyun #define TAS2552_PLL_CTRL_2 0x09 24*4882a593Smuzhiyun #define TAS2552_PLL_CTRL_3 0x0a 25*4882a593Smuzhiyun #define TAS2552_BTIP 0x0b 26*4882a593Smuzhiyun #define TAS2552_BTS_CTRL 0x0c 27*4882a593Smuzhiyun #define TAS2552_RESERVED_0D 0x0d 28*4882a593Smuzhiyun #define TAS2552_LIMIT_RATE_HYS 0x0e 29*4882a593Smuzhiyun #define TAS2552_LIMIT_RELEASE 0x0f 30*4882a593Smuzhiyun #define TAS2552_LIMIT_INT_COUNT 0x10 31*4882a593Smuzhiyun #define TAS2552_PDM_CFG 0x11 32*4882a593Smuzhiyun #define TAS2552_PGA_GAIN 0x12 33*4882a593Smuzhiyun #define TAS2552_EDGE_RATE_CTRL 0x13 34*4882a593Smuzhiyun #define TAS2552_BOOST_APT_CTRL 0x14 35*4882a593Smuzhiyun #define TAS2552_VER_NUM 0x16 36*4882a593Smuzhiyun #define TAS2552_VBAT_DATA 0x19 37*4882a593Smuzhiyun #define TAS2552_MAX_REG TAS2552_VBAT_DATA 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* CFG1 Register Masks */ 40*4882a593Smuzhiyun #define TAS2552_DEV_RESET (1 << 0) 41*4882a593Smuzhiyun #define TAS2552_SWS (1 << 1) 42*4882a593Smuzhiyun #define TAS2552_MUTE (1 << 2) 43*4882a593Smuzhiyun #define TAS2552_PLL_SRC_MCLK (0x0 << 4) 44*4882a593Smuzhiyun #define TAS2552_PLL_SRC_BCLK (0x1 << 4) 45*4882a593Smuzhiyun #define TAS2552_PLL_SRC_IVCLKIN (0x2 << 4) 46*4882a593Smuzhiyun #define TAS2552_PLL_SRC_1_8_FIXED (0x3 << 4) 47*4882a593Smuzhiyun #define TAS2552_PLL_SRC_MASK TAS2552_PLL_SRC_1_8_FIXED 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* CFG2 Register Masks */ 50*4882a593Smuzhiyun #define TAS2552_CLASSD_EN (1 << 7) 51*4882a593Smuzhiyun #define TAS2552_BOOST_EN (1 << 6) 52*4882a593Smuzhiyun #define TAS2552_APT_EN (1 << 5) 53*4882a593Smuzhiyun #define TAS2552_PLL_ENABLE (1 << 3) 54*4882a593Smuzhiyun #define TAS2552_LIM_EN (1 << 2) 55*4882a593Smuzhiyun #define TAS2552_IVSENSE_EN (1 << 1) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* CFG3 Register Masks */ 58*4882a593Smuzhiyun #define TAS2552_WCLK_FREQ_8KHZ (0x0 << 0) 59*4882a593Smuzhiyun #define TAS2552_WCLK_FREQ_11_12KHZ (0x1 << 0) 60*4882a593Smuzhiyun #define TAS2552_WCLK_FREQ_16KHZ (0x2 << 0) 61*4882a593Smuzhiyun #define TAS2552_WCLK_FREQ_22_24KHZ (0x3 << 0) 62*4882a593Smuzhiyun #define TAS2552_WCLK_FREQ_32KHZ (0x4 << 0) 63*4882a593Smuzhiyun #define TAS2552_WCLK_FREQ_44_48KHZ (0x5 << 0) 64*4882a593Smuzhiyun #define TAS2552_WCLK_FREQ_88_96KHZ (0x6 << 0) 65*4882a593Smuzhiyun #define TAS2552_WCLK_FREQ_176_192KHZ (0x7 << 0) 66*4882a593Smuzhiyun #define TAS2552_WCLK_FREQ_MASK TAS2552_WCLK_FREQ_176_192KHZ 67*4882a593Smuzhiyun #define TAS2552_DIN_SRC_SEL_MUTED (0x0 << 3) 68*4882a593Smuzhiyun #define TAS2552_DIN_SRC_SEL_LEFT (0x1 << 3) 69*4882a593Smuzhiyun #define TAS2552_DIN_SRC_SEL_RIGHT (0x2 << 3) 70*4882a593Smuzhiyun #define TAS2552_DIN_SRC_SEL_AVG_L_R (0x3 << 3) 71*4882a593Smuzhiyun #define TAS2552_PDM_IN_SEL (1 << 5) 72*4882a593Smuzhiyun #define TAS2552_I2S_OUT_SEL (1 << 6) 73*4882a593Smuzhiyun #define TAS2552_ANALOG_IN_SEL (1 << 7) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* DOUT Register Masks */ 76*4882a593Smuzhiyun #define TAS2552_SDOUT_TRISTATE (1 << 2) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Serial Interface Control Register Masks */ 79*4882a593Smuzhiyun #define TAS2552_WORDLENGTH_16BIT (0x0 << 0) 80*4882a593Smuzhiyun #define TAS2552_WORDLENGTH_20BIT (0x1 << 0) 81*4882a593Smuzhiyun #define TAS2552_WORDLENGTH_24BIT (0x2 << 0) 82*4882a593Smuzhiyun #define TAS2552_WORDLENGTH_32BIT (0x3 << 0) 83*4882a593Smuzhiyun #define TAS2552_WORDLENGTH_MASK TAS2552_WORDLENGTH_32BIT 84*4882a593Smuzhiyun #define TAS2552_DATAFORMAT_I2S (0x0 << 2) 85*4882a593Smuzhiyun #define TAS2552_DATAFORMAT_DSP (0x1 << 2) 86*4882a593Smuzhiyun #define TAS2552_DATAFORMAT_RIGHT_J (0x2 << 2) 87*4882a593Smuzhiyun #define TAS2552_DATAFORMAT_LEFT_J (0x3 << 2) 88*4882a593Smuzhiyun #define TAS2552_DATAFORMAT_MASK TAS2552_DATAFORMAT_LEFT_J 89*4882a593Smuzhiyun #define TAS2552_CLKSPERFRAME_32 (0x0 << 4) 90*4882a593Smuzhiyun #define TAS2552_CLKSPERFRAME_64 (0x1 << 4) 91*4882a593Smuzhiyun #define TAS2552_CLKSPERFRAME_128 (0x2 << 4) 92*4882a593Smuzhiyun #define TAS2552_CLKSPERFRAME_256 (0x3 << 4) 93*4882a593Smuzhiyun #define TAS2552_CLKSPERFRAME_MASK TAS2552_CLKSPERFRAME_256 94*4882a593Smuzhiyun #define TAS2552_BCLKDIR (1 << 6) 95*4882a593Smuzhiyun #define TAS2552_WCLKDIR (1 << 7) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* OUTPUT_DATA register */ 98*4882a593Smuzhiyun #define TAS2552_DATA_OUT_I_DATA (0x0) 99*4882a593Smuzhiyun #define TAS2552_DATA_OUT_V_DATA (0x1) 100*4882a593Smuzhiyun #define TAS2552_DATA_OUT_VBAT_DATA (0x2) 101*4882a593Smuzhiyun #define TAS2552_DATA_OUT_VBOOST_DATA (0x3) 102*4882a593Smuzhiyun #define TAS2552_DATA_OUT_PGA_GAIN (0x4) 103*4882a593Smuzhiyun #define TAS2552_DATA_OUT_IV_DATA (0x5) 104*4882a593Smuzhiyun #define TAS2552_DATA_OUT_VBAT_VBOOST_GAIN (0x6) 105*4882a593Smuzhiyun #define TAS2552_DATA_OUT_DISABLED (0x7) 106*4882a593Smuzhiyun #define TAS2552_L_DATA_OUT(x) ((x) << 0) 107*4882a593Smuzhiyun #define TAS2552_R_DATA_OUT(x) ((x) << 3) 108*4882a593Smuzhiyun #define TAS2552_PDM_DATA_SEL_I (0x0 << 6) 109*4882a593Smuzhiyun #define TAS2552_PDM_DATA_SEL_V (0x1 << 6) 110*4882a593Smuzhiyun #define TAS2552_PDM_DATA_SEL_I_V (0x2 << 6) 111*4882a593Smuzhiyun #define TAS2552_PDM_DATA_SEL_V_I (0x3 << 6) 112*4882a593Smuzhiyun #define TAS2552_PDM_DATA_SEL_MASK TAS2552_PDM_DATA_SEL_V_I 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* PDM CFG Register */ 115*4882a593Smuzhiyun #define TAS2552_PDM_CLK_SEL_PLL (0x0 << 0) 116*4882a593Smuzhiyun #define TAS2552_PDM_CLK_SEL_IVCLKIN (0x1 << 0) 117*4882a593Smuzhiyun #define TAS2552_PDM_CLK_SEL_BCLK (0x2 << 0) 118*4882a593Smuzhiyun #define TAS2552_PDM_CLK_SEL_MCLK (0x3 << 0) 119*4882a593Smuzhiyun #define TAS2552_PDM_CLK_SEL_MASK TAS2552_PDM_CLK_SEL_MCLK 120*4882a593Smuzhiyun #define TAS2552_PDM_DATA_ES (1 << 2) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* Boost Auto-pass through register */ 123*4882a593Smuzhiyun #define TAS2552_APT_DELAY_50 (0x0 << 0) 124*4882a593Smuzhiyun #define TAS2552_APT_DELAY_75 (0x1 << 0) 125*4882a593Smuzhiyun #define TAS2552_APT_DELAY_125 (0x2 << 0) 126*4882a593Smuzhiyun #define TAS2552_APT_DELAY_200 (0x3 << 0) 127*4882a593Smuzhiyun #define TAS2552_APT_THRESH_05_02 (0x0 << 2) 128*4882a593Smuzhiyun #define TAS2552_APT_THRESH_10_07 (0x1 << 2) 129*4882a593Smuzhiyun #define TAS2552_APT_THRESH_14_11 (0x2 << 2) 130*4882a593Smuzhiyun #define TAS2552_APT_THRESH_20_17 (0x3 << 2) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* PLL Control Register */ 133*4882a593Smuzhiyun #define TAS2552_PLL_J_MASK 0x7f 134*4882a593Smuzhiyun #define TAS2552_PLL_D_UPPER(x) (((x) >> 8) & 0x3f) 135*4882a593Smuzhiyun #define TAS2552_PLL_D_LOWER(x) ((x) & 0xff) 136*4882a593Smuzhiyun #define TAS2552_PLL_BYPASS (1 << 7) 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #endif 139