1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * ASoC codec driver for spear platform
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * sound/soc/codecs/sta529.c -- spear ALSA Soc codec driver
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2012 ST Microelectronics
7*4882a593Smuzhiyun * Rajeev Kumar <rajeevkumar.linux@gmail.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
10*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
11*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/clk.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/io.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/moduleparam.h>
20*4882a593Smuzhiyun #include <linux/pm.h>
21*4882a593Smuzhiyun #include <linux/regmap.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include <sound/core.h>
25*4882a593Smuzhiyun #include <sound/initval.h>
26*4882a593Smuzhiyun #include <sound/pcm.h>
27*4882a593Smuzhiyun #include <sound/pcm_params.h>
28*4882a593Smuzhiyun #include <sound/soc.h>
29*4882a593Smuzhiyun #include <sound/soc-dapm.h>
30*4882a593Smuzhiyun #include <sound/tlv.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* STA529 Register offsets */
33*4882a593Smuzhiyun #define STA529_FFXCFG0 0x00
34*4882a593Smuzhiyun #define STA529_FFXCFG1 0x01
35*4882a593Smuzhiyun #define STA529_MVOL 0x02
36*4882a593Smuzhiyun #define STA529_LVOL 0x03
37*4882a593Smuzhiyun #define STA529_RVOL 0x04
38*4882a593Smuzhiyun #define STA529_TTF0 0x05
39*4882a593Smuzhiyun #define STA529_TTF1 0x06
40*4882a593Smuzhiyun #define STA529_TTP0 0x07
41*4882a593Smuzhiyun #define STA529_TTP1 0x08
42*4882a593Smuzhiyun #define STA529_S2PCFG0 0x0A
43*4882a593Smuzhiyun #define STA529_S2PCFG1 0x0B
44*4882a593Smuzhiyun #define STA529_P2SCFG0 0x0C
45*4882a593Smuzhiyun #define STA529_P2SCFG1 0x0D
46*4882a593Smuzhiyun #define STA529_PLLCFG0 0x14
47*4882a593Smuzhiyun #define STA529_PLLCFG1 0x15
48*4882a593Smuzhiyun #define STA529_PLLCFG2 0x16
49*4882a593Smuzhiyun #define STA529_PLLCFG3 0x17
50*4882a593Smuzhiyun #define STA529_PLLPFE 0x18
51*4882a593Smuzhiyun #define STA529_PLLST 0x19
52*4882a593Smuzhiyun #define STA529_ADCCFG 0x1E /*mic_select*/
53*4882a593Smuzhiyun #define STA529_CKOCFG 0x1F
54*4882a593Smuzhiyun #define STA529_MISC 0x20
55*4882a593Smuzhiyun #define STA529_PADST0 0x21
56*4882a593Smuzhiyun #define STA529_PADST1 0x22
57*4882a593Smuzhiyun #define STA529_FFXST 0x23
58*4882a593Smuzhiyun #define STA529_PWMIN1 0x2D
59*4882a593Smuzhiyun #define STA529_PWMIN2 0x2E
60*4882a593Smuzhiyun #define STA529_POWST 0x32
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define STA529_MAX_REGISTER 0x32
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define STA529_RATES (SNDRV_PCM_RATE_8000 | \
65*4882a593Smuzhiyun SNDRV_PCM_RATE_11025 | \
66*4882a593Smuzhiyun SNDRV_PCM_RATE_16000 | \
67*4882a593Smuzhiyun SNDRV_PCM_RATE_22050 | \
68*4882a593Smuzhiyun SNDRV_PCM_RATE_32000 | \
69*4882a593Smuzhiyun SNDRV_PCM_RATE_44100 | \
70*4882a593Smuzhiyun SNDRV_PCM_RATE_48000)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define STA529_FORMAT (SNDRV_PCM_FMTBIT_S16_LE | \
73*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | \
74*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE)
75*4882a593Smuzhiyun #define S2PC_VALUE 0x98
76*4882a593Smuzhiyun #define CLOCK_OUT 0x60
77*4882a593Smuzhiyun #define DATA_FORMAT_MSK 0x0E
78*4882a593Smuzhiyun #define LEFT_J_DATA_FORMAT 0x00
79*4882a593Smuzhiyun #define I2S_DATA_FORMAT 0x02
80*4882a593Smuzhiyun #define RIGHT_J_DATA_FORMAT 0x04
81*4882a593Smuzhiyun #define CODEC_MUTE_VAL 0x80
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define POWER_CNTLMSAK 0x40
84*4882a593Smuzhiyun #define POWER_STDBY 0x40
85*4882a593Smuzhiyun #define FFX_MASK 0x80
86*4882a593Smuzhiyun #define FFX_OFF 0x80
87*4882a593Smuzhiyun #define POWER_UP 0x00
88*4882a593Smuzhiyun #define FFX_CLK_ENB 0x01
89*4882a593Smuzhiyun #define FFX_CLK_DIS 0x00
90*4882a593Smuzhiyun #define FFX_CLK_MSK 0x01
91*4882a593Smuzhiyun #define PLAY_FREQ_RANGE_MSK 0x70
92*4882a593Smuzhiyun #define CAP_FREQ_RANGE_MSK 0x0C
93*4882a593Smuzhiyun #define PDATA_LEN_MSK 0xC0
94*4882a593Smuzhiyun #define BCLK_TO_FS_MSK 0x30
95*4882a593Smuzhiyun #define AUDIO_MUTE_MSK 0x80
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static const struct reg_default sta529_reg_defaults[] = {
98*4882a593Smuzhiyun { 0, 0x35 }, /* R0 - FFX Configuration reg 0 */
99*4882a593Smuzhiyun { 1, 0xc8 }, /* R1 - FFX Configuration reg 1 */
100*4882a593Smuzhiyun { 2, 0x50 }, /* R2 - Master Volume */
101*4882a593Smuzhiyun { 3, 0x00 }, /* R3 - Left Volume */
102*4882a593Smuzhiyun { 4, 0x00 }, /* R4 - Right Volume */
103*4882a593Smuzhiyun { 10, 0xb2 }, /* R10 - S2P Config Reg 0 */
104*4882a593Smuzhiyun { 11, 0x41 }, /* R11 - S2P Config Reg 1 */
105*4882a593Smuzhiyun { 12, 0x92 }, /* R12 - P2S Config Reg 0 */
106*4882a593Smuzhiyun { 13, 0x41 }, /* R13 - P2S Config Reg 1 */
107*4882a593Smuzhiyun { 30, 0xd2 }, /* R30 - ADC Config Reg */
108*4882a593Smuzhiyun { 31, 0x40 }, /* R31 - clock Out Reg */
109*4882a593Smuzhiyun { 32, 0x21 }, /* R32 - Misc Register */
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun struct sta529 {
113*4882a593Smuzhiyun struct regmap *regmap;
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
sta529_readable(struct device * dev,unsigned int reg)116*4882a593Smuzhiyun static bool sta529_readable(struct device *dev, unsigned int reg)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun switch (reg) {
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun case STA529_FFXCFG0:
121*4882a593Smuzhiyun case STA529_FFXCFG1:
122*4882a593Smuzhiyun case STA529_MVOL:
123*4882a593Smuzhiyun case STA529_LVOL:
124*4882a593Smuzhiyun case STA529_RVOL:
125*4882a593Smuzhiyun case STA529_S2PCFG0:
126*4882a593Smuzhiyun case STA529_S2PCFG1:
127*4882a593Smuzhiyun case STA529_P2SCFG0:
128*4882a593Smuzhiyun case STA529_P2SCFG1:
129*4882a593Smuzhiyun case STA529_ADCCFG:
130*4882a593Smuzhiyun case STA529_CKOCFG:
131*4882a593Smuzhiyun case STA529_MISC:
132*4882a593Smuzhiyun return true;
133*4882a593Smuzhiyun default:
134*4882a593Smuzhiyun return false;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun static const char *pwm_mode_text[] = { "Binary", "Headphone", "Ternary",
140*4882a593Smuzhiyun "Phase-shift"};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(out_gain_tlv, -9150, 50, 0);
143*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(master_vol_tlv, -12750, 50, 0);
144*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(pwm_src, STA529_FFXCFG1, 4, pwm_mode_text);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun static const struct snd_kcontrol_new sta529_snd_controls[] = {
147*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Digital Playback Volume", STA529_LVOL, STA529_RVOL, 0,
148*4882a593Smuzhiyun 127, 0, out_gain_tlv),
149*4882a593Smuzhiyun SOC_SINGLE_TLV("Master Playback Volume", STA529_MVOL, 0, 127, 1,
150*4882a593Smuzhiyun master_vol_tlv),
151*4882a593Smuzhiyun SOC_ENUM("PWM Select", pwm_src),
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun
sta529_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)154*4882a593Smuzhiyun static int sta529_set_bias_level(struct snd_soc_component *component, enum
155*4882a593Smuzhiyun snd_soc_bias_level level)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun struct sta529 *sta529 = snd_soc_component_get_drvdata(component);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun switch (level) {
160*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
161*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
162*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_FFXCFG0, POWER_CNTLMSAK,
163*4882a593Smuzhiyun POWER_UP);
164*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_MISC, FFX_CLK_MSK,
165*4882a593Smuzhiyun FFX_CLK_ENB);
166*4882a593Smuzhiyun break;
167*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
168*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
169*4882a593Smuzhiyun regcache_sync(sta529->regmap);
170*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_FFXCFG0,
171*4882a593Smuzhiyun POWER_CNTLMSAK, POWER_STDBY);
172*4882a593Smuzhiyun /* Making FFX output to zero */
173*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_FFXCFG0, FFX_MASK,
174*4882a593Smuzhiyun FFX_OFF);
175*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_MISC, FFX_CLK_MSK,
176*4882a593Smuzhiyun FFX_CLK_DIS);
177*4882a593Smuzhiyun break;
178*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
179*4882a593Smuzhiyun break;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun return 0;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
sta529_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)186*4882a593Smuzhiyun static int sta529_hw_params(struct snd_pcm_substream *substream,
187*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
188*4882a593Smuzhiyun struct snd_soc_dai *dai)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
191*4882a593Smuzhiyun int pdata, play_freq_val, record_freq_val;
192*4882a593Smuzhiyun int bclk_to_fs_ratio;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun switch (params_width(params)) {
195*4882a593Smuzhiyun case 16:
196*4882a593Smuzhiyun pdata = 1;
197*4882a593Smuzhiyun bclk_to_fs_ratio = 0;
198*4882a593Smuzhiyun break;
199*4882a593Smuzhiyun case 24:
200*4882a593Smuzhiyun pdata = 2;
201*4882a593Smuzhiyun bclk_to_fs_ratio = 1;
202*4882a593Smuzhiyun break;
203*4882a593Smuzhiyun case 32:
204*4882a593Smuzhiyun pdata = 3;
205*4882a593Smuzhiyun bclk_to_fs_ratio = 2;
206*4882a593Smuzhiyun break;
207*4882a593Smuzhiyun default:
208*4882a593Smuzhiyun dev_err(component->dev, "Unsupported format\n");
209*4882a593Smuzhiyun return -EINVAL;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun switch (params_rate(params)) {
213*4882a593Smuzhiyun case 8000:
214*4882a593Smuzhiyun case 11025:
215*4882a593Smuzhiyun play_freq_val = 0;
216*4882a593Smuzhiyun record_freq_val = 2;
217*4882a593Smuzhiyun break;
218*4882a593Smuzhiyun case 16000:
219*4882a593Smuzhiyun case 22050:
220*4882a593Smuzhiyun play_freq_val = 1;
221*4882a593Smuzhiyun record_freq_val = 0;
222*4882a593Smuzhiyun break;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun case 32000:
225*4882a593Smuzhiyun case 44100:
226*4882a593Smuzhiyun case 48000:
227*4882a593Smuzhiyun play_freq_val = 2;
228*4882a593Smuzhiyun record_freq_val = 0;
229*4882a593Smuzhiyun break;
230*4882a593Smuzhiyun default:
231*4882a593Smuzhiyun dev_err(component->dev, "Unsupported rate\n");
232*4882a593Smuzhiyun return -EINVAL;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
236*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_S2PCFG1, PDATA_LEN_MSK,
237*4882a593Smuzhiyun pdata << 6);
238*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_S2PCFG1, BCLK_TO_FS_MSK,
239*4882a593Smuzhiyun bclk_to_fs_ratio << 4);
240*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_MISC, PLAY_FREQ_RANGE_MSK,
241*4882a593Smuzhiyun play_freq_val << 4);
242*4882a593Smuzhiyun } else {
243*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_P2SCFG1, PDATA_LEN_MSK,
244*4882a593Smuzhiyun pdata << 6);
245*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_P2SCFG1, BCLK_TO_FS_MSK,
246*4882a593Smuzhiyun bclk_to_fs_ratio << 4);
247*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_MISC, CAP_FREQ_RANGE_MSK,
248*4882a593Smuzhiyun record_freq_val << 2);
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun return 0;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
sta529_mute(struct snd_soc_dai * dai,int mute,int direction)254*4882a593Smuzhiyun static int sta529_mute(struct snd_soc_dai *dai, int mute, int direction)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun u8 val = 0;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun if (mute)
259*4882a593Smuzhiyun val |= CODEC_MUTE_VAL;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun snd_soc_component_update_bits(dai->component, STA529_FFXCFG0, AUDIO_MUTE_MSK, val);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun return 0;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
sta529_set_dai_fmt(struct snd_soc_dai * codec_dai,u32 fmt)266*4882a593Smuzhiyun static int sta529_set_dai_fmt(struct snd_soc_dai *codec_dai, u32 fmt)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
269*4882a593Smuzhiyun u8 mode = 0;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun /* interface format */
272*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
273*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
274*4882a593Smuzhiyun mode = LEFT_J_DATA_FORMAT;
275*4882a593Smuzhiyun break;
276*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
277*4882a593Smuzhiyun mode = I2S_DATA_FORMAT;
278*4882a593Smuzhiyun break;
279*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
280*4882a593Smuzhiyun mode = RIGHT_J_DATA_FORMAT;
281*4882a593Smuzhiyun break;
282*4882a593Smuzhiyun default:
283*4882a593Smuzhiyun return -EINVAL;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun snd_soc_component_update_bits(component, STA529_S2PCFG0, DATA_FORMAT_MSK, mode);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun return 0;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun static const struct snd_soc_dai_ops sta529_dai_ops = {
292*4882a593Smuzhiyun .hw_params = sta529_hw_params,
293*4882a593Smuzhiyun .set_fmt = sta529_set_dai_fmt,
294*4882a593Smuzhiyun .mute_stream = sta529_mute,
295*4882a593Smuzhiyun .no_capture_mute = 1,
296*4882a593Smuzhiyun };
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun static struct snd_soc_dai_driver sta529_dai = {
299*4882a593Smuzhiyun .name = "sta529-audio",
300*4882a593Smuzhiyun .playback = {
301*4882a593Smuzhiyun .stream_name = "Playback",
302*4882a593Smuzhiyun .channels_min = 2,
303*4882a593Smuzhiyun .channels_max = 2,
304*4882a593Smuzhiyun .rates = STA529_RATES,
305*4882a593Smuzhiyun .formats = STA529_FORMAT,
306*4882a593Smuzhiyun },
307*4882a593Smuzhiyun .capture = {
308*4882a593Smuzhiyun .stream_name = "Capture",
309*4882a593Smuzhiyun .channels_min = 2,
310*4882a593Smuzhiyun .channels_max = 2,
311*4882a593Smuzhiyun .rates = STA529_RATES,
312*4882a593Smuzhiyun .formats = STA529_FORMAT,
313*4882a593Smuzhiyun },
314*4882a593Smuzhiyun .ops = &sta529_dai_ops,
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun static const struct snd_soc_component_driver sta529_component_driver = {
318*4882a593Smuzhiyun .set_bias_level = sta529_set_bias_level,
319*4882a593Smuzhiyun .controls = sta529_snd_controls,
320*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(sta529_snd_controls),
321*4882a593Smuzhiyun .suspend_bias_off = 1,
322*4882a593Smuzhiyun .idle_bias_on = 1,
323*4882a593Smuzhiyun .use_pmdown_time = 1,
324*4882a593Smuzhiyun .endianness = 1,
325*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun static const struct regmap_config sta529_regmap = {
329*4882a593Smuzhiyun .reg_bits = 8,
330*4882a593Smuzhiyun .val_bits = 8,
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun .max_register = STA529_MAX_REGISTER,
333*4882a593Smuzhiyun .readable_reg = sta529_readable,
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
336*4882a593Smuzhiyun .reg_defaults = sta529_reg_defaults,
337*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(sta529_reg_defaults),
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun
sta529_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)340*4882a593Smuzhiyun static int sta529_i2c_probe(struct i2c_client *i2c,
341*4882a593Smuzhiyun const struct i2c_device_id *id)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun struct sta529 *sta529;
344*4882a593Smuzhiyun int ret;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun sta529 = devm_kzalloc(&i2c->dev, sizeof(struct sta529), GFP_KERNEL);
347*4882a593Smuzhiyun if (!sta529)
348*4882a593Smuzhiyun return -ENOMEM;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun sta529->regmap = devm_regmap_init_i2c(i2c, &sta529_regmap);
351*4882a593Smuzhiyun if (IS_ERR(sta529->regmap)) {
352*4882a593Smuzhiyun ret = PTR_ERR(sta529->regmap);
353*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
354*4882a593Smuzhiyun return ret;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun i2c_set_clientdata(i2c, sta529);
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev,
360*4882a593Smuzhiyun &sta529_component_driver, &sta529_dai, 1);
361*4882a593Smuzhiyun if (ret != 0)
362*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun return ret;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun static const struct i2c_device_id sta529_i2c_id[] = {
368*4882a593Smuzhiyun { "sta529", 0 },
369*4882a593Smuzhiyun { }
370*4882a593Smuzhiyun };
371*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, sta529_i2c_id);
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun static const struct of_device_id sta529_of_match[] = {
374*4882a593Smuzhiyun { .compatible = "st,sta529", },
375*4882a593Smuzhiyun { }
376*4882a593Smuzhiyun };
377*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sta529_of_match);
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun static struct i2c_driver sta529_i2c_driver = {
380*4882a593Smuzhiyun .driver = {
381*4882a593Smuzhiyun .name = "sta529",
382*4882a593Smuzhiyun .of_match_table = sta529_of_match,
383*4882a593Smuzhiyun },
384*4882a593Smuzhiyun .probe = sta529_i2c_probe,
385*4882a593Smuzhiyun .id_table = sta529_i2c_id,
386*4882a593Smuzhiyun };
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun module_i2c_driver(sta529_i2c_driver);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC STA529 codec driver");
391*4882a593Smuzhiyun MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
392*4882a593Smuzhiyun MODULE_LICENSE("GPL");
393