1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright: 2011 Raumfeld GmbH 6*4882a593Smuzhiyun * Author: Johannes Stezenbach <js@sig21.net> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * based on code from: 9*4882a593Smuzhiyun * Wolfson Microelectronics PLC. 10*4882a593Smuzhiyun * Mark Brown <broonie@opensource.wolfsonmicro.com> 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #ifndef _ASOC_STA_32X_H 13*4882a593Smuzhiyun #define _ASOC_STA_32X_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* STA326 register addresses */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define STA32X_REGISTER_COUNT 0x2d 18*4882a593Smuzhiyun #define STA32X_COEF_COUNT 62 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define STA32X_CONFA 0x00 21*4882a593Smuzhiyun #define STA32X_CONFB 0x01 22*4882a593Smuzhiyun #define STA32X_CONFC 0x02 23*4882a593Smuzhiyun #define STA32X_CONFD 0x03 24*4882a593Smuzhiyun #define STA32X_CONFE 0x04 25*4882a593Smuzhiyun #define STA32X_CONFF 0x05 26*4882a593Smuzhiyun #define STA32X_MMUTE 0x06 27*4882a593Smuzhiyun #define STA32X_MVOL 0x07 28*4882a593Smuzhiyun #define STA32X_C1VOL 0x08 29*4882a593Smuzhiyun #define STA32X_C2VOL 0x09 30*4882a593Smuzhiyun #define STA32X_C3VOL 0x0a 31*4882a593Smuzhiyun #define STA32X_AUTO1 0x0b 32*4882a593Smuzhiyun #define STA32X_AUTO2 0x0c 33*4882a593Smuzhiyun #define STA32X_AUTO3 0x0d 34*4882a593Smuzhiyun #define STA32X_C1CFG 0x0e 35*4882a593Smuzhiyun #define STA32X_C2CFG 0x0f 36*4882a593Smuzhiyun #define STA32X_C3CFG 0x10 37*4882a593Smuzhiyun #define STA32X_TONE 0x11 38*4882a593Smuzhiyun #define STA32X_L1AR 0x12 39*4882a593Smuzhiyun #define STA32X_L1ATRT 0x13 40*4882a593Smuzhiyun #define STA32X_L2AR 0x14 41*4882a593Smuzhiyun #define STA32X_L2ATRT 0x15 42*4882a593Smuzhiyun #define STA32X_CFADDR2 0x16 43*4882a593Smuzhiyun #define STA32X_B1CF1 0x17 44*4882a593Smuzhiyun #define STA32X_B1CF2 0x18 45*4882a593Smuzhiyun #define STA32X_B1CF3 0x19 46*4882a593Smuzhiyun #define STA32X_B2CF1 0x1a 47*4882a593Smuzhiyun #define STA32X_B2CF2 0x1b 48*4882a593Smuzhiyun #define STA32X_B2CF3 0x1c 49*4882a593Smuzhiyun #define STA32X_A1CF1 0x1d 50*4882a593Smuzhiyun #define STA32X_A1CF2 0x1e 51*4882a593Smuzhiyun #define STA32X_A1CF3 0x1f 52*4882a593Smuzhiyun #define STA32X_A2CF1 0x20 53*4882a593Smuzhiyun #define STA32X_A2CF2 0x21 54*4882a593Smuzhiyun #define STA32X_A2CF3 0x22 55*4882a593Smuzhiyun #define STA32X_B0CF1 0x23 56*4882a593Smuzhiyun #define STA32X_B0CF2 0x24 57*4882a593Smuzhiyun #define STA32X_B0CF3 0x25 58*4882a593Smuzhiyun #define STA32X_CFUD 0x26 59*4882a593Smuzhiyun #define STA32X_MPCC1 0x27 60*4882a593Smuzhiyun #define STA32X_MPCC2 0x28 61*4882a593Smuzhiyun /* Reserved 0x29 */ 62*4882a593Smuzhiyun /* Reserved 0x2a */ 63*4882a593Smuzhiyun #define STA32X_Reserved 0x2a 64*4882a593Smuzhiyun #define STA32X_FDRC1 0x2b 65*4882a593Smuzhiyun #define STA32X_FDRC2 0x2c 66*4882a593Smuzhiyun /* Reserved 0x2d */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* STA326 register field definitions */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 0x00 CONFA */ 72*4882a593Smuzhiyun #define STA32X_CONFA_MCS_MASK 0x03 73*4882a593Smuzhiyun #define STA32X_CONFA_MCS_SHIFT 0 74*4882a593Smuzhiyun #define STA32X_CONFA_IR_MASK 0x18 75*4882a593Smuzhiyun #define STA32X_CONFA_IR_SHIFT 3 76*4882a593Smuzhiyun #define STA32X_CONFA_TWRB 0x20 77*4882a593Smuzhiyun #define STA32X_CONFA_TWAB 0x40 78*4882a593Smuzhiyun #define STA32X_CONFA_FDRB 0x80 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* 0x01 CONFB */ 81*4882a593Smuzhiyun #define STA32X_CONFB_SAI_MASK 0x0f 82*4882a593Smuzhiyun #define STA32X_CONFB_SAI_SHIFT 0 83*4882a593Smuzhiyun #define STA32X_CONFB_SAIFB 0x10 84*4882a593Smuzhiyun #define STA32X_CONFB_DSCKE 0x20 85*4882a593Smuzhiyun #define STA32X_CONFB_C1IM 0x40 86*4882a593Smuzhiyun #define STA32X_CONFB_C2IM 0x80 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 0x02 CONFC */ 89*4882a593Smuzhiyun #define STA32X_CONFC_OM_MASK 0x03 90*4882a593Smuzhiyun #define STA32X_CONFC_OM_SHIFT 0 91*4882a593Smuzhiyun #define STA32X_CONFC_CSZ_MASK 0x7c 92*4882a593Smuzhiyun #define STA32X_CONFC_CSZ_SHIFT 2 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* 0x03 CONFD */ 95*4882a593Smuzhiyun #define STA32X_CONFD_HPB 0x01 96*4882a593Smuzhiyun #define STA32X_CONFD_HPB_SHIFT 0 97*4882a593Smuzhiyun #define STA32X_CONFD_DEMP 0x02 98*4882a593Smuzhiyun #define STA32X_CONFD_DEMP_SHIFT 1 99*4882a593Smuzhiyun #define STA32X_CONFD_DSPB 0x04 100*4882a593Smuzhiyun #define STA32X_CONFD_DSPB_SHIFT 2 101*4882a593Smuzhiyun #define STA32X_CONFD_PSL 0x08 102*4882a593Smuzhiyun #define STA32X_CONFD_PSL_SHIFT 3 103*4882a593Smuzhiyun #define STA32X_CONFD_BQL 0x10 104*4882a593Smuzhiyun #define STA32X_CONFD_BQL_SHIFT 4 105*4882a593Smuzhiyun #define STA32X_CONFD_DRC 0x20 106*4882a593Smuzhiyun #define STA32X_CONFD_DRC_SHIFT 5 107*4882a593Smuzhiyun #define STA32X_CONFD_ZDE 0x40 108*4882a593Smuzhiyun #define STA32X_CONFD_ZDE_SHIFT 6 109*4882a593Smuzhiyun #define STA32X_CONFD_MME 0x80 110*4882a593Smuzhiyun #define STA32X_CONFD_MME_SHIFT 7 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 0x04 CONFE */ 113*4882a593Smuzhiyun #define STA32X_CONFE_MPCV 0x01 114*4882a593Smuzhiyun #define STA32X_CONFE_MPCV_SHIFT 0 115*4882a593Smuzhiyun #define STA32X_CONFE_MPC 0x02 116*4882a593Smuzhiyun #define STA32X_CONFE_MPC_SHIFT 1 117*4882a593Smuzhiyun #define STA32X_CONFE_AME 0x08 118*4882a593Smuzhiyun #define STA32X_CONFE_AME_SHIFT 3 119*4882a593Smuzhiyun #define STA32X_CONFE_PWMS 0x10 120*4882a593Smuzhiyun #define STA32X_CONFE_PWMS_SHIFT 4 121*4882a593Smuzhiyun #define STA32X_CONFE_ZCE 0x40 122*4882a593Smuzhiyun #define STA32X_CONFE_ZCE_SHIFT 6 123*4882a593Smuzhiyun #define STA32X_CONFE_SVE 0x80 124*4882a593Smuzhiyun #define STA32X_CONFE_SVE_SHIFT 7 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* 0x05 CONFF */ 127*4882a593Smuzhiyun #define STA32X_CONFF_OCFG_MASK 0x03 128*4882a593Smuzhiyun #define STA32X_CONFF_OCFG_SHIFT 0 129*4882a593Smuzhiyun #define STA32X_CONFF_IDE 0x04 130*4882a593Smuzhiyun #define STA32X_CONFF_IDE_SHIFT 2 131*4882a593Smuzhiyun #define STA32X_CONFF_BCLE 0x08 132*4882a593Smuzhiyun #define STA32X_CONFF_ECLE 0x20 133*4882a593Smuzhiyun #define STA32X_CONFF_PWDN 0x40 134*4882a593Smuzhiyun #define STA32X_CONFF_EAPD 0x80 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* 0x06 MMUTE */ 137*4882a593Smuzhiyun #define STA32X_MMUTE_MMUTE 0x01 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* 0x0b AUTO1 */ 140*4882a593Smuzhiyun #define STA32X_AUTO1_AMEQ_MASK 0x03 141*4882a593Smuzhiyun #define STA32X_AUTO1_AMEQ_SHIFT 0 142*4882a593Smuzhiyun #define STA32X_AUTO1_AMV_MASK 0xc0 143*4882a593Smuzhiyun #define STA32X_AUTO1_AMV_SHIFT 2 144*4882a593Smuzhiyun #define STA32X_AUTO1_AMGC_MASK 0x30 145*4882a593Smuzhiyun #define STA32X_AUTO1_AMGC_SHIFT 4 146*4882a593Smuzhiyun #define STA32X_AUTO1_AMPS 0x80 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* 0x0c AUTO2 */ 149*4882a593Smuzhiyun #define STA32X_AUTO2_AMAME 0x01 150*4882a593Smuzhiyun #define STA32X_AUTO2_AMAM_MASK 0x0e 151*4882a593Smuzhiyun #define STA32X_AUTO2_AMAM_SHIFT 1 152*4882a593Smuzhiyun #define STA32X_AUTO2_XO_MASK 0xf0 153*4882a593Smuzhiyun #define STA32X_AUTO2_XO_SHIFT 4 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* 0x0d AUTO3 */ 156*4882a593Smuzhiyun #define STA32X_AUTO3_PEQ_MASK 0x1f 157*4882a593Smuzhiyun #define STA32X_AUTO3_PEQ_SHIFT 0 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* 0x0e 0x0f 0x10 CxCFG */ 160*4882a593Smuzhiyun #define STA32X_CxCFG_TCB 0x01 /* only C1 and C2 */ 161*4882a593Smuzhiyun #define STA32X_CxCFG_TCB_SHIFT 0 162*4882a593Smuzhiyun #define STA32X_CxCFG_EQBP 0x02 /* only C1 and C2 */ 163*4882a593Smuzhiyun #define STA32X_CxCFG_EQBP_SHIFT 1 164*4882a593Smuzhiyun #define STA32X_CxCFG_VBP 0x03 165*4882a593Smuzhiyun #define STA32X_CxCFG_VBP_SHIFT 2 166*4882a593Smuzhiyun #define STA32X_CxCFG_BO 0x04 167*4882a593Smuzhiyun #define STA32X_CxCFG_LS_MASK 0x30 168*4882a593Smuzhiyun #define STA32X_CxCFG_LS_SHIFT 4 169*4882a593Smuzhiyun #define STA32X_CxCFG_OM_MASK 0xc0 170*4882a593Smuzhiyun #define STA32X_CxCFG_OM_SHIFT 6 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* 0x11 TONE */ 173*4882a593Smuzhiyun #define STA32X_TONE_BTC_SHIFT 0 174*4882a593Smuzhiyun #define STA32X_TONE_TTC_SHIFT 4 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* 0x12 0x13 0x14 0x15 limiter attack/release */ 177*4882a593Smuzhiyun #define STA32X_LxA_SHIFT 0 178*4882a593Smuzhiyun #define STA32X_LxR_SHIFT 4 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* 0x26 CFUD */ 181*4882a593Smuzhiyun #define STA32X_CFUD_W1 0x01 182*4882a593Smuzhiyun #define STA32X_CFUD_WA 0x02 183*4882a593Smuzhiyun #define STA32X_CFUD_R1 0x04 184*4882a593Smuzhiyun #define STA32X_CFUD_RA 0x08 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* biquad filter coefficient table offsets */ 188*4882a593Smuzhiyun #define STA32X_C1_BQ_BASE 0 189*4882a593Smuzhiyun #define STA32X_C2_BQ_BASE 20 190*4882a593Smuzhiyun #define STA32X_CH_BQ_NUM 4 191*4882a593Smuzhiyun #define STA32X_BQ_NUM_COEF 5 192*4882a593Smuzhiyun #define STA32X_XO_HP_BQ_BASE 40 193*4882a593Smuzhiyun #define STA32X_XO_LP_BQ_BASE 45 194*4882a593Smuzhiyun #define STA32X_C1_PRESCALE 50 195*4882a593Smuzhiyun #define STA32X_C2_PRESCALE 51 196*4882a593Smuzhiyun #define STA32X_C1_POSTSCALE 52 197*4882a593Smuzhiyun #define STA32X_C2_POSTSCALE 53 198*4882a593Smuzhiyun #define STA32X_C3_POSTSCALE 54 199*4882a593Smuzhiyun #define STA32X_TW_POSTSCALE 55 200*4882a593Smuzhiyun #define STA32X_C1_MIX1 56 201*4882a593Smuzhiyun #define STA32X_C1_MIX2 57 202*4882a593Smuzhiyun #define STA32X_C2_MIX1 58 203*4882a593Smuzhiyun #define STA32X_C2_MIX2 59 204*4882a593Smuzhiyun #define STA32X_C3_MIX1 60 205*4882a593Smuzhiyun #define STA32X_C3_MIX2 61 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #endif /* _ASOC_STA_32X_H */ 208