1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SSM2518 amplifier audio driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2013 Analog Devices Inc.
6*4882a593Smuzhiyun * Author: Lars-Peter Clausen <lars@metafoo.de>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/gpio.h>
15*4882a593Smuzhiyun #include <linux/of_gpio.h>
16*4882a593Smuzhiyun #include <linux/platform_data/ssm2518.h>
17*4882a593Smuzhiyun #include <sound/core.h>
18*4882a593Smuzhiyun #include <sound/pcm.h>
19*4882a593Smuzhiyun #include <sound/pcm_params.h>
20*4882a593Smuzhiyun #include <sound/soc.h>
21*4882a593Smuzhiyun #include <sound/initval.h>
22*4882a593Smuzhiyun #include <sound/tlv.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "ssm2518.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define SSM2518_REG_POWER1 0x00
27*4882a593Smuzhiyun #define SSM2518_REG_CLOCK 0x01
28*4882a593Smuzhiyun #define SSM2518_REG_SAI_CTRL1 0x02
29*4882a593Smuzhiyun #define SSM2518_REG_SAI_CTRL2 0x03
30*4882a593Smuzhiyun #define SSM2518_REG_CHAN_MAP 0x04
31*4882a593Smuzhiyun #define SSM2518_REG_LEFT_VOL 0x05
32*4882a593Smuzhiyun #define SSM2518_REG_RIGHT_VOL 0x06
33*4882a593Smuzhiyun #define SSM2518_REG_MUTE_CTRL 0x07
34*4882a593Smuzhiyun #define SSM2518_REG_FAULT_CTRL 0x08
35*4882a593Smuzhiyun #define SSM2518_REG_POWER2 0x09
36*4882a593Smuzhiyun #define SSM2518_REG_DRC_1 0x0a
37*4882a593Smuzhiyun #define SSM2518_REG_DRC_2 0x0b
38*4882a593Smuzhiyun #define SSM2518_REG_DRC_3 0x0c
39*4882a593Smuzhiyun #define SSM2518_REG_DRC_4 0x0d
40*4882a593Smuzhiyun #define SSM2518_REG_DRC_5 0x0e
41*4882a593Smuzhiyun #define SSM2518_REG_DRC_6 0x0f
42*4882a593Smuzhiyun #define SSM2518_REG_DRC_7 0x10
43*4882a593Smuzhiyun #define SSM2518_REG_DRC_8 0x11
44*4882a593Smuzhiyun #define SSM2518_REG_DRC_9 0x12
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define SSM2518_POWER1_RESET BIT(7)
47*4882a593Smuzhiyun #define SSM2518_POWER1_NO_BCLK BIT(5)
48*4882a593Smuzhiyun #define SSM2518_POWER1_MCS_MASK (0xf << 1)
49*4882a593Smuzhiyun #define SSM2518_POWER1_MCS_64FS (0x0 << 1)
50*4882a593Smuzhiyun #define SSM2518_POWER1_MCS_128FS (0x1 << 1)
51*4882a593Smuzhiyun #define SSM2518_POWER1_MCS_256FS (0x2 << 1)
52*4882a593Smuzhiyun #define SSM2518_POWER1_MCS_384FS (0x3 << 1)
53*4882a593Smuzhiyun #define SSM2518_POWER1_MCS_512FS (0x4 << 1)
54*4882a593Smuzhiyun #define SSM2518_POWER1_MCS_768FS (0x5 << 1)
55*4882a593Smuzhiyun #define SSM2518_POWER1_MCS_100FS (0x6 << 1)
56*4882a593Smuzhiyun #define SSM2518_POWER1_MCS_200FS (0x7 << 1)
57*4882a593Smuzhiyun #define SSM2518_POWER1_MCS_400FS (0x8 << 1)
58*4882a593Smuzhiyun #define SSM2518_POWER1_SPWDN BIT(0)
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define SSM2518_CLOCK_ASR BIT(0)
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_FMT_MASK (0x3 << 5)
63*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_FMT_I2S (0x0 << 5)
64*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_FMT_LJ (0x1 << 5)
65*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_FMT_RJ_24BIT (0x2 << 5)
66*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_FMT_RJ_16BIT (0x3 << 5)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_SAI_MASK (0x7 << 2)
69*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_SAI_I2S (0x0 << 2)
70*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_SAI_TDM_2 (0x1 << 2)
71*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_SAI_TDM_4 (0x2 << 2)
72*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_SAI_TDM_8 (0x3 << 2)
73*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_SAI_TDM_16 (0x4 << 2)
74*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_SAI_MONO (0x5 << 2)
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_FS_MASK (0x3)
77*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_FS_8000_12000 (0x0)
78*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_FS_16000_24000 (0x1)
79*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_FS_32000_48000 (0x2)
80*4882a593Smuzhiyun #define SSM2518_SAI_CTRL1_FS_64000_96000 (0x3)
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #define SSM2518_SAI_CTRL2_BCLK_INTERAL BIT(7)
83*4882a593Smuzhiyun #define SSM2518_SAI_CTRL2_LRCLK_PULSE BIT(6)
84*4882a593Smuzhiyun #define SSM2518_SAI_CTRL2_LRCLK_INVERT BIT(5)
85*4882a593Smuzhiyun #define SSM2518_SAI_CTRL2_MSB BIT(4)
86*4882a593Smuzhiyun #define SSM2518_SAI_CTRL2_SLOT_WIDTH_MASK (0x3 << 2)
87*4882a593Smuzhiyun #define SSM2518_SAI_CTRL2_SLOT_WIDTH_32 (0x0 << 2)
88*4882a593Smuzhiyun #define SSM2518_SAI_CTRL2_SLOT_WIDTH_24 (0x1 << 2)
89*4882a593Smuzhiyun #define SSM2518_SAI_CTRL2_SLOT_WIDTH_16 (0x2 << 2)
90*4882a593Smuzhiyun #define SSM2518_SAI_CTRL2_BCLK_INVERT BIT(1)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define SSM2518_CHAN_MAP_RIGHT_SLOT_OFFSET 4
93*4882a593Smuzhiyun #define SSM2518_CHAN_MAP_RIGHT_SLOT_MASK 0xf0
94*4882a593Smuzhiyun #define SSM2518_CHAN_MAP_LEFT_SLOT_OFFSET 0
95*4882a593Smuzhiyun #define SSM2518_CHAN_MAP_LEFT_SLOT_MASK 0x0f
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #define SSM2518_MUTE_CTRL_ANA_GAIN BIT(5)
98*4882a593Smuzhiyun #define SSM2518_MUTE_CTRL_MUTE_MASTER BIT(0)
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #define SSM2518_POWER2_APWDN BIT(0)
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #define SSM2518_DAC_MUTE BIT(6)
103*4882a593Smuzhiyun #define SSM2518_DAC_FS_MASK 0x07
104*4882a593Smuzhiyun #define SSM2518_DAC_FS_8000 0x00
105*4882a593Smuzhiyun #define SSM2518_DAC_FS_16000 0x01
106*4882a593Smuzhiyun #define SSM2518_DAC_FS_32000 0x02
107*4882a593Smuzhiyun #define SSM2518_DAC_FS_64000 0x03
108*4882a593Smuzhiyun #define SSM2518_DAC_FS_128000 0x04
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun struct ssm2518 {
111*4882a593Smuzhiyun struct regmap *regmap;
112*4882a593Smuzhiyun bool right_j;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun unsigned int sysclk;
115*4882a593Smuzhiyun const struct snd_pcm_hw_constraint_list *constraints;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun int enable_gpio;
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static const struct reg_default ssm2518_reg_defaults[] = {
121*4882a593Smuzhiyun { 0x00, 0x05 },
122*4882a593Smuzhiyun { 0x01, 0x00 },
123*4882a593Smuzhiyun { 0x02, 0x02 },
124*4882a593Smuzhiyun { 0x03, 0x00 },
125*4882a593Smuzhiyun { 0x04, 0x10 },
126*4882a593Smuzhiyun { 0x05, 0x40 },
127*4882a593Smuzhiyun { 0x06, 0x40 },
128*4882a593Smuzhiyun { 0x07, 0x81 },
129*4882a593Smuzhiyun { 0x08, 0x0c },
130*4882a593Smuzhiyun { 0x09, 0x99 },
131*4882a593Smuzhiyun { 0x0a, 0x7c },
132*4882a593Smuzhiyun { 0x0b, 0x5b },
133*4882a593Smuzhiyun { 0x0c, 0x57 },
134*4882a593Smuzhiyun { 0x0d, 0x89 },
135*4882a593Smuzhiyun { 0x0e, 0x8c },
136*4882a593Smuzhiyun { 0x0f, 0x77 },
137*4882a593Smuzhiyun { 0x10, 0x26 },
138*4882a593Smuzhiyun { 0x11, 0x1c },
139*4882a593Smuzhiyun { 0x12, 0x97 },
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static const DECLARE_TLV_DB_MINMAX_MUTE(ssm2518_vol_tlv, -7125, 2400);
143*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(ssm2518_compressor_tlv, -3400, 200, 0);
144*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(ssm2518_expander_tlv, -8100, 300, 0);
145*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(ssm2518_noise_gate_tlv, -9600, 300, 0);
146*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(ssm2518_post_drc_tlv, -2400, 300, 0);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(ssm2518_limiter_tlv,
149*4882a593Smuzhiyun 0, 7, TLV_DB_SCALE_ITEM(-2200, 200, 0),
150*4882a593Smuzhiyun 7, 15, TLV_DB_SCALE_ITEM(-800, 100, 0),
151*4882a593Smuzhiyun );
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static const char * const ssm2518_drc_peak_detector_attack_time_text[] = {
154*4882a593Smuzhiyun "0 ms", "0.1 ms", "0.19 ms", "0.37 ms", "0.75 ms", "1.5 ms", "3 ms",
155*4882a593Smuzhiyun "6 ms", "12 ms", "24 ms", "48 ms", "96 ms", "192 ms", "384 ms",
156*4882a593Smuzhiyun "768 ms", "1536 ms",
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static const char * const ssm2518_drc_peak_detector_release_time_text[] = {
160*4882a593Smuzhiyun "0 ms", "1.5 ms", "3 ms", "6 ms", "12 ms", "24 ms", "48 ms", "96 ms",
161*4882a593Smuzhiyun "192 ms", "384 ms", "768 ms", "1536 ms", "3072 ms", "6144 ms",
162*4882a593Smuzhiyun "12288 ms", "24576 ms"
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun static const char * const ssm2518_drc_hold_time_text[] = {
166*4882a593Smuzhiyun "0 ms", "0.67 ms", "1.33 ms", "2.67 ms", "5.33 ms", "10.66 ms",
167*4882a593Smuzhiyun "21.32 ms", "42.64 ms", "85.28 ms", "170.56 ms", "341.12 ms",
168*4882a593Smuzhiyun "682.24 ms", "1364 ms",
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(ssm2518_drc_peak_detector_attack_time_enum,
172*4882a593Smuzhiyun SSM2518_REG_DRC_2, 4, ssm2518_drc_peak_detector_attack_time_text);
173*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(ssm2518_drc_peak_detector_release_time_enum,
174*4882a593Smuzhiyun SSM2518_REG_DRC_2, 0, ssm2518_drc_peak_detector_release_time_text);
175*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(ssm2518_drc_attack_time_enum,
176*4882a593Smuzhiyun SSM2518_REG_DRC_6, 4, ssm2518_drc_peak_detector_attack_time_text);
177*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(ssm2518_drc_decay_time_enum,
178*4882a593Smuzhiyun SSM2518_REG_DRC_6, 0, ssm2518_drc_peak_detector_release_time_text);
179*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(ssm2518_drc_hold_time_enum,
180*4882a593Smuzhiyun SSM2518_REG_DRC_7, 4, ssm2518_drc_hold_time_text);
181*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(ssm2518_drc_noise_gate_hold_time_enum,
182*4882a593Smuzhiyun SSM2518_REG_DRC_7, 0, ssm2518_drc_hold_time_text);
183*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(ssm2518_drc_rms_averaging_time_enum,
184*4882a593Smuzhiyun SSM2518_REG_DRC_9, 0, ssm2518_drc_peak_detector_release_time_text);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static const struct snd_kcontrol_new ssm2518_snd_controls[] = {
187*4882a593Smuzhiyun SOC_SINGLE("Playback De-emphasis Switch", SSM2518_REG_MUTE_CTRL,
188*4882a593Smuzhiyun 4, 1, 0),
189*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Master Playback Volume", SSM2518_REG_LEFT_VOL,
190*4882a593Smuzhiyun SSM2518_REG_RIGHT_VOL, 0, 0xff, 1, ssm2518_vol_tlv),
191*4882a593Smuzhiyun SOC_DOUBLE("Master Playback Switch", SSM2518_REG_MUTE_CTRL, 2, 1, 1, 1),
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun SOC_SINGLE("Amp Low Power Mode Switch", SSM2518_REG_POWER2, 4, 1, 0),
194*4882a593Smuzhiyun SOC_SINGLE("DAC Low Power Mode Switch", SSM2518_REG_POWER2, 3, 1, 0),
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun SOC_SINGLE("DRC Limiter Switch", SSM2518_REG_DRC_1, 5, 1, 0),
197*4882a593Smuzhiyun SOC_SINGLE("DRC Compressor Switch", SSM2518_REG_DRC_1, 4, 1, 0),
198*4882a593Smuzhiyun SOC_SINGLE("DRC Expander Switch", SSM2518_REG_DRC_1, 3, 1, 0),
199*4882a593Smuzhiyun SOC_SINGLE("DRC Noise Gate Switch", SSM2518_REG_DRC_1, 2, 1, 0),
200*4882a593Smuzhiyun SOC_DOUBLE("DRC Switch", SSM2518_REG_DRC_1, 0, 1, 1, 0),
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun SOC_SINGLE_TLV("DRC Limiter Threshold Volume",
203*4882a593Smuzhiyun SSM2518_REG_DRC_3, 4, 15, 1, ssm2518_limiter_tlv),
204*4882a593Smuzhiyun SOC_SINGLE_TLV("DRC Compressor Lower Threshold Volume",
205*4882a593Smuzhiyun SSM2518_REG_DRC_3, 0, 15, 1, ssm2518_compressor_tlv),
206*4882a593Smuzhiyun SOC_SINGLE_TLV("DRC Expander Upper Threshold Volume", SSM2518_REG_DRC_4,
207*4882a593Smuzhiyun 4, 15, 1, ssm2518_expander_tlv),
208*4882a593Smuzhiyun SOC_SINGLE_TLV("DRC Noise Gate Threshold Volume",
209*4882a593Smuzhiyun SSM2518_REG_DRC_4, 0, 15, 1, ssm2518_noise_gate_tlv),
210*4882a593Smuzhiyun SOC_SINGLE_TLV("DRC Upper Output Threshold Volume",
211*4882a593Smuzhiyun SSM2518_REG_DRC_5, 4, 15, 1, ssm2518_limiter_tlv),
212*4882a593Smuzhiyun SOC_SINGLE_TLV("DRC Lower Output Threshold Volume",
213*4882a593Smuzhiyun SSM2518_REG_DRC_5, 0, 15, 1, ssm2518_noise_gate_tlv),
214*4882a593Smuzhiyun SOC_SINGLE_TLV("DRC Post Volume", SSM2518_REG_DRC_8,
215*4882a593Smuzhiyun 2, 15, 1, ssm2518_post_drc_tlv),
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun SOC_ENUM("DRC Peak Detector Attack Time",
218*4882a593Smuzhiyun ssm2518_drc_peak_detector_attack_time_enum),
219*4882a593Smuzhiyun SOC_ENUM("DRC Peak Detector Release Time",
220*4882a593Smuzhiyun ssm2518_drc_peak_detector_release_time_enum),
221*4882a593Smuzhiyun SOC_ENUM("DRC Attack Time", ssm2518_drc_attack_time_enum),
222*4882a593Smuzhiyun SOC_ENUM("DRC Decay Time", ssm2518_drc_decay_time_enum),
223*4882a593Smuzhiyun SOC_ENUM("DRC Hold Time", ssm2518_drc_hold_time_enum),
224*4882a593Smuzhiyun SOC_ENUM("DRC Noise Gate Hold Time",
225*4882a593Smuzhiyun ssm2518_drc_noise_gate_hold_time_enum),
226*4882a593Smuzhiyun SOC_ENUM("DRC RMS Averaging Time", ssm2518_drc_rms_averaging_time_enum),
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun static const struct snd_soc_dapm_widget ssm2518_dapm_widgets[] = {
230*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DACL", "HiFi Playback", SSM2518_REG_POWER2, 1, 1),
231*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DACR", "HiFi Playback", SSM2518_REG_POWER2, 2, 1),
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("OUTL"),
234*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("OUTR"),
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun static const struct snd_soc_dapm_route ssm2518_routes[] = {
238*4882a593Smuzhiyun { "OUTL", NULL, "DACL" },
239*4882a593Smuzhiyun { "OUTR", NULL, "DACR" },
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun struct ssm2518_mcs_lut {
243*4882a593Smuzhiyun unsigned int rate;
244*4882a593Smuzhiyun const unsigned int *sysclks;
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun static const unsigned int ssm2518_sysclks_2048000[] = {
248*4882a593Smuzhiyun 2048000, 4096000, 8192000, 12288000, 16384000, 24576000,
249*4882a593Smuzhiyun 3200000, 6400000, 12800000, 0
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static const unsigned int ssm2518_sysclks_2822000[] = {
253*4882a593Smuzhiyun 2822000, 5644800, 11289600, 16934400, 22579200, 33868800,
254*4882a593Smuzhiyun 4410000, 8820000, 17640000, 0
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun static const unsigned int ssm2518_sysclks_3072000[] = {
258*4882a593Smuzhiyun 3072000, 6144000, 12288000, 16384000, 24576000, 38864000,
259*4882a593Smuzhiyun 4800000, 9600000, 19200000, 0
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun static const struct ssm2518_mcs_lut ssm2518_mcs_lut[] = {
263*4882a593Smuzhiyun { 8000, ssm2518_sysclks_2048000, },
264*4882a593Smuzhiyun { 11025, ssm2518_sysclks_2822000, },
265*4882a593Smuzhiyun { 12000, ssm2518_sysclks_3072000, },
266*4882a593Smuzhiyun { 16000, ssm2518_sysclks_2048000, },
267*4882a593Smuzhiyun { 24000, ssm2518_sysclks_3072000, },
268*4882a593Smuzhiyun { 22050, ssm2518_sysclks_2822000, },
269*4882a593Smuzhiyun { 32000, ssm2518_sysclks_2048000, },
270*4882a593Smuzhiyun { 44100, ssm2518_sysclks_2822000, },
271*4882a593Smuzhiyun { 48000, ssm2518_sysclks_3072000, },
272*4882a593Smuzhiyun { 96000, ssm2518_sysclks_3072000, },
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static const unsigned int ssm2518_rates_2048000[] = {
276*4882a593Smuzhiyun 8000, 16000, 32000,
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list ssm2518_constraints_2048000 = {
280*4882a593Smuzhiyun .list = ssm2518_rates_2048000,
281*4882a593Smuzhiyun .count = ARRAY_SIZE(ssm2518_rates_2048000),
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun static const unsigned int ssm2518_rates_2822000[] = {
285*4882a593Smuzhiyun 11025, 22050, 44100,
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list ssm2518_constraints_2822000 = {
289*4882a593Smuzhiyun .list = ssm2518_rates_2822000,
290*4882a593Smuzhiyun .count = ARRAY_SIZE(ssm2518_rates_2822000),
291*4882a593Smuzhiyun };
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun static const unsigned int ssm2518_rates_3072000[] = {
294*4882a593Smuzhiyun 12000, 24000, 48000, 96000,
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list ssm2518_constraints_3072000 = {
298*4882a593Smuzhiyun .list = ssm2518_rates_3072000,
299*4882a593Smuzhiyun .count = ARRAY_SIZE(ssm2518_rates_3072000),
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun static const unsigned int ssm2518_rates_12288000[] = {
303*4882a593Smuzhiyun 8000, 12000, 16000, 24000, 32000, 48000, 96000,
304*4882a593Smuzhiyun };
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list ssm2518_constraints_12288000 = {
307*4882a593Smuzhiyun .list = ssm2518_rates_12288000,
308*4882a593Smuzhiyun .count = ARRAY_SIZE(ssm2518_rates_12288000),
309*4882a593Smuzhiyun };
310*4882a593Smuzhiyun
ssm2518_lookup_mcs(struct ssm2518 * ssm2518,unsigned int rate)311*4882a593Smuzhiyun static int ssm2518_lookup_mcs(struct ssm2518 *ssm2518,
312*4882a593Smuzhiyun unsigned int rate)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun const unsigned int *sysclks = NULL;
315*4882a593Smuzhiyun int i;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(ssm2518_mcs_lut); i++) {
318*4882a593Smuzhiyun if (ssm2518_mcs_lut[i].rate == rate) {
319*4882a593Smuzhiyun sysclks = ssm2518_mcs_lut[i].sysclks;
320*4882a593Smuzhiyun break;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun if (!sysclks)
325*4882a593Smuzhiyun return -EINVAL;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun for (i = 0; sysclks[i]; i++) {
328*4882a593Smuzhiyun if (sysclks[i] == ssm2518->sysclk)
329*4882a593Smuzhiyun return i;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun return -EINVAL;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
ssm2518_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)335*4882a593Smuzhiyun static int ssm2518_hw_params(struct snd_pcm_substream *substream,
336*4882a593Smuzhiyun struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
339*4882a593Smuzhiyun struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
340*4882a593Smuzhiyun unsigned int rate = params_rate(params);
341*4882a593Smuzhiyun unsigned int ctrl1, ctrl1_mask;
342*4882a593Smuzhiyun int mcs;
343*4882a593Smuzhiyun int ret;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun mcs = ssm2518_lookup_mcs(ssm2518, rate);
346*4882a593Smuzhiyun if (mcs < 0)
347*4882a593Smuzhiyun return mcs;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun ctrl1_mask = SSM2518_SAI_CTRL1_FS_MASK;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun if (rate >= 8000 && rate <= 12000)
352*4882a593Smuzhiyun ctrl1 = SSM2518_SAI_CTRL1_FS_8000_12000;
353*4882a593Smuzhiyun else if (rate >= 16000 && rate <= 24000)
354*4882a593Smuzhiyun ctrl1 = SSM2518_SAI_CTRL1_FS_16000_24000;
355*4882a593Smuzhiyun else if (rate >= 32000 && rate <= 48000)
356*4882a593Smuzhiyun ctrl1 = SSM2518_SAI_CTRL1_FS_32000_48000;
357*4882a593Smuzhiyun else if (rate >= 64000 && rate <= 96000)
358*4882a593Smuzhiyun ctrl1 = SSM2518_SAI_CTRL1_FS_64000_96000;
359*4882a593Smuzhiyun else
360*4882a593Smuzhiyun return -EINVAL;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun if (ssm2518->right_j) {
363*4882a593Smuzhiyun switch (params_width(params)) {
364*4882a593Smuzhiyun case 16:
365*4882a593Smuzhiyun ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_16BIT;
366*4882a593Smuzhiyun break;
367*4882a593Smuzhiyun case 24:
368*4882a593Smuzhiyun ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_24BIT;
369*4882a593Smuzhiyun break;
370*4882a593Smuzhiyun default:
371*4882a593Smuzhiyun return -EINVAL;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun ctrl1_mask |= SSM2518_SAI_CTRL1_FMT_MASK;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun /* Disable auto samplerate detection */
377*4882a593Smuzhiyun ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_CLOCK,
378*4882a593Smuzhiyun SSM2518_CLOCK_ASR, SSM2518_CLOCK_ASR);
379*4882a593Smuzhiyun if (ret < 0)
380*4882a593Smuzhiyun return ret;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL1,
383*4882a593Smuzhiyun ctrl1_mask, ctrl1);
384*4882a593Smuzhiyun if (ret < 0)
385*4882a593Smuzhiyun return ret;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun return regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
388*4882a593Smuzhiyun SSM2518_POWER1_MCS_MASK, mcs << 1);
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
ssm2518_mute(struct snd_soc_dai * dai,int mute,int direction)391*4882a593Smuzhiyun static int ssm2518_mute(struct snd_soc_dai *dai, int mute, int direction)
392*4882a593Smuzhiyun {
393*4882a593Smuzhiyun struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
394*4882a593Smuzhiyun unsigned int val;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun if (mute)
397*4882a593Smuzhiyun val = SSM2518_MUTE_CTRL_MUTE_MASTER;
398*4882a593Smuzhiyun else
399*4882a593Smuzhiyun val = 0;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun return regmap_update_bits(ssm2518->regmap, SSM2518_REG_MUTE_CTRL,
402*4882a593Smuzhiyun SSM2518_MUTE_CTRL_MUTE_MASTER, val);
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
ssm2518_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)405*4882a593Smuzhiyun static int ssm2518_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
408*4882a593Smuzhiyun unsigned int ctrl1 = 0, ctrl2 = 0;
409*4882a593Smuzhiyun bool invert_fclk;
410*4882a593Smuzhiyun int ret;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
413*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
414*4882a593Smuzhiyun break;
415*4882a593Smuzhiyun default:
416*4882a593Smuzhiyun return -EINVAL;
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
420*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
421*4882a593Smuzhiyun invert_fclk = false;
422*4882a593Smuzhiyun break;
423*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
424*4882a593Smuzhiyun ctrl2 |= SSM2518_SAI_CTRL2_BCLK_INVERT;
425*4882a593Smuzhiyun invert_fclk = false;
426*4882a593Smuzhiyun break;
427*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
428*4882a593Smuzhiyun invert_fclk = true;
429*4882a593Smuzhiyun break;
430*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
431*4882a593Smuzhiyun ctrl2 |= SSM2518_SAI_CTRL2_BCLK_INVERT;
432*4882a593Smuzhiyun invert_fclk = true;
433*4882a593Smuzhiyun break;
434*4882a593Smuzhiyun default:
435*4882a593Smuzhiyun return -EINVAL;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun ssm2518->right_j = false;
439*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
440*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
441*4882a593Smuzhiyun ctrl1 |= SSM2518_SAI_CTRL1_FMT_I2S;
442*4882a593Smuzhiyun break;
443*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
444*4882a593Smuzhiyun ctrl1 |= SSM2518_SAI_CTRL1_FMT_LJ;
445*4882a593Smuzhiyun invert_fclk = !invert_fclk;
446*4882a593Smuzhiyun break;
447*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
448*4882a593Smuzhiyun ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_24BIT;
449*4882a593Smuzhiyun ssm2518->right_j = true;
450*4882a593Smuzhiyun invert_fclk = !invert_fclk;
451*4882a593Smuzhiyun break;
452*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
453*4882a593Smuzhiyun ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_PULSE;
454*4882a593Smuzhiyun ctrl1 |= SSM2518_SAI_CTRL1_FMT_I2S;
455*4882a593Smuzhiyun invert_fclk = false;
456*4882a593Smuzhiyun break;
457*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
458*4882a593Smuzhiyun ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_PULSE;
459*4882a593Smuzhiyun ctrl1 |= SSM2518_SAI_CTRL1_FMT_LJ;
460*4882a593Smuzhiyun invert_fclk = false;
461*4882a593Smuzhiyun break;
462*4882a593Smuzhiyun default:
463*4882a593Smuzhiyun return -EINVAL;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun if (invert_fclk)
467*4882a593Smuzhiyun ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_INVERT;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun ret = regmap_write(ssm2518->regmap, SSM2518_REG_SAI_CTRL1, ctrl1);
470*4882a593Smuzhiyun if (ret)
471*4882a593Smuzhiyun return ret;
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun return regmap_write(ssm2518->regmap, SSM2518_REG_SAI_CTRL2, ctrl2);
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun
ssm2518_set_power(struct ssm2518 * ssm2518,bool enable)476*4882a593Smuzhiyun static int ssm2518_set_power(struct ssm2518 *ssm2518, bool enable)
477*4882a593Smuzhiyun {
478*4882a593Smuzhiyun int ret = 0;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun if (!enable) {
481*4882a593Smuzhiyun ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
482*4882a593Smuzhiyun SSM2518_POWER1_SPWDN, SSM2518_POWER1_SPWDN);
483*4882a593Smuzhiyun regcache_mark_dirty(ssm2518->regmap);
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun if (gpio_is_valid(ssm2518->enable_gpio))
487*4882a593Smuzhiyun gpio_set_value(ssm2518->enable_gpio, enable);
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun regcache_cache_only(ssm2518->regmap, !enable);
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun if (enable) {
492*4882a593Smuzhiyun ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
493*4882a593Smuzhiyun SSM2518_POWER1_SPWDN | SSM2518_POWER1_RESET, 0x00);
494*4882a593Smuzhiyun regcache_sync(ssm2518->regmap);
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun return ret;
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
ssm2518_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)500*4882a593Smuzhiyun static int ssm2518_set_bias_level(struct snd_soc_component *component,
501*4882a593Smuzhiyun enum snd_soc_bias_level level)
502*4882a593Smuzhiyun {
503*4882a593Smuzhiyun struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
504*4882a593Smuzhiyun int ret = 0;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun switch (level) {
507*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
508*4882a593Smuzhiyun break;
509*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
510*4882a593Smuzhiyun break;
511*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
512*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
513*4882a593Smuzhiyun ret = ssm2518_set_power(ssm2518, true);
514*4882a593Smuzhiyun break;
515*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
516*4882a593Smuzhiyun ret = ssm2518_set_power(ssm2518, false);
517*4882a593Smuzhiyun break;
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun return ret;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
ssm2518_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int width)523*4882a593Smuzhiyun static int ssm2518_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
524*4882a593Smuzhiyun unsigned int rx_mask, int slots, int width)
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
527*4882a593Smuzhiyun unsigned int ctrl1, ctrl2;
528*4882a593Smuzhiyun int left_slot, right_slot;
529*4882a593Smuzhiyun int ret;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun if (slots == 0)
532*4882a593Smuzhiyun return regmap_update_bits(ssm2518->regmap,
533*4882a593Smuzhiyun SSM2518_REG_SAI_CTRL1, SSM2518_SAI_CTRL1_SAI_MASK,
534*4882a593Smuzhiyun SSM2518_SAI_CTRL1_SAI_I2S);
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun if (tx_mask == 0 || rx_mask != 0)
537*4882a593Smuzhiyun return -EINVAL;
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun if (slots == 1) {
540*4882a593Smuzhiyun if (tx_mask != 1)
541*4882a593Smuzhiyun return -EINVAL;
542*4882a593Smuzhiyun left_slot = 0;
543*4882a593Smuzhiyun right_slot = 0;
544*4882a593Smuzhiyun } else {
545*4882a593Smuzhiyun /* We assume the left channel < right channel */
546*4882a593Smuzhiyun left_slot = __ffs(tx_mask);
547*4882a593Smuzhiyun tx_mask &= ~(1 << left_slot);
548*4882a593Smuzhiyun if (tx_mask == 0) {
549*4882a593Smuzhiyun right_slot = left_slot;
550*4882a593Smuzhiyun } else {
551*4882a593Smuzhiyun right_slot = __ffs(tx_mask);
552*4882a593Smuzhiyun tx_mask &= ~(1 << right_slot);
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun if (tx_mask != 0 || left_slot >= slots || right_slot >= slots)
557*4882a593Smuzhiyun return -EINVAL;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun switch (width) {
560*4882a593Smuzhiyun case 16:
561*4882a593Smuzhiyun ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_16;
562*4882a593Smuzhiyun break;
563*4882a593Smuzhiyun case 24:
564*4882a593Smuzhiyun ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_24;
565*4882a593Smuzhiyun break;
566*4882a593Smuzhiyun case 32:
567*4882a593Smuzhiyun ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_32;
568*4882a593Smuzhiyun break;
569*4882a593Smuzhiyun default:
570*4882a593Smuzhiyun return -EINVAL;
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun switch (slots) {
574*4882a593Smuzhiyun case 1:
575*4882a593Smuzhiyun ctrl1 = SSM2518_SAI_CTRL1_SAI_MONO;
576*4882a593Smuzhiyun break;
577*4882a593Smuzhiyun case 2:
578*4882a593Smuzhiyun ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_2;
579*4882a593Smuzhiyun break;
580*4882a593Smuzhiyun case 4:
581*4882a593Smuzhiyun ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_4;
582*4882a593Smuzhiyun break;
583*4882a593Smuzhiyun case 8:
584*4882a593Smuzhiyun ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_8;
585*4882a593Smuzhiyun break;
586*4882a593Smuzhiyun case 16:
587*4882a593Smuzhiyun ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_16;
588*4882a593Smuzhiyun break;
589*4882a593Smuzhiyun default:
590*4882a593Smuzhiyun return -EINVAL;
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun ret = regmap_write(ssm2518->regmap, SSM2518_REG_CHAN_MAP,
594*4882a593Smuzhiyun (left_slot << SSM2518_CHAN_MAP_LEFT_SLOT_OFFSET) |
595*4882a593Smuzhiyun (right_slot << SSM2518_CHAN_MAP_RIGHT_SLOT_OFFSET));
596*4882a593Smuzhiyun if (ret)
597*4882a593Smuzhiyun return ret;
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL1,
600*4882a593Smuzhiyun SSM2518_SAI_CTRL1_SAI_MASK, ctrl1);
601*4882a593Smuzhiyun if (ret)
602*4882a593Smuzhiyun return ret;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun return regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL2,
605*4882a593Smuzhiyun SSM2518_SAI_CTRL2_SLOT_WIDTH_MASK, ctrl2);
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
ssm2518_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)608*4882a593Smuzhiyun static int ssm2518_startup(struct snd_pcm_substream *substream,
609*4882a593Smuzhiyun struct snd_soc_dai *dai)
610*4882a593Smuzhiyun {
611*4882a593Smuzhiyun struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun if (ssm2518->constraints)
614*4882a593Smuzhiyun snd_pcm_hw_constraint_list(substream->runtime, 0,
615*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE, ssm2518->constraints);
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun return 0;
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun #define SSM2518_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
621*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32)
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun static const struct snd_soc_dai_ops ssm2518_dai_ops = {
624*4882a593Smuzhiyun .startup = ssm2518_startup,
625*4882a593Smuzhiyun .hw_params = ssm2518_hw_params,
626*4882a593Smuzhiyun .mute_stream = ssm2518_mute,
627*4882a593Smuzhiyun .set_fmt = ssm2518_set_dai_fmt,
628*4882a593Smuzhiyun .set_tdm_slot = ssm2518_set_tdm_slot,
629*4882a593Smuzhiyun .no_capture_mute = 1,
630*4882a593Smuzhiyun };
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun static struct snd_soc_dai_driver ssm2518_dai = {
633*4882a593Smuzhiyun .name = "ssm2518-hifi",
634*4882a593Smuzhiyun .playback = {
635*4882a593Smuzhiyun .stream_name = "Playback",
636*4882a593Smuzhiyun .channels_min = 2,
637*4882a593Smuzhiyun .channels_max = 2,
638*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_96000,
639*4882a593Smuzhiyun .formats = SSM2518_FORMATS,
640*4882a593Smuzhiyun },
641*4882a593Smuzhiyun .ops = &ssm2518_dai_ops,
642*4882a593Smuzhiyun };
643*4882a593Smuzhiyun
ssm2518_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)644*4882a593Smuzhiyun static int ssm2518_set_sysclk(struct snd_soc_component *component, int clk_id,
645*4882a593Smuzhiyun int source, unsigned int freq, int dir)
646*4882a593Smuzhiyun {
647*4882a593Smuzhiyun struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
648*4882a593Smuzhiyun unsigned int val;
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun if (clk_id != SSM2518_SYSCLK)
651*4882a593Smuzhiyun return -EINVAL;
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun switch (source) {
654*4882a593Smuzhiyun case SSM2518_SYSCLK_SRC_MCLK:
655*4882a593Smuzhiyun val = 0;
656*4882a593Smuzhiyun break;
657*4882a593Smuzhiyun case SSM2518_SYSCLK_SRC_BCLK:
658*4882a593Smuzhiyun /* In this case the bitclock is used as the system clock, and
659*4882a593Smuzhiyun * the bitclock signal needs to be connected to the MCLK pin and
660*4882a593Smuzhiyun * the BCLK pin is left unconnected */
661*4882a593Smuzhiyun val = SSM2518_POWER1_NO_BCLK;
662*4882a593Smuzhiyun break;
663*4882a593Smuzhiyun default:
664*4882a593Smuzhiyun return -EINVAL;
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun switch (freq) {
668*4882a593Smuzhiyun case 0:
669*4882a593Smuzhiyun ssm2518->constraints = NULL;
670*4882a593Smuzhiyun break;
671*4882a593Smuzhiyun case 2048000:
672*4882a593Smuzhiyun case 4096000:
673*4882a593Smuzhiyun case 8192000:
674*4882a593Smuzhiyun case 3200000:
675*4882a593Smuzhiyun case 6400000:
676*4882a593Smuzhiyun case 12800000:
677*4882a593Smuzhiyun ssm2518->constraints = &ssm2518_constraints_2048000;
678*4882a593Smuzhiyun break;
679*4882a593Smuzhiyun case 2822000:
680*4882a593Smuzhiyun case 5644800:
681*4882a593Smuzhiyun case 11289600:
682*4882a593Smuzhiyun case 16934400:
683*4882a593Smuzhiyun case 22579200:
684*4882a593Smuzhiyun case 33868800:
685*4882a593Smuzhiyun case 4410000:
686*4882a593Smuzhiyun case 8820000:
687*4882a593Smuzhiyun case 17640000:
688*4882a593Smuzhiyun ssm2518->constraints = &ssm2518_constraints_2822000;
689*4882a593Smuzhiyun break;
690*4882a593Smuzhiyun case 3072000:
691*4882a593Smuzhiyun case 6144000:
692*4882a593Smuzhiyun case 38864000:
693*4882a593Smuzhiyun case 4800000:
694*4882a593Smuzhiyun case 9600000:
695*4882a593Smuzhiyun case 19200000:
696*4882a593Smuzhiyun ssm2518->constraints = &ssm2518_constraints_3072000;
697*4882a593Smuzhiyun break;
698*4882a593Smuzhiyun case 12288000:
699*4882a593Smuzhiyun case 16384000:
700*4882a593Smuzhiyun case 24576000:
701*4882a593Smuzhiyun ssm2518->constraints = &ssm2518_constraints_12288000;
702*4882a593Smuzhiyun break;
703*4882a593Smuzhiyun default:
704*4882a593Smuzhiyun return -EINVAL;
705*4882a593Smuzhiyun }
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun ssm2518->sysclk = freq;
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun return regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
710*4882a593Smuzhiyun SSM2518_POWER1_NO_BCLK, val);
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun static const struct snd_soc_component_driver ssm2518_component_driver = {
714*4882a593Smuzhiyun .set_bias_level = ssm2518_set_bias_level,
715*4882a593Smuzhiyun .set_sysclk = ssm2518_set_sysclk,
716*4882a593Smuzhiyun .controls = ssm2518_snd_controls,
717*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(ssm2518_snd_controls),
718*4882a593Smuzhiyun .dapm_widgets = ssm2518_dapm_widgets,
719*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(ssm2518_dapm_widgets),
720*4882a593Smuzhiyun .dapm_routes = ssm2518_routes,
721*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(ssm2518_routes),
722*4882a593Smuzhiyun .use_pmdown_time = 1,
723*4882a593Smuzhiyun .endianness = 1,
724*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
725*4882a593Smuzhiyun };
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun static const struct regmap_config ssm2518_regmap_config = {
728*4882a593Smuzhiyun .val_bits = 8,
729*4882a593Smuzhiyun .reg_bits = 8,
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun .max_register = SSM2518_REG_DRC_9,
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
734*4882a593Smuzhiyun .reg_defaults = ssm2518_reg_defaults,
735*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(ssm2518_reg_defaults),
736*4882a593Smuzhiyun };
737*4882a593Smuzhiyun
ssm2518_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)738*4882a593Smuzhiyun static int ssm2518_i2c_probe(struct i2c_client *i2c,
739*4882a593Smuzhiyun const struct i2c_device_id *id)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun struct ssm2518_platform_data *pdata = i2c->dev.platform_data;
742*4882a593Smuzhiyun struct ssm2518 *ssm2518;
743*4882a593Smuzhiyun int ret;
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun ssm2518 = devm_kzalloc(&i2c->dev, sizeof(*ssm2518), GFP_KERNEL);
746*4882a593Smuzhiyun if (ssm2518 == NULL)
747*4882a593Smuzhiyun return -ENOMEM;
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun if (pdata) {
750*4882a593Smuzhiyun ssm2518->enable_gpio = pdata->enable_gpio;
751*4882a593Smuzhiyun } else if (i2c->dev.of_node) {
752*4882a593Smuzhiyun ssm2518->enable_gpio = of_get_gpio(i2c->dev.of_node, 0);
753*4882a593Smuzhiyun if (ssm2518->enable_gpio < 0 && ssm2518->enable_gpio != -ENOENT)
754*4882a593Smuzhiyun return ssm2518->enable_gpio;
755*4882a593Smuzhiyun } else {
756*4882a593Smuzhiyun ssm2518->enable_gpio = -1;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun if (gpio_is_valid(ssm2518->enable_gpio)) {
760*4882a593Smuzhiyun ret = devm_gpio_request_one(&i2c->dev, ssm2518->enable_gpio,
761*4882a593Smuzhiyun GPIOF_OUT_INIT_HIGH, "SSM2518 nSD");
762*4882a593Smuzhiyun if (ret)
763*4882a593Smuzhiyun return ret;
764*4882a593Smuzhiyun }
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun i2c_set_clientdata(i2c, ssm2518);
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun ssm2518->regmap = devm_regmap_init_i2c(i2c, &ssm2518_regmap_config);
769*4882a593Smuzhiyun if (IS_ERR(ssm2518->regmap))
770*4882a593Smuzhiyun return PTR_ERR(ssm2518->regmap);
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun /*
773*4882a593Smuzhiyun * The reset bit is obviously volatile, but we need to be able to cache
774*4882a593Smuzhiyun * the other bits in the register, so we can't just mark the whole
775*4882a593Smuzhiyun * register as volatile. Since this is the only place where we'll ever
776*4882a593Smuzhiyun * touch the reset bit just bypass the cache for this operation.
777*4882a593Smuzhiyun */
778*4882a593Smuzhiyun regcache_cache_bypass(ssm2518->regmap, true);
779*4882a593Smuzhiyun ret = regmap_write(ssm2518->regmap, SSM2518_REG_POWER1,
780*4882a593Smuzhiyun SSM2518_POWER1_RESET);
781*4882a593Smuzhiyun regcache_cache_bypass(ssm2518->regmap, false);
782*4882a593Smuzhiyun if (ret)
783*4882a593Smuzhiyun return ret;
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER2,
786*4882a593Smuzhiyun SSM2518_POWER2_APWDN, 0x00);
787*4882a593Smuzhiyun if (ret)
788*4882a593Smuzhiyun return ret;
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun ret = ssm2518_set_power(ssm2518, false);
791*4882a593Smuzhiyun if (ret)
792*4882a593Smuzhiyun return ret;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun return devm_snd_soc_register_component(&i2c->dev,
795*4882a593Smuzhiyun &ssm2518_component_driver,
796*4882a593Smuzhiyun &ssm2518_dai, 1);
797*4882a593Smuzhiyun }
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun #ifdef CONFIG_OF
800*4882a593Smuzhiyun static const struct of_device_id ssm2518_dt_ids[] = {
801*4882a593Smuzhiyun { .compatible = "adi,ssm2518", },
802*4882a593Smuzhiyun { }
803*4882a593Smuzhiyun };
804*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ssm2518_dt_ids);
805*4882a593Smuzhiyun #endif
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun static const struct i2c_device_id ssm2518_i2c_ids[] = {
808*4882a593Smuzhiyun { "ssm2518", 0 },
809*4882a593Smuzhiyun { }
810*4882a593Smuzhiyun };
811*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ssm2518_i2c_ids);
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun static struct i2c_driver ssm2518_driver = {
814*4882a593Smuzhiyun .driver = {
815*4882a593Smuzhiyun .name = "ssm2518",
816*4882a593Smuzhiyun .of_match_table = of_match_ptr(ssm2518_dt_ids),
817*4882a593Smuzhiyun },
818*4882a593Smuzhiyun .probe = ssm2518_i2c_probe,
819*4882a593Smuzhiyun .id_table = ssm2518_i2c_ids,
820*4882a593Smuzhiyun };
821*4882a593Smuzhiyun module_i2c_driver(ssm2518_driver);
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC SSM2518 driver");
824*4882a593Smuzhiyun MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
825*4882a593Smuzhiyun MODULE_LICENSE("GPL");
826