1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * sgtl5000.h - SGTL5000 audio codec interface 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2010-2011 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SGTL5000_H 9*4882a593Smuzhiyun #define _SGTL5000_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Registers addresses 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define SGTL5000_CHIP_ID 0x0000 15*4882a593Smuzhiyun #define SGTL5000_CHIP_DIG_POWER 0x0002 16*4882a593Smuzhiyun #define SGTL5000_CHIP_CLK_CTRL 0x0004 17*4882a593Smuzhiyun #define SGTL5000_CHIP_I2S_CTRL 0x0006 18*4882a593Smuzhiyun #define SGTL5000_CHIP_SSS_CTRL 0x000a 19*4882a593Smuzhiyun #define SGTL5000_CHIP_ADCDAC_CTRL 0x000e 20*4882a593Smuzhiyun #define SGTL5000_CHIP_DAC_VOL 0x0010 21*4882a593Smuzhiyun #define SGTL5000_CHIP_PAD_STRENGTH 0x0014 22*4882a593Smuzhiyun #define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020 23*4882a593Smuzhiyun #define SGTL5000_CHIP_ANA_HP_CTRL 0x0022 24*4882a593Smuzhiyun #define SGTL5000_CHIP_ANA_CTRL 0x0024 25*4882a593Smuzhiyun #define SGTL5000_CHIP_LINREG_CTRL 0x0026 26*4882a593Smuzhiyun #define SGTL5000_CHIP_REF_CTRL 0x0028 27*4882a593Smuzhiyun #define SGTL5000_CHIP_MIC_CTRL 0x002a 28*4882a593Smuzhiyun #define SGTL5000_CHIP_LINE_OUT_CTRL 0x002c 29*4882a593Smuzhiyun #define SGTL5000_CHIP_LINE_OUT_VOL 0x002e 30*4882a593Smuzhiyun #define SGTL5000_CHIP_ANA_POWER 0x0030 31*4882a593Smuzhiyun #define SGTL5000_CHIP_PLL_CTRL 0x0032 32*4882a593Smuzhiyun #define SGTL5000_CHIP_CLK_TOP_CTRL 0x0034 33*4882a593Smuzhiyun #define SGTL5000_CHIP_ANA_STATUS 0x0036 34*4882a593Smuzhiyun #define SGTL5000_CHIP_SHORT_CTRL 0x003c 35*4882a593Smuzhiyun #define SGTL5000_CHIP_ANA_TEST2 0x003a 36*4882a593Smuzhiyun #define SGTL5000_DAP_CTRL 0x0100 37*4882a593Smuzhiyun #define SGTL5000_DAP_PEQ 0x0102 38*4882a593Smuzhiyun #define SGTL5000_DAP_BASS_ENHANCE 0x0104 39*4882a593Smuzhiyun #define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106 40*4882a593Smuzhiyun #define SGTL5000_DAP_AUDIO_EQ 0x0108 41*4882a593Smuzhiyun #define SGTL5000_DAP_SURROUND 0x010a 42*4882a593Smuzhiyun #define SGTL5000_DAP_FLT_COEF_ACCESS 0x010c 43*4882a593Smuzhiyun #define SGTL5000_DAP_COEF_WR_B0_MSB 0x010e 44*4882a593Smuzhiyun #define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110 45*4882a593Smuzhiyun #define SGTL5000_DAP_EQ_BASS_BAND0 0x0116 46*4882a593Smuzhiyun #define SGTL5000_DAP_EQ_BASS_BAND1 0x0118 47*4882a593Smuzhiyun #define SGTL5000_DAP_EQ_BASS_BAND2 0x011a 48*4882a593Smuzhiyun #define SGTL5000_DAP_EQ_BASS_BAND3 0x011c 49*4882a593Smuzhiyun #define SGTL5000_DAP_EQ_BASS_BAND4 0x011e 50*4882a593Smuzhiyun #define SGTL5000_DAP_MAIN_CHAN 0x0120 51*4882a593Smuzhiyun #define SGTL5000_DAP_MIX_CHAN 0x0122 52*4882a593Smuzhiyun #define SGTL5000_DAP_AVC_CTRL 0x0124 53*4882a593Smuzhiyun #define SGTL5000_DAP_AVC_THRESHOLD 0x0126 54*4882a593Smuzhiyun #define SGTL5000_DAP_AVC_ATTACK 0x0128 55*4882a593Smuzhiyun #define SGTL5000_DAP_AVC_DECAY 0x012a 56*4882a593Smuzhiyun #define SGTL5000_DAP_COEF_WR_B1_MSB 0x012c 57*4882a593Smuzhiyun #define SGTL5000_DAP_COEF_WR_B1_LSB 0x012e 58*4882a593Smuzhiyun #define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130 59*4882a593Smuzhiyun #define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132 60*4882a593Smuzhiyun #define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134 61*4882a593Smuzhiyun #define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136 62*4882a593Smuzhiyun #define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138 63*4882a593Smuzhiyun #define SGTL5000_DAP_COEF_WR_A2_LSB 0x013a 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * Field Definitions. 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * SGTL5000_CHIP_ID 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun #define SGTL5000_PARTID_MASK 0xff00 73*4882a593Smuzhiyun #define SGTL5000_PARTID_SHIFT 8 74*4882a593Smuzhiyun #define SGTL5000_PARTID_WIDTH 8 75*4882a593Smuzhiyun #define SGTL5000_PARTID_PART_ID 0xa0 76*4882a593Smuzhiyun #define SGTL5000_REVID_MASK 0x00ff 77*4882a593Smuzhiyun #define SGTL5000_REVID_SHIFT 0 78*4882a593Smuzhiyun #define SGTL5000_REVID_WIDTH 8 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* 81*4882a593Smuzhiyun * SGTL5000_CHIP_DIG_POWER 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun #define SGTL5000_DIG_POWER_DEFAULT 0x0000 84*4882a593Smuzhiyun #define SGTL5000_ADC_EN 0x0040 85*4882a593Smuzhiyun #define SGTL5000_DAC_EN 0x0020 86*4882a593Smuzhiyun #define SGTL5000_DAP_POWERUP 0x0010 87*4882a593Smuzhiyun #define SGTL5000_I2S_OUT_POWERUP 0x0002 88*4882a593Smuzhiyun #define SGTL5000_I2S_IN_POWERUP 0x0001 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* 91*4882a593Smuzhiyun * SGTL5000_CHIP_CLK_CTRL 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun #define SGTL5000_CHIP_CLK_CTRL_DEFAULT 0x0008 94*4882a593Smuzhiyun #define SGTL5000_RATE_MODE_MASK 0x0030 95*4882a593Smuzhiyun #define SGTL5000_RATE_MODE_SHIFT 4 96*4882a593Smuzhiyun #define SGTL5000_RATE_MODE_WIDTH 2 97*4882a593Smuzhiyun #define SGTL5000_RATE_MODE_DIV_1 0 98*4882a593Smuzhiyun #define SGTL5000_RATE_MODE_DIV_2 1 99*4882a593Smuzhiyun #define SGTL5000_RATE_MODE_DIV_4 2 100*4882a593Smuzhiyun #define SGTL5000_RATE_MODE_DIV_6 3 101*4882a593Smuzhiyun #define SGTL5000_SYS_FS_MASK 0x000c 102*4882a593Smuzhiyun #define SGTL5000_SYS_FS_SHIFT 2 103*4882a593Smuzhiyun #define SGTL5000_SYS_FS_WIDTH 2 104*4882a593Smuzhiyun #define SGTL5000_SYS_FS_32k 0x0 105*4882a593Smuzhiyun #define SGTL5000_SYS_FS_44_1k 0x1 106*4882a593Smuzhiyun #define SGTL5000_SYS_FS_48k 0x2 107*4882a593Smuzhiyun #define SGTL5000_SYS_FS_96k 0x3 108*4882a593Smuzhiyun #define SGTL5000_MCLK_FREQ_MASK 0x0003 109*4882a593Smuzhiyun #define SGTL5000_MCLK_FREQ_SHIFT 0 110*4882a593Smuzhiyun #define SGTL5000_MCLK_FREQ_WIDTH 2 111*4882a593Smuzhiyun #define SGTL5000_MCLK_FREQ_256FS 0x0 112*4882a593Smuzhiyun #define SGTL5000_MCLK_FREQ_384FS 0x1 113*4882a593Smuzhiyun #define SGTL5000_MCLK_FREQ_512FS 0x2 114*4882a593Smuzhiyun #define SGTL5000_MCLK_FREQ_PLL 0x3 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* 117*4882a593Smuzhiyun * SGTL5000_CHIP_I2S_CTRL 118*4882a593Smuzhiyun */ 119*4882a593Smuzhiyun #define SGTL5000_I2S_SCLKFREQ_MASK 0x0100 120*4882a593Smuzhiyun #define SGTL5000_I2S_SCLKFREQ_SHIFT 8 121*4882a593Smuzhiyun #define SGTL5000_I2S_SCLKFREQ_WIDTH 1 122*4882a593Smuzhiyun #define SGTL5000_I2S_SCLKFREQ_64FS 0x0 123*4882a593Smuzhiyun #define SGTL5000_I2S_SCLKFREQ_32FS 0x1 /* Not for RJ mode */ 124*4882a593Smuzhiyun #define SGTL5000_I2S_MASTER 0x0080 125*4882a593Smuzhiyun #define SGTL5000_I2S_SCLK_INV 0x0040 126*4882a593Smuzhiyun #define SGTL5000_I2S_DLEN_MASK 0x0030 127*4882a593Smuzhiyun #define SGTL5000_I2S_DLEN_SHIFT 4 128*4882a593Smuzhiyun #define SGTL5000_I2S_DLEN_WIDTH 2 129*4882a593Smuzhiyun #define SGTL5000_I2S_DLEN_32 0x0 130*4882a593Smuzhiyun #define SGTL5000_I2S_DLEN_24 0x1 131*4882a593Smuzhiyun #define SGTL5000_I2S_DLEN_20 0x2 132*4882a593Smuzhiyun #define SGTL5000_I2S_DLEN_16 0x3 133*4882a593Smuzhiyun #define SGTL5000_I2S_MODE_MASK 0x000c 134*4882a593Smuzhiyun #define SGTL5000_I2S_MODE_SHIFT 2 135*4882a593Smuzhiyun #define SGTL5000_I2S_MODE_WIDTH 2 136*4882a593Smuzhiyun #define SGTL5000_I2S_MODE_I2S_LJ 0x0 137*4882a593Smuzhiyun #define SGTL5000_I2S_MODE_RJ 0x1 138*4882a593Smuzhiyun #define SGTL5000_I2S_MODE_PCM 0x2 139*4882a593Smuzhiyun #define SGTL5000_I2S_LRALIGN 0x0002 140*4882a593Smuzhiyun #define SGTL5000_I2S_LRPOL 0x0001 /* set for which mode */ 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* 143*4882a593Smuzhiyun * SGTL5000_CHIP_SSS_CTRL 144*4882a593Smuzhiyun */ 145*4882a593Smuzhiyun #define SGTL5000_DAP_MIX_LRSWAP 0x4000 146*4882a593Smuzhiyun #define SGTL5000_DAP_LRSWAP 0x2000 147*4882a593Smuzhiyun #define SGTL5000_DAC_LRSWAP 0x1000 148*4882a593Smuzhiyun #define SGTL5000_I2S_OUT_LRSWAP 0x0400 149*4882a593Smuzhiyun #define SGTL5000_DAP_MIX_SEL_MASK 0x0300 150*4882a593Smuzhiyun #define SGTL5000_DAP_MIX_SEL_SHIFT 8 151*4882a593Smuzhiyun #define SGTL5000_DAP_MIX_SEL_WIDTH 2 152*4882a593Smuzhiyun #define SGTL5000_DAP_MIX_SEL_ADC 0x0 153*4882a593Smuzhiyun #define SGTL5000_DAP_MIX_SEL_I2S_IN 0x1 154*4882a593Smuzhiyun #define SGTL5000_DAP_SEL_MASK 0x00c0 155*4882a593Smuzhiyun #define SGTL5000_DAP_SEL_SHIFT 6 156*4882a593Smuzhiyun #define SGTL5000_DAP_SEL_WIDTH 2 157*4882a593Smuzhiyun #define SGTL5000_DAP_SEL_ADC 0x0 158*4882a593Smuzhiyun #define SGTL5000_DAP_SEL_I2S_IN 0x1 159*4882a593Smuzhiyun #define SGTL5000_DAC_SEL_MASK 0x0030 160*4882a593Smuzhiyun #define SGTL5000_DAC_SEL_SHIFT 4 161*4882a593Smuzhiyun #define SGTL5000_DAC_SEL_WIDTH 2 162*4882a593Smuzhiyun #define SGTL5000_DAC_SEL_ADC 0x0 163*4882a593Smuzhiyun #define SGTL5000_DAC_SEL_I2S_IN 0x1 164*4882a593Smuzhiyun #define SGTL5000_DAC_SEL_DAP 0x3 165*4882a593Smuzhiyun #define SGTL5000_I2S_OUT_SEL_MASK 0x0003 166*4882a593Smuzhiyun #define SGTL5000_I2S_OUT_SEL_SHIFT 0 167*4882a593Smuzhiyun #define SGTL5000_I2S_OUT_SEL_WIDTH 2 168*4882a593Smuzhiyun #define SGTL5000_I2S_OUT_SEL_ADC 0x0 169*4882a593Smuzhiyun #define SGTL5000_I2S_OUT_SEL_I2S_IN 0x1 170*4882a593Smuzhiyun #define SGTL5000_I2S_OUT_SEL_DAP 0x3 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* 173*4882a593Smuzhiyun * SGTL5000_CHIP_ADCDAC_CTRL 174*4882a593Smuzhiyun */ 175*4882a593Smuzhiyun #define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000 176*4882a593Smuzhiyun #define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000 177*4882a593Smuzhiyun #define SGTL5000_DAC_VOL_RAMP_EN 0x0200 178*4882a593Smuzhiyun #define SGTL5000_DAC_VOL_RAMP_EXPO 0x0100 179*4882a593Smuzhiyun #define SGTL5000_DAC_MUTE_RIGHT 0x0008 180*4882a593Smuzhiyun #define SGTL5000_DAC_MUTE_LEFT 0x0004 181*4882a593Smuzhiyun #define SGTL5000_ADC_HPF_FREEZE 0x0002 182*4882a593Smuzhiyun #define SGTL5000_ADC_HPF_BYPASS 0x0001 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* 185*4882a593Smuzhiyun * SGTL5000_CHIP_DAC_VOL 186*4882a593Smuzhiyun */ 187*4882a593Smuzhiyun #define SGTL5000_DAC_VOL_RIGHT_MASK 0xff00 188*4882a593Smuzhiyun #define SGTL5000_DAC_VOL_RIGHT_SHIFT 8 189*4882a593Smuzhiyun #define SGTL5000_DAC_VOL_RIGHT_WIDTH 8 190*4882a593Smuzhiyun #define SGTL5000_DAC_VOL_LEFT_MASK 0x00ff 191*4882a593Smuzhiyun #define SGTL5000_DAC_VOL_LEFT_SHIFT 0 192*4882a593Smuzhiyun #define SGTL5000_DAC_VOL_LEFT_WIDTH 8 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* 195*4882a593Smuzhiyun * SGTL5000_CHIP_PAD_STRENGTH 196*4882a593Smuzhiyun */ 197*4882a593Smuzhiyun #define SGTL5000_PAD_I2S_LRCLK_MASK 0x0300 198*4882a593Smuzhiyun #define SGTL5000_PAD_I2S_LRCLK_SHIFT 8 199*4882a593Smuzhiyun #define SGTL5000_PAD_I2S_LRCLK_WIDTH 2 200*4882a593Smuzhiyun #define SGTL5000_PAD_I2S_SCLK_MASK 0x00c0 201*4882a593Smuzhiyun #define SGTL5000_PAD_I2S_SCLK_SHIFT 6 202*4882a593Smuzhiyun #define SGTL5000_PAD_I2S_SCLK_WIDTH 2 203*4882a593Smuzhiyun #define SGTL5000_PAD_I2S_DOUT_MASK 0x0030 204*4882a593Smuzhiyun #define SGTL5000_PAD_I2S_DOUT_SHIFT 4 205*4882a593Smuzhiyun #define SGTL5000_PAD_I2S_DOUT_WIDTH 2 206*4882a593Smuzhiyun #define SGTL5000_PAD_I2C_SDA_MASK 0x000c 207*4882a593Smuzhiyun #define SGTL5000_PAD_I2C_SDA_SHIFT 2 208*4882a593Smuzhiyun #define SGTL5000_PAD_I2C_SDA_WIDTH 2 209*4882a593Smuzhiyun #define SGTL5000_PAD_I2C_SCL_MASK 0x0003 210*4882a593Smuzhiyun #define SGTL5000_PAD_I2C_SCL_SHIFT 0 211*4882a593Smuzhiyun #define SGTL5000_PAD_I2C_SCL_WIDTH 2 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun /* 214*4882a593Smuzhiyun * SGTL5000_CHIP_ANA_ADC_CTRL 215*4882a593Smuzhiyun */ 216*4882a593Smuzhiyun #define SGTL5000_ADC_VOL_M6DB 0x0100 217*4882a593Smuzhiyun #define SGTL5000_ADC_VOL_RIGHT_MASK 0x00f0 218*4882a593Smuzhiyun #define SGTL5000_ADC_VOL_RIGHT_SHIFT 4 219*4882a593Smuzhiyun #define SGTL5000_ADC_VOL_RIGHT_WIDTH 4 220*4882a593Smuzhiyun #define SGTL5000_ADC_VOL_LEFT_MASK 0x000f 221*4882a593Smuzhiyun #define SGTL5000_ADC_VOL_LEFT_SHIFT 0 222*4882a593Smuzhiyun #define SGTL5000_ADC_VOL_LEFT_WIDTH 4 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* 225*4882a593Smuzhiyun * SGTL5000_CHIP_ANA_HP_CTRL 226*4882a593Smuzhiyun */ 227*4882a593Smuzhiyun #define SGTL5000_HP_VOL_RIGHT_MASK 0x7f00 228*4882a593Smuzhiyun #define SGTL5000_HP_VOL_RIGHT_SHIFT 8 229*4882a593Smuzhiyun #define SGTL5000_HP_VOL_RIGHT_WIDTH 7 230*4882a593Smuzhiyun #define SGTL5000_HP_VOL_LEFT_MASK 0x007f 231*4882a593Smuzhiyun #define SGTL5000_HP_VOL_LEFT_SHIFT 0 232*4882a593Smuzhiyun #define SGTL5000_HP_VOL_LEFT_WIDTH 7 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* 235*4882a593Smuzhiyun * SGTL5000_CHIP_ANA_CTRL 236*4882a593Smuzhiyun */ 237*4882a593Smuzhiyun #define SGTL5000_CHIP_ANA_CTRL_DEFAULT 0x0133 238*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_MUTE 0x0100 239*4882a593Smuzhiyun #define SGTL5000_HP_SEL_MASK 0x0040 240*4882a593Smuzhiyun #define SGTL5000_HP_SEL_SHIFT 6 241*4882a593Smuzhiyun #define SGTL5000_HP_SEL_WIDTH 1 242*4882a593Smuzhiyun #define SGTL5000_HP_SEL_DAC 0x0 243*4882a593Smuzhiyun #define SGTL5000_HP_SEL_LINE_IN 0x1 244*4882a593Smuzhiyun #define SGTL5000_HP_ZCD_EN 0x0020 245*4882a593Smuzhiyun #define SGTL5000_HP_MUTE 0x0010 246*4882a593Smuzhiyun #define SGTL5000_ADC_SEL_MASK 0x0004 247*4882a593Smuzhiyun #define SGTL5000_ADC_SEL_SHIFT 2 248*4882a593Smuzhiyun #define SGTL5000_ADC_SEL_WIDTH 1 249*4882a593Smuzhiyun #define SGTL5000_ADC_SEL_MIC 0x0 250*4882a593Smuzhiyun #define SGTL5000_ADC_SEL_LINE_IN 0x1 251*4882a593Smuzhiyun #define SGTL5000_ADC_ZCD_EN 0x0002 252*4882a593Smuzhiyun #define SGTL5000_ADC_MUTE 0x0001 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun /* 255*4882a593Smuzhiyun * SGTL5000_CHIP_LINREG_CTRL 256*4882a593Smuzhiyun */ 257*4882a593Smuzhiyun #define SGTL5000_VDDC_MAN_ASSN_MASK 0x0040 258*4882a593Smuzhiyun #define SGTL5000_VDDC_MAN_ASSN_SHIFT 6 259*4882a593Smuzhiyun #define SGTL5000_VDDC_MAN_ASSN_WIDTH 1 260*4882a593Smuzhiyun #define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0 261*4882a593Smuzhiyun #define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x1 262*4882a593Smuzhiyun #define SGTL5000_VDDC_ASSN_OVRD 0x0020 263*4882a593Smuzhiyun #define SGTL5000_LINREG_VDDD_MASK 0x000f 264*4882a593Smuzhiyun #define SGTL5000_LINREG_VDDD_SHIFT 0 265*4882a593Smuzhiyun #define SGTL5000_LINREG_VDDD_WIDTH 4 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun /* 268*4882a593Smuzhiyun * SGTL5000_CHIP_REF_CTRL 269*4882a593Smuzhiyun */ 270*4882a593Smuzhiyun #define SGTL5000_ANA_GND_MASK 0x01f0 271*4882a593Smuzhiyun #define SGTL5000_ANA_GND_SHIFT 4 272*4882a593Smuzhiyun #define SGTL5000_ANA_GND_WIDTH 5 273*4882a593Smuzhiyun #define SGTL5000_ANA_GND_BASE 800 /* mv */ 274*4882a593Smuzhiyun #define SGTL5000_ANA_GND_STP 25 /*mv */ 275*4882a593Smuzhiyun #define SGTL5000_BIAS_CTRL_MASK 0x000e 276*4882a593Smuzhiyun #define SGTL5000_BIAS_CTRL_SHIFT 1 277*4882a593Smuzhiyun #define SGTL5000_BIAS_CTRL_WIDTH 3 278*4882a593Smuzhiyun #define SGTL5000_SMALL_POP 0x0001 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun /* 281*4882a593Smuzhiyun * SGTL5000_CHIP_MIC_CTRL 282*4882a593Smuzhiyun */ 283*4882a593Smuzhiyun #define SGTL5000_BIAS_R_MASK 0x0300 284*4882a593Smuzhiyun #define SGTL5000_BIAS_R_SHIFT 8 285*4882a593Smuzhiyun #define SGTL5000_BIAS_R_WIDTH 2 286*4882a593Smuzhiyun #define SGTL5000_BIAS_R_off 0x0 287*4882a593Smuzhiyun #define SGTL5000_BIAS_R_2K 0x1 288*4882a593Smuzhiyun #define SGTL5000_BIAS_R_4k 0x2 289*4882a593Smuzhiyun #define SGTL5000_BIAS_R_8k 0x3 290*4882a593Smuzhiyun #define SGTL5000_BIAS_VOLT_MASK 0x0070 291*4882a593Smuzhiyun #define SGTL5000_BIAS_VOLT_SHIFT 4 292*4882a593Smuzhiyun #define SGTL5000_BIAS_VOLT_WIDTH 3 293*4882a593Smuzhiyun #define SGTL5000_MIC_GAIN_MASK 0x0003 294*4882a593Smuzhiyun #define SGTL5000_MIC_GAIN_SHIFT 0 295*4882a593Smuzhiyun #define SGTL5000_MIC_GAIN_WIDTH 2 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun /* 298*4882a593Smuzhiyun * SGTL5000_CHIP_LINE_OUT_CTRL 299*4882a593Smuzhiyun */ 300*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_CURRENT_MASK 0x0f00 301*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_CURRENT_SHIFT 8 302*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_CURRENT_WIDTH 4 303*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_CURRENT_180u 0x0 304*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_CURRENT_270u 0x1 305*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_CURRENT_360u 0x3 306*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_CURRENT_450u 0x7 307*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_CURRENT_540u 0xf 308*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_GND_MASK 0x003f 309*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_GND_SHIFT 0 310*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_GND_WIDTH 6 311*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_GND_BASE 800 /* mv */ 312*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_GND_STP 25 313*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_GND_MAX 0x23 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun /* 316*4882a593Smuzhiyun * SGTL5000_CHIP_LINE_OUT_VOL 317*4882a593Smuzhiyun */ 318*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_VOL_RIGHT_MASK 0x1f00 319*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 8 320*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_VOL_RIGHT_WIDTH 5 321*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_VOL_LEFT_MASK 0x001f 322*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0 323*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_VOL_LEFT_WIDTH 5 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun /* 326*4882a593Smuzhiyun * SGTL5000_CHIP_ANA_POWER 327*4882a593Smuzhiyun */ 328*4882a593Smuzhiyun #define SGTL5000_ANA_POWER_DEFAULT 0x7060 329*4882a593Smuzhiyun #define SGTL5000_DAC_STEREO 0x4000 330*4882a593Smuzhiyun #define SGTL5000_LINREG_SIMPLE_POWERUP 0x2000 331*4882a593Smuzhiyun #define SGTL5000_STARTUP_POWERUP 0x1000 332*4882a593Smuzhiyun #define SGTL5000_VDDC_CHRGPMP_POWERUP 0x0800 333*4882a593Smuzhiyun #define SGTL5000_PLL_POWERUP 0x0400 334*4882a593Smuzhiyun #define SGTL5000_LINEREG_D_POWERUP 0x0200 335*4882a593Smuzhiyun #define SGTL5000_VCOAMP_POWERUP 0x0100 336*4882a593Smuzhiyun #define SGTL5000_VAG_POWERUP 0x0080 337*4882a593Smuzhiyun #define SGTL5000_ADC_STEREO 0x0040 338*4882a593Smuzhiyun #define SGTL5000_REFTOP_POWERUP 0x0020 339*4882a593Smuzhiyun #define SGTL5000_HP_POWERUP 0x0010 340*4882a593Smuzhiyun #define SGTL5000_DAC_POWERUP 0x0008 341*4882a593Smuzhiyun #define SGTL5000_CAPLESS_HP_POWERUP 0x0004 342*4882a593Smuzhiyun #define SGTL5000_ADC_POWERUP 0x0002 343*4882a593Smuzhiyun #define SGTL5000_LINE_OUT_POWERUP 0x0001 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun /* 346*4882a593Smuzhiyun * SGTL5000_CHIP_PLL_CTRL 347*4882a593Smuzhiyun */ 348*4882a593Smuzhiyun #define SGTL5000_PLL_INT_DIV_MASK 0xf800 349*4882a593Smuzhiyun #define SGTL5000_PLL_INT_DIV_SHIFT 11 350*4882a593Smuzhiyun #define SGTL5000_PLL_INT_DIV_WIDTH 5 351*4882a593Smuzhiyun #define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff 352*4882a593Smuzhiyun #define SGTL5000_PLL_FRAC_DIV_SHIFT 0 353*4882a593Smuzhiyun #define SGTL5000_PLL_FRAC_DIV_WIDTH 11 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun /* 356*4882a593Smuzhiyun * SGTL5000_CHIP_CLK_TOP_CTRL 357*4882a593Smuzhiyun */ 358*4882a593Smuzhiyun #define SGTL5000_INT_OSC_EN 0x0800 359*4882a593Smuzhiyun #define SGTL5000_INPUT_FREQ_DIV2 0x0008 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun /* 362*4882a593Smuzhiyun * SGTL5000_CHIP_ANA_STATUS 363*4882a593Smuzhiyun */ 364*4882a593Smuzhiyun #define SGTL5000_HP_LRSHORT 0x0200 365*4882a593Smuzhiyun #define SGTL5000_CAPLESS_SHORT 0x0100 366*4882a593Smuzhiyun #define SGTL5000_PLL_LOCKED 0x0010 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun /* 369*4882a593Smuzhiyun * SGTL5000_CHIP_SHORT_CTRL 370*4882a593Smuzhiyun */ 371*4882a593Smuzhiyun #define SGTL5000_LVLADJR_MASK 0x7000 372*4882a593Smuzhiyun #define SGTL5000_LVLADJR_SHIFT 12 373*4882a593Smuzhiyun #define SGTL5000_LVLADJR_WIDTH 3 374*4882a593Smuzhiyun #define SGTL5000_LVLADJL_MASK 0x0700 375*4882a593Smuzhiyun #define SGTL5000_LVLADJL_SHIFT 8 376*4882a593Smuzhiyun #define SGTL5000_LVLADJL_WIDTH 3 377*4882a593Smuzhiyun #define SGTL5000_LVLADJC_MASK 0x0070 378*4882a593Smuzhiyun #define SGTL5000_LVLADJC_SHIFT 4 379*4882a593Smuzhiyun #define SGTL5000_LVLADJC_WIDTH 3 380*4882a593Smuzhiyun #define SGTL5000_LR_SHORT_MOD_MASK 0x000c 381*4882a593Smuzhiyun #define SGTL5000_LR_SHORT_MOD_SHIFT 2 382*4882a593Smuzhiyun #define SGTL5000_LR_SHORT_MOD_WIDTH 2 383*4882a593Smuzhiyun #define SGTL5000_CM_SHORT_MOD_MASK 0x0003 384*4882a593Smuzhiyun #define SGTL5000_CM_SHORT_MOD_SHIFT 0 385*4882a593Smuzhiyun #define SGTL5000_CM_SHORT_MOD_WIDTH 2 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun /* 388*4882a593Smuzhiyun *SGTL5000_CHIP_ANA_TEST2 389*4882a593Smuzhiyun */ 390*4882a593Smuzhiyun #define SGTL5000_MONO_DAC 0x1000 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun /* 393*4882a593Smuzhiyun * SGTL5000_DAP_CTRL 394*4882a593Smuzhiyun */ 395*4882a593Smuzhiyun #define SGTL5000_DAP_MIX_EN 0x0010 396*4882a593Smuzhiyun #define SGTL5000_DAP_EN 0x0001 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun #define SGTL5000_SYSCLK 0x00 399*4882a593Smuzhiyun #define SGTL5000_LRCLK 0x01 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun /* 402*4882a593Smuzhiyun * SGTL5000_DAP_AUDIO_EQ 403*4882a593Smuzhiyun */ 404*4882a593Smuzhiyun #define SGTL5000_DAP_SEL_PEQ 1 405*4882a593Smuzhiyun #define SGTL5000_DAP_SEL_TONE_CTRL 2 406*4882a593Smuzhiyun #define SGTL5000_DAP_SEL_GEQ 3 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun #endif 409