xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/rt715.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * rt715.h -- RT715 ALSA SoC audio driver header
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright(c) 2019 Realtek Semiconductor Corp.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __RT715_H__
9*4882a593Smuzhiyun #define __RT715_H__
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun struct rt715_priv {
14*4882a593Smuzhiyun 	struct regmap *regmap;
15*4882a593Smuzhiyun 	struct regmap *sdw_regmap;
16*4882a593Smuzhiyun 	struct snd_soc_codec *codec;
17*4882a593Smuzhiyun 	struct sdw_slave *slave;
18*4882a593Smuzhiyun 	int dbg_nid;
19*4882a593Smuzhiyun 	int dbg_vid;
20*4882a593Smuzhiyun 	int dbg_payload;
21*4882a593Smuzhiyun 	enum sdw_slave_status status;
22*4882a593Smuzhiyun 	struct sdw_bus_params params;
23*4882a593Smuzhiyun 	bool hw_init;
24*4882a593Smuzhiyun 	bool first_hw_init;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun struct sdw_stream_data {
28*4882a593Smuzhiyun 	struct sdw_stream_runtime *sdw_stream;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /* NID */
32*4882a593Smuzhiyun #define RT715_AUDIO_FUNCTION_GROUP			0x01
33*4882a593Smuzhiyun #define RT715_MIC_ADC					0x07
34*4882a593Smuzhiyun #define RT715_LINE_ADC					0x08
35*4882a593Smuzhiyun #define RT715_MIX_ADC					0x09
36*4882a593Smuzhiyun #define RT715_DMIC1					0x12
37*4882a593Smuzhiyun #define RT715_DMIC2					0x13
38*4882a593Smuzhiyun #define RT715_MIC1					0x18
39*4882a593Smuzhiyun #define RT715_MIC2					0x19
40*4882a593Smuzhiyun #define RT715_LINE1					0x1a
41*4882a593Smuzhiyun #define RT715_LINE2					0x1b
42*4882a593Smuzhiyun #define RT715_DMIC3					0x1d
43*4882a593Smuzhiyun #define RT715_DMIC4					0x29
44*4882a593Smuzhiyun #define RT715_VENDOR_REGISTERS				0x20
45*4882a593Smuzhiyun #define RT715_MUX_IN1					0x22
46*4882a593Smuzhiyun #define RT715_MUX_IN2					0x23
47*4882a593Smuzhiyun #define RT715_MUX_IN3					0x24
48*4882a593Smuzhiyun #define RT715_MUX_IN4					0x25
49*4882a593Smuzhiyun #define RT715_MIX_ADC2					0x27
50*4882a593Smuzhiyun #define RT715_INLINE_CMD				0x55
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /* Index (NID:20h) */
53*4882a593Smuzhiyun #define RT715_SDW_INPUT_SEL				0x39
54*4882a593Smuzhiyun #define RT715_EXT_DMIC_CLK_CTRL2			0x54
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* Verb */
57*4882a593Smuzhiyun #define RT715_VERB_SET_CONNECT_SEL			0x3100
58*4882a593Smuzhiyun #define RT715_VERB_GET_CONNECT_SEL			0xb100
59*4882a593Smuzhiyun #define RT715_VERB_SET_EAPD_BTLENABLE			0x3c00
60*4882a593Smuzhiyun #define RT715_VERB_SET_POWER_STATE			0x3500
61*4882a593Smuzhiyun #define RT715_VERB_SET_CHANNEL_STREAMID			0x3600
62*4882a593Smuzhiyun #define RT715_VERB_SET_PIN_WIDGET_CONTROL		0x3700
63*4882a593Smuzhiyun #define RT715_VERB_SET_CONFIG_DEFAULT1			0x4c00
64*4882a593Smuzhiyun #define RT715_VERB_SET_CONFIG_DEFAULT2			0x4d00
65*4882a593Smuzhiyun #define RT715_VERB_SET_CONFIG_DEFAULT3			0x4e00
66*4882a593Smuzhiyun #define RT715_VERB_SET_CONFIG_DEFAULT4			0x4f00
67*4882a593Smuzhiyun #define RT715_VERB_SET_UNSOLICITED_ENABLE		0x3800
68*4882a593Smuzhiyun #define RT715_SET_AMP_GAIN_MUTE_H			0x7300
69*4882a593Smuzhiyun #define RT715_SET_AMP_GAIN_MUTE_L			0x8380
70*4882a593Smuzhiyun #define RT715_READ_HDA_3				0x2012
71*4882a593Smuzhiyun #define RT715_READ_HDA_2				0x2013
72*4882a593Smuzhiyun #define RT715_READ_HDA_1				0x2014
73*4882a593Smuzhiyun #define RT715_READ_HDA_0				0x2015
74*4882a593Smuzhiyun #define RT715_PRIV_INDEX_W_H				0x7520
75*4882a593Smuzhiyun #define RT715_PRIV_INDEX_W_L				0x85a0
76*4882a593Smuzhiyun #define RT715_PRIV_DATA_W_H				0x7420
77*4882a593Smuzhiyun #define RT715_PRIV_DATA_W_L				0x84a0
78*4882a593Smuzhiyun #define RT715_PRIV_INDEX_R_H				0x9d20
79*4882a593Smuzhiyun #define RT715_PRIV_INDEX_R_L				0xada0
80*4882a593Smuzhiyun #define RT715_PRIV_DATA_R_H				0x9c20
81*4882a593Smuzhiyun #define RT715_PRIV_DATA_R_L				0xaca0
82*4882a593Smuzhiyun #define RT715_MIC_ADC_FORMAT_H				0x7207
83*4882a593Smuzhiyun #define RT715_MIC_ADC_FORMAT_L				0x8287
84*4882a593Smuzhiyun #define RT715_MIC_LINE_FORMAT_H				0x7208
85*4882a593Smuzhiyun #define RT715_MIC_LINE_FORMAT_L				0x8288
86*4882a593Smuzhiyun #define RT715_MIX_ADC_FORMAT_H				0x7209
87*4882a593Smuzhiyun #define RT715_MIX_ADC_FORMAT_L				0x8289
88*4882a593Smuzhiyun #define RT715_MIX_ADC2_FORMAT_H				0x7227
89*4882a593Smuzhiyun #define RT715_MIX_ADC2_FORMAT_L				0x82a7
90*4882a593Smuzhiyun #define RT715_FUNC_RESET				0xff01
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define RT715_SET_AUDIO_POWER_STATE\
93*4882a593Smuzhiyun 	(RT715_VERB_SET_POWER_STATE | RT715_AUDIO_FUNCTION_GROUP)
94*4882a593Smuzhiyun #define RT715_SET_PIN_DMIC1\
95*4882a593Smuzhiyun 	(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC1)
96*4882a593Smuzhiyun #define RT715_SET_PIN_DMIC2\
97*4882a593Smuzhiyun 	(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC2)
98*4882a593Smuzhiyun #define RT715_SET_PIN_DMIC3\
99*4882a593Smuzhiyun 	(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC3)
100*4882a593Smuzhiyun #define RT715_SET_PIN_DMIC4\
101*4882a593Smuzhiyun 	(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC4)
102*4882a593Smuzhiyun #define RT715_SET_PIN_MIC1\
103*4882a593Smuzhiyun 	(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_MIC1)
104*4882a593Smuzhiyun #define RT715_SET_PIN_MIC2\
105*4882a593Smuzhiyun 	(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_MIC2)
106*4882a593Smuzhiyun #define RT715_SET_PIN_LINE1\
107*4882a593Smuzhiyun 	(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_LINE1)
108*4882a593Smuzhiyun #define RT715_SET_PIN_LINE2\
109*4882a593Smuzhiyun 	(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_LINE2)
110*4882a593Smuzhiyun #define RT715_SET_MIC1_UNSOLICITED_ENABLE\
111*4882a593Smuzhiyun 	(RT715_VERB_SET_UNSOLICITED_ENABLE | RT715_MIC1)
112*4882a593Smuzhiyun #define RT715_SET_MIC2_UNSOLICITED_ENABLE\
113*4882a593Smuzhiyun 	(RT715_VERB_SET_UNSOLICITED_ENABLE | RT715_MIC2)
114*4882a593Smuzhiyun #define RT715_SET_STREAMID_MIC_ADC\
115*4882a593Smuzhiyun 	(RT715_VERB_SET_CHANNEL_STREAMID | RT715_MIC_ADC)
116*4882a593Smuzhiyun #define RT715_SET_STREAMID_LINE_ADC\
117*4882a593Smuzhiyun 	(RT715_VERB_SET_CHANNEL_STREAMID | RT715_LINE_ADC)
118*4882a593Smuzhiyun #define RT715_SET_STREAMID_MIX_ADC\
119*4882a593Smuzhiyun 	(RT715_VERB_SET_CHANNEL_STREAMID | RT715_MIX_ADC)
120*4882a593Smuzhiyun #define RT715_SET_STREAMID_MIX_ADC2\
121*4882a593Smuzhiyun 	(RT715_VERB_SET_CHANNEL_STREAMID | RT715_MIX_ADC2)
122*4882a593Smuzhiyun #define RT715_SET_GAIN_MIC_ADC_L\
123*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_MIC_ADC)
124*4882a593Smuzhiyun #define RT715_SET_GAIN_MIC_ADC_H\
125*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_MIC_ADC)
126*4882a593Smuzhiyun #define RT715_SET_GAIN_LINE_ADC_L\
127*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_LINE_ADC)
128*4882a593Smuzhiyun #define RT715_SET_GAIN_LINE_ADC_H\
129*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_LINE_ADC)
130*4882a593Smuzhiyun #define RT715_SET_GAIN_MIX_ADC_L\
131*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_MIX_ADC)
132*4882a593Smuzhiyun #define RT715_SET_GAIN_MIX_ADC_H\
133*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_MIX_ADC)
134*4882a593Smuzhiyun #define RT715_SET_GAIN_MIX_ADC2_L\
135*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_MIX_ADC2)
136*4882a593Smuzhiyun #define RT715_SET_GAIN_MIX_ADC2_H\
137*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_MIX_ADC2)
138*4882a593Smuzhiyun #define RT715_SET_GAIN_DMIC1_L\
139*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC1)
140*4882a593Smuzhiyun #define RT715_SET_GAIN_DMIC1_H\
141*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC1)
142*4882a593Smuzhiyun #define RT715_SET_GAIN_DMIC2_L\
143*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC2)
144*4882a593Smuzhiyun #define RT715_SET_GAIN_DMIC2_H\
145*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC2)
146*4882a593Smuzhiyun #define RT715_SET_GAIN_DMIC3_L\
147*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC3)
148*4882a593Smuzhiyun #define RT715_SET_GAIN_DMIC3_H\
149*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC3)
150*4882a593Smuzhiyun #define RT715_SET_GAIN_DMIC4_L\
151*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC4)
152*4882a593Smuzhiyun #define RT715_SET_GAIN_DMIC4_H\
153*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC4)
154*4882a593Smuzhiyun #define RT715_SET_GAIN_MIC1_L\
155*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_MIC1)
156*4882a593Smuzhiyun #define RT715_SET_GAIN_MIC1_H\
157*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_MIC1)
158*4882a593Smuzhiyun #define RT715_SET_GAIN_MIC2_L\
159*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_MIC2)
160*4882a593Smuzhiyun #define RT715_SET_GAIN_MIC2_H\
161*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_MIC2)
162*4882a593Smuzhiyun #define RT715_SET_GAIN_LINE1_L\
163*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_LINE1)
164*4882a593Smuzhiyun #define RT715_SET_GAIN_LINE1_H\
165*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_LINE1)
166*4882a593Smuzhiyun #define RT715_SET_GAIN_LINE2_L\
167*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_L | RT715_LINE2)
168*4882a593Smuzhiyun #define RT715_SET_GAIN_LINE2_H\
169*4882a593Smuzhiyun 	(RT715_SET_AMP_GAIN_MUTE_H | RT715_LINE2)
170*4882a593Smuzhiyun #define RT715_SET_DMIC1_CONFIG_DEFAULT1\
171*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC1)
172*4882a593Smuzhiyun #define RT715_SET_DMIC2_CONFIG_DEFAULT1\
173*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC2)
174*4882a593Smuzhiyun #define RT715_SET_DMIC1_CONFIG_DEFAULT2\
175*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC1)
176*4882a593Smuzhiyun #define RT715_SET_DMIC2_CONFIG_DEFAULT2\
177*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC2)
178*4882a593Smuzhiyun #define RT715_SET_DMIC1_CONFIG_DEFAULT3\
179*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC1)
180*4882a593Smuzhiyun #define RT715_SET_DMIC2_CONFIG_DEFAULT3\
181*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC2)
182*4882a593Smuzhiyun #define RT715_SET_DMIC1_CONFIG_DEFAULT4\
183*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC1)
184*4882a593Smuzhiyun #define RT715_SET_DMIC2_CONFIG_DEFAULT4\
185*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC2)
186*4882a593Smuzhiyun #define RT715_SET_DMIC3_CONFIG_DEFAULT1\
187*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC3)
188*4882a593Smuzhiyun #define RT715_SET_DMIC4_CONFIG_DEFAULT1\
189*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC4)
190*4882a593Smuzhiyun #define RT715_SET_DMIC3_CONFIG_DEFAULT2\
191*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC3)
192*4882a593Smuzhiyun #define RT715_SET_DMIC4_CONFIG_DEFAULT2\
193*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC4)
194*4882a593Smuzhiyun #define RT715_SET_DMIC3_CONFIG_DEFAULT3\
195*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC3)
196*4882a593Smuzhiyun #define RT715_SET_DMIC4_CONFIG_DEFAULT3\
197*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC4)
198*4882a593Smuzhiyun #define RT715_SET_DMIC3_CONFIG_DEFAULT4\
199*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC3)
200*4882a593Smuzhiyun #define RT715_SET_DMIC4_CONFIG_DEFAULT4\
201*4882a593Smuzhiyun 	(RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC4)
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun #define RT715_MUTE_SFT					7
204*4882a593Smuzhiyun #define RT715_DIR_IN_SFT				6
205*4882a593Smuzhiyun #define RT715_DIR_OUT_SFT				7
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun enum {
208*4882a593Smuzhiyun 	RT715_AIF1,
209*4882a593Smuzhiyun 	RT715_AIF2,
210*4882a593Smuzhiyun 	RT715_AIFS,
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun #define RT715_POWER_UP_DELAY_MS 400
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun int rt715_io_init(struct device *dev, struct sdw_slave *slave);
216*4882a593Smuzhiyun int rt715_init(struct device *dev, struct regmap *sdw_regmap,
217*4882a593Smuzhiyun 	struct regmap *regmap, struct sdw_slave *slave);
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun int hda_to_sdw(unsigned int nid, unsigned int verb, unsigned int payload,
220*4882a593Smuzhiyun 	       unsigned int *sdw_addr_h, unsigned int *sdw_data_h,
221*4882a593Smuzhiyun 	       unsigned int *sdw_addr_l, unsigned int *sdw_data_l);
222*4882a593Smuzhiyun int rt715_clock_config(struct device *dev);
223*4882a593Smuzhiyun #endif /* __RT715_H__ */
224