xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/rt711-sdw.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // rt711-sdw.c -- rt711 ALSA SoC audio driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright(c) 2019 Realtek Semiconductor Corp.
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
12*4882a593Smuzhiyun #include <linux/soundwire/sdw.h>
13*4882a593Smuzhiyun #include <linux/soundwire/sdw_type.h>
14*4882a593Smuzhiyun #include <linux/soundwire/sdw_registers.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <sound/soc.h>
18*4882a593Smuzhiyun #include "rt711.h"
19*4882a593Smuzhiyun #include "rt711-sdw.h"
20*4882a593Smuzhiyun 
rt711_readable_register(struct device * dev,unsigned int reg)21*4882a593Smuzhiyun static bool rt711_readable_register(struct device *dev, unsigned int reg)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun 	switch (reg) {
24*4882a593Smuzhiyun 	case 0x00e0:
25*4882a593Smuzhiyun 	case 0x00f0:
26*4882a593Smuzhiyun 	case 0x2012 ... 0x2016:
27*4882a593Smuzhiyun 	case 0x201a ... 0x2027:
28*4882a593Smuzhiyun 	case 0x2029 ... 0x202a:
29*4882a593Smuzhiyun 	case 0x202d ... 0x2034:
30*4882a593Smuzhiyun 	case 0x2201 ... 0x2204:
31*4882a593Smuzhiyun 	case 0x2206 ... 0x2212:
32*4882a593Smuzhiyun 	case 0x2220 ... 0x2223:
33*4882a593Smuzhiyun 	case 0x2230 ... 0x2239:
34*4882a593Smuzhiyun 	case 0x2f01 ... 0x2f0f:
35*4882a593Smuzhiyun 	case 0x3000 ... 0x3fff:
36*4882a593Smuzhiyun 	case 0x7000 ... 0x7fff:
37*4882a593Smuzhiyun 	case 0x8300 ... 0x83ff:
38*4882a593Smuzhiyun 	case 0x9c00 ... 0x9cff:
39*4882a593Smuzhiyun 	case 0xb900 ... 0xb9ff:
40*4882a593Smuzhiyun 	case 0x752009:
41*4882a593Smuzhiyun 	case 0x752011:
42*4882a593Smuzhiyun 	case 0x75201a:
43*4882a593Smuzhiyun 	case 0x752045:
44*4882a593Smuzhiyun 	case 0x752046:
45*4882a593Smuzhiyun 	case 0x752048:
46*4882a593Smuzhiyun 	case 0x75204a:
47*4882a593Smuzhiyun 	case 0x75206b:
48*4882a593Smuzhiyun 	case 0x75206f:
49*4882a593Smuzhiyun 	case 0x752080:
50*4882a593Smuzhiyun 	case 0x752081:
51*4882a593Smuzhiyun 	case 0x752091:
52*4882a593Smuzhiyun 	case 0x755800:
53*4882a593Smuzhiyun 		return true;
54*4882a593Smuzhiyun 	default:
55*4882a593Smuzhiyun 		return false;
56*4882a593Smuzhiyun 	}
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
rt711_volatile_register(struct device * dev,unsigned int reg)59*4882a593Smuzhiyun static bool rt711_volatile_register(struct device *dev, unsigned int reg)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	switch (reg) {
62*4882a593Smuzhiyun 	case 0x2016:
63*4882a593Smuzhiyun 	case 0x201b:
64*4882a593Smuzhiyun 	case 0x201c:
65*4882a593Smuzhiyun 	case 0x201d:
66*4882a593Smuzhiyun 	case 0x201f:
67*4882a593Smuzhiyun 	case 0x2021:
68*4882a593Smuzhiyun 	case 0x2023:
69*4882a593Smuzhiyun 	case 0x2230:
70*4882a593Smuzhiyun 	case 0x2012 ... 0x2015: /* HD-A read */
71*4882a593Smuzhiyun 	case 0x202d ... 0x202f: /* BRA */
72*4882a593Smuzhiyun 	case 0x2201 ... 0x2212: /* i2c debug */
73*4882a593Smuzhiyun 	case 0x2220 ... 0x2223: /* decoded HD-A */
74*4882a593Smuzhiyun 	case 0x9c00 ... 0x9cff:
75*4882a593Smuzhiyun 	case 0xb900 ... 0xb9ff:
76*4882a593Smuzhiyun 	case 0xff01:
77*4882a593Smuzhiyun 	case 0x75201a:
78*4882a593Smuzhiyun 	case 0x752046:
79*4882a593Smuzhiyun 	case 0x752080:
80*4882a593Smuzhiyun 	case 0x752081:
81*4882a593Smuzhiyun 	case 0x755800:
82*4882a593Smuzhiyun 		return true;
83*4882a593Smuzhiyun 	default:
84*4882a593Smuzhiyun 		return false;
85*4882a593Smuzhiyun 	}
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun 
rt711_sdw_read(void * context,unsigned int reg,unsigned int * val)88*4882a593Smuzhiyun static int rt711_sdw_read(void *context, unsigned int reg, unsigned int *val)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	struct device *dev = context;
91*4882a593Smuzhiyun 	struct rt711_priv *rt711 = dev_get_drvdata(dev);
92*4882a593Smuzhiyun 	unsigned int sdw_data_3, sdw_data_2, sdw_data_1, sdw_data_0;
93*4882a593Smuzhiyun 	unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2;
94*4882a593Smuzhiyun 	unsigned int is_hda_reg = 1, is_index_reg = 0;
95*4882a593Smuzhiyun 	int ret;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	if (reg > 0xffff)
98*4882a593Smuzhiyun 		is_index_reg = 1;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	mask = reg & 0xf000;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	if (is_index_reg) { /* index registers */
103*4882a593Smuzhiyun 		val2 = reg & 0xff;
104*4882a593Smuzhiyun 		reg = reg >> 8;
105*4882a593Smuzhiyun 		nid = reg & 0xff;
106*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg, 0);
107*4882a593Smuzhiyun 		if (ret < 0)
108*4882a593Smuzhiyun 			return ret;
109*4882a593Smuzhiyun 		reg2 = reg + 0x1000;
110*4882a593Smuzhiyun 		reg2 |= 0x80;
111*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg2, val2);
112*4882a593Smuzhiyun 		if (ret < 0)
113*4882a593Smuzhiyun 			return ret;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 		reg3 = RT711_PRIV_DATA_R_H | nid;
116*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap,
117*4882a593Smuzhiyun 			reg3, ((*val >> 8) & 0xff));
118*4882a593Smuzhiyun 		if (ret < 0)
119*4882a593Smuzhiyun 			return ret;
120*4882a593Smuzhiyun 		reg4 = reg3 + 0x1000;
121*4882a593Smuzhiyun 		reg4 |= 0x80;
122*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg4, (*val & 0xff));
123*4882a593Smuzhiyun 		if (ret < 0)
124*4882a593Smuzhiyun 			return ret;
125*4882a593Smuzhiyun 	} else if (mask   == 0x3000) {
126*4882a593Smuzhiyun 		reg += 0x8000;
127*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg, *val);
128*4882a593Smuzhiyun 		if (ret < 0)
129*4882a593Smuzhiyun 			return ret;
130*4882a593Smuzhiyun 	} else if (mask == 0x7000) {
131*4882a593Smuzhiyun 		reg += 0x2000;
132*4882a593Smuzhiyun 		reg |= 0x800;
133*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap,
134*4882a593Smuzhiyun 			reg, ((*val >> 8) & 0xff));
135*4882a593Smuzhiyun 		if (ret < 0)
136*4882a593Smuzhiyun 			return ret;
137*4882a593Smuzhiyun 		reg2 = reg + 0x1000;
138*4882a593Smuzhiyun 		reg2 |= 0x80;
139*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg2, (*val & 0xff));
140*4882a593Smuzhiyun 		if (ret < 0)
141*4882a593Smuzhiyun 			return ret;
142*4882a593Smuzhiyun 	} else if ((reg & 0xff00) == 0x8300) { /* for R channel */
143*4882a593Smuzhiyun 		reg2 = reg - 0x1000;
144*4882a593Smuzhiyun 		reg2 &= ~0x80;
145*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap,
146*4882a593Smuzhiyun 			reg2, ((*val >> 8) & 0xff));
147*4882a593Smuzhiyun 		if (ret < 0)
148*4882a593Smuzhiyun 			return ret;
149*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg, (*val & 0xff));
150*4882a593Smuzhiyun 		if (ret < 0)
151*4882a593Smuzhiyun 			return ret;
152*4882a593Smuzhiyun 	} else if (mask == 0x9000) {
153*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap,
154*4882a593Smuzhiyun 			reg, ((*val >> 8) & 0xff));
155*4882a593Smuzhiyun 		if (ret < 0)
156*4882a593Smuzhiyun 			return ret;
157*4882a593Smuzhiyun 		reg2 = reg + 0x1000;
158*4882a593Smuzhiyun 		reg2 |= 0x80;
159*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg2, (*val & 0xff));
160*4882a593Smuzhiyun 		if (ret < 0)
161*4882a593Smuzhiyun 			return ret;
162*4882a593Smuzhiyun 	} else if (mask == 0xb000) {
163*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg, *val);
164*4882a593Smuzhiyun 		if (ret < 0)
165*4882a593Smuzhiyun 			return ret;
166*4882a593Smuzhiyun 	} else {
167*4882a593Smuzhiyun 		ret = regmap_read(rt711->sdw_regmap, reg, val);
168*4882a593Smuzhiyun 		if (ret < 0)
169*4882a593Smuzhiyun 			return ret;
170*4882a593Smuzhiyun 		is_hda_reg = 0;
171*4882a593Smuzhiyun 	}
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	if (is_hda_reg || is_index_reg) {
174*4882a593Smuzhiyun 		sdw_data_3 = 0;
175*4882a593Smuzhiyun 		sdw_data_2 = 0;
176*4882a593Smuzhiyun 		sdw_data_1 = 0;
177*4882a593Smuzhiyun 		sdw_data_0 = 0;
178*4882a593Smuzhiyun 		ret = regmap_read(rt711->sdw_regmap,
179*4882a593Smuzhiyun 			RT711_READ_HDA_3, &sdw_data_3);
180*4882a593Smuzhiyun 		if (ret < 0)
181*4882a593Smuzhiyun 			return ret;
182*4882a593Smuzhiyun 		ret = regmap_read(rt711->sdw_regmap,
183*4882a593Smuzhiyun 			RT711_READ_HDA_2, &sdw_data_2);
184*4882a593Smuzhiyun 		if (ret < 0)
185*4882a593Smuzhiyun 			return ret;
186*4882a593Smuzhiyun 		ret = regmap_read(rt711->sdw_regmap,
187*4882a593Smuzhiyun 			RT711_READ_HDA_1, &sdw_data_1);
188*4882a593Smuzhiyun 		if (ret < 0)
189*4882a593Smuzhiyun 			return ret;
190*4882a593Smuzhiyun 		ret = regmap_read(rt711->sdw_regmap,
191*4882a593Smuzhiyun 			RT711_READ_HDA_0, &sdw_data_0);
192*4882a593Smuzhiyun 		if (ret < 0)
193*4882a593Smuzhiyun 			return ret;
194*4882a593Smuzhiyun 		*val = ((sdw_data_3 & 0xff) << 24) |
195*4882a593Smuzhiyun 			((sdw_data_2 & 0xff) << 16) |
196*4882a593Smuzhiyun 			((sdw_data_1 & 0xff) << 8) | (sdw_data_0 & 0xff);
197*4882a593Smuzhiyun 	}
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	if (is_hda_reg == 0)
200*4882a593Smuzhiyun 		dev_dbg(dev, "[%s] %04x => %08x\n", __func__, reg, *val);
201*4882a593Smuzhiyun 	else if (is_index_reg)
202*4882a593Smuzhiyun 		dev_dbg(dev, "[%s] %04x %04x %04x %04x => %08x\n",
203*4882a593Smuzhiyun 			__func__, reg, reg2, reg3, reg4, *val);
204*4882a593Smuzhiyun 	else
205*4882a593Smuzhiyun 		dev_dbg(dev, "[%s] %04x %04x => %08x\n",
206*4882a593Smuzhiyun 			__func__, reg, reg2, *val);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	return 0;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
rt711_sdw_write(void * context,unsigned int reg,unsigned int val)211*4882a593Smuzhiyun static int rt711_sdw_write(void *context, unsigned int reg, unsigned int val)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	struct device *dev = context;
214*4882a593Smuzhiyun 	struct rt711_priv *rt711 = dev_get_drvdata(dev);
215*4882a593Smuzhiyun 	unsigned int reg2 = 0, reg3, reg4, nid, mask, val2;
216*4882a593Smuzhiyun 	unsigned int is_index_reg = 0;
217*4882a593Smuzhiyun 	int ret;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	if (reg > 0xffff)
220*4882a593Smuzhiyun 		is_index_reg = 1;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	mask = reg & 0xf000;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	if (is_index_reg) { /* index registers */
225*4882a593Smuzhiyun 		val2 = reg & 0xff;
226*4882a593Smuzhiyun 		reg = reg >> 8;
227*4882a593Smuzhiyun 		nid = reg & 0xff;
228*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg, 0);
229*4882a593Smuzhiyun 		if (ret < 0)
230*4882a593Smuzhiyun 			return ret;
231*4882a593Smuzhiyun 		reg2 = reg + 0x1000;
232*4882a593Smuzhiyun 		reg2 |= 0x80;
233*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg2, val2);
234*4882a593Smuzhiyun 		if (ret < 0)
235*4882a593Smuzhiyun 			return ret;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 		reg3 = RT711_PRIV_DATA_W_H | nid;
238*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap,
239*4882a593Smuzhiyun 			reg3, ((val >> 8) & 0xff));
240*4882a593Smuzhiyun 		if (ret < 0)
241*4882a593Smuzhiyun 			return ret;
242*4882a593Smuzhiyun 		reg4 = reg3 + 0x1000;
243*4882a593Smuzhiyun 		reg4 |= 0x80;
244*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg4, (val & 0xff));
245*4882a593Smuzhiyun 		if (ret < 0)
246*4882a593Smuzhiyun 			return ret;
247*4882a593Smuzhiyun 		is_index_reg = 1;
248*4882a593Smuzhiyun 	} else if (reg < 0x4fff) {
249*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg, val);
250*4882a593Smuzhiyun 		if (ret < 0)
251*4882a593Smuzhiyun 			return ret;
252*4882a593Smuzhiyun 	} else if (reg == RT711_FUNC_RESET) {
253*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg, val);
254*4882a593Smuzhiyun 		if (ret < 0)
255*4882a593Smuzhiyun 			return ret;
256*4882a593Smuzhiyun 	} else if (mask == 0x7000) {
257*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap,
258*4882a593Smuzhiyun 			reg, ((val >> 8) & 0xff));
259*4882a593Smuzhiyun 		if (ret < 0)
260*4882a593Smuzhiyun 			return ret;
261*4882a593Smuzhiyun 		reg2 = reg + 0x1000;
262*4882a593Smuzhiyun 		reg2 |= 0x80;
263*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg2, (val & 0xff));
264*4882a593Smuzhiyun 		if (ret < 0)
265*4882a593Smuzhiyun 			return ret;
266*4882a593Smuzhiyun 	} else if ((reg & 0xff00) == 0x8300) {  /* for R channel */
267*4882a593Smuzhiyun 		reg2 = reg - 0x1000;
268*4882a593Smuzhiyun 		reg2 &= ~0x80;
269*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap,
270*4882a593Smuzhiyun 			reg2, ((val >> 8) & 0xff));
271*4882a593Smuzhiyun 		if (ret < 0)
272*4882a593Smuzhiyun 			return ret;
273*4882a593Smuzhiyun 		ret = regmap_write(rt711->sdw_regmap, reg, (val & 0xff));
274*4882a593Smuzhiyun 		if (ret < 0)
275*4882a593Smuzhiyun 			return ret;
276*4882a593Smuzhiyun 	}
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	if (reg2 == 0)
279*4882a593Smuzhiyun 		dev_dbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
280*4882a593Smuzhiyun 	else if (is_index_reg)
281*4882a593Smuzhiyun 		dev_dbg(dev, "[%s] %04x %04x %04x %04x <= %04x %04x\n",
282*4882a593Smuzhiyun 			__func__, reg, reg2, reg3, reg4, val2, val);
283*4882a593Smuzhiyun 	else
284*4882a593Smuzhiyun 		dev_dbg(dev, "[%s] %04x %04x <= %04x\n",
285*4882a593Smuzhiyun 			__func__, reg, reg2, val);
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	return 0;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun static const struct regmap_config rt711_regmap = {
291*4882a593Smuzhiyun 	.reg_bits = 24,
292*4882a593Smuzhiyun 	.val_bits = 32,
293*4882a593Smuzhiyun 	.readable_reg = rt711_readable_register,
294*4882a593Smuzhiyun 	.volatile_reg = rt711_volatile_register,
295*4882a593Smuzhiyun 	.max_register = 0x755800,
296*4882a593Smuzhiyun 	.reg_defaults = rt711_reg_defaults,
297*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(rt711_reg_defaults),
298*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
299*4882a593Smuzhiyun 	.use_single_read = true,
300*4882a593Smuzhiyun 	.use_single_write = true,
301*4882a593Smuzhiyun 	.reg_read = rt711_sdw_read,
302*4882a593Smuzhiyun 	.reg_write = rt711_sdw_write,
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun static const struct regmap_config rt711_sdw_regmap = {
306*4882a593Smuzhiyun 	.name = "sdw",
307*4882a593Smuzhiyun 	.reg_bits = 32,
308*4882a593Smuzhiyun 	.val_bits = 8,
309*4882a593Smuzhiyun 	.readable_reg = rt711_readable_register,
310*4882a593Smuzhiyun 	.max_register = 0xff01,
311*4882a593Smuzhiyun 	.cache_type = REGCACHE_NONE,
312*4882a593Smuzhiyun 	.use_single_read = true,
313*4882a593Smuzhiyun 	.use_single_write = true,
314*4882a593Smuzhiyun };
315*4882a593Smuzhiyun 
rt711_update_status(struct sdw_slave * slave,enum sdw_slave_status status)316*4882a593Smuzhiyun static int rt711_update_status(struct sdw_slave *slave,
317*4882a593Smuzhiyun 				enum sdw_slave_status status)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun 	struct rt711_priv *rt711 = dev_get_drvdata(&slave->dev);
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	/* Update the status */
322*4882a593Smuzhiyun 	rt711->status = status;
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	if (status == SDW_SLAVE_UNATTACHED)
325*4882a593Smuzhiyun 		rt711->hw_init = false;
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	/*
328*4882a593Smuzhiyun 	 * Perform initialization only if slave status is present and
329*4882a593Smuzhiyun 	 * hw_init flag is false
330*4882a593Smuzhiyun 	 */
331*4882a593Smuzhiyun 	if (rt711->hw_init || rt711->status != SDW_SLAVE_ATTACHED)
332*4882a593Smuzhiyun 		return 0;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	/* perform I/O transfers required for Slave initialization */
335*4882a593Smuzhiyun 	return rt711_io_init(&slave->dev, slave);
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun 
rt711_read_prop(struct sdw_slave * slave)338*4882a593Smuzhiyun static int rt711_read_prop(struct sdw_slave *slave)
339*4882a593Smuzhiyun {
340*4882a593Smuzhiyun 	struct sdw_slave_prop *prop = &slave->prop;
341*4882a593Smuzhiyun 	int nval, i;
342*4882a593Smuzhiyun 	u32 bit;
343*4882a593Smuzhiyun 	unsigned long addr;
344*4882a593Smuzhiyun 	struct sdw_dpn_prop *dpn;
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
347*4882a593Smuzhiyun 		SDW_SCP_INT1_PARITY;
348*4882a593Smuzhiyun 	prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	prop->paging_support = false;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	/* first we need to allocate memory for set bits in port lists */
353*4882a593Smuzhiyun 	prop->source_ports = 0x14; /* BITMAP: 00010100 */
354*4882a593Smuzhiyun 	prop->sink_ports = 0x8; /* BITMAP:  00001000 */
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	nval = hweight32(prop->source_ports);
357*4882a593Smuzhiyun 	prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
358*4882a593Smuzhiyun 						sizeof(*prop->src_dpn_prop),
359*4882a593Smuzhiyun 						GFP_KERNEL);
360*4882a593Smuzhiyun 	if (!prop->src_dpn_prop)
361*4882a593Smuzhiyun 		return -ENOMEM;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	i = 0;
364*4882a593Smuzhiyun 	dpn = prop->src_dpn_prop;
365*4882a593Smuzhiyun 	addr = prop->source_ports;
366*4882a593Smuzhiyun 	for_each_set_bit(bit, &addr, 32) {
367*4882a593Smuzhiyun 		dpn[i].num = bit;
368*4882a593Smuzhiyun 		dpn[i].type = SDW_DPN_FULL;
369*4882a593Smuzhiyun 		dpn[i].simple_ch_prep_sm = true;
370*4882a593Smuzhiyun 		dpn[i].ch_prep_timeout = 10;
371*4882a593Smuzhiyun 		i++;
372*4882a593Smuzhiyun 	}
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	/* do this again for sink now */
375*4882a593Smuzhiyun 	nval = hweight32(prop->sink_ports);
376*4882a593Smuzhiyun 	prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
377*4882a593Smuzhiyun 						sizeof(*prop->sink_dpn_prop),
378*4882a593Smuzhiyun 						GFP_KERNEL);
379*4882a593Smuzhiyun 	if (!prop->sink_dpn_prop)
380*4882a593Smuzhiyun 		return -ENOMEM;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	i = 0;
383*4882a593Smuzhiyun 	dpn = prop->sink_dpn_prop;
384*4882a593Smuzhiyun 	addr = prop->sink_ports;
385*4882a593Smuzhiyun 	for_each_set_bit(bit, &addr, 32) {
386*4882a593Smuzhiyun 		dpn[i].num = bit;
387*4882a593Smuzhiyun 		dpn[i].type = SDW_DPN_FULL;
388*4882a593Smuzhiyun 		dpn[i].simple_ch_prep_sm = true;
389*4882a593Smuzhiyun 		dpn[i].ch_prep_timeout = 10;
390*4882a593Smuzhiyun 		i++;
391*4882a593Smuzhiyun 	}
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	/* set the timeout values */
394*4882a593Smuzhiyun 	prop->clk_stop_timeout = 20;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	/* wake-up event */
397*4882a593Smuzhiyun 	prop->wake_capable = 1;
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	return 0;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun 
rt711_bus_config(struct sdw_slave * slave,struct sdw_bus_params * params)402*4882a593Smuzhiyun static int rt711_bus_config(struct sdw_slave *slave,
403*4882a593Smuzhiyun 				struct sdw_bus_params *params)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	struct rt711_priv *rt711 = dev_get_drvdata(&slave->dev);
406*4882a593Smuzhiyun 	int ret;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	memcpy(&rt711->params, params, sizeof(*params));
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	ret = rt711_clock_config(&slave->dev);
411*4882a593Smuzhiyun 	if (ret < 0)
412*4882a593Smuzhiyun 		dev_err(&slave->dev, "Invalid clk config");
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	return ret;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun 
rt711_interrupt_callback(struct sdw_slave * slave,struct sdw_slave_intr_status * status)417*4882a593Smuzhiyun static int rt711_interrupt_callback(struct sdw_slave *slave,
418*4882a593Smuzhiyun 					struct sdw_slave_intr_status *status)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun 	struct rt711_priv *rt711 = dev_get_drvdata(&slave->dev);
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	dev_dbg(&slave->dev,
423*4882a593Smuzhiyun 		"%s control_port_stat=%x", __func__, status->control_port);
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	if (status->control_port & 0x4) {
426*4882a593Smuzhiyun 		mod_delayed_work(system_power_efficient_wq,
427*4882a593Smuzhiyun 			&rt711->jack_detect_work, msecs_to_jiffies(250));
428*4882a593Smuzhiyun 	}
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	return 0;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun static struct sdw_slave_ops rt711_slave_ops = {
434*4882a593Smuzhiyun 	.read_prop = rt711_read_prop,
435*4882a593Smuzhiyun 	.interrupt_callback = rt711_interrupt_callback,
436*4882a593Smuzhiyun 	.update_status = rt711_update_status,
437*4882a593Smuzhiyun 	.bus_config = rt711_bus_config,
438*4882a593Smuzhiyun };
439*4882a593Smuzhiyun 
rt711_sdw_probe(struct sdw_slave * slave,const struct sdw_device_id * id)440*4882a593Smuzhiyun static int rt711_sdw_probe(struct sdw_slave *slave,
441*4882a593Smuzhiyun 				const struct sdw_device_id *id)
442*4882a593Smuzhiyun {
443*4882a593Smuzhiyun 	struct regmap *sdw_regmap, *regmap;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	/* Regmap Initialization */
446*4882a593Smuzhiyun 	sdw_regmap = devm_regmap_init_sdw(slave, &rt711_sdw_regmap);
447*4882a593Smuzhiyun 	if (IS_ERR(sdw_regmap))
448*4882a593Smuzhiyun 		return PTR_ERR(sdw_regmap);
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	regmap = devm_regmap_init(&slave->dev, NULL,
451*4882a593Smuzhiyun 		&slave->dev, &rt711_regmap);
452*4882a593Smuzhiyun 	if (IS_ERR(regmap))
453*4882a593Smuzhiyun 		return PTR_ERR(regmap);
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	rt711_init(&slave->dev, sdw_regmap, regmap, slave);
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	return 0;
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun 
rt711_sdw_remove(struct sdw_slave * slave)460*4882a593Smuzhiyun static int rt711_sdw_remove(struct sdw_slave *slave)
461*4882a593Smuzhiyun {
462*4882a593Smuzhiyun 	struct rt711_priv *rt711 = dev_get_drvdata(&slave->dev);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	if (rt711 && rt711->hw_init) {
465*4882a593Smuzhiyun 		cancel_delayed_work(&rt711->jack_detect_work);
466*4882a593Smuzhiyun 		cancel_delayed_work(&rt711->jack_btn_check_work);
467*4882a593Smuzhiyun 		cancel_work_sync(&rt711->calibration_work);
468*4882a593Smuzhiyun 	}
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	return 0;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun static const struct sdw_device_id rt711_id[] = {
474*4882a593Smuzhiyun 	SDW_SLAVE_ENTRY_EXT(0x025d, 0x711, 0x2, 0, 0),
475*4882a593Smuzhiyun 	{},
476*4882a593Smuzhiyun };
477*4882a593Smuzhiyun MODULE_DEVICE_TABLE(sdw, rt711_id);
478*4882a593Smuzhiyun 
rt711_dev_suspend(struct device * dev)479*4882a593Smuzhiyun static int __maybe_unused rt711_dev_suspend(struct device *dev)
480*4882a593Smuzhiyun {
481*4882a593Smuzhiyun 	struct rt711_priv *rt711 = dev_get_drvdata(dev);
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	if (!rt711->hw_init)
484*4882a593Smuzhiyun 		return 0;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	cancel_delayed_work_sync(&rt711->jack_detect_work);
487*4882a593Smuzhiyun 	cancel_delayed_work_sync(&rt711->jack_btn_check_work);
488*4882a593Smuzhiyun 	cancel_work_sync(&rt711->calibration_work);
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	regcache_cache_only(rt711->regmap, true);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	return 0;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun #define RT711_PROBE_TIMEOUT 2000
496*4882a593Smuzhiyun 
rt711_dev_resume(struct device * dev)497*4882a593Smuzhiyun static int __maybe_unused rt711_dev_resume(struct device *dev)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun 	struct sdw_slave *slave = dev_to_sdw_dev(dev);
500*4882a593Smuzhiyun 	struct rt711_priv *rt711 = dev_get_drvdata(dev);
501*4882a593Smuzhiyun 	unsigned long time;
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	if (!rt711->first_hw_init)
504*4882a593Smuzhiyun 		return 0;
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	if (!slave->unattach_request)
507*4882a593Smuzhiyun 		goto regmap_sync;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	time = wait_for_completion_timeout(&slave->initialization_complete,
510*4882a593Smuzhiyun 				msecs_to_jiffies(RT711_PROBE_TIMEOUT));
511*4882a593Smuzhiyun 	if (!time) {
512*4882a593Smuzhiyun 		dev_err(&slave->dev, "Initialization not complete, timed out\n");
513*4882a593Smuzhiyun 		return -ETIMEDOUT;
514*4882a593Smuzhiyun 	}
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun regmap_sync:
517*4882a593Smuzhiyun 	slave->unattach_request = 0;
518*4882a593Smuzhiyun 	regcache_cache_only(rt711->regmap, false);
519*4882a593Smuzhiyun 	regcache_sync_region(rt711->regmap, 0x3000, 0x8fff);
520*4882a593Smuzhiyun 	regcache_sync_region(rt711->regmap, 0x752009, 0x752091);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	return 0;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun static const struct dev_pm_ops rt711_pm = {
526*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(rt711_dev_suspend, rt711_dev_resume)
527*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(rt711_dev_suspend, rt711_dev_resume, NULL)
528*4882a593Smuzhiyun };
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun static struct sdw_driver rt711_sdw_driver = {
531*4882a593Smuzhiyun 	.driver = {
532*4882a593Smuzhiyun 		.name = "rt711",
533*4882a593Smuzhiyun 		.owner = THIS_MODULE,
534*4882a593Smuzhiyun 		.pm = &rt711_pm,
535*4882a593Smuzhiyun 	},
536*4882a593Smuzhiyun 	.probe = rt711_sdw_probe,
537*4882a593Smuzhiyun 	.remove = rt711_sdw_remove,
538*4882a593Smuzhiyun 	.ops = &rt711_slave_ops,
539*4882a593Smuzhiyun 	.id_table = rt711_id,
540*4882a593Smuzhiyun };
541*4882a593Smuzhiyun module_sdw_driver(rt711_sdw_driver);
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC RT711 SDW driver");
544*4882a593Smuzhiyun MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
545*4882a593Smuzhiyun MODULE_LICENSE("GPL");
546