xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/rt5682-sdw.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // rt5682-sdw.c  --  RT5682 ALSA SoC audio component driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright 2019 Realtek Semiconductor Corp.
6*4882a593Smuzhiyun // Author: Oder Chiou <oder_chiou@realtek.com>
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/moduleparam.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/pm.h>
14*4882a593Smuzhiyun #include <linux/acpi.h>
15*4882a593Smuzhiyun #include <linux/gpio.h>
16*4882a593Smuzhiyun #include <linux/of_gpio.h>
17*4882a593Smuzhiyun #include <linux/pm_runtime.h>
18*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
19*4882a593Smuzhiyun #include <linux/mutex.h>
20*4882a593Smuzhiyun #include <linux/soundwire/sdw.h>
21*4882a593Smuzhiyun #include <linux/soundwire/sdw_type.h>
22*4882a593Smuzhiyun #include <linux/soundwire/sdw_registers.h>
23*4882a593Smuzhiyun #include <sound/core.h>
24*4882a593Smuzhiyun #include <sound/pcm.h>
25*4882a593Smuzhiyun #include <sound/pcm_params.h>
26*4882a593Smuzhiyun #include <sound/jack.h>
27*4882a593Smuzhiyun #include <sound/soc.h>
28*4882a593Smuzhiyun #include <sound/soc-dapm.h>
29*4882a593Smuzhiyun #include <sound/initval.h>
30*4882a593Smuzhiyun #include <sound/tlv.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #include "rt5682.h"
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define RT5682_SDW_ADDR_L			0x3000
35*4882a593Smuzhiyun #define RT5682_SDW_ADDR_H			0x3001
36*4882a593Smuzhiyun #define RT5682_SDW_DATA_L			0x3004
37*4882a593Smuzhiyun #define RT5682_SDW_DATA_H			0x3005
38*4882a593Smuzhiyun #define RT5682_SDW_CMD				0x3008
39*4882a593Smuzhiyun 
rt5682_sdw_read(void * context,unsigned int reg,unsigned int * val)40*4882a593Smuzhiyun static int rt5682_sdw_read(void *context, unsigned int reg, unsigned int *val)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	struct device *dev = context;
43*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
44*4882a593Smuzhiyun 	unsigned int data_l, data_h;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 0);
47*4882a593Smuzhiyun 	regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
48*4882a593Smuzhiyun 	regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
49*4882a593Smuzhiyun 	regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_H, &data_h);
50*4882a593Smuzhiyun 	regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_L, &data_l);
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	*val = (data_h << 8) | data_l;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	dev_vdbg(dev, "[%s] %04x => %04x\n", __func__, reg, *val);
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
rt5682_sdw_write(void * context,unsigned int reg,unsigned int val)59*4882a593Smuzhiyun static int rt5682_sdw_write(void *context, unsigned int reg, unsigned int val)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	struct device *dev = context;
62*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 1);
65*4882a593Smuzhiyun 	regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
66*4882a593Smuzhiyun 	regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
67*4882a593Smuzhiyun 	regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_H, (val >> 8) & 0xff);
68*4882a593Smuzhiyun 	regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_L, (val & 0xff));
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	dev_vdbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun static const struct regmap_config rt5682_sdw_indirect_regmap = {
76*4882a593Smuzhiyun 	.reg_bits = 16,
77*4882a593Smuzhiyun 	.val_bits = 16,
78*4882a593Smuzhiyun 	.max_register = RT5682_I2C_MODE,
79*4882a593Smuzhiyun 	.volatile_reg = rt5682_volatile_register,
80*4882a593Smuzhiyun 	.readable_reg = rt5682_readable_register,
81*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
82*4882a593Smuzhiyun 	.reg_defaults = rt5682_reg,
83*4882a593Smuzhiyun 	.num_reg_defaults = RT5682_REG_NUM,
84*4882a593Smuzhiyun 	.use_single_read = true,
85*4882a593Smuzhiyun 	.use_single_write = true,
86*4882a593Smuzhiyun 	.reg_read = rt5682_sdw_read,
87*4882a593Smuzhiyun 	.reg_write = rt5682_sdw_write,
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun struct sdw_stream_data {
91*4882a593Smuzhiyun 	struct sdw_stream_runtime *sdw_stream;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
rt5682_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)94*4882a593Smuzhiyun static int rt5682_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
95*4882a593Smuzhiyun 				 int direction)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	struct sdw_stream_data *stream;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	if (!sdw_stream)
100*4882a593Smuzhiyun 		return 0;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	stream = kzalloc(sizeof(*stream), GFP_KERNEL);
103*4882a593Smuzhiyun 	if (!stream)
104*4882a593Smuzhiyun 		return -ENOMEM;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	stream->sdw_stream = (struct sdw_stream_runtime *)sdw_stream;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	/* Use tx_mask or rx_mask to configure stream tag and set dma_data */
109*4882a593Smuzhiyun 	if (direction == SNDRV_PCM_STREAM_PLAYBACK)
110*4882a593Smuzhiyun 		dai->playback_dma_data = stream;
111*4882a593Smuzhiyun 	else
112*4882a593Smuzhiyun 		dai->capture_dma_data = stream;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun 
rt5682_sdw_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)117*4882a593Smuzhiyun static void rt5682_sdw_shutdown(struct snd_pcm_substream *substream,
118*4882a593Smuzhiyun 				struct snd_soc_dai *dai)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun 	struct sdw_stream_data *stream;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	stream = snd_soc_dai_get_dma_data(dai, substream);
123*4882a593Smuzhiyun 	snd_soc_dai_set_dma_data(dai, substream, NULL);
124*4882a593Smuzhiyun 	kfree(stream);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun 
rt5682_sdw_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)127*4882a593Smuzhiyun static int rt5682_sdw_hw_params(struct snd_pcm_substream *substream,
128*4882a593Smuzhiyun 				struct snd_pcm_hw_params *params,
129*4882a593Smuzhiyun 				struct snd_soc_dai *dai)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
132*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
133*4882a593Smuzhiyun 	struct sdw_stream_config stream_config;
134*4882a593Smuzhiyun 	struct sdw_port_config port_config;
135*4882a593Smuzhiyun 	enum sdw_data_direction direction;
136*4882a593Smuzhiyun 	struct sdw_stream_data *stream;
137*4882a593Smuzhiyun 	int retval, port, num_channels;
138*4882a593Smuzhiyun 	unsigned int val_p = 0, val_c = 0, osr_p = 0, osr_c = 0;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	dev_dbg(dai->dev, "%s %s", __func__, dai->name);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	stream = snd_soc_dai_get_dma_data(dai, substream);
143*4882a593Smuzhiyun 	if (!stream)
144*4882a593Smuzhiyun 		return -ENOMEM;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	if (!rt5682->slave)
147*4882a593Smuzhiyun 		return -EINVAL;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	/* SoundWire specific configuration */
150*4882a593Smuzhiyun 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
151*4882a593Smuzhiyun 		direction = SDW_DATA_DIR_RX;
152*4882a593Smuzhiyun 		port = 1;
153*4882a593Smuzhiyun 	} else {
154*4882a593Smuzhiyun 		direction = SDW_DATA_DIR_TX;
155*4882a593Smuzhiyun 		port = 2;
156*4882a593Smuzhiyun 	}
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	stream_config.frame_rate = params_rate(params);
159*4882a593Smuzhiyun 	stream_config.ch_count = params_channels(params);
160*4882a593Smuzhiyun 	stream_config.bps = snd_pcm_format_width(params_format(params));
161*4882a593Smuzhiyun 	stream_config.direction = direction;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	num_channels = params_channels(params);
164*4882a593Smuzhiyun 	port_config.ch_mask = (1 << (num_channels)) - 1;
165*4882a593Smuzhiyun 	port_config.num = port;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	retval = sdw_stream_add_slave(rt5682->slave, &stream_config,
168*4882a593Smuzhiyun 				      &port_config, 1, stream->sdw_stream);
169*4882a593Smuzhiyun 	if (retval) {
170*4882a593Smuzhiyun 		dev_err(dai->dev, "Unable to configure port\n");
171*4882a593Smuzhiyun 		return retval;
172*4882a593Smuzhiyun 	}
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	switch (params_rate(params)) {
175*4882a593Smuzhiyun 	case 48000:
176*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_48K;
177*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_48K;
178*4882a593Smuzhiyun 		break;
179*4882a593Smuzhiyun 	case 96000:
180*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_96K;
181*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_96K;
182*4882a593Smuzhiyun 		break;
183*4882a593Smuzhiyun 	case 192000:
184*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_192K;
185*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_192K;
186*4882a593Smuzhiyun 		break;
187*4882a593Smuzhiyun 	case 32000:
188*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_32K;
189*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_32K;
190*4882a593Smuzhiyun 		break;
191*4882a593Smuzhiyun 	case 24000:
192*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_24K;
193*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_24K;
194*4882a593Smuzhiyun 		break;
195*4882a593Smuzhiyun 	case 16000:
196*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_16K;
197*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_16K;
198*4882a593Smuzhiyun 		break;
199*4882a593Smuzhiyun 	case 12000:
200*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_12K;
201*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_12K;
202*4882a593Smuzhiyun 		break;
203*4882a593Smuzhiyun 	case 8000:
204*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_8K;
205*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_8K;
206*4882a593Smuzhiyun 		break;
207*4882a593Smuzhiyun 	case 44100:
208*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_44K;
209*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_44K;
210*4882a593Smuzhiyun 		break;
211*4882a593Smuzhiyun 	case 88200:
212*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_88K;
213*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_88K;
214*4882a593Smuzhiyun 		break;
215*4882a593Smuzhiyun 	case 176400:
216*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_176K;
217*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_176K;
218*4882a593Smuzhiyun 		break;
219*4882a593Smuzhiyun 	case 22050:
220*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_22K;
221*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_22K;
222*4882a593Smuzhiyun 		break;
223*4882a593Smuzhiyun 	case 11025:
224*4882a593Smuzhiyun 		val_p = RT5682_SDW_REF_1_11K;
225*4882a593Smuzhiyun 		val_c = RT5682_SDW_REF_2_11K;
226*4882a593Smuzhiyun 		break;
227*4882a593Smuzhiyun 	default:
228*4882a593Smuzhiyun 		return -EINVAL;
229*4882a593Smuzhiyun 	}
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	if (params_rate(params) <= 48000) {
232*4882a593Smuzhiyun 		osr_p = RT5682_DAC_OSR_D_8;
233*4882a593Smuzhiyun 		osr_c = RT5682_ADC_OSR_D_8;
234*4882a593Smuzhiyun 	} else if (params_rate(params) <= 96000) {
235*4882a593Smuzhiyun 		osr_p = RT5682_DAC_OSR_D_4;
236*4882a593Smuzhiyun 		osr_c = RT5682_ADC_OSR_D_4;
237*4882a593Smuzhiyun 	} else {
238*4882a593Smuzhiyun 		osr_p = RT5682_DAC_OSR_D_2;
239*4882a593Smuzhiyun 		osr_c = RT5682_ADC_OSR_D_2;
240*4882a593Smuzhiyun 	}
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
243*4882a593Smuzhiyun 		regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
244*4882a593Smuzhiyun 			RT5682_SDW_REF_1_MASK, val_p);
245*4882a593Smuzhiyun 		regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
246*4882a593Smuzhiyun 			RT5682_DAC_OSR_MASK, osr_p);
247*4882a593Smuzhiyun 	} else {
248*4882a593Smuzhiyun 		regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
249*4882a593Smuzhiyun 			RT5682_SDW_REF_2_MASK, val_c);
250*4882a593Smuzhiyun 		regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
251*4882a593Smuzhiyun 			RT5682_ADC_OSR_MASK, osr_c);
252*4882a593Smuzhiyun 	}
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	return retval;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
rt5682_sdw_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)257*4882a593Smuzhiyun static int rt5682_sdw_hw_free(struct snd_pcm_substream *substream,
258*4882a593Smuzhiyun 			      struct snd_soc_dai *dai)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
261*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
262*4882a593Smuzhiyun 	struct sdw_stream_data *stream =
263*4882a593Smuzhiyun 		snd_soc_dai_get_dma_data(dai, substream);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	if (!rt5682->slave)
266*4882a593Smuzhiyun 		return -EINVAL;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	sdw_stream_remove_slave(rt5682->slave, stream->sdw_stream);
269*4882a593Smuzhiyun 	return 0;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun static struct snd_soc_dai_ops rt5682_sdw_ops = {
273*4882a593Smuzhiyun 	.hw_params	= rt5682_sdw_hw_params,
274*4882a593Smuzhiyun 	.hw_free	= rt5682_sdw_hw_free,
275*4882a593Smuzhiyun 	.set_sdw_stream	= rt5682_set_sdw_stream,
276*4882a593Smuzhiyun 	.shutdown	= rt5682_sdw_shutdown,
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun static struct snd_soc_dai_driver rt5682_dai[] = {
280*4882a593Smuzhiyun 	{
281*4882a593Smuzhiyun 		.name = "rt5682-aif1",
282*4882a593Smuzhiyun 		.id = RT5682_AIF1,
283*4882a593Smuzhiyun 		.playback = {
284*4882a593Smuzhiyun 			.stream_name = "AIF1 Playback",
285*4882a593Smuzhiyun 			.channels_min = 1,
286*4882a593Smuzhiyun 			.channels_max = 2,
287*4882a593Smuzhiyun 			.rates = RT5682_STEREO_RATES,
288*4882a593Smuzhiyun 			.formats = RT5682_FORMATS,
289*4882a593Smuzhiyun 		},
290*4882a593Smuzhiyun 		.capture = {
291*4882a593Smuzhiyun 			.stream_name = "AIF1 Capture",
292*4882a593Smuzhiyun 			.channels_min = 1,
293*4882a593Smuzhiyun 			.channels_max = 2,
294*4882a593Smuzhiyun 			.rates = RT5682_STEREO_RATES,
295*4882a593Smuzhiyun 			.formats = RT5682_FORMATS,
296*4882a593Smuzhiyun 		},
297*4882a593Smuzhiyun 		.ops = &rt5682_aif1_dai_ops,
298*4882a593Smuzhiyun 	},
299*4882a593Smuzhiyun 	{
300*4882a593Smuzhiyun 		.name = "rt5682-aif2",
301*4882a593Smuzhiyun 		.id = RT5682_AIF2,
302*4882a593Smuzhiyun 		.capture = {
303*4882a593Smuzhiyun 			.stream_name = "AIF2 Capture",
304*4882a593Smuzhiyun 			.channels_min = 1,
305*4882a593Smuzhiyun 			.channels_max = 2,
306*4882a593Smuzhiyun 			.rates = RT5682_STEREO_RATES,
307*4882a593Smuzhiyun 			.formats = RT5682_FORMATS,
308*4882a593Smuzhiyun 		},
309*4882a593Smuzhiyun 		.ops = &rt5682_aif2_dai_ops,
310*4882a593Smuzhiyun 	},
311*4882a593Smuzhiyun 	{
312*4882a593Smuzhiyun 		.name = "rt5682-sdw",
313*4882a593Smuzhiyun 		.id = RT5682_SDW,
314*4882a593Smuzhiyun 		.playback = {
315*4882a593Smuzhiyun 			.stream_name = "SDW Playback",
316*4882a593Smuzhiyun 			.channels_min = 1,
317*4882a593Smuzhiyun 			.channels_max = 2,
318*4882a593Smuzhiyun 			.rates = RT5682_STEREO_RATES,
319*4882a593Smuzhiyun 			.formats = RT5682_FORMATS,
320*4882a593Smuzhiyun 		},
321*4882a593Smuzhiyun 		.capture = {
322*4882a593Smuzhiyun 			.stream_name = "SDW Capture",
323*4882a593Smuzhiyun 			.channels_min = 1,
324*4882a593Smuzhiyun 			.channels_max = 2,
325*4882a593Smuzhiyun 			.rates = RT5682_STEREO_RATES,
326*4882a593Smuzhiyun 			.formats = RT5682_FORMATS,
327*4882a593Smuzhiyun 		},
328*4882a593Smuzhiyun 		.ops = &rt5682_sdw_ops,
329*4882a593Smuzhiyun 	},
330*4882a593Smuzhiyun };
331*4882a593Smuzhiyun 
rt5682_sdw_init(struct device * dev,struct regmap * regmap,struct sdw_slave * slave)332*4882a593Smuzhiyun static int rt5682_sdw_init(struct device *dev, struct regmap *regmap,
333*4882a593Smuzhiyun 			   struct sdw_slave *slave)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun 	struct rt5682_priv *rt5682;
336*4882a593Smuzhiyun 	int ret;
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	rt5682 = devm_kzalloc(dev, sizeof(*rt5682), GFP_KERNEL);
339*4882a593Smuzhiyun 	if (!rt5682)
340*4882a593Smuzhiyun 		return -ENOMEM;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	dev_set_drvdata(dev, rt5682);
343*4882a593Smuzhiyun 	rt5682->slave = slave;
344*4882a593Smuzhiyun 	rt5682->sdw_regmap = regmap;
345*4882a593Smuzhiyun 	rt5682->is_sdw = true;
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	rt5682->regmap = devm_regmap_init(dev, NULL, dev,
348*4882a593Smuzhiyun 					  &rt5682_sdw_indirect_regmap);
349*4882a593Smuzhiyun 	if (IS_ERR(rt5682->regmap)) {
350*4882a593Smuzhiyun 		ret = PTR_ERR(rt5682->regmap);
351*4882a593Smuzhiyun 		dev_err(dev, "Failed to allocate register map: %d\n",
352*4882a593Smuzhiyun 			ret);
353*4882a593Smuzhiyun 		return ret;
354*4882a593Smuzhiyun 	}
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	/*
357*4882a593Smuzhiyun 	 * Mark hw_init to false
358*4882a593Smuzhiyun 	 * HW init will be performed when device reports present
359*4882a593Smuzhiyun 	 */
360*4882a593Smuzhiyun 	rt5682->hw_init = false;
361*4882a593Smuzhiyun 	rt5682->first_hw_init = false;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	mutex_init(&rt5682->calibrate_mutex);
364*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&rt5682->jack_detect_work,
365*4882a593Smuzhiyun 		rt5682_jack_detect_handler);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(dev,
368*4882a593Smuzhiyun 					      &rt5682_soc_component_dev,
369*4882a593Smuzhiyun 					      rt5682_dai, ARRAY_SIZE(rt5682_dai));
370*4882a593Smuzhiyun 	dev_dbg(&slave->dev, "%s\n", __func__);
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	return ret;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun 
rt5682_io_init(struct device * dev,struct sdw_slave * slave)375*4882a593Smuzhiyun static int rt5682_io_init(struct device *dev, struct sdw_slave *slave)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
378*4882a593Smuzhiyun 	int ret = 0, loop = 10;
379*4882a593Smuzhiyun 	unsigned int val;
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	if (rt5682->hw_init)
382*4882a593Smuzhiyun 		return 0;
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	/*
385*4882a593Smuzhiyun 	 * PM runtime is only enabled when a Slave reports as Attached
386*4882a593Smuzhiyun 	 */
387*4882a593Smuzhiyun 	if (!rt5682->first_hw_init) {
388*4882a593Smuzhiyun 		/* set autosuspend parameters */
389*4882a593Smuzhiyun 		pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
390*4882a593Smuzhiyun 		pm_runtime_use_autosuspend(&slave->dev);
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 		/* update count of parent 'active' children */
393*4882a593Smuzhiyun 		pm_runtime_set_active(&slave->dev);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 		/* make sure the device does not suspend immediately */
396*4882a593Smuzhiyun 		pm_runtime_mark_last_busy(&slave->dev);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 		pm_runtime_enable(&slave->dev);
399*4882a593Smuzhiyun 	}
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	pm_runtime_get_noresume(&slave->dev);
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	if (rt5682->first_hw_init) {
404*4882a593Smuzhiyun 		regcache_cache_only(rt5682->regmap, false);
405*4882a593Smuzhiyun 		regcache_cache_bypass(rt5682->regmap, true);
406*4882a593Smuzhiyun 	}
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	while (loop > 0) {
409*4882a593Smuzhiyun 		regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
410*4882a593Smuzhiyun 		if (val == DEVICE_ID)
411*4882a593Smuzhiyun 			break;
412*4882a593Smuzhiyun 		dev_warn(dev, "Device with ID register %x is not rt5682\n", val);
413*4882a593Smuzhiyun 		usleep_range(30000, 30005);
414*4882a593Smuzhiyun 		loop--;
415*4882a593Smuzhiyun 	}
416*4882a593Smuzhiyun 	if (val != DEVICE_ID) {
417*4882a593Smuzhiyun 		dev_err(dev, "Device with ID register %x is not rt5682\n", val);
418*4882a593Smuzhiyun 		return -ENODEV;
419*4882a593Smuzhiyun 	}
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	rt5682_calibrate(rt5682);
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	if (rt5682->first_hw_init) {
424*4882a593Smuzhiyun 		regcache_cache_bypass(rt5682->regmap, false);
425*4882a593Smuzhiyun 		regcache_mark_dirty(rt5682->regmap);
426*4882a593Smuzhiyun 		regcache_sync(rt5682->regmap);
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 		/* volatile registers */
429*4882a593Smuzhiyun 		regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
430*4882a593Smuzhiyun 			RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 		goto reinit;
433*4882a593Smuzhiyun 	}
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	rt5682_apply_patch_list(rt5682, dev);
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
440*4882a593Smuzhiyun 		RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
441*4882a593Smuzhiyun 		RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
442*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
443*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
444*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
445*4882a593Smuzhiyun 		RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
446*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
447*4882a593Smuzhiyun 		RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
448*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1,
449*4882a593Smuzhiyun 		RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	/* Soundwire */
452*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_PLL2_INTERNAL, 0xa266);
453*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_1, 0x1700);
454*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_2, 0x0006);
455*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_3, 0x2600);
456*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_4, 0x0c8f);
457*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_PLL_TRACK_2, 0x3000);
458*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_PLL_TRACK_3, 0x4000);
459*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_GLB_CLK,
460*4882a593Smuzhiyun 		RT5682_SCLK_SRC_MASK | RT5682_PLL2_SRC_MASK,
461*4882a593Smuzhiyun 		RT5682_SCLK_SRC_PLL2 | RT5682_PLL2_SRC_SDW);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
464*4882a593Smuzhiyun 		RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
465*4882a593Smuzhiyun 	regmap_write(rt5682->regmap, RT5682_CBJ_CTRL_1, 0xd142);
466*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
467*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_3,
468*4882a593Smuzhiyun 		RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
469*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_SAR_IL_CMD_1,
470*4882a593Smuzhiyun 		RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
471*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
472*4882a593Smuzhiyun 		RT5682_POW_IRQ | RT5682_POW_JDH |
473*4882a593Smuzhiyun 		RT5682_POW_ANA, RT5682_POW_IRQ |
474*4882a593Smuzhiyun 		RT5682_POW_JDH | RT5682_POW_ANA);
475*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
476*4882a593Smuzhiyun 		RT5682_PWR_JDH, RT5682_PWR_JDH);
477*4882a593Smuzhiyun 	regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
478*4882a593Smuzhiyun 		RT5682_JD1_EN_MASK | RT5682_JD1_IRQ_MASK,
479*4882a593Smuzhiyun 		RT5682_JD1_EN | RT5682_JD1_IRQ_PUL);
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun reinit:
482*4882a593Smuzhiyun 	mod_delayed_work(system_power_efficient_wq,
483*4882a593Smuzhiyun 		&rt5682->jack_detect_work, msecs_to_jiffies(250));
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	/* Mark Slave initialization complete */
486*4882a593Smuzhiyun 	rt5682->hw_init = true;
487*4882a593Smuzhiyun 	rt5682->first_hw_init = true;
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	pm_runtime_mark_last_busy(&slave->dev);
490*4882a593Smuzhiyun 	pm_runtime_put_autosuspend(&slave->dev);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	return ret;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun 
rt5682_sdw_readable_register(struct device * dev,unsigned int reg)497*4882a593Smuzhiyun static bool rt5682_sdw_readable_register(struct device *dev, unsigned int reg)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun 	switch (reg) {
500*4882a593Smuzhiyun 	case 0x00e0:
501*4882a593Smuzhiyun 	case 0x00f0:
502*4882a593Smuzhiyun 	case 0x3000:
503*4882a593Smuzhiyun 	case 0x3001:
504*4882a593Smuzhiyun 	case 0x3004:
505*4882a593Smuzhiyun 	case 0x3005:
506*4882a593Smuzhiyun 	case 0x3008:
507*4882a593Smuzhiyun 		return true;
508*4882a593Smuzhiyun 	default:
509*4882a593Smuzhiyun 		return false;
510*4882a593Smuzhiyun 	}
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun static const struct regmap_config rt5682_sdw_regmap = {
514*4882a593Smuzhiyun 	.name = "sdw",
515*4882a593Smuzhiyun 	.reg_bits = 32,
516*4882a593Smuzhiyun 	.val_bits = 8,
517*4882a593Smuzhiyun 	.max_register = RT5682_I2C_MODE,
518*4882a593Smuzhiyun 	.readable_reg = rt5682_sdw_readable_register,
519*4882a593Smuzhiyun 	.cache_type = REGCACHE_NONE,
520*4882a593Smuzhiyun 	.use_single_read = true,
521*4882a593Smuzhiyun 	.use_single_write = true,
522*4882a593Smuzhiyun };
523*4882a593Smuzhiyun 
rt5682_update_status(struct sdw_slave * slave,enum sdw_slave_status status)524*4882a593Smuzhiyun static int rt5682_update_status(struct sdw_slave *slave,
525*4882a593Smuzhiyun 					enum sdw_slave_status status)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	/* Update the status */
530*4882a593Smuzhiyun 	rt5682->status = status;
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	if (status == SDW_SLAVE_UNATTACHED)
533*4882a593Smuzhiyun 		rt5682->hw_init = false;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	/*
536*4882a593Smuzhiyun 	 * Perform initialization only if slave status is present and
537*4882a593Smuzhiyun 	 * hw_init flag is false
538*4882a593Smuzhiyun 	 */
539*4882a593Smuzhiyun 	if (rt5682->hw_init || rt5682->status != SDW_SLAVE_ATTACHED)
540*4882a593Smuzhiyun 		return 0;
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	/* perform I/O transfers required for Slave initialization */
543*4882a593Smuzhiyun 	return rt5682_io_init(&slave->dev, slave);
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun 
rt5682_read_prop(struct sdw_slave * slave)546*4882a593Smuzhiyun static int rt5682_read_prop(struct sdw_slave *slave)
547*4882a593Smuzhiyun {
548*4882a593Smuzhiyun 	struct sdw_slave_prop *prop = &slave->prop;
549*4882a593Smuzhiyun 	int nval, i;
550*4882a593Smuzhiyun 	u32 bit;
551*4882a593Smuzhiyun 	unsigned long addr;
552*4882a593Smuzhiyun 	struct sdw_dpn_prop *dpn;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
555*4882a593Smuzhiyun 		SDW_SCP_INT1_PARITY;
556*4882a593Smuzhiyun 	prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	prop->paging_support = false;
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 	/* first we need to allocate memory for set bits in port lists */
561*4882a593Smuzhiyun 	prop->source_ports = 0x4;	/* BITMAP: 00000100 */
562*4882a593Smuzhiyun 	prop->sink_ports = 0x2;		/* BITMAP: 00000010 */
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	nval = hweight32(prop->source_ports);
565*4882a593Smuzhiyun 	prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
566*4882a593Smuzhiyun 					  sizeof(*prop->src_dpn_prop),
567*4882a593Smuzhiyun 					  GFP_KERNEL);
568*4882a593Smuzhiyun 	if (!prop->src_dpn_prop)
569*4882a593Smuzhiyun 		return -ENOMEM;
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	i = 0;
572*4882a593Smuzhiyun 	dpn = prop->src_dpn_prop;
573*4882a593Smuzhiyun 	addr = prop->source_ports;
574*4882a593Smuzhiyun 	for_each_set_bit(bit, &addr, 32) {
575*4882a593Smuzhiyun 		dpn[i].num = bit;
576*4882a593Smuzhiyun 		dpn[i].type = SDW_DPN_FULL;
577*4882a593Smuzhiyun 		dpn[i].simple_ch_prep_sm = true;
578*4882a593Smuzhiyun 		dpn[i].ch_prep_timeout = 10;
579*4882a593Smuzhiyun 		i++;
580*4882a593Smuzhiyun 	}
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	/* do this again for sink now */
583*4882a593Smuzhiyun 	nval = hweight32(prop->sink_ports);
584*4882a593Smuzhiyun 	prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
585*4882a593Smuzhiyun 					   sizeof(*prop->sink_dpn_prop),
586*4882a593Smuzhiyun 					   GFP_KERNEL);
587*4882a593Smuzhiyun 	if (!prop->sink_dpn_prop)
588*4882a593Smuzhiyun 		return -ENOMEM;
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	i = 0;
591*4882a593Smuzhiyun 	dpn = prop->sink_dpn_prop;
592*4882a593Smuzhiyun 	addr = prop->sink_ports;
593*4882a593Smuzhiyun 	for_each_set_bit(bit, &addr, 32) {
594*4882a593Smuzhiyun 		dpn[i].num = bit;
595*4882a593Smuzhiyun 		dpn[i].type = SDW_DPN_FULL;
596*4882a593Smuzhiyun 		dpn[i].simple_ch_prep_sm = true;
597*4882a593Smuzhiyun 		dpn[i].ch_prep_timeout = 10;
598*4882a593Smuzhiyun 		i++;
599*4882a593Smuzhiyun 	}
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	/* set the timeout values */
602*4882a593Smuzhiyun 	prop->clk_stop_timeout = 20;
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 	/* wake-up event */
605*4882a593Smuzhiyun 	prop->wake_capable = 1;
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	return 0;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun /* Bus clock frequency */
611*4882a593Smuzhiyun #define RT5682_CLK_FREQ_9600000HZ 9600000
612*4882a593Smuzhiyun #define RT5682_CLK_FREQ_12000000HZ 12000000
613*4882a593Smuzhiyun #define RT5682_CLK_FREQ_6000000HZ 6000000
614*4882a593Smuzhiyun #define RT5682_CLK_FREQ_4800000HZ 4800000
615*4882a593Smuzhiyun #define RT5682_CLK_FREQ_2400000HZ 2400000
616*4882a593Smuzhiyun #define RT5682_CLK_FREQ_12288000HZ 12288000
617*4882a593Smuzhiyun 
rt5682_clock_config(struct device * dev)618*4882a593Smuzhiyun static int rt5682_clock_config(struct device *dev)
619*4882a593Smuzhiyun {
620*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
621*4882a593Smuzhiyun 	unsigned int clk_freq, value;
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	clk_freq = (rt5682->params.curr_dr_freq >> 1);
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	switch (clk_freq) {
626*4882a593Smuzhiyun 	case RT5682_CLK_FREQ_12000000HZ:
627*4882a593Smuzhiyun 		value = 0x0;
628*4882a593Smuzhiyun 		break;
629*4882a593Smuzhiyun 	case RT5682_CLK_FREQ_6000000HZ:
630*4882a593Smuzhiyun 		value = 0x1;
631*4882a593Smuzhiyun 		break;
632*4882a593Smuzhiyun 	case RT5682_CLK_FREQ_9600000HZ:
633*4882a593Smuzhiyun 		value = 0x2;
634*4882a593Smuzhiyun 		break;
635*4882a593Smuzhiyun 	case RT5682_CLK_FREQ_4800000HZ:
636*4882a593Smuzhiyun 		value = 0x3;
637*4882a593Smuzhiyun 		break;
638*4882a593Smuzhiyun 	case RT5682_CLK_FREQ_2400000HZ:
639*4882a593Smuzhiyun 		value = 0x4;
640*4882a593Smuzhiyun 		break;
641*4882a593Smuzhiyun 	case RT5682_CLK_FREQ_12288000HZ:
642*4882a593Smuzhiyun 		value = 0x5;
643*4882a593Smuzhiyun 		break;
644*4882a593Smuzhiyun 	default:
645*4882a593Smuzhiyun 		return -EINVAL;
646*4882a593Smuzhiyun 	}
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	regmap_write(rt5682->sdw_regmap, 0xe0, value);
649*4882a593Smuzhiyun 	regmap_write(rt5682->sdw_regmap, 0xf0, value);
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 	dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	return 0;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun 
rt5682_bus_config(struct sdw_slave * slave,struct sdw_bus_params * params)656*4882a593Smuzhiyun static int rt5682_bus_config(struct sdw_slave *slave,
657*4882a593Smuzhiyun 					struct sdw_bus_params *params)
658*4882a593Smuzhiyun {
659*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
660*4882a593Smuzhiyun 	int ret;
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun 	memcpy(&rt5682->params, params, sizeof(*params));
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	ret = rt5682_clock_config(&slave->dev);
665*4882a593Smuzhiyun 	if (ret < 0)
666*4882a593Smuzhiyun 		dev_err(&slave->dev, "Invalid clk config");
667*4882a593Smuzhiyun 
668*4882a593Smuzhiyun 	return ret;
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun 
rt5682_interrupt_callback(struct sdw_slave * slave,struct sdw_slave_intr_status * status)671*4882a593Smuzhiyun static int rt5682_interrupt_callback(struct sdw_slave *slave,
672*4882a593Smuzhiyun 					struct sdw_slave_intr_status *status)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	dev_dbg(&slave->dev,
677*4882a593Smuzhiyun 		"%s control_port_stat=%x", __func__, status->control_port);
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun 	if (status->control_port & 0x4) {
680*4882a593Smuzhiyun 		mod_delayed_work(system_power_efficient_wq,
681*4882a593Smuzhiyun 			&rt5682->jack_detect_work, msecs_to_jiffies(250));
682*4882a593Smuzhiyun 	}
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun 	return 0;
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun static struct sdw_slave_ops rt5682_slave_ops = {
688*4882a593Smuzhiyun 	.read_prop = rt5682_read_prop,
689*4882a593Smuzhiyun 	.interrupt_callback = rt5682_interrupt_callback,
690*4882a593Smuzhiyun 	.update_status = rt5682_update_status,
691*4882a593Smuzhiyun 	.bus_config = rt5682_bus_config,
692*4882a593Smuzhiyun };
693*4882a593Smuzhiyun 
rt5682_sdw_probe(struct sdw_slave * slave,const struct sdw_device_id * id)694*4882a593Smuzhiyun static int rt5682_sdw_probe(struct sdw_slave *slave,
695*4882a593Smuzhiyun 			   const struct sdw_device_id *id)
696*4882a593Smuzhiyun {
697*4882a593Smuzhiyun 	struct regmap *regmap;
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 	/* Regmap Initialization */
700*4882a593Smuzhiyun 	regmap = devm_regmap_init_sdw(slave, &rt5682_sdw_regmap);
701*4882a593Smuzhiyun 	if (IS_ERR(regmap))
702*4882a593Smuzhiyun 		return -EINVAL;
703*4882a593Smuzhiyun 
704*4882a593Smuzhiyun 	rt5682_sdw_init(&slave->dev, regmap, slave);
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	return 0;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun 
rt5682_sdw_remove(struct sdw_slave * slave)709*4882a593Smuzhiyun static int rt5682_sdw_remove(struct sdw_slave *slave)
710*4882a593Smuzhiyun {
711*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun 	if (rt5682 && rt5682->hw_init)
714*4882a593Smuzhiyun 		cancel_delayed_work(&rt5682->jack_detect_work);
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun 	return 0;
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun static const struct sdw_device_id rt5682_id[] = {
720*4882a593Smuzhiyun 	SDW_SLAVE_ENTRY_EXT(0x025d, 0x5682, 0x2, 0, 0),
721*4882a593Smuzhiyun 	{},
722*4882a593Smuzhiyun };
723*4882a593Smuzhiyun MODULE_DEVICE_TABLE(sdw, rt5682_id);
724*4882a593Smuzhiyun 
rt5682_dev_suspend(struct device * dev)725*4882a593Smuzhiyun static int __maybe_unused rt5682_dev_suspend(struct device *dev)
726*4882a593Smuzhiyun {
727*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	if (!rt5682->hw_init)
730*4882a593Smuzhiyun 		return 0;
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun 	regcache_cache_only(rt5682->regmap, true);
733*4882a593Smuzhiyun 	regcache_mark_dirty(rt5682->regmap);
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun 	return 0;
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun 
rt5682_dev_resume(struct device * dev)738*4882a593Smuzhiyun static int __maybe_unused rt5682_dev_resume(struct device *dev)
739*4882a593Smuzhiyun {
740*4882a593Smuzhiyun 	struct sdw_slave *slave = dev_to_sdw_dev(dev);
741*4882a593Smuzhiyun 	struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
742*4882a593Smuzhiyun 	unsigned long time;
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	if (!rt5682->first_hw_init)
745*4882a593Smuzhiyun 		return 0;
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun 	if (!slave->unattach_request)
748*4882a593Smuzhiyun 		goto regmap_sync;
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun 	time = wait_for_completion_timeout(&slave->initialization_complete,
751*4882a593Smuzhiyun 				msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
752*4882a593Smuzhiyun 	if (!time) {
753*4882a593Smuzhiyun 		dev_err(&slave->dev, "Initialization not complete, timed out\n");
754*4882a593Smuzhiyun 		return -ETIMEDOUT;
755*4882a593Smuzhiyun 	}
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun regmap_sync:
758*4882a593Smuzhiyun 	slave->unattach_request = 0;
759*4882a593Smuzhiyun 	regcache_cache_only(rt5682->regmap, false);
760*4882a593Smuzhiyun 	regcache_sync(rt5682->regmap);
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun 	return 0;
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun static const struct dev_pm_ops rt5682_pm = {
766*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(rt5682_dev_suspend, rt5682_dev_resume)
767*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(rt5682_dev_suspend, rt5682_dev_resume, NULL)
768*4882a593Smuzhiyun };
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun static struct sdw_driver rt5682_sdw_driver = {
771*4882a593Smuzhiyun 	.driver = {
772*4882a593Smuzhiyun 		.name = "rt5682",
773*4882a593Smuzhiyun 		.owner = THIS_MODULE,
774*4882a593Smuzhiyun 		.pm = &rt5682_pm,
775*4882a593Smuzhiyun 	},
776*4882a593Smuzhiyun 	.probe = rt5682_sdw_probe,
777*4882a593Smuzhiyun 	.remove = rt5682_sdw_remove,
778*4882a593Smuzhiyun 	.ops = &rt5682_slave_ops,
779*4882a593Smuzhiyun 	.id_table = rt5682_id,
780*4882a593Smuzhiyun };
781*4882a593Smuzhiyun module_sdw_driver(rt5682_sdw_driver);
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC RT5682 driver SDW");
784*4882a593Smuzhiyun MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
785*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
786