1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * rt5670-dsp.h -- RT5670 ALSA SoC DSP driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2014 Realtek Microelectronics 6*4882a593Smuzhiyun * Author: Bard Liao <bardliao@realtek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __RT5670_DSP_H__ 10*4882a593Smuzhiyun #define __RT5670_DSP_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define RT5670_DSP_CTRL1 0xe0 13*4882a593Smuzhiyun #define RT5670_DSP_CTRL2 0xe1 14*4882a593Smuzhiyun #define RT5670_DSP_CTRL3 0xe2 15*4882a593Smuzhiyun #define RT5670_DSP_CTRL4 0xe3 16*4882a593Smuzhiyun #define RT5670_DSP_CTRL5 0xe4 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* DSP Control 1 (0xe0) */ 19*4882a593Smuzhiyun #define RT5670_DSP_CMD_MASK (0xff << 8) 20*4882a593Smuzhiyun #define RT5670_DSP_CMD_PE (0x0d << 8) /* Patch Entry */ 21*4882a593Smuzhiyun #define RT5670_DSP_CMD_MW (0x3b << 8) /* Memory Write */ 22*4882a593Smuzhiyun #define RT5670_DSP_CMD_MR (0x37 << 8) /* Memory Read */ 23*4882a593Smuzhiyun #define RT5670_DSP_CMD_RR (0x60 << 8) /* Register Read */ 24*4882a593Smuzhiyun #define RT5670_DSP_CMD_RW (0x68 << 8) /* Register Write */ 25*4882a593Smuzhiyun #define RT5670_DSP_REG_DATHI (0x26 << 8) /* High Data Addr */ 26*4882a593Smuzhiyun #define RT5670_DSP_REG_DATLO (0x25 << 8) /* Low Data Addr */ 27*4882a593Smuzhiyun #define RT5670_DSP_CLK_MASK (0x3 << 6) 28*4882a593Smuzhiyun #define RT5670_DSP_CLK_SFT 6 29*4882a593Smuzhiyun #define RT5670_DSP_CLK_768K (0x0 << 6) 30*4882a593Smuzhiyun #define RT5670_DSP_CLK_384K (0x1 << 6) 31*4882a593Smuzhiyun #define RT5670_DSP_CLK_192K (0x2 << 6) 32*4882a593Smuzhiyun #define RT5670_DSP_CLK_96K (0x3 << 6) 33*4882a593Smuzhiyun #define RT5670_DSP_BUSY_MASK (0x1 << 5) 34*4882a593Smuzhiyun #define RT5670_DSP_RW_MASK (0x1 << 4) 35*4882a593Smuzhiyun #define RT5670_DSP_DL_MASK (0x3 << 2) 36*4882a593Smuzhiyun #define RT5670_DSP_DL_0 (0x0 << 2) 37*4882a593Smuzhiyun #define RT5670_DSP_DL_1 (0x1 << 2) 38*4882a593Smuzhiyun #define RT5670_DSP_DL_2 (0x2 << 2) 39*4882a593Smuzhiyun #define RT5670_DSP_DL_3 (0x3 << 2) 40*4882a593Smuzhiyun #define RT5670_DSP_I2C_AL_16 (0x1 << 1) 41*4882a593Smuzhiyun #define RT5670_DSP_CMD_EN (0x1) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct rt5670_dsp_param { 44*4882a593Smuzhiyun u16 cmd_fmt; 45*4882a593Smuzhiyun u16 addr; 46*4882a593Smuzhiyun u16 data; 47*4882a593Smuzhiyun u8 cmd; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif /* __RT5670_DSP_H__ */ 51*4882a593Smuzhiyun 52