1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * rt5660.c -- RT5660 ALSA SoC audio codec driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2016 Realtek Semiconductor Corp.
6*4882a593Smuzhiyun * Author: Oder Chiou <oder_chiou@realtek.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/moduleparam.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/pm.h>
14*4882a593Smuzhiyun #include <linux/gpio.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/of_gpio.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/spi/spi.h>
21*4882a593Smuzhiyun #include <linux/acpi.h>
22*4882a593Smuzhiyun #include <sound/core.h>
23*4882a593Smuzhiyun #include <sound/pcm.h>
24*4882a593Smuzhiyun #include <sound/pcm_params.h>
25*4882a593Smuzhiyun #include <sound/soc.h>
26*4882a593Smuzhiyun #include <sound/soc-dapm.h>
27*4882a593Smuzhiyun #include <sound/initval.h>
28*4882a593Smuzhiyun #include <sound/tlv.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "rl6231.h"
31*4882a593Smuzhiyun #include "rt5660.h"
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define RT5660_DEVICE_ID 0x6338
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define RT5660_PR_RANGE_BASE (0xff + 1)
36*4882a593Smuzhiyun #define RT5660_PR_SPACING 0x100
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define RT5660_PR_BASE (RT5660_PR_RANGE_BASE + (0 * RT5660_PR_SPACING))
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static const struct regmap_range_cfg rt5660_ranges[] = {
41*4882a593Smuzhiyun { .name = "PR", .range_min = RT5660_PR_BASE,
42*4882a593Smuzhiyun .range_max = RT5660_PR_BASE + 0xf3,
43*4882a593Smuzhiyun .selector_reg = RT5660_PRIV_INDEX,
44*4882a593Smuzhiyun .selector_mask = 0xff,
45*4882a593Smuzhiyun .selector_shift = 0x0,
46*4882a593Smuzhiyun .window_start = RT5660_PRIV_DATA,
47*4882a593Smuzhiyun .window_len = 0x1, },
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct reg_sequence rt5660_patch[] = {
51*4882a593Smuzhiyun { RT5660_ALC_PGA_CTRL2, 0x44c3 },
52*4882a593Smuzhiyun { RT5660_PR_BASE + 0x3d, 0x2600 },
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static const struct reg_default rt5660_reg[] = {
56*4882a593Smuzhiyun { 0x00, 0x0000 },
57*4882a593Smuzhiyun { 0x01, 0xc800 },
58*4882a593Smuzhiyun { 0x02, 0xc8c8 },
59*4882a593Smuzhiyun { 0x0d, 0x1010 },
60*4882a593Smuzhiyun { 0x0e, 0x1010 },
61*4882a593Smuzhiyun { 0x19, 0xafaf },
62*4882a593Smuzhiyun { 0x1c, 0x2f2f },
63*4882a593Smuzhiyun { 0x1e, 0x0000 },
64*4882a593Smuzhiyun { 0x27, 0x6060 },
65*4882a593Smuzhiyun { 0x29, 0x8080 },
66*4882a593Smuzhiyun { 0x2a, 0x4242 },
67*4882a593Smuzhiyun { 0x2f, 0x0000 },
68*4882a593Smuzhiyun { 0x3b, 0x0000 },
69*4882a593Smuzhiyun { 0x3c, 0x007f },
70*4882a593Smuzhiyun { 0x3d, 0x0000 },
71*4882a593Smuzhiyun { 0x3e, 0x007f },
72*4882a593Smuzhiyun { 0x45, 0xe000 },
73*4882a593Smuzhiyun { 0x46, 0x003e },
74*4882a593Smuzhiyun { 0x48, 0xf800 },
75*4882a593Smuzhiyun { 0x4a, 0x0004 },
76*4882a593Smuzhiyun { 0x4d, 0x0000 },
77*4882a593Smuzhiyun { 0x4e, 0x0000 },
78*4882a593Smuzhiyun { 0x4f, 0x01ff },
79*4882a593Smuzhiyun { 0x50, 0x0000 },
80*4882a593Smuzhiyun { 0x51, 0x0000 },
81*4882a593Smuzhiyun { 0x52, 0x01ff },
82*4882a593Smuzhiyun { 0x61, 0x0000 },
83*4882a593Smuzhiyun { 0x62, 0x0000 },
84*4882a593Smuzhiyun { 0x63, 0x00c0 },
85*4882a593Smuzhiyun { 0x64, 0x0000 },
86*4882a593Smuzhiyun { 0x65, 0x0000 },
87*4882a593Smuzhiyun { 0x66, 0x0000 },
88*4882a593Smuzhiyun { 0x70, 0x8000 },
89*4882a593Smuzhiyun { 0x73, 0x7000 },
90*4882a593Smuzhiyun { 0x74, 0x3c00 },
91*4882a593Smuzhiyun { 0x75, 0x2800 },
92*4882a593Smuzhiyun { 0x80, 0x0000 },
93*4882a593Smuzhiyun { 0x81, 0x0000 },
94*4882a593Smuzhiyun { 0x82, 0x0000 },
95*4882a593Smuzhiyun { 0x8c, 0x0228 },
96*4882a593Smuzhiyun { 0x8d, 0xa000 },
97*4882a593Smuzhiyun { 0x8e, 0x0000 },
98*4882a593Smuzhiyun { 0x92, 0x0000 },
99*4882a593Smuzhiyun { 0x93, 0x3000 },
100*4882a593Smuzhiyun { 0xa1, 0x0059 },
101*4882a593Smuzhiyun { 0xa2, 0x0001 },
102*4882a593Smuzhiyun { 0xa3, 0x5c80 },
103*4882a593Smuzhiyun { 0xa4, 0x0146 },
104*4882a593Smuzhiyun { 0xa5, 0x1f1f },
105*4882a593Smuzhiyun { 0xa6, 0x78c6 },
106*4882a593Smuzhiyun { 0xa7, 0xe5ec },
107*4882a593Smuzhiyun { 0xa8, 0xba61 },
108*4882a593Smuzhiyun { 0xa9, 0x3c78 },
109*4882a593Smuzhiyun { 0xaa, 0x8ae2 },
110*4882a593Smuzhiyun { 0xab, 0xe5ec },
111*4882a593Smuzhiyun { 0xac, 0xc600 },
112*4882a593Smuzhiyun { 0xad, 0xba61 },
113*4882a593Smuzhiyun { 0xae, 0x17ed },
114*4882a593Smuzhiyun { 0xb0, 0x2080 },
115*4882a593Smuzhiyun { 0xb1, 0x0000 },
116*4882a593Smuzhiyun { 0xb3, 0x001f },
117*4882a593Smuzhiyun { 0xb4, 0x020c },
118*4882a593Smuzhiyun { 0xb5, 0x1f00 },
119*4882a593Smuzhiyun { 0xb6, 0x0000 },
120*4882a593Smuzhiyun { 0xb7, 0x4000 },
121*4882a593Smuzhiyun { 0xbb, 0x0000 },
122*4882a593Smuzhiyun { 0xbd, 0x0000 },
123*4882a593Smuzhiyun { 0xbe, 0x0000 },
124*4882a593Smuzhiyun { 0xbf, 0x0100 },
125*4882a593Smuzhiyun { 0xc0, 0x0000 },
126*4882a593Smuzhiyun { 0xc2, 0x0000 },
127*4882a593Smuzhiyun { 0xd3, 0xa220 },
128*4882a593Smuzhiyun { 0xd9, 0x0809 },
129*4882a593Smuzhiyun { 0xda, 0x0000 },
130*4882a593Smuzhiyun { 0xe0, 0x8000 },
131*4882a593Smuzhiyun { 0xe1, 0x0200 },
132*4882a593Smuzhiyun { 0xe2, 0x8000 },
133*4882a593Smuzhiyun { 0xe3, 0x0200 },
134*4882a593Smuzhiyun { 0xe4, 0x0f20 },
135*4882a593Smuzhiyun { 0xe5, 0x001f },
136*4882a593Smuzhiyun { 0xe6, 0x020c },
137*4882a593Smuzhiyun { 0xe7, 0x1f00 },
138*4882a593Smuzhiyun { 0xe8, 0x0000 },
139*4882a593Smuzhiyun { 0xe9, 0x4000 },
140*4882a593Smuzhiyun { 0xea, 0x00a6 },
141*4882a593Smuzhiyun { 0xeb, 0x04c3 },
142*4882a593Smuzhiyun { 0xec, 0x27c8 },
143*4882a593Smuzhiyun { 0xed, 0x7418 },
144*4882a593Smuzhiyun { 0xee, 0xbf50 },
145*4882a593Smuzhiyun { 0xef, 0x0045 },
146*4882a593Smuzhiyun { 0xf0, 0x0007 },
147*4882a593Smuzhiyun { 0xfa, 0x0000 },
148*4882a593Smuzhiyun { 0xfd, 0x0000 },
149*4882a593Smuzhiyun { 0xfe, 0x10ec },
150*4882a593Smuzhiyun { 0xff, 0x6338 },
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
rt5660_volatile_register(struct device * dev,unsigned int reg)153*4882a593Smuzhiyun static bool rt5660_volatile_register(struct device *dev, unsigned int reg)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun int i;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(rt5660_ranges); i++)
158*4882a593Smuzhiyun if ((reg >= rt5660_ranges[i].window_start &&
159*4882a593Smuzhiyun reg <= rt5660_ranges[i].window_start +
160*4882a593Smuzhiyun rt5660_ranges[i].window_len) ||
161*4882a593Smuzhiyun (reg >= rt5660_ranges[i].range_min &&
162*4882a593Smuzhiyun reg <= rt5660_ranges[i].range_max))
163*4882a593Smuzhiyun return true;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun switch (reg) {
166*4882a593Smuzhiyun case RT5660_RESET:
167*4882a593Smuzhiyun case RT5660_PRIV_DATA:
168*4882a593Smuzhiyun case RT5660_EQ_CTRL1:
169*4882a593Smuzhiyun case RT5660_IRQ_CTRL2:
170*4882a593Smuzhiyun case RT5660_INT_IRQ_ST:
171*4882a593Smuzhiyun case RT5660_VENDOR_ID:
172*4882a593Smuzhiyun case RT5660_VENDOR_ID1:
173*4882a593Smuzhiyun case RT5660_VENDOR_ID2:
174*4882a593Smuzhiyun return true;
175*4882a593Smuzhiyun default:
176*4882a593Smuzhiyun return false;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
rt5660_readable_register(struct device * dev,unsigned int reg)180*4882a593Smuzhiyun static bool rt5660_readable_register(struct device *dev, unsigned int reg)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun int i;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(rt5660_ranges); i++)
185*4882a593Smuzhiyun if ((reg >= rt5660_ranges[i].window_start &&
186*4882a593Smuzhiyun reg <= rt5660_ranges[i].window_start +
187*4882a593Smuzhiyun rt5660_ranges[i].window_len) ||
188*4882a593Smuzhiyun (reg >= rt5660_ranges[i].range_min &&
189*4882a593Smuzhiyun reg <= rt5660_ranges[i].range_max))
190*4882a593Smuzhiyun return true;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun switch (reg) {
193*4882a593Smuzhiyun case RT5660_RESET:
194*4882a593Smuzhiyun case RT5660_SPK_VOL:
195*4882a593Smuzhiyun case RT5660_LOUT_VOL:
196*4882a593Smuzhiyun case RT5660_IN1_IN2:
197*4882a593Smuzhiyun case RT5660_IN3_IN4:
198*4882a593Smuzhiyun case RT5660_DAC1_DIG_VOL:
199*4882a593Smuzhiyun case RT5660_STO1_ADC_DIG_VOL:
200*4882a593Smuzhiyun case RT5660_ADC_BST_VOL1:
201*4882a593Smuzhiyun case RT5660_STO1_ADC_MIXER:
202*4882a593Smuzhiyun case RT5660_AD_DA_MIXER:
203*4882a593Smuzhiyun case RT5660_STO_DAC_MIXER:
204*4882a593Smuzhiyun case RT5660_DIG_INF1_DATA:
205*4882a593Smuzhiyun case RT5660_REC_L1_MIXER:
206*4882a593Smuzhiyun case RT5660_REC_L2_MIXER:
207*4882a593Smuzhiyun case RT5660_REC_R1_MIXER:
208*4882a593Smuzhiyun case RT5660_REC_R2_MIXER:
209*4882a593Smuzhiyun case RT5660_LOUT_MIXER:
210*4882a593Smuzhiyun case RT5660_SPK_MIXER:
211*4882a593Smuzhiyun case RT5660_SPO_MIXER:
212*4882a593Smuzhiyun case RT5660_SPO_CLSD_RATIO:
213*4882a593Smuzhiyun case RT5660_OUT_L_GAIN1:
214*4882a593Smuzhiyun case RT5660_OUT_L_GAIN2:
215*4882a593Smuzhiyun case RT5660_OUT_L1_MIXER:
216*4882a593Smuzhiyun case RT5660_OUT_R_GAIN1:
217*4882a593Smuzhiyun case RT5660_OUT_R_GAIN2:
218*4882a593Smuzhiyun case RT5660_OUT_R1_MIXER:
219*4882a593Smuzhiyun case RT5660_PWR_DIG1:
220*4882a593Smuzhiyun case RT5660_PWR_DIG2:
221*4882a593Smuzhiyun case RT5660_PWR_ANLG1:
222*4882a593Smuzhiyun case RT5660_PWR_ANLG2:
223*4882a593Smuzhiyun case RT5660_PWR_MIXER:
224*4882a593Smuzhiyun case RT5660_PWR_VOL:
225*4882a593Smuzhiyun case RT5660_PRIV_INDEX:
226*4882a593Smuzhiyun case RT5660_PRIV_DATA:
227*4882a593Smuzhiyun case RT5660_I2S1_SDP:
228*4882a593Smuzhiyun case RT5660_ADDA_CLK1:
229*4882a593Smuzhiyun case RT5660_ADDA_CLK2:
230*4882a593Smuzhiyun case RT5660_DMIC_CTRL1:
231*4882a593Smuzhiyun case RT5660_GLB_CLK:
232*4882a593Smuzhiyun case RT5660_PLL_CTRL1:
233*4882a593Smuzhiyun case RT5660_PLL_CTRL2:
234*4882a593Smuzhiyun case RT5660_CLSD_AMP_OC_CTRL:
235*4882a593Smuzhiyun case RT5660_CLSD_AMP_CTRL:
236*4882a593Smuzhiyun case RT5660_LOUT_AMP_CTRL:
237*4882a593Smuzhiyun case RT5660_SPK_AMP_SPKVDD:
238*4882a593Smuzhiyun case RT5660_MICBIAS:
239*4882a593Smuzhiyun case RT5660_CLSD_OUT_CTRL1:
240*4882a593Smuzhiyun case RT5660_CLSD_OUT_CTRL2:
241*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL1:
242*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL2:
243*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL3:
244*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL4:
245*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL5:
246*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL6:
247*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL7:
248*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL8:
249*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL9:
250*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL10:
251*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL11:
252*4882a593Smuzhiyun case RT5660_DIPOLE_MIC_CTRL12:
253*4882a593Smuzhiyun case RT5660_EQ_CTRL1:
254*4882a593Smuzhiyun case RT5660_EQ_CTRL2:
255*4882a593Smuzhiyun case RT5660_DRC_AGC_CTRL1:
256*4882a593Smuzhiyun case RT5660_DRC_AGC_CTRL2:
257*4882a593Smuzhiyun case RT5660_DRC_AGC_CTRL3:
258*4882a593Smuzhiyun case RT5660_DRC_AGC_CTRL4:
259*4882a593Smuzhiyun case RT5660_DRC_AGC_CTRL5:
260*4882a593Smuzhiyun case RT5660_JD_CTRL:
261*4882a593Smuzhiyun case RT5660_IRQ_CTRL1:
262*4882a593Smuzhiyun case RT5660_IRQ_CTRL2:
263*4882a593Smuzhiyun case RT5660_INT_IRQ_ST:
264*4882a593Smuzhiyun case RT5660_GPIO_CTRL1:
265*4882a593Smuzhiyun case RT5660_GPIO_CTRL2:
266*4882a593Smuzhiyun case RT5660_WIND_FILTER_CTRL1:
267*4882a593Smuzhiyun case RT5660_SV_ZCD1:
268*4882a593Smuzhiyun case RT5660_SV_ZCD2:
269*4882a593Smuzhiyun case RT5660_DRC1_LM_CTRL1:
270*4882a593Smuzhiyun case RT5660_DRC1_LM_CTRL2:
271*4882a593Smuzhiyun case RT5660_DRC2_LM_CTRL1:
272*4882a593Smuzhiyun case RT5660_DRC2_LM_CTRL2:
273*4882a593Smuzhiyun case RT5660_MULTI_DRC_CTRL:
274*4882a593Smuzhiyun case RT5660_DRC2_CTRL1:
275*4882a593Smuzhiyun case RT5660_DRC2_CTRL2:
276*4882a593Smuzhiyun case RT5660_DRC2_CTRL3:
277*4882a593Smuzhiyun case RT5660_DRC2_CTRL4:
278*4882a593Smuzhiyun case RT5660_DRC2_CTRL5:
279*4882a593Smuzhiyun case RT5660_ALC_PGA_CTRL1:
280*4882a593Smuzhiyun case RT5660_ALC_PGA_CTRL2:
281*4882a593Smuzhiyun case RT5660_ALC_PGA_CTRL3:
282*4882a593Smuzhiyun case RT5660_ALC_PGA_CTRL4:
283*4882a593Smuzhiyun case RT5660_ALC_PGA_CTRL5:
284*4882a593Smuzhiyun case RT5660_ALC_PGA_CTRL6:
285*4882a593Smuzhiyun case RT5660_ALC_PGA_CTRL7:
286*4882a593Smuzhiyun case RT5660_GEN_CTRL1:
287*4882a593Smuzhiyun case RT5660_GEN_CTRL2:
288*4882a593Smuzhiyun case RT5660_GEN_CTRL3:
289*4882a593Smuzhiyun case RT5660_VENDOR_ID:
290*4882a593Smuzhiyun case RT5660_VENDOR_ID1:
291*4882a593Smuzhiyun case RT5660_VENDOR_ID2:
292*4882a593Smuzhiyun return true;
293*4882a593Smuzhiyun default:
294*4882a593Smuzhiyun return false;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(rt5660_out_vol_tlv, -4650, 150, 0);
299*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(rt5660_dac_vol_tlv, -6525, 75, 0);
300*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(rt5660_adc_vol_tlv, -1725, 75, 0);
301*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(rt5660_adc_bst_tlv, 0, 1200, 0);
302*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(rt5660_bst_tlv, -1200, 75, 0);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_snd_controls[] = {
305*4882a593Smuzhiyun /* Speaker Output Volume */
306*4882a593Smuzhiyun SOC_SINGLE("Speaker Playback Switch", RT5660_SPK_VOL, RT5660_L_MUTE_SFT,
307*4882a593Smuzhiyun 1, 1),
308*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker Playback Volume", RT5660_SPK_VOL,
309*4882a593Smuzhiyun RT5660_L_VOL_SFT, 39, 1, rt5660_out_vol_tlv),
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /* OUTPUT Control */
312*4882a593Smuzhiyun SOC_DOUBLE("OUT Playback Switch", RT5660_LOUT_VOL, RT5660_L_MUTE_SFT,
313*4882a593Smuzhiyun RT5660_R_MUTE_SFT, 1, 1),
314*4882a593Smuzhiyun SOC_DOUBLE_TLV("OUT Playback Volume", RT5660_LOUT_VOL, RT5660_L_VOL_SFT,
315*4882a593Smuzhiyun RT5660_R_VOL_SFT, 39, 1, rt5660_out_vol_tlv),
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun /* DAC Digital Volume */
318*4882a593Smuzhiyun SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5660_DAC1_DIG_VOL,
319*4882a593Smuzhiyun RT5660_DAC_L1_VOL_SFT, RT5660_DAC_R1_VOL_SFT, 87, 0,
320*4882a593Smuzhiyun rt5660_dac_vol_tlv),
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* IN1/IN2/IN3 Control */
323*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1 Boost Volume", RT5660_IN1_IN2, RT5660_BST_SFT1, 69,
324*4882a593Smuzhiyun 0, rt5660_bst_tlv),
325*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2 Boost Volume", RT5660_IN1_IN2, RT5660_BST_SFT2, 69,
326*4882a593Smuzhiyun 0, rt5660_bst_tlv),
327*4882a593Smuzhiyun SOC_SINGLE_TLV("IN3 Boost Volume", RT5660_IN3_IN4, RT5660_BST_SFT3, 69,
328*4882a593Smuzhiyun 0, rt5660_bst_tlv),
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun /* ADC Digital Volume Control */
331*4882a593Smuzhiyun SOC_DOUBLE("ADC Capture Switch", RT5660_STO1_ADC_DIG_VOL,
332*4882a593Smuzhiyun RT5660_L_MUTE_SFT, RT5660_R_MUTE_SFT, 1, 1),
333*4882a593Smuzhiyun SOC_DOUBLE_TLV("ADC Capture Volume", RT5660_STO1_ADC_DIG_VOL,
334*4882a593Smuzhiyun RT5660_ADC_L_VOL_SFT, RT5660_ADC_R_VOL_SFT, 63, 0,
335*4882a593Smuzhiyun rt5660_adc_vol_tlv),
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun /* ADC Boost Volume Control */
338*4882a593Smuzhiyun SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5660_ADC_BST_VOL1,
339*4882a593Smuzhiyun RT5660_STO1_ADC_L_BST_SFT, RT5660_STO1_ADC_R_BST_SFT, 3, 0,
340*4882a593Smuzhiyun rt5660_adc_bst_tlv),
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun /**
344*4882a593Smuzhiyun * rt5660_set_dmic_clk - Set parameter of dmic.
345*4882a593Smuzhiyun *
346*4882a593Smuzhiyun * @w: DAPM widget.
347*4882a593Smuzhiyun * @kcontrol: The kcontrol of this widget.
348*4882a593Smuzhiyun * @event: Event id.
349*4882a593Smuzhiyun *
350*4882a593Smuzhiyun */
rt5660_set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)351*4882a593Smuzhiyun static int rt5660_set_dmic_clk(struct snd_soc_dapm_widget *w,
352*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
355*4882a593Smuzhiyun struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
356*4882a593Smuzhiyun int idx, rate;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun rate = rt5660->sysclk / rl6231_get_pre_div(rt5660->regmap,
359*4882a593Smuzhiyun RT5660_ADDA_CLK1, RT5660_I2S_PD1_SFT);
360*4882a593Smuzhiyun idx = rl6231_calc_dmic_clk(rate);
361*4882a593Smuzhiyun if (idx < 0)
362*4882a593Smuzhiyun dev_err(component->dev, "Failed to set DMIC clock\n");
363*4882a593Smuzhiyun else
364*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_DMIC_CTRL1,
365*4882a593Smuzhiyun RT5660_DMIC_CLK_MASK, idx << RT5660_DMIC_CLK_SFT);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun return idx;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
rt5660_is_sys_clk_from_pll(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)370*4882a593Smuzhiyun static int rt5660_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
371*4882a593Smuzhiyun struct snd_soc_dapm_widget *sink)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
374*4882a593Smuzhiyun unsigned int val;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun val = snd_soc_component_read(component, RT5660_GLB_CLK);
377*4882a593Smuzhiyun val &= RT5660_SCLK_SRC_MASK;
378*4882a593Smuzhiyun if (val == RT5660_SCLK_SRC_PLL1)
379*4882a593Smuzhiyun return 1;
380*4882a593Smuzhiyun else
381*4882a593Smuzhiyun return 0;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun /* Digital Mixer */
385*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_sto1_adc_l_mix[] = {
386*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC1 Switch", RT5660_STO1_ADC_MIXER,
387*4882a593Smuzhiyun RT5660_M_ADC_L1_SFT, 1, 1),
388*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC2 Switch", RT5660_STO1_ADC_MIXER,
389*4882a593Smuzhiyun RT5660_M_ADC_L2_SFT, 1, 1),
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_sto1_adc_r_mix[] = {
393*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC1 Switch", RT5660_STO1_ADC_MIXER,
394*4882a593Smuzhiyun RT5660_M_ADC_R1_SFT, 1, 1),
395*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC2 Switch", RT5660_STO1_ADC_MIXER,
396*4882a593Smuzhiyun RT5660_M_ADC_R2_SFT, 1, 1),
397*4882a593Smuzhiyun };
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_dac_l_mix[] = {
400*4882a593Smuzhiyun SOC_DAPM_SINGLE("Stereo ADC Switch", RT5660_AD_DA_MIXER,
401*4882a593Smuzhiyun RT5660_M_ADCMIX_L_SFT, 1, 1),
402*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC1 Switch", RT5660_AD_DA_MIXER,
403*4882a593Smuzhiyun RT5660_M_DAC1_L_SFT, 1, 1),
404*4882a593Smuzhiyun };
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_dac_r_mix[] = {
407*4882a593Smuzhiyun SOC_DAPM_SINGLE("Stereo ADC Switch", RT5660_AD_DA_MIXER,
408*4882a593Smuzhiyun RT5660_M_ADCMIX_R_SFT, 1, 1),
409*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC1 Switch", RT5660_AD_DA_MIXER,
410*4882a593Smuzhiyun RT5660_M_DAC1_R_SFT, 1, 1),
411*4882a593Smuzhiyun };
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_sto_dac_l_mix[] = {
414*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5660_STO_DAC_MIXER,
415*4882a593Smuzhiyun RT5660_M_DAC_L1_SFT, 1, 1),
416*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5660_STO_DAC_MIXER,
417*4882a593Smuzhiyun RT5660_M_DAC_R1_STO_L_SFT, 1, 1),
418*4882a593Smuzhiyun };
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_sto_dac_r_mix[] = {
421*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5660_STO_DAC_MIXER,
422*4882a593Smuzhiyun RT5660_M_DAC_R1_SFT, 1, 1),
423*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5660_STO_DAC_MIXER,
424*4882a593Smuzhiyun RT5660_M_DAC_L1_STO_R_SFT, 1, 1),
425*4882a593Smuzhiyun };
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun /* Analog Input Mixer */
428*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_rec_l_mix[] = {
429*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST3 Switch", RT5660_REC_L2_MIXER,
430*4882a593Smuzhiyun RT5660_M_BST3_RM_L_SFT, 1, 1),
431*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST2 Switch", RT5660_REC_L2_MIXER,
432*4882a593Smuzhiyun RT5660_M_BST2_RM_L_SFT, 1, 1),
433*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5660_REC_L2_MIXER,
434*4882a593Smuzhiyun RT5660_M_BST1_RM_L_SFT, 1, 1),
435*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUT MIXL Switch", RT5660_REC_L2_MIXER,
436*4882a593Smuzhiyun RT5660_M_OM_L_RM_L_SFT, 1, 1),
437*4882a593Smuzhiyun };
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_rec_r_mix[] = {
440*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST3 Switch", RT5660_REC_R2_MIXER,
441*4882a593Smuzhiyun RT5660_M_BST3_RM_R_SFT, 1, 1),
442*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST2 Switch", RT5660_REC_R2_MIXER,
443*4882a593Smuzhiyun RT5660_M_BST2_RM_R_SFT, 1, 1),
444*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5660_REC_R2_MIXER,
445*4882a593Smuzhiyun RT5660_M_BST1_RM_R_SFT, 1, 1),
446*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUT MIXR Switch", RT5660_REC_R2_MIXER,
447*4882a593Smuzhiyun RT5660_M_OM_R_RM_R_SFT, 1, 1),
448*4882a593Smuzhiyun };
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_spk_mix[] = {
451*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST3 Switch", RT5660_SPK_MIXER,
452*4882a593Smuzhiyun RT5660_M_BST3_SM_SFT, 1, 1),
453*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5660_SPK_MIXER,
454*4882a593Smuzhiyun RT5660_M_BST1_SM_SFT, 1, 1),
455*4882a593Smuzhiyun SOC_DAPM_SINGLE("DACL Switch", RT5660_SPK_MIXER,
456*4882a593Smuzhiyun RT5660_M_DACL_SM_SFT, 1, 1),
457*4882a593Smuzhiyun SOC_DAPM_SINGLE("DACR Switch", RT5660_SPK_MIXER,
458*4882a593Smuzhiyun RT5660_M_DACR_SM_SFT, 1, 1),
459*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUTMIXL Switch", RT5660_SPK_MIXER,
460*4882a593Smuzhiyun RT5660_M_OM_L_SM_SFT, 1, 1),
461*4882a593Smuzhiyun };
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_out_l_mix[] = {
464*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST3 Switch", RT5660_OUT_L1_MIXER,
465*4882a593Smuzhiyun RT5660_M_BST3_OM_L_SFT, 1, 1),
466*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST2 Switch", RT5660_OUT_L1_MIXER,
467*4882a593Smuzhiyun RT5660_M_BST2_OM_L_SFT, 1, 1),
468*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5660_OUT_L1_MIXER,
469*4882a593Smuzhiyun RT5660_M_BST1_OM_L_SFT, 1, 1),
470*4882a593Smuzhiyun SOC_DAPM_SINGLE("RECMIXL Switch", RT5660_OUT_L1_MIXER,
471*4882a593Smuzhiyun RT5660_M_RM_L_OM_L_SFT, 1, 1),
472*4882a593Smuzhiyun SOC_DAPM_SINGLE("DACR Switch", RT5660_OUT_L1_MIXER,
473*4882a593Smuzhiyun RT5660_M_DAC_R_OM_L_SFT, 1, 1),
474*4882a593Smuzhiyun SOC_DAPM_SINGLE("DACL Switch", RT5660_OUT_L1_MIXER,
475*4882a593Smuzhiyun RT5660_M_DAC_L_OM_L_SFT, 1, 1),
476*4882a593Smuzhiyun };
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_out_r_mix[] = {
479*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST2 Switch", RT5660_OUT_R1_MIXER,
480*4882a593Smuzhiyun RT5660_M_BST2_OM_R_SFT, 1, 1),
481*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5660_OUT_R1_MIXER,
482*4882a593Smuzhiyun RT5660_M_BST1_OM_R_SFT, 1, 1),
483*4882a593Smuzhiyun SOC_DAPM_SINGLE("RECMIXR Switch", RT5660_OUT_R1_MIXER,
484*4882a593Smuzhiyun RT5660_M_RM_R_OM_R_SFT, 1, 1),
485*4882a593Smuzhiyun SOC_DAPM_SINGLE("DACR Switch", RT5660_OUT_R1_MIXER,
486*4882a593Smuzhiyun RT5660_M_DAC_R_OM_R_SFT, 1, 1),
487*4882a593Smuzhiyun SOC_DAPM_SINGLE("DACL Switch", RT5660_OUT_R1_MIXER,
488*4882a593Smuzhiyun RT5660_M_DAC_L_OM_R_SFT, 1, 1),
489*4882a593Smuzhiyun };
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_spo_mix[] = {
492*4882a593Smuzhiyun SOC_DAPM_SINGLE("DACR Switch", RT5660_SPO_MIXER,
493*4882a593Smuzhiyun RT5660_M_DAC_R_SPM_SFT, 1, 1),
494*4882a593Smuzhiyun SOC_DAPM_SINGLE("DACL Switch", RT5660_SPO_MIXER,
495*4882a593Smuzhiyun RT5660_M_DAC_L_SPM_SFT, 1, 1),
496*4882a593Smuzhiyun SOC_DAPM_SINGLE("SPKVOL Switch", RT5660_SPO_MIXER,
497*4882a593Smuzhiyun RT5660_M_SV_SPM_SFT, 1, 1),
498*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5660_SPO_MIXER,
499*4882a593Smuzhiyun RT5660_M_BST1_SPM_SFT, 1, 1),
500*4882a593Smuzhiyun };
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_lout_mix[] = {
503*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC Switch", RT5660_LOUT_MIXER,
504*4882a593Smuzhiyun RT5660_M_DAC1_LM_SFT, 1, 1),
505*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUTMIX Switch", RT5660_LOUT_MIXER,
506*4882a593Smuzhiyun RT5660_M_LOVOL_LM_SFT, 1, 1),
507*4882a593Smuzhiyun };
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun static const struct snd_kcontrol_new spk_vol_control =
510*4882a593Smuzhiyun SOC_DAPM_SINGLE("Switch", RT5660_SPK_VOL,
511*4882a593Smuzhiyun RT5660_VOL_L_SFT, 1, 1);
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun static const struct snd_kcontrol_new lout_l_vol_control =
514*4882a593Smuzhiyun SOC_DAPM_SINGLE("Switch", RT5660_LOUT_VOL,
515*4882a593Smuzhiyun RT5660_VOL_L_SFT, 1, 1);
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun static const struct snd_kcontrol_new lout_r_vol_control =
518*4882a593Smuzhiyun SOC_DAPM_SINGLE("Switch", RT5660_LOUT_VOL,
519*4882a593Smuzhiyun RT5660_VOL_R_SFT, 1, 1);
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun /* Interface data select */
522*4882a593Smuzhiyun static const char * const rt5660_data_select[] = {
523*4882a593Smuzhiyun "L/R", "R/L", "L/L", "R/R"
524*4882a593Smuzhiyun };
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5660_if1_dac_enum,
527*4882a593Smuzhiyun RT5660_DIG_INF1_DATA, RT5660_IF1_DAC_IN_SFT, rt5660_data_select);
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5660_if1_adc_enum,
530*4882a593Smuzhiyun RT5660_DIG_INF1_DATA, RT5660_IF1_ADC_IN_SFT, rt5660_data_select);
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_if1_dac_swap_mux =
533*4882a593Smuzhiyun SOC_DAPM_ENUM("IF1 DAC Swap Source", rt5660_if1_dac_enum);
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5660_if1_adc_swap_mux =
536*4882a593Smuzhiyun SOC_DAPM_ENUM("IF1 ADC Swap Source", rt5660_if1_adc_enum);
537*4882a593Smuzhiyun
rt5660_lout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)538*4882a593Smuzhiyun static int rt5660_lout_event(struct snd_soc_dapm_widget *w,
539*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
540*4882a593Smuzhiyun {
541*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun switch (event) {
544*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
545*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_LOUT_AMP_CTRL,
546*4882a593Smuzhiyun RT5660_LOUT_CO_MASK | RT5660_LOUT_CB_MASK,
547*4882a593Smuzhiyun RT5660_LOUT_CO_EN | RT5660_LOUT_CB_PU);
548*4882a593Smuzhiyun break;
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
551*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_LOUT_AMP_CTRL,
552*4882a593Smuzhiyun RT5660_LOUT_CO_MASK | RT5660_LOUT_CB_MASK,
553*4882a593Smuzhiyun RT5660_LOUT_CO_DIS | RT5660_LOUT_CB_PD);
554*4882a593Smuzhiyun break;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun default:
557*4882a593Smuzhiyun return 0;
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun return 0;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun static const struct snd_soc_dapm_widget rt5660_dapm_widgets[] = {
564*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("LDO2", RT5660_PWR_ANLG1,
565*4882a593Smuzhiyun RT5660_PWR_LDO2_BIT, 0, NULL, 0),
566*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("PLL1", RT5660_PWR_ANLG2,
567*4882a593Smuzhiyun RT5660_PWR_PLL_BIT, 0, NULL, 0),
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun /* MICBIAS */
570*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5660_PWR_ANLG2,
571*4882a593Smuzhiyun RT5660_PWR_MB1_BIT, 0, NULL, 0),
572*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5660_PWR_ANLG2,
573*4882a593Smuzhiyun RT5660_PWR_MB2_BIT, 0, NULL, 0),
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun /* Input Side */
576*4882a593Smuzhiyun /* Input Lines */
577*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC L1"),
578*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC R1"),
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1P"),
581*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1N"),
582*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2P"),
583*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN3P"),
584*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN3N"),
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
587*4882a593Smuzhiyun rt5660_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
588*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMIC Power", RT5660_DMIC_CTRL1,
589*4882a593Smuzhiyun RT5660_DMIC_1_EN_SFT, 0, NULL, 0),
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun /* Boost */
592*4882a593Smuzhiyun SND_SOC_DAPM_PGA("BST1", RT5660_PWR_ANLG2, RT5660_PWR_BST1_BIT, 0,
593*4882a593Smuzhiyun NULL, 0),
594*4882a593Smuzhiyun SND_SOC_DAPM_PGA("BST2", RT5660_PWR_ANLG2, RT5660_PWR_BST2_BIT, 0,
595*4882a593Smuzhiyun NULL, 0),
596*4882a593Smuzhiyun SND_SOC_DAPM_PGA("BST3", RT5660_PWR_ANLG2, RT5660_PWR_BST3_BIT, 0,
597*4882a593Smuzhiyun NULL, 0),
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun /* REC Mixer */
600*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("RECMIXL", RT5660_PWR_MIXER, RT5660_PWR_RM_L_BIT,
601*4882a593Smuzhiyun 0, rt5660_rec_l_mix, ARRAY_SIZE(rt5660_rec_l_mix)),
602*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("RECMIXR", RT5660_PWR_MIXER, RT5660_PWR_RM_R_BIT,
603*4882a593Smuzhiyun 0, rt5660_rec_r_mix, ARRAY_SIZE(rt5660_rec_r_mix)),
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun /* ADCs */
606*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
607*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ADC L power", RT5660_PWR_DIG1,
610*4882a593Smuzhiyun RT5660_PWR_ADC_L_BIT, 0, NULL, 0),
611*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ADC R power", RT5660_PWR_DIG1,
612*4882a593Smuzhiyun RT5660_PWR_ADC_R_BIT, 0, NULL, 0),
613*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ADC clock", RT5660_PR_BASE + RT5660_CHOP_DAC_ADC,
614*4882a593Smuzhiyun 12, 0, NULL, 0),
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun /* ADC Mixer */
617*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5660_PWR_DIG2,
618*4882a593Smuzhiyun RT5660_PWR_ADC_S1F_BIT, 0, NULL, 0),
619*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
620*4882a593Smuzhiyun rt5660_sto1_adc_l_mix, ARRAY_SIZE(rt5660_sto1_adc_l_mix)),
621*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
622*4882a593Smuzhiyun rt5660_sto1_adc_r_mix, ARRAY_SIZE(rt5660_sto1_adc_r_mix)),
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun /* ADC */
625*4882a593Smuzhiyun SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5660_STO1_ADC_DIG_VOL,
626*4882a593Smuzhiyun RT5660_L_MUTE_SFT, 1),
627*4882a593Smuzhiyun SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5660_STO1_ADC_DIG_VOL,
628*4882a593Smuzhiyun RT5660_R_MUTE_SFT, 1),
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun /* Digital Interface */
631*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("I2S1", RT5660_PWR_DIG1, RT5660_PWR_I2S1_BIT, 0,
632*4882a593Smuzhiyun NULL, 0),
633*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
634*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
635*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
636*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IF1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
637*4882a593Smuzhiyun &rt5660_if1_dac_swap_mux),
638*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
639*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IF1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
640*4882a593Smuzhiyun &rt5660_if1_adc_swap_mux),
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun /* Audio Interface */
643*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
644*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun /* Output Side */
647*4882a593Smuzhiyun /* DAC mixer before sound effect */
648*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, rt5660_dac_l_mix,
649*4882a593Smuzhiyun ARRAY_SIZE(rt5660_dac_l_mix)),
650*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, rt5660_dac_r_mix,
651*4882a593Smuzhiyun ARRAY_SIZE(rt5660_dac_r_mix)),
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun /* DAC Mixer */
654*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5660_PWR_DIG2,
655*4882a593Smuzhiyun RT5660_PWR_DAC_S1F_BIT, 0, NULL, 0),
656*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
657*4882a593Smuzhiyun rt5660_sto_dac_l_mix, ARRAY_SIZE(rt5660_sto_dac_l_mix)),
658*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
659*4882a593Smuzhiyun rt5660_sto_dac_r_mix, ARRAY_SIZE(rt5660_sto_dac_r_mix)),
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun /* DACs */
662*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC L1", NULL, RT5660_PWR_DIG1,
663*4882a593Smuzhiyun RT5660_PWR_DAC_L1_BIT, 0),
664*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC R1", NULL, RT5660_PWR_DIG1,
665*4882a593Smuzhiyun RT5660_PWR_DAC_R1_BIT, 0),
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun /* OUT Mixer */
668*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("SPK MIX", RT5660_PWR_MIXER, RT5660_PWR_SM_BIT,
669*4882a593Smuzhiyun 0, rt5660_spk_mix, ARRAY_SIZE(rt5660_spk_mix)),
670*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("OUT MIXL", RT5660_PWR_MIXER, RT5660_PWR_OM_L_BIT,
671*4882a593Smuzhiyun 0, rt5660_out_l_mix, ARRAY_SIZE(rt5660_out_l_mix)),
672*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("OUT MIXR", RT5660_PWR_MIXER, RT5660_PWR_OM_R_BIT,
673*4882a593Smuzhiyun 0, rt5660_out_r_mix, ARRAY_SIZE(rt5660_out_r_mix)),
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun /* Output Volume */
676*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("SPKVOL", RT5660_PWR_VOL,
677*4882a593Smuzhiyun RT5660_PWR_SV_BIT, 0, &spk_vol_control),
678*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
679*4882a593Smuzhiyun 0, 0, NULL, 0),
680*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LOUTVOL", SND_SOC_NOPM,
681*4882a593Smuzhiyun 0, 0, NULL, 0),
682*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("LOUTVOL L", SND_SOC_NOPM,
683*4882a593Smuzhiyun RT5660_PWR_LV_L_BIT, 0, &lout_l_vol_control),
684*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("LOUTVOL R", SND_SOC_NOPM,
685*4882a593Smuzhiyun RT5660_PWR_LV_R_BIT, 0, &lout_r_vol_control),
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun /* HPO/LOUT/Mono Mixer */
688*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("SPO MIX", SND_SOC_NOPM, 0,
689*4882a593Smuzhiyun 0, rt5660_spo_mix, ARRAY_SIZE(rt5660_spo_mix)),
690*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
691*4882a593Smuzhiyun rt5660_lout_mix, ARRAY_SIZE(rt5660_lout_mix)),
692*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("VREF HP", RT5660_GEN_CTRL1,
693*4882a593Smuzhiyun RT5660_PWR_VREF_HP_SFT, 0, NULL, 0),
694*4882a593Smuzhiyun SND_SOC_DAPM_PGA_S("LOUT amp", 1, RT5660_PWR_ANLG1,
695*4882a593Smuzhiyun RT5660_PWR_HA_BIT, 0, rt5660_lout_event,
696*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
697*4882a593Smuzhiyun SND_SOC_DAPM_PGA_S("SPK amp", 1, RT5660_PWR_DIG1,
698*4882a593Smuzhiyun RT5660_PWR_CLS_D_BIT, 0, NULL, 0),
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun /* Output Lines */
701*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LOUTL"),
702*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LOUTR"),
703*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPO"),
704*4882a593Smuzhiyun };
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun static const struct snd_soc_dapm_route rt5660_dapm_routes[] = {
707*4882a593Smuzhiyun { "MICBIAS1", NULL, "LDO2" },
708*4882a593Smuzhiyun { "MICBIAS2", NULL, "LDO2" },
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun { "BST1", NULL, "IN1P" },
711*4882a593Smuzhiyun { "BST1", NULL, "IN1N" },
712*4882a593Smuzhiyun { "BST2", NULL, "IN2P" },
713*4882a593Smuzhiyun { "BST3", NULL, "IN3P" },
714*4882a593Smuzhiyun { "BST3", NULL, "IN3N" },
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun { "RECMIXL", "BST3 Switch", "BST3" },
717*4882a593Smuzhiyun { "RECMIXL", "BST2 Switch", "BST2" },
718*4882a593Smuzhiyun { "RECMIXL", "BST1 Switch", "BST1" },
719*4882a593Smuzhiyun { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun { "RECMIXR", "BST3 Switch", "BST3" },
722*4882a593Smuzhiyun { "RECMIXR", "BST2 Switch", "BST2" },
723*4882a593Smuzhiyun { "RECMIXR", "BST1 Switch", "BST1" },
724*4882a593Smuzhiyun { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun { "ADC L", NULL, "RECMIXL" },
727*4882a593Smuzhiyun { "ADC L", NULL, "ADC L power" },
728*4882a593Smuzhiyun { "ADC L", NULL, "ADC clock" },
729*4882a593Smuzhiyun { "ADC R", NULL, "RECMIXR" },
730*4882a593Smuzhiyun { "ADC R", NULL, "ADC R power" },
731*4882a593Smuzhiyun { "ADC R", NULL, "ADC clock" },
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun {"DMIC L1", NULL, "DMIC CLK"},
734*4882a593Smuzhiyun {"DMIC L1", NULL, "DMIC Power"},
735*4882a593Smuzhiyun {"DMIC R1", NULL, "DMIC CLK"},
736*4882a593Smuzhiyun {"DMIC R1", NULL, "DMIC Power"},
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun { "Sto1 ADC MIXL", "ADC1 Switch", "ADC L" },
739*4882a593Smuzhiyun { "Sto1 ADC MIXL", "ADC2 Switch", "DMIC L1" },
740*4882a593Smuzhiyun { "Sto1 ADC MIXR", "ADC1 Switch", "ADC R" },
741*4882a593Smuzhiyun { "Sto1 ADC MIXR", "ADC2 Switch", "DMIC R1" },
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
744*4882a593Smuzhiyun { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
745*4882a593Smuzhiyun { "adc stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll },
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
748*4882a593Smuzhiyun { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
749*4882a593Smuzhiyun { "adc stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll },
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun { "IF1 ADC", NULL, "Stereo1 ADC MIXL" },
752*4882a593Smuzhiyun { "IF1 ADC", NULL, "Stereo1 ADC MIXR" },
753*4882a593Smuzhiyun { "IF1 ADC", NULL, "I2S1" },
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun { "IF1 ADC Swap Mux", "L/R", "IF1 ADC" },
756*4882a593Smuzhiyun { "IF1 ADC Swap Mux", "R/L", "IF1 ADC" },
757*4882a593Smuzhiyun { "IF1 ADC Swap Mux", "L/L", "IF1 ADC" },
758*4882a593Smuzhiyun { "IF1 ADC Swap Mux", "R/R", "IF1 ADC" },
759*4882a593Smuzhiyun { "AIF1TX", NULL, "IF1 ADC Swap Mux" },
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun { "IF1 DAC", NULL, "AIF1RX" },
762*4882a593Smuzhiyun { "IF1 DAC", NULL, "I2S1" },
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun { "IF1 DAC Swap Mux", "L/R", "IF1 DAC" },
765*4882a593Smuzhiyun { "IF1 DAC Swap Mux", "R/L", "IF1 DAC" },
766*4882a593Smuzhiyun { "IF1 DAC Swap Mux", "L/L", "IF1 DAC" },
767*4882a593Smuzhiyun { "IF1 DAC Swap Mux", "R/R", "IF1 DAC" },
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun { "IF1 DAC L", NULL, "IF1 DAC Swap Mux" },
770*4882a593Smuzhiyun { "IF1 DAC R", NULL, "IF1 DAC Swap Mux" },
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
773*4882a593Smuzhiyun { "DAC1 MIXL", "DAC1 Switch", "IF1 DAC L" },
774*4882a593Smuzhiyun { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
775*4882a593Smuzhiyun { "DAC1 MIXR", "DAC1 Switch", "IF1 DAC R" },
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
778*4882a593Smuzhiyun { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
779*4882a593Smuzhiyun { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
780*4882a593Smuzhiyun { "dac stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll },
781*4882a593Smuzhiyun { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
782*4882a593Smuzhiyun { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
783*4882a593Smuzhiyun { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
784*4882a593Smuzhiyun { "dac stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll },
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun { "DAC L1", NULL, "Stereo DAC MIXL" },
787*4882a593Smuzhiyun { "DAC R1", NULL, "Stereo DAC MIXR" },
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun { "SPK MIX", "BST3 Switch", "BST3" },
790*4882a593Smuzhiyun { "SPK MIX", "BST1 Switch", "BST1" },
791*4882a593Smuzhiyun { "SPK MIX", "DACL Switch", "DAC L1" },
792*4882a593Smuzhiyun { "SPK MIX", "DACR Switch", "DAC R1" },
793*4882a593Smuzhiyun { "SPK MIX", "OUTMIXL Switch", "OUT MIXL" },
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun { "OUT MIXL", "BST3 Switch", "BST3" },
796*4882a593Smuzhiyun { "OUT MIXL", "BST2 Switch", "BST2" },
797*4882a593Smuzhiyun { "OUT MIXL", "BST1 Switch", "BST1" },
798*4882a593Smuzhiyun { "OUT MIXL", "RECMIXL Switch", "RECMIXL" },
799*4882a593Smuzhiyun { "OUT MIXL", "DACR Switch", "DAC R1" },
800*4882a593Smuzhiyun { "OUT MIXL", "DACL Switch", "DAC L1" },
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun { "OUT MIXR", "BST2 Switch", "BST2" },
803*4882a593Smuzhiyun { "OUT MIXR", "BST1 Switch", "BST1" },
804*4882a593Smuzhiyun { "OUT MIXR", "RECMIXR Switch", "RECMIXR" },
805*4882a593Smuzhiyun { "OUT MIXR", "DACR Switch", "DAC R1" },
806*4882a593Smuzhiyun { "OUT MIXR", "DACL Switch", "DAC L1" },
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun { "SPO MIX", "DACR Switch", "DAC R1" },
809*4882a593Smuzhiyun { "SPO MIX", "DACL Switch", "DAC L1" },
810*4882a593Smuzhiyun { "SPO MIX", "SPKVOL Switch", "SPKVOL" },
811*4882a593Smuzhiyun { "SPO MIX", "BST1 Switch", "BST1" },
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun { "SPKVOL", "Switch", "SPK MIX" },
814*4882a593Smuzhiyun { "LOUTVOL L", "Switch", "OUT MIXL" },
815*4882a593Smuzhiyun { "LOUTVOL R", "Switch", "OUT MIXR" },
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun { "LOUTVOL", NULL, "LOUTVOL L" },
818*4882a593Smuzhiyun { "LOUTVOL", NULL, "LOUTVOL R" },
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun { "DAC 1", NULL, "DAC L1" },
821*4882a593Smuzhiyun { "DAC 1", NULL, "DAC R1" },
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun { "LOUT MIX", "DAC Switch", "DAC 1" },
824*4882a593Smuzhiyun { "LOUT MIX", "OUTMIX Switch", "LOUTVOL" },
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun { "LOUT amp", NULL, "LOUT MIX" },
827*4882a593Smuzhiyun { "LOUT amp", NULL, "VREF HP" },
828*4882a593Smuzhiyun { "LOUTL", NULL, "LOUT amp" },
829*4882a593Smuzhiyun { "LOUTR", NULL, "LOUT amp" },
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun { "SPK amp", NULL, "SPO MIX" },
832*4882a593Smuzhiyun { "SPO", NULL, "SPK amp" },
833*4882a593Smuzhiyun };
834*4882a593Smuzhiyun
rt5660_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)835*4882a593Smuzhiyun static int rt5660_hw_params(struct snd_pcm_substream *substream,
836*4882a593Smuzhiyun struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
839*4882a593Smuzhiyun struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
840*4882a593Smuzhiyun unsigned int val_len = 0, val_clk, mask_clk;
841*4882a593Smuzhiyun int pre_div, bclk_ms, frame_size;
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun rt5660->lrck[dai->id] = params_rate(params);
844*4882a593Smuzhiyun pre_div = rl6231_get_clk_info(rt5660->sysclk, rt5660->lrck[dai->id]);
845*4882a593Smuzhiyun if (pre_div < 0) {
846*4882a593Smuzhiyun dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
847*4882a593Smuzhiyun rt5660->lrck[dai->id], dai->id);
848*4882a593Smuzhiyun return -EINVAL;
849*4882a593Smuzhiyun }
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun frame_size = snd_soc_params_to_frame_size(params);
852*4882a593Smuzhiyun if (frame_size < 0) {
853*4882a593Smuzhiyun dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
854*4882a593Smuzhiyun return frame_size;
855*4882a593Smuzhiyun }
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun if (frame_size > 32)
858*4882a593Smuzhiyun bclk_ms = 1;
859*4882a593Smuzhiyun else
860*4882a593Smuzhiyun bclk_ms = 0;
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun rt5660->bclk[dai->id] = rt5660->lrck[dai->id] * (32 << bclk_ms);
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
865*4882a593Smuzhiyun rt5660->bclk[dai->id], rt5660->lrck[dai->id]);
866*4882a593Smuzhiyun dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
867*4882a593Smuzhiyun bclk_ms, pre_div, dai->id);
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun switch (params_width(params)) {
870*4882a593Smuzhiyun case 16:
871*4882a593Smuzhiyun break;
872*4882a593Smuzhiyun case 20:
873*4882a593Smuzhiyun val_len |= RT5660_I2S_DL_20;
874*4882a593Smuzhiyun break;
875*4882a593Smuzhiyun case 24:
876*4882a593Smuzhiyun val_len |= RT5660_I2S_DL_24;
877*4882a593Smuzhiyun break;
878*4882a593Smuzhiyun case 8:
879*4882a593Smuzhiyun val_len |= RT5660_I2S_DL_8;
880*4882a593Smuzhiyun break;
881*4882a593Smuzhiyun default:
882*4882a593Smuzhiyun return -EINVAL;
883*4882a593Smuzhiyun }
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun switch (dai->id) {
886*4882a593Smuzhiyun case RT5660_AIF1:
887*4882a593Smuzhiyun mask_clk = RT5660_I2S_BCLK_MS1_MASK | RT5660_I2S_PD1_MASK;
888*4882a593Smuzhiyun val_clk = bclk_ms << RT5660_I2S_BCLK_MS1_SFT |
889*4882a593Smuzhiyun pre_div << RT5660_I2S_PD1_SFT;
890*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_I2S1_SDP, RT5660_I2S_DL_MASK,
891*4882a593Smuzhiyun val_len);
892*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_ADDA_CLK1, mask_clk, val_clk);
893*4882a593Smuzhiyun break;
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun default:
896*4882a593Smuzhiyun dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
897*4882a593Smuzhiyun return -EINVAL;
898*4882a593Smuzhiyun }
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun return 0;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun
rt5660_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)903*4882a593Smuzhiyun static int rt5660_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
904*4882a593Smuzhiyun {
905*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
906*4882a593Smuzhiyun struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
907*4882a593Smuzhiyun unsigned int reg_val = 0;
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
910*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
911*4882a593Smuzhiyun rt5660->master[dai->id] = 1;
912*4882a593Smuzhiyun break;
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
915*4882a593Smuzhiyun reg_val |= RT5660_I2S_MS_S;
916*4882a593Smuzhiyun rt5660->master[dai->id] = 0;
917*4882a593Smuzhiyun break;
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun default:
920*4882a593Smuzhiyun return -EINVAL;
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
924*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
925*4882a593Smuzhiyun break;
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
928*4882a593Smuzhiyun reg_val |= RT5660_I2S_BP_INV;
929*4882a593Smuzhiyun break;
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun default:
932*4882a593Smuzhiyun return -EINVAL;
933*4882a593Smuzhiyun }
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
936*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
937*4882a593Smuzhiyun break;
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
940*4882a593Smuzhiyun reg_val |= RT5660_I2S_DF_LEFT;
941*4882a593Smuzhiyun break;
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
944*4882a593Smuzhiyun reg_val |= RT5660_I2S_DF_PCM_A;
945*4882a593Smuzhiyun break;
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
948*4882a593Smuzhiyun reg_val |= RT5660_I2S_DF_PCM_B;
949*4882a593Smuzhiyun break;
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun default:
952*4882a593Smuzhiyun return -EINVAL;
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun switch (dai->id) {
956*4882a593Smuzhiyun case RT5660_AIF1:
957*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_I2S1_SDP,
958*4882a593Smuzhiyun RT5660_I2S_MS_MASK | RT5660_I2S_BP_MASK |
959*4882a593Smuzhiyun RT5660_I2S_DF_MASK, reg_val);
960*4882a593Smuzhiyun break;
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun default:
963*4882a593Smuzhiyun dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
964*4882a593Smuzhiyun return -EINVAL;
965*4882a593Smuzhiyun }
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun return 0;
968*4882a593Smuzhiyun }
969*4882a593Smuzhiyun
rt5660_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)970*4882a593Smuzhiyun static int rt5660_set_dai_sysclk(struct snd_soc_dai *dai,
971*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
974*4882a593Smuzhiyun struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
975*4882a593Smuzhiyun unsigned int reg_val = 0;
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun if (freq == rt5660->sysclk && clk_id == rt5660->sysclk_src)
978*4882a593Smuzhiyun return 0;
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun switch (clk_id) {
981*4882a593Smuzhiyun case RT5660_SCLK_S_MCLK:
982*4882a593Smuzhiyun reg_val |= RT5660_SCLK_SRC_MCLK;
983*4882a593Smuzhiyun break;
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun case RT5660_SCLK_S_PLL1:
986*4882a593Smuzhiyun reg_val |= RT5660_SCLK_SRC_PLL1;
987*4882a593Smuzhiyun break;
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun case RT5660_SCLK_S_RCCLK:
990*4882a593Smuzhiyun reg_val |= RT5660_SCLK_SRC_RCCLK;
991*4882a593Smuzhiyun break;
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun default:
994*4882a593Smuzhiyun dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
995*4882a593Smuzhiyun return -EINVAL;
996*4882a593Smuzhiyun }
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_GLB_CLK, RT5660_SCLK_SRC_MASK,
999*4882a593Smuzhiyun reg_val);
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun rt5660->sysclk = freq;
1002*4882a593Smuzhiyun rt5660->sysclk_src = clk_id;
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun return 0;
1007*4882a593Smuzhiyun }
1008*4882a593Smuzhiyun
rt5660_set_dai_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)1009*4882a593Smuzhiyun static int rt5660_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1010*4882a593Smuzhiyun unsigned int freq_in, unsigned int freq_out)
1011*4882a593Smuzhiyun {
1012*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
1013*4882a593Smuzhiyun struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
1014*4882a593Smuzhiyun struct rl6231_pll_code pll_code;
1015*4882a593Smuzhiyun int ret;
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun if (source == rt5660->pll_src && freq_in == rt5660->pll_in &&
1018*4882a593Smuzhiyun freq_out == rt5660->pll_out)
1019*4882a593Smuzhiyun return 0;
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun if (!freq_in || !freq_out) {
1022*4882a593Smuzhiyun dev_dbg(component->dev, "PLL disabled\n");
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun rt5660->pll_in = 0;
1025*4882a593Smuzhiyun rt5660->pll_out = 0;
1026*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_GLB_CLK,
1027*4882a593Smuzhiyun RT5660_SCLK_SRC_MASK, RT5660_SCLK_SRC_MCLK);
1028*4882a593Smuzhiyun return 0;
1029*4882a593Smuzhiyun }
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun switch (source) {
1032*4882a593Smuzhiyun case RT5660_PLL1_S_MCLK:
1033*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_GLB_CLK,
1034*4882a593Smuzhiyun RT5660_PLL1_SRC_MASK, RT5660_PLL1_SRC_MCLK);
1035*4882a593Smuzhiyun break;
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun case RT5660_PLL1_S_BCLK:
1038*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_GLB_CLK,
1039*4882a593Smuzhiyun RT5660_PLL1_SRC_MASK, RT5660_PLL1_SRC_BCLK1);
1040*4882a593Smuzhiyun break;
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun default:
1043*4882a593Smuzhiyun dev_err(component->dev, "Unknown PLL source %d\n", source);
1044*4882a593Smuzhiyun return -EINVAL;
1045*4882a593Smuzhiyun }
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1048*4882a593Smuzhiyun if (ret < 0) {
1049*4882a593Smuzhiyun dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
1050*4882a593Smuzhiyun return ret;
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
1054*4882a593Smuzhiyun pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1055*4882a593Smuzhiyun pll_code.n_code, pll_code.k_code);
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun snd_soc_component_write(component, RT5660_PLL_CTRL1,
1058*4882a593Smuzhiyun pll_code.n_code << RT5660_PLL_N_SFT | pll_code.k_code);
1059*4882a593Smuzhiyun snd_soc_component_write(component, RT5660_PLL_CTRL2,
1060*4882a593Smuzhiyun (pll_code.m_bp ? 0 : pll_code.m_code) << RT5660_PLL_M_SFT |
1061*4882a593Smuzhiyun pll_code.m_bp << RT5660_PLL_M_BP_SFT);
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun rt5660->pll_in = freq_in;
1064*4882a593Smuzhiyun rt5660->pll_out = freq_out;
1065*4882a593Smuzhiyun rt5660->pll_src = source;
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun return 0;
1068*4882a593Smuzhiyun }
1069*4882a593Smuzhiyun
rt5660_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1070*4882a593Smuzhiyun static int rt5660_set_bias_level(struct snd_soc_component *component,
1071*4882a593Smuzhiyun enum snd_soc_bias_level level)
1072*4882a593Smuzhiyun {
1073*4882a593Smuzhiyun struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
1074*4882a593Smuzhiyun int ret;
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun switch (level) {
1077*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
1078*4882a593Smuzhiyun break;
1079*4882a593Smuzhiyun
1080*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
1081*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_GEN_CTRL1,
1082*4882a593Smuzhiyun RT5660_DIG_GATE_CTRL, RT5660_DIG_GATE_CTRL);
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun if (IS_ERR(rt5660->mclk))
1085*4882a593Smuzhiyun break;
1086*4882a593Smuzhiyun
1087*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1088*4882a593Smuzhiyun clk_disable_unprepare(rt5660->mclk);
1089*4882a593Smuzhiyun } else {
1090*4882a593Smuzhiyun ret = clk_prepare_enable(rt5660->mclk);
1091*4882a593Smuzhiyun if (ret)
1092*4882a593Smuzhiyun return ret;
1093*4882a593Smuzhiyun }
1094*4882a593Smuzhiyun break;
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
1097*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1098*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_PWR_ANLG1,
1099*4882a593Smuzhiyun RT5660_PWR_VREF1 | RT5660_PWR_MB |
1100*4882a593Smuzhiyun RT5660_PWR_BG | RT5660_PWR_VREF2,
1101*4882a593Smuzhiyun RT5660_PWR_VREF1 | RT5660_PWR_MB |
1102*4882a593Smuzhiyun RT5660_PWR_BG | RT5660_PWR_VREF2);
1103*4882a593Smuzhiyun usleep_range(10000, 15000);
1104*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_PWR_ANLG1,
1105*4882a593Smuzhiyun RT5660_PWR_FV1 | RT5660_PWR_FV2,
1106*4882a593Smuzhiyun RT5660_PWR_FV1 | RT5660_PWR_FV2);
1107*4882a593Smuzhiyun }
1108*4882a593Smuzhiyun break;
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
1111*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5660_GEN_CTRL1,
1112*4882a593Smuzhiyun RT5660_DIG_GATE_CTRL, 0);
1113*4882a593Smuzhiyun break;
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun default:
1116*4882a593Smuzhiyun break;
1117*4882a593Smuzhiyun }
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun return 0;
1120*4882a593Smuzhiyun }
1121*4882a593Smuzhiyun
rt5660_probe(struct snd_soc_component * component)1122*4882a593Smuzhiyun static int rt5660_probe(struct snd_soc_component *component)
1123*4882a593Smuzhiyun {
1124*4882a593Smuzhiyun struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun rt5660->component = component;
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun return 0;
1129*4882a593Smuzhiyun }
1130*4882a593Smuzhiyun
rt5660_remove(struct snd_soc_component * component)1131*4882a593Smuzhiyun static void rt5660_remove(struct snd_soc_component *component)
1132*4882a593Smuzhiyun {
1133*4882a593Smuzhiyun snd_soc_component_write(component, RT5660_RESET, 0);
1134*4882a593Smuzhiyun }
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun #ifdef CONFIG_PM
rt5660_suspend(struct snd_soc_component * component)1137*4882a593Smuzhiyun static int rt5660_suspend(struct snd_soc_component *component)
1138*4882a593Smuzhiyun {
1139*4882a593Smuzhiyun struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun regcache_cache_only(rt5660->regmap, true);
1142*4882a593Smuzhiyun regcache_mark_dirty(rt5660->regmap);
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun return 0;
1145*4882a593Smuzhiyun }
1146*4882a593Smuzhiyun
rt5660_resume(struct snd_soc_component * component)1147*4882a593Smuzhiyun static int rt5660_resume(struct snd_soc_component *component)
1148*4882a593Smuzhiyun {
1149*4882a593Smuzhiyun struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun if (rt5660->pdata.poweroff_codec_in_suspend)
1152*4882a593Smuzhiyun msleep(350);
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun regcache_cache_only(rt5660->regmap, false);
1155*4882a593Smuzhiyun regcache_sync(rt5660->regmap);
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun return 0;
1158*4882a593Smuzhiyun }
1159*4882a593Smuzhiyun #else
1160*4882a593Smuzhiyun #define rt5660_suspend NULL
1161*4882a593Smuzhiyun #define rt5660_resume NULL
1162*4882a593Smuzhiyun #endif
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun #define RT5660_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1165*4882a593Smuzhiyun #define RT5660_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1166*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1167*4882a593Smuzhiyun
1168*4882a593Smuzhiyun static const struct snd_soc_dai_ops rt5660_aif_dai_ops = {
1169*4882a593Smuzhiyun .hw_params = rt5660_hw_params,
1170*4882a593Smuzhiyun .set_fmt = rt5660_set_dai_fmt,
1171*4882a593Smuzhiyun .set_sysclk = rt5660_set_dai_sysclk,
1172*4882a593Smuzhiyun .set_pll = rt5660_set_dai_pll,
1173*4882a593Smuzhiyun };
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun static struct snd_soc_dai_driver rt5660_dai[] = {
1176*4882a593Smuzhiyun {
1177*4882a593Smuzhiyun .name = "rt5660-aif1",
1178*4882a593Smuzhiyun .id = RT5660_AIF1,
1179*4882a593Smuzhiyun .playback = {
1180*4882a593Smuzhiyun .stream_name = "AIF1 Playback",
1181*4882a593Smuzhiyun .channels_min = 1,
1182*4882a593Smuzhiyun .channels_max = 2,
1183*4882a593Smuzhiyun .rates = RT5660_STEREO_RATES,
1184*4882a593Smuzhiyun .formats = RT5660_FORMATS,
1185*4882a593Smuzhiyun },
1186*4882a593Smuzhiyun .capture = {
1187*4882a593Smuzhiyun .stream_name = "AIF1 Capture",
1188*4882a593Smuzhiyun .channels_min = 1,
1189*4882a593Smuzhiyun .channels_max = 2,
1190*4882a593Smuzhiyun .rates = RT5660_STEREO_RATES,
1191*4882a593Smuzhiyun .formats = RT5660_FORMATS,
1192*4882a593Smuzhiyun },
1193*4882a593Smuzhiyun .ops = &rt5660_aif_dai_ops,
1194*4882a593Smuzhiyun },
1195*4882a593Smuzhiyun };
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_rt5660 = {
1198*4882a593Smuzhiyun .probe = rt5660_probe,
1199*4882a593Smuzhiyun .remove = rt5660_remove,
1200*4882a593Smuzhiyun .suspend = rt5660_suspend,
1201*4882a593Smuzhiyun .resume = rt5660_resume,
1202*4882a593Smuzhiyun .set_bias_level = rt5660_set_bias_level,
1203*4882a593Smuzhiyun .controls = rt5660_snd_controls,
1204*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(rt5660_snd_controls),
1205*4882a593Smuzhiyun .dapm_widgets = rt5660_dapm_widgets,
1206*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(rt5660_dapm_widgets),
1207*4882a593Smuzhiyun .dapm_routes = rt5660_dapm_routes,
1208*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(rt5660_dapm_routes),
1209*4882a593Smuzhiyun .use_pmdown_time = 1,
1210*4882a593Smuzhiyun .endianness = 1,
1211*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
1212*4882a593Smuzhiyun };
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun static const struct regmap_config rt5660_regmap = {
1215*4882a593Smuzhiyun .reg_bits = 8,
1216*4882a593Smuzhiyun .val_bits = 16,
1217*4882a593Smuzhiyun .use_single_read = true,
1218*4882a593Smuzhiyun .use_single_write = true,
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun .max_register = RT5660_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5660_ranges) *
1221*4882a593Smuzhiyun RT5660_PR_SPACING),
1222*4882a593Smuzhiyun .volatile_reg = rt5660_volatile_register,
1223*4882a593Smuzhiyun .readable_reg = rt5660_readable_register,
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
1226*4882a593Smuzhiyun .reg_defaults = rt5660_reg,
1227*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(rt5660_reg),
1228*4882a593Smuzhiyun .ranges = rt5660_ranges,
1229*4882a593Smuzhiyun .num_ranges = ARRAY_SIZE(rt5660_ranges),
1230*4882a593Smuzhiyun };
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun static const struct i2c_device_id rt5660_i2c_id[] = {
1233*4882a593Smuzhiyun { "rt5660", 0 },
1234*4882a593Smuzhiyun { }
1235*4882a593Smuzhiyun };
1236*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, rt5660_i2c_id);
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun static const struct of_device_id rt5660_of_match[] = {
1239*4882a593Smuzhiyun { .compatible = "realtek,rt5660", },
1240*4882a593Smuzhiyun {},
1241*4882a593Smuzhiyun };
1242*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rt5660_of_match);
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun #ifdef CONFIG_ACPI
1245*4882a593Smuzhiyun static const struct acpi_device_id rt5660_acpi_match[] = {
1246*4882a593Smuzhiyun { "10EC5660", 0 },
1247*4882a593Smuzhiyun { "10EC3277", 0 },
1248*4882a593Smuzhiyun { },
1249*4882a593Smuzhiyun };
1250*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, rt5660_acpi_match);
1251*4882a593Smuzhiyun #endif
1252*4882a593Smuzhiyun
rt5660_parse_dt(struct rt5660_priv * rt5660,struct device * dev)1253*4882a593Smuzhiyun static int rt5660_parse_dt(struct rt5660_priv *rt5660, struct device *dev)
1254*4882a593Smuzhiyun {
1255*4882a593Smuzhiyun rt5660->pdata.in1_diff = device_property_read_bool(dev,
1256*4882a593Smuzhiyun "realtek,in1-differential");
1257*4882a593Smuzhiyun rt5660->pdata.in3_diff = device_property_read_bool(dev,
1258*4882a593Smuzhiyun "realtek,in3-differential");
1259*4882a593Smuzhiyun rt5660->pdata.poweroff_codec_in_suspend = device_property_read_bool(dev,
1260*4882a593Smuzhiyun "realtek,poweroff-in-suspend");
1261*4882a593Smuzhiyun device_property_read_u32(dev, "realtek,dmic1-data-pin",
1262*4882a593Smuzhiyun &rt5660->pdata.dmic1_data_pin);
1263*4882a593Smuzhiyun
1264*4882a593Smuzhiyun return 0;
1265*4882a593Smuzhiyun }
1266*4882a593Smuzhiyun
rt5660_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1267*4882a593Smuzhiyun static int rt5660_i2c_probe(struct i2c_client *i2c,
1268*4882a593Smuzhiyun const struct i2c_device_id *id)
1269*4882a593Smuzhiyun {
1270*4882a593Smuzhiyun struct rt5660_platform_data *pdata = dev_get_platdata(&i2c->dev);
1271*4882a593Smuzhiyun struct rt5660_priv *rt5660;
1272*4882a593Smuzhiyun int ret;
1273*4882a593Smuzhiyun unsigned int val;
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun rt5660 = devm_kzalloc(&i2c->dev, sizeof(struct rt5660_priv),
1276*4882a593Smuzhiyun GFP_KERNEL);
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun if (rt5660 == NULL)
1279*4882a593Smuzhiyun return -ENOMEM;
1280*4882a593Smuzhiyun
1281*4882a593Smuzhiyun /* Check if MCLK provided */
1282*4882a593Smuzhiyun rt5660->mclk = devm_clk_get(&i2c->dev, "mclk");
1283*4882a593Smuzhiyun if (PTR_ERR(rt5660->mclk) == -EPROBE_DEFER)
1284*4882a593Smuzhiyun return -EPROBE_DEFER;
1285*4882a593Smuzhiyun
1286*4882a593Smuzhiyun i2c_set_clientdata(i2c, rt5660);
1287*4882a593Smuzhiyun
1288*4882a593Smuzhiyun if (pdata)
1289*4882a593Smuzhiyun rt5660->pdata = *pdata;
1290*4882a593Smuzhiyun else if (i2c->dev.of_node)
1291*4882a593Smuzhiyun rt5660_parse_dt(rt5660, &i2c->dev);
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun rt5660->regmap = devm_regmap_init_i2c(i2c, &rt5660_regmap);
1294*4882a593Smuzhiyun if (IS_ERR(rt5660->regmap)) {
1295*4882a593Smuzhiyun ret = PTR_ERR(rt5660->regmap);
1296*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1297*4882a593Smuzhiyun ret);
1298*4882a593Smuzhiyun return ret;
1299*4882a593Smuzhiyun }
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun regmap_read(rt5660->regmap, RT5660_VENDOR_ID2, &val);
1302*4882a593Smuzhiyun if (val != RT5660_DEVICE_ID) {
1303*4882a593Smuzhiyun dev_err(&i2c->dev,
1304*4882a593Smuzhiyun "Device with ID register %#x is not rt5660\n", val);
1305*4882a593Smuzhiyun return -ENODEV;
1306*4882a593Smuzhiyun }
1307*4882a593Smuzhiyun
1308*4882a593Smuzhiyun regmap_write(rt5660->regmap, RT5660_RESET, 0);
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun ret = regmap_register_patch(rt5660->regmap, rt5660_patch,
1311*4882a593Smuzhiyun ARRAY_SIZE(rt5660_patch));
1312*4882a593Smuzhiyun if (ret != 0)
1313*4882a593Smuzhiyun dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1314*4882a593Smuzhiyun
1315*4882a593Smuzhiyun regmap_update_bits(rt5660->regmap, RT5660_GEN_CTRL1,
1316*4882a593Smuzhiyun RT5660_AUTO_DIS_AMP | RT5660_MCLK_DET | RT5660_POW_CLKDET,
1317*4882a593Smuzhiyun RT5660_AUTO_DIS_AMP | RT5660_MCLK_DET | RT5660_POW_CLKDET);
1318*4882a593Smuzhiyun
1319*4882a593Smuzhiyun if (rt5660->pdata.dmic1_data_pin) {
1320*4882a593Smuzhiyun regmap_update_bits(rt5660->regmap, RT5660_GPIO_CTRL1,
1321*4882a593Smuzhiyun RT5660_GP1_PIN_MASK, RT5660_GP1_PIN_DMIC1_SCL);
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun if (rt5660->pdata.dmic1_data_pin == RT5660_DMIC1_DATA_GPIO2)
1324*4882a593Smuzhiyun regmap_update_bits(rt5660->regmap, RT5660_DMIC_CTRL1,
1325*4882a593Smuzhiyun RT5660_SEL_DMIC_DATA_MASK,
1326*4882a593Smuzhiyun RT5660_SEL_DMIC_DATA_GPIO2);
1327*4882a593Smuzhiyun else if (rt5660->pdata.dmic1_data_pin == RT5660_DMIC1_DATA_IN1P)
1328*4882a593Smuzhiyun regmap_update_bits(rt5660->regmap, RT5660_DMIC_CTRL1,
1329*4882a593Smuzhiyun RT5660_SEL_DMIC_DATA_MASK,
1330*4882a593Smuzhiyun RT5660_SEL_DMIC_DATA_IN1P);
1331*4882a593Smuzhiyun }
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun return devm_snd_soc_register_component(&i2c->dev,
1334*4882a593Smuzhiyun &soc_component_dev_rt5660,
1335*4882a593Smuzhiyun rt5660_dai, ARRAY_SIZE(rt5660_dai));
1336*4882a593Smuzhiyun }
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun static struct i2c_driver rt5660_i2c_driver = {
1339*4882a593Smuzhiyun .driver = {
1340*4882a593Smuzhiyun .name = "rt5660",
1341*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(rt5660_acpi_match),
1342*4882a593Smuzhiyun .of_match_table = of_match_ptr(rt5660_of_match),
1343*4882a593Smuzhiyun },
1344*4882a593Smuzhiyun .probe = rt5660_i2c_probe,
1345*4882a593Smuzhiyun .id_table = rt5660_i2c_id,
1346*4882a593Smuzhiyun };
1347*4882a593Smuzhiyun module_i2c_driver(rt5660_i2c_driver);
1348*4882a593Smuzhiyun
1349*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC RT5660 driver");
1350*4882a593Smuzhiyun MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
1351*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1352