1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * rt5640.c -- RT5640/RT5639 ALSA SoC audio codec driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2011 Realtek Semiconductor Corp.
6*4882a593Smuzhiyun * Author: Johnny Hsu <johnnyhsu@realtek.com>
7*4882a593Smuzhiyun * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/moduleparam.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/pm.h>
15*4882a593Smuzhiyun #include <linux/gpio.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/of.h>
19*4882a593Smuzhiyun #include <linux/of_gpio.h>
20*4882a593Smuzhiyun #include <linux/platform_device.h>
21*4882a593Smuzhiyun #include <linux/spi/spi.h>
22*4882a593Smuzhiyun #include <linux/acpi.h>
23*4882a593Smuzhiyun #include <sound/core.h>
24*4882a593Smuzhiyun #include <sound/jack.h>
25*4882a593Smuzhiyun #include <sound/pcm.h>
26*4882a593Smuzhiyun #include <sound/pcm_params.h>
27*4882a593Smuzhiyun #include <sound/soc.h>
28*4882a593Smuzhiyun #include <sound/soc-dapm.h>
29*4882a593Smuzhiyun #include <sound/initval.h>
30*4882a593Smuzhiyun #include <sound/tlv.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #include "rl6231.h"
33*4882a593Smuzhiyun #include "rt5640.h"
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define RT5640_DEVICE_ID 0x6231
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define RT5640_PR_RANGE_BASE (0xff + 1)
38*4882a593Smuzhiyun #define RT5640_PR_SPACING 0x100
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define RT5640_PR_BASE (RT5640_PR_RANGE_BASE + (0 * RT5640_PR_SPACING))
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static const struct regmap_range_cfg rt5640_ranges[] = {
43*4882a593Smuzhiyun { .name = "PR", .range_min = RT5640_PR_BASE,
44*4882a593Smuzhiyun .range_max = RT5640_PR_BASE + 0xb4,
45*4882a593Smuzhiyun .selector_reg = RT5640_PRIV_INDEX,
46*4882a593Smuzhiyun .selector_mask = 0xff,
47*4882a593Smuzhiyun .selector_shift = 0x0,
48*4882a593Smuzhiyun .window_start = RT5640_PRIV_DATA,
49*4882a593Smuzhiyun .window_len = 0x1, },
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static const struct reg_sequence init_list[] = {
53*4882a593Smuzhiyun {RT5640_PR_BASE + 0x3d, 0x3600},
54*4882a593Smuzhiyun {RT5640_PR_BASE + 0x12, 0x0aa8},
55*4882a593Smuzhiyun {RT5640_PR_BASE + 0x14, 0x0aaa},
56*4882a593Smuzhiyun {RT5640_PR_BASE + 0x20, 0x6110},
57*4882a593Smuzhiyun {RT5640_PR_BASE + 0x21, 0xe0e0},
58*4882a593Smuzhiyun {RT5640_PR_BASE + 0x23, 0x1804},
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static const struct reg_default rt5640_reg[] = {
62*4882a593Smuzhiyun { 0x00, 0x000e },
63*4882a593Smuzhiyun { 0x01, 0xc8c8 },
64*4882a593Smuzhiyun { 0x02, 0xc8c8 },
65*4882a593Smuzhiyun { 0x03, 0xc8c8 },
66*4882a593Smuzhiyun { 0x04, 0x8000 },
67*4882a593Smuzhiyun { 0x0d, 0x0000 },
68*4882a593Smuzhiyun { 0x0e, 0x0000 },
69*4882a593Smuzhiyun { 0x0f, 0x0808 },
70*4882a593Smuzhiyun { 0x19, 0xafaf },
71*4882a593Smuzhiyun { 0x1a, 0xafaf },
72*4882a593Smuzhiyun { 0x1b, 0x0000 },
73*4882a593Smuzhiyun { 0x1c, 0x2f2f },
74*4882a593Smuzhiyun { 0x1d, 0x2f2f },
75*4882a593Smuzhiyun { 0x1e, 0x0000 },
76*4882a593Smuzhiyun { 0x27, 0x7060 },
77*4882a593Smuzhiyun { 0x28, 0x7070 },
78*4882a593Smuzhiyun { 0x29, 0x8080 },
79*4882a593Smuzhiyun { 0x2a, 0x5454 },
80*4882a593Smuzhiyun { 0x2b, 0x5454 },
81*4882a593Smuzhiyun { 0x2c, 0xaa00 },
82*4882a593Smuzhiyun { 0x2d, 0x0000 },
83*4882a593Smuzhiyun { 0x2e, 0xa000 },
84*4882a593Smuzhiyun { 0x2f, 0x0000 },
85*4882a593Smuzhiyun { 0x3b, 0x0000 },
86*4882a593Smuzhiyun { 0x3c, 0x007f },
87*4882a593Smuzhiyun { 0x3d, 0x0000 },
88*4882a593Smuzhiyun { 0x3e, 0x007f },
89*4882a593Smuzhiyun { 0x45, 0xe000 },
90*4882a593Smuzhiyun { 0x46, 0x003e },
91*4882a593Smuzhiyun { 0x47, 0x003e },
92*4882a593Smuzhiyun { 0x48, 0xf800 },
93*4882a593Smuzhiyun { 0x49, 0x3800 },
94*4882a593Smuzhiyun { 0x4a, 0x0004 },
95*4882a593Smuzhiyun { 0x4c, 0xfc00 },
96*4882a593Smuzhiyun { 0x4d, 0x0000 },
97*4882a593Smuzhiyun { 0x4f, 0x01ff },
98*4882a593Smuzhiyun { 0x50, 0x0000 },
99*4882a593Smuzhiyun { 0x51, 0x0000 },
100*4882a593Smuzhiyun { 0x52, 0x01ff },
101*4882a593Smuzhiyun { 0x53, 0xf000 },
102*4882a593Smuzhiyun { 0x61, 0x0000 },
103*4882a593Smuzhiyun { 0x62, 0x0000 },
104*4882a593Smuzhiyun { 0x63, 0x00c0 },
105*4882a593Smuzhiyun { 0x64, 0x0000 },
106*4882a593Smuzhiyun { 0x65, 0x0000 },
107*4882a593Smuzhiyun { 0x66, 0x0000 },
108*4882a593Smuzhiyun { 0x6a, 0x0000 },
109*4882a593Smuzhiyun { 0x6c, 0x0000 },
110*4882a593Smuzhiyun { 0x70, 0x8000 },
111*4882a593Smuzhiyun { 0x71, 0x8000 },
112*4882a593Smuzhiyun { 0x72, 0x8000 },
113*4882a593Smuzhiyun { 0x73, 0x1114 },
114*4882a593Smuzhiyun { 0x74, 0x0c00 },
115*4882a593Smuzhiyun { 0x75, 0x1d00 },
116*4882a593Smuzhiyun { 0x80, 0x0000 },
117*4882a593Smuzhiyun { 0x81, 0x0000 },
118*4882a593Smuzhiyun { 0x82, 0x0000 },
119*4882a593Smuzhiyun { 0x83, 0x0000 },
120*4882a593Smuzhiyun { 0x84, 0x0000 },
121*4882a593Smuzhiyun { 0x85, 0x0008 },
122*4882a593Smuzhiyun { 0x89, 0x0000 },
123*4882a593Smuzhiyun { 0x8a, 0x0000 },
124*4882a593Smuzhiyun { 0x8b, 0x0600 },
125*4882a593Smuzhiyun { 0x8c, 0x0228 },
126*4882a593Smuzhiyun { 0x8d, 0xa000 },
127*4882a593Smuzhiyun { 0x8e, 0x0004 },
128*4882a593Smuzhiyun { 0x8f, 0x1100 },
129*4882a593Smuzhiyun { 0x90, 0x0646 },
130*4882a593Smuzhiyun { 0x91, 0x0c00 },
131*4882a593Smuzhiyun { 0x92, 0x0000 },
132*4882a593Smuzhiyun { 0x93, 0x3000 },
133*4882a593Smuzhiyun { 0xb0, 0x2080 },
134*4882a593Smuzhiyun { 0xb1, 0x0000 },
135*4882a593Smuzhiyun { 0xb4, 0x2206 },
136*4882a593Smuzhiyun { 0xb5, 0x1f00 },
137*4882a593Smuzhiyun { 0xb6, 0x0000 },
138*4882a593Smuzhiyun { 0xb8, 0x034b },
139*4882a593Smuzhiyun { 0xb9, 0x0066 },
140*4882a593Smuzhiyun { 0xba, 0x000b },
141*4882a593Smuzhiyun { 0xbb, 0x0000 },
142*4882a593Smuzhiyun { 0xbc, 0x0000 },
143*4882a593Smuzhiyun { 0xbd, 0x0000 },
144*4882a593Smuzhiyun { 0xbe, 0x0000 },
145*4882a593Smuzhiyun { 0xbf, 0x0000 },
146*4882a593Smuzhiyun { 0xc0, 0x0400 },
147*4882a593Smuzhiyun { 0xc2, 0x0000 },
148*4882a593Smuzhiyun { 0xc4, 0x0000 },
149*4882a593Smuzhiyun { 0xc5, 0x0000 },
150*4882a593Smuzhiyun { 0xc6, 0x2000 },
151*4882a593Smuzhiyun { 0xc8, 0x0000 },
152*4882a593Smuzhiyun { 0xc9, 0x0000 },
153*4882a593Smuzhiyun { 0xca, 0x0000 },
154*4882a593Smuzhiyun { 0xcb, 0x0000 },
155*4882a593Smuzhiyun { 0xcc, 0x0000 },
156*4882a593Smuzhiyun { 0xcf, 0x0013 },
157*4882a593Smuzhiyun { 0xd0, 0x0680 },
158*4882a593Smuzhiyun { 0xd1, 0x1c17 },
159*4882a593Smuzhiyun { 0xd2, 0x8c00 },
160*4882a593Smuzhiyun { 0xd3, 0xaa20 },
161*4882a593Smuzhiyun { 0xd6, 0x0400 },
162*4882a593Smuzhiyun { 0xd9, 0x0809 },
163*4882a593Smuzhiyun { 0xfe, 0x10ec },
164*4882a593Smuzhiyun { 0xff, 0x6231 },
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun
rt5640_reset(struct snd_soc_component * component)167*4882a593Smuzhiyun static int rt5640_reset(struct snd_soc_component *component)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun return snd_soc_component_write(component, RT5640_RESET, 0);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
rt5640_volatile_register(struct device * dev,unsigned int reg)172*4882a593Smuzhiyun static bool rt5640_volatile_register(struct device *dev, unsigned int reg)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun int i;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(rt5640_ranges); i++)
177*4882a593Smuzhiyun if ((reg >= rt5640_ranges[i].window_start &&
178*4882a593Smuzhiyun reg <= rt5640_ranges[i].window_start +
179*4882a593Smuzhiyun rt5640_ranges[i].window_len) ||
180*4882a593Smuzhiyun (reg >= rt5640_ranges[i].range_min &&
181*4882a593Smuzhiyun reg <= rt5640_ranges[i].range_max))
182*4882a593Smuzhiyun return true;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun switch (reg) {
185*4882a593Smuzhiyun case RT5640_RESET:
186*4882a593Smuzhiyun case RT5640_ASRC_5:
187*4882a593Smuzhiyun case RT5640_EQ_CTRL1:
188*4882a593Smuzhiyun case RT5640_DRC_AGC_1:
189*4882a593Smuzhiyun case RT5640_ANC_CTRL1:
190*4882a593Smuzhiyun case RT5640_IRQ_CTRL2:
191*4882a593Smuzhiyun case RT5640_INT_IRQ_ST:
192*4882a593Smuzhiyun case RT5640_DSP_CTRL2:
193*4882a593Smuzhiyun case RT5640_DSP_CTRL3:
194*4882a593Smuzhiyun case RT5640_PRIV_INDEX:
195*4882a593Smuzhiyun case RT5640_PRIV_DATA:
196*4882a593Smuzhiyun case RT5640_PGM_REG_ARR1:
197*4882a593Smuzhiyun case RT5640_PGM_REG_ARR3:
198*4882a593Smuzhiyun case RT5640_VENDOR_ID:
199*4882a593Smuzhiyun case RT5640_VENDOR_ID1:
200*4882a593Smuzhiyun case RT5640_VENDOR_ID2:
201*4882a593Smuzhiyun return true;
202*4882a593Smuzhiyun default:
203*4882a593Smuzhiyun return false;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
rt5640_readable_register(struct device * dev,unsigned int reg)207*4882a593Smuzhiyun static bool rt5640_readable_register(struct device *dev, unsigned int reg)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun int i;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(rt5640_ranges); i++)
212*4882a593Smuzhiyun if ((reg >= rt5640_ranges[i].window_start &&
213*4882a593Smuzhiyun reg <= rt5640_ranges[i].window_start +
214*4882a593Smuzhiyun rt5640_ranges[i].window_len) ||
215*4882a593Smuzhiyun (reg >= rt5640_ranges[i].range_min &&
216*4882a593Smuzhiyun reg <= rt5640_ranges[i].range_max))
217*4882a593Smuzhiyun return true;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun switch (reg) {
220*4882a593Smuzhiyun case RT5640_RESET:
221*4882a593Smuzhiyun case RT5640_SPK_VOL:
222*4882a593Smuzhiyun case RT5640_HP_VOL:
223*4882a593Smuzhiyun case RT5640_OUTPUT:
224*4882a593Smuzhiyun case RT5640_MONO_OUT:
225*4882a593Smuzhiyun case RT5640_IN1_IN2:
226*4882a593Smuzhiyun case RT5640_IN3_IN4:
227*4882a593Smuzhiyun case RT5640_INL_INR_VOL:
228*4882a593Smuzhiyun case RT5640_DAC1_DIG_VOL:
229*4882a593Smuzhiyun case RT5640_DAC2_DIG_VOL:
230*4882a593Smuzhiyun case RT5640_DAC2_CTRL:
231*4882a593Smuzhiyun case RT5640_ADC_DIG_VOL:
232*4882a593Smuzhiyun case RT5640_ADC_DATA:
233*4882a593Smuzhiyun case RT5640_ADC_BST_VOL:
234*4882a593Smuzhiyun case RT5640_STO_ADC_MIXER:
235*4882a593Smuzhiyun case RT5640_MONO_ADC_MIXER:
236*4882a593Smuzhiyun case RT5640_AD_DA_MIXER:
237*4882a593Smuzhiyun case RT5640_STO_DAC_MIXER:
238*4882a593Smuzhiyun case RT5640_MONO_DAC_MIXER:
239*4882a593Smuzhiyun case RT5640_DIG_MIXER:
240*4882a593Smuzhiyun case RT5640_DSP_PATH1:
241*4882a593Smuzhiyun case RT5640_DSP_PATH2:
242*4882a593Smuzhiyun case RT5640_DIG_INF_DATA:
243*4882a593Smuzhiyun case RT5640_REC_L1_MIXER:
244*4882a593Smuzhiyun case RT5640_REC_L2_MIXER:
245*4882a593Smuzhiyun case RT5640_REC_R1_MIXER:
246*4882a593Smuzhiyun case RT5640_REC_R2_MIXER:
247*4882a593Smuzhiyun case RT5640_HPO_MIXER:
248*4882a593Smuzhiyun case RT5640_SPK_L_MIXER:
249*4882a593Smuzhiyun case RT5640_SPK_R_MIXER:
250*4882a593Smuzhiyun case RT5640_SPO_L_MIXER:
251*4882a593Smuzhiyun case RT5640_SPO_R_MIXER:
252*4882a593Smuzhiyun case RT5640_SPO_CLSD_RATIO:
253*4882a593Smuzhiyun case RT5640_MONO_MIXER:
254*4882a593Smuzhiyun case RT5640_OUT_L1_MIXER:
255*4882a593Smuzhiyun case RT5640_OUT_L2_MIXER:
256*4882a593Smuzhiyun case RT5640_OUT_L3_MIXER:
257*4882a593Smuzhiyun case RT5640_OUT_R1_MIXER:
258*4882a593Smuzhiyun case RT5640_OUT_R2_MIXER:
259*4882a593Smuzhiyun case RT5640_OUT_R3_MIXER:
260*4882a593Smuzhiyun case RT5640_LOUT_MIXER:
261*4882a593Smuzhiyun case RT5640_PWR_DIG1:
262*4882a593Smuzhiyun case RT5640_PWR_DIG2:
263*4882a593Smuzhiyun case RT5640_PWR_ANLG1:
264*4882a593Smuzhiyun case RT5640_PWR_ANLG2:
265*4882a593Smuzhiyun case RT5640_PWR_MIXER:
266*4882a593Smuzhiyun case RT5640_PWR_VOL:
267*4882a593Smuzhiyun case RT5640_PRIV_INDEX:
268*4882a593Smuzhiyun case RT5640_PRIV_DATA:
269*4882a593Smuzhiyun case RT5640_I2S1_SDP:
270*4882a593Smuzhiyun case RT5640_I2S2_SDP:
271*4882a593Smuzhiyun case RT5640_ADDA_CLK1:
272*4882a593Smuzhiyun case RT5640_ADDA_CLK2:
273*4882a593Smuzhiyun case RT5640_DMIC:
274*4882a593Smuzhiyun case RT5640_GLB_CLK:
275*4882a593Smuzhiyun case RT5640_PLL_CTRL1:
276*4882a593Smuzhiyun case RT5640_PLL_CTRL2:
277*4882a593Smuzhiyun case RT5640_ASRC_1:
278*4882a593Smuzhiyun case RT5640_ASRC_2:
279*4882a593Smuzhiyun case RT5640_ASRC_3:
280*4882a593Smuzhiyun case RT5640_ASRC_4:
281*4882a593Smuzhiyun case RT5640_ASRC_5:
282*4882a593Smuzhiyun case RT5640_HP_OVCD:
283*4882a593Smuzhiyun case RT5640_CLS_D_OVCD:
284*4882a593Smuzhiyun case RT5640_CLS_D_OUT:
285*4882a593Smuzhiyun case RT5640_DEPOP_M1:
286*4882a593Smuzhiyun case RT5640_DEPOP_M2:
287*4882a593Smuzhiyun case RT5640_DEPOP_M3:
288*4882a593Smuzhiyun case RT5640_CHARGE_PUMP:
289*4882a593Smuzhiyun case RT5640_PV_DET_SPK_G:
290*4882a593Smuzhiyun case RT5640_MICBIAS:
291*4882a593Smuzhiyun case RT5640_EQ_CTRL1:
292*4882a593Smuzhiyun case RT5640_EQ_CTRL2:
293*4882a593Smuzhiyun case RT5640_WIND_FILTER:
294*4882a593Smuzhiyun case RT5640_DRC_AGC_1:
295*4882a593Smuzhiyun case RT5640_DRC_AGC_2:
296*4882a593Smuzhiyun case RT5640_DRC_AGC_3:
297*4882a593Smuzhiyun case RT5640_SVOL_ZC:
298*4882a593Smuzhiyun case RT5640_ANC_CTRL1:
299*4882a593Smuzhiyun case RT5640_ANC_CTRL2:
300*4882a593Smuzhiyun case RT5640_ANC_CTRL3:
301*4882a593Smuzhiyun case RT5640_JD_CTRL:
302*4882a593Smuzhiyun case RT5640_ANC_JD:
303*4882a593Smuzhiyun case RT5640_IRQ_CTRL1:
304*4882a593Smuzhiyun case RT5640_IRQ_CTRL2:
305*4882a593Smuzhiyun case RT5640_INT_IRQ_ST:
306*4882a593Smuzhiyun case RT5640_GPIO_CTRL1:
307*4882a593Smuzhiyun case RT5640_GPIO_CTRL2:
308*4882a593Smuzhiyun case RT5640_GPIO_CTRL3:
309*4882a593Smuzhiyun case RT5640_DSP_CTRL1:
310*4882a593Smuzhiyun case RT5640_DSP_CTRL2:
311*4882a593Smuzhiyun case RT5640_DSP_CTRL3:
312*4882a593Smuzhiyun case RT5640_DSP_CTRL4:
313*4882a593Smuzhiyun case RT5640_PGM_REG_ARR1:
314*4882a593Smuzhiyun case RT5640_PGM_REG_ARR2:
315*4882a593Smuzhiyun case RT5640_PGM_REG_ARR3:
316*4882a593Smuzhiyun case RT5640_PGM_REG_ARR4:
317*4882a593Smuzhiyun case RT5640_PGM_REG_ARR5:
318*4882a593Smuzhiyun case RT5640_SCB_FUNC:
319*4882a593Smuzhiyun case RT5640_SCB_CTRL:
320*4882a593Smuzhiyun case RT5640_BASE_BACK:
321*4882a593Smuzhiyun case RT5640_MP3_PLUS1:
322*4882a593Smuzhiyun case RT5640_MP3_PLUS2:
323*4882a593Smuzhiyun case RT5640_3D_HP:
324*4882a593Smuzhiyun case RT5640_ADJ_HPF:
325*4882a593Smuzhiyun case RT5640_HP_CALIB_AMP_DET:
326*4882a593Smuzhiyun case RT5640_HP_CALIB2:
327*4882a593Smuzhiyun case RT5640_SV_ZCD1:
328*4882a593Smuzhiyun case RT5640_SV_ZCD2:
329*4882a593Smuzhiyun case RT5640_DUMMY1:
330*4882a593Smuzhiyun case RT5640_DUMMY2:
331*4882a593Smuzhiyun case RT5640_DUMMY3:
332*4882a593Smuzhiyun case RT5640_VENDOR_ID:
333*4882a593Smuzhiyun case RT5640_VENDOR_ID1:
334*4882a593Smuzhiyun case RT5640_VENDOR_ID2:
335*4882a593Smuzhiyun return true;
336*4882a593Smuzhiyun default:
337*4882a593Smuzhiyun return false;
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
342*4882a593Smuzhiyun static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -6562, 0);
343*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
344*4882a593Smuzhiyun static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -1762, 3000);
345*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
348*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(bst_tlv,
349*4882a593Smuzhiyun 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
350*4882a593Smuzhiyun 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
351*4882a593Smuzhiyun 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
352*4882a593Smuzhiyun 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
353*4882a593Smuzhiyun 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
354*4882a593Smuzhiyun 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
355*4882a593Smuzhiyun 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
356*4882a593Smuzhiyun );
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun /* Interface data select */
359*4882a593Smuzhiyun static const char * const rt5640_data_select[] = {
360*4882a593Smuzhiyun "Normal", "Swap", "left copy to right", "right copy to left"};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,
363*4882a593Smuzhiyun RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_if1_adc_enum, RT5640_DIG_INF_DATA,
366*4882a593Smuzhiyun RT5640_IF1_ADC_SEL_SFT, rt5640_data_select);
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_if2_dac_enum, RT5640_DIG_INF_DATA,
369*4882a593Smuzhiyun RT5640_IF2_DAC_SEL_SFT, rt5640_data_select);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_enum, RT5640_DIG_INF_DATA,
372*4882a593Smuzhiyun RT5640_IF2_ADC_SEL_SFT, rt5640_data_select);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun /* Class D speaker gain ratio */
375*4882a593Smuzhiyun static const char * const rt5640_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x",
376*4882a593Smuzhiyun "2x", "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_clsd_spk_ratio_enum, RT5640_CLS_D_OUT,
379*4882a593Smuzhiyun RT5640_CLSD_RATIO_SFT, rt5640_clsd_spk_ratio);
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_snd_controls[] = {
382*4882a593Smuzhiyun /* Speaker Output Volume */
383*4882a593Smuzhiyun SOC_DOUBLE("Speaker Channel Switch", RT5640_SPK_VOL,
384*4882a593Smuzhiyun RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
385*4882a593Smuzhiyun SOC_DOUBLE_TLV("Speaker Playback Volume", RT5640_SPK_VOL,
386*4882a593Smuzhiyun RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
387*4882a593Smuzhiyun /* Headphone Output Volume */
388*4882a593Smuzhiyun SOC_DOUBLE("HP Channel Switch", RT5640_HP_VOL,
389*4882a593Smuzhiyun RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
390*4882a593Smuzhiyun SOC_DOUBLE_TLV("HP Playback Volume", RT5640_HP_VOL,
391*4882a593Smuzhiyun RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
392*4882a593Smuzhiyun /* OUTPUT Control */
393*4882a593Smuzhiyun SOC_DOUBLE("OUT Playback Switch", RT5640_OUTPUT,
394*4882a593Smuzhiyun RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
395*4882a593Smuzhiyun SOC_DOUBLE("OUT Channel Switch", RT5640_OUTPUT,
396*4882a593Smuzhiyun RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
397*4882a593Smuzhiyun SOC_DOUBLE_TLV("OUT Playback Volume", RT5640_OUTPUT,
398*4882a593Smuzhiyun RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun /* DAC Digital Volume */
401*4882a593Smuzhiyun SOC_DOUBLE("DAC2 Playback Switch", RT5640_DAC2_CTRL,
402*4882a593Smuzhiyun RT5640_M_DAC_L2_VOL_SFT, RT5640_M_DAC_R2_VOL_SFT, 1, 1),
403*4882a593Smuzhiyun SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5640_DAC1_DIG_VOL,
404*4882a593Smuzhiyun RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
405*4882a593Smuzhiyun 175, 0, dac_vol_tlv),
406*4882a593Smuzhiyun /* IN1/IN2/IN3 Control */
407*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1 Boost", RT5640_IN1_IN2,
408*4882a593Smuzhiyun RT5640_BST_SFT1, 8, 0, bst_tlv),
409*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2 Boost", RT5640_IN3_IN4,
410*4882a593Smuzhiyun RT5640_BST_SFT2, 8, 0, bst_tlv),
411*4882a593Smuzhiyun SOC_SINGLE_TLV("IN3 Boost", RT5640_IN1_IN2,
412*4882a593Smuzhiyun RT5640_BST_SFT2, 8, 0, bst_tlv),
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun /* INL/INR Volume Control */
415*4882a593Smuzhiyun SOC_DOUBLE_TLV("IN Capture Volume", RT5640_INL_INR_VOL,
416*4882a593Smuzhiyun RT5640_INL_VOL_SFT, RT5640_INR_VOL_SFT,
417*4882a593Smuzhiyun 31, 1, in_vol_tlv),
418*4882a593Smuzhiyun /* ADC Digital Volume Control */
419*4882a593Smuzhiyun SOC_DOUBLE("ADC Capture Switch", RT5640_ADC_DIG_VOL,
420*4882a593Smuzhiyun RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
421*4882a593Smuzhiyun SOC_DOUBLE_TLV("ADC Capture Volume", RT5640_ADC_DIG_VOL,
422*4882a593Smuzhiyun RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
423*4882a593Smuzhiyun 127, 0, adc_vol_tlv),
424*4882a593Smuzhiyun SOC_DOUBLE("Mono ADC Capture Switch", RT5640_DUMMY1,
425*4882a593Smuzhiyun RT5640_M_MONO_ADC_L_SFT, RT5640_M_MONO_ADC_R_SFT, 1, 1),
426*4882a593Smuzhiyun SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5640_ADC_DATA,
427*4882a593Smuzhiyun RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
428*4882a593Smuzhiyun 127, 0, adc_vol_tlv),
429*4882a593Smuzhiyun /* ADC Boost Volume Control */
430*4882a593Smuzhiyun SOC_DOUBLE_TLV("ADC Boost Gain", RT5640_ADC_BST_VOL,
431*4882a593Smuzhiyun RT5640_ADC_L_BST_SFT, RT5640_ADC_R_BST_SFT,
432*4882a593Smuzhiyun 3, 0, adc_bst_tlv),
433*4882a593Smuzhiyun /* Class D speaker gain ratio */
434*4882a593Smuzhiyun SOC_ENUM("Class D SPK Ratio Control", rt5640_clsd_spk_ratio_enum),
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun SOC_ENUM("ADC IF1 Data Switch", rt5640_if1_adc_enum),
437*4882a593Smuzhiyun SOC_ENUM("DAC IF1 Data Switch", rt5640_if1_dac_enum),
438*4882a593Smuzhiyun SOC_ENUM("ADC IF2 Data Switch", rt5640_if2_adc_enum),
439*4882a593Smuzhiyun SOC_ENUM("DAC IF2 Data Switch", rt5640_if2_dac_enum),
440*4882a593Smuzhiyun };
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_specific_snd_controls[] = {
443*4882a593Smuzhiyun /* MONO Output Control */
444*4882a593Smuzhiyun SOC_SINGLE("Mono Playback Switch", RT5640_MONO_OUT, RT5640_L_MUTE_SFT,
445*4882a593Smuzhiyun 1, 1),
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5640_DAC2_DIG_VOL,
448*4882a593Smuzhiyun RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 175, 0, dac_vol_tlv),
449*4882a593Smuzhiyun };
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun /**
452*4882a593Smuzhiyun * set_dmic_clk - Set parameter of dmic.
453*4882a593Smuzhiyun *
454*4882a593Smuzhiyun * @w: DAPM widget.
455*4882a593Smuzhiyun * @kcontrol: The kcontrol of this widget.
456*4882a593Smuzhiyun * @event: Event id.
457*4882a593Smuzhiyun *
458*4882a593Smuzhiyun */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)459*4882a593Smuzhiyun static int set_dmic_clk(struct snd_soc_dapm_widget *w,
460*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
461*4882a593Smuzhiyun {
462*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
463*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
464*4882a593Smuzhiyun int idx, rate;
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun rate = rt5640->sysclk / rl6231_get_pre_div(rt5640->regmap,
467*4882a593Smuzhiyun RT5640_ADDA_CLK1, RT5640_I2S_PD1_SFT);
468*4882a593Smuzhiyun idx = rl6231_calc_dmic_clk(rate);
469*4882a593Smuzhiyun if (idx < 0)
470*4882a593Smuzhiyun dev_err(component->dev, "Failed to set DMIC clock\n");
471*4882a593Smuzhiyun else
472*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_DMIC, RT5640_DMIC_CLK_MASK,
473*4882a593Smuzhiyun idx << RT5640_DMIC_CLK_SFT);
474*4882a593Smuzhiyun return idx;
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun
is_using_asrc(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)477*4882a593Smuzhiyun static int is_using_asrc(struct snd_soc_dapm_widget *source,
478*4882a593Smuzhiyun struct snd_soc_dapm_widget *sink)
479*4882a593Smuzhiyun {
480*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
481*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun if (!rt5640->asrc_en)
484*4882a593Smuzhiyun return 0;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun return 1;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun /* Digital Mixer */
490*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_sto_adc_l_mix[] = {
491*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
492*4882a593Smuzhiyun RT5640_M_ADC_L1_SFT, 1, 1),
493*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
494*4882a593Smuzhiyun RT5640_M_ADC_L2_SFT, 1, 1),
495*4882a593Smuzhiyun };
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_sto_adc_r_mix[] = {
498*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
499*4882a593Smuzhiyun RT5640_M_ADC_R1_SFT, 1, 1),
500*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
501*4882a593Smuzhiyun RT5640_M_ADC_R2_SFT, 1, 1),
502*4882a593Smuzhiyun };
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_mono_adc_l_mix[] = {
505*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
506*4882a593Smuzhiyun RT5640_M_MONO_ADC_L1_SFT, 1, 1),
507*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
508*4882a593Smuzhiyun RT5640_M_MONO_ADC_L2_SFT, 1, 1),
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_mono_adc_r_mix[] = {
512*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
513*4882a593Smuzhiyun RT5640_M_MONO_ADC_R1_SFT, 1, 1),
514*4882a593Smuzhiyun SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
515*4882a593Smuzhiyun RT5640_M_MONO_ADC_R2_SFT, 1, 1),
516*4882a593Smuzhiyun };
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_dac_l_mix[] = {
519*4882a593Smuzhiyun SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
520*4882a593Smuzhiyun RT5640_M_ADCMIX_L_SFT, 1, 1),
521*4882a593Smuzhiyun SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
522*4882a593Smuzhiyun RT5640_M_IF1_DAC_L_SFT, 1, 1),
523*4882a593Smuzhiyun };
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_dac_r_mix[] = {
526*4882a593Smuzhiyun SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
527*4882a593Smuzhiyun RT5640_M_ADCMIX_R_SFT, 1, 1),
528*4882a593Smuzhiyun SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
529*4882a593Smuzhiyun RT5640_M_IF1_DAC_R_SFT, 1, 1),
530*4882a593Smuzhiyun };
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_sto_dac_l_mix[] = {
533*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
534*4882a593Smuzhiyun RT5640_M_DAC_L1_SFT, 1, 1),
535*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
536*4882a593Smuzhiyun RT5640_M_DAC_L2_SFT, 1, 1),
537*4882a593Smuzhiyun SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
538*4882a593Smuzhiyun RT5640_M_ANC_DAC_L_SFT, 1, 1),
539*4882a593Smuzhiyun };
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_sto_dac_r_mix[] = {
542*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
543*4882a593Smuzhiyun RT5640_M_DAC_R1_SFT, 1, 1),
544*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
545*4882a593Smuzhiyun RT5640_M_DAC_R2_SFT, 1, 1),
546*4882a593Smuzhiyun SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
547*4882a593Smuzhiyun RT5640_M_ANC_DAC_R_SFT, 1, 1),
548*4882a593Smuzhiyun };
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5639_sto_dac_l_mix[] = {
551*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
552*4882a593Smuzhiyun RT5640_M_DAC_L1_SFT, 1, 1),
553*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
554*4882a593Smuzhiyun RT5640_M_DAC_L2_SFT, 1, 1),
555*4882a593Smuzhiyun };
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5639_sto_dac_r_mix[] = {
558*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
559*4882a593Smuzhiyun RT5640_M_DAC_R1_SFT, 1, 1),
560*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
561*4882a593Smuzhiyun RT5640_M_DAC_R2_SFT, 1, 1),
562*4882a593Smuzhiyun };
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_mono_dac_l_mix[] = {
565*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_MONO_DAC_MIXER,
566*4882a593Smuzhiyun RT5640_M_DAC_L1_MONO_L_SFT, 1, 1),
567*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
568*4882a593Smuzhiyun RT5640_M_DAC_L2_MONO_L_SFT, 1, 1),
569*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
570*4882a593Smuzhiyun RT5640_M_DAC_R2_MONO_L_SFT, 1, 1),
571*4882a593Smuzhiyun };
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_mono_dac_r_mix[] = {
574*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_MONO_DAC_MIXER,
575*4882a593Smuzhiyun RT5640_M_DAC_R1_MONO_R_SFT, 1, 1),
576*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
577*4882a593Smuzhiyun RT5640_M_DAC_R2_MONO_R_SFT, 1, 1),
578*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
579*4882a593Smuzhiyun RT5640_M_DAC_L2_MONO_R_SFT, 1, 1),
580*4882a593Smuzhiyun };
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_dig_l_mix[] = {
583*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_DIG_MIXER,
584*4882a593Smuzhiyun RT5640_M_STO_L_DAC_L_SFT, 1, 1),
585*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_DIG_MIXER,
586*4882a593Smuzhiyun RT5640_M_DAC_L2_DAC_L_SFT, 1, 1),
587*4882a593Smuzhiyun };
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_dig_r_mix[] = {
590*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_DIG_MIXER,
591*4882a593Smuzhiyun RT5640_M_STO_R_DAC_R_SFT, 1, 1),
592*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_DIG_MIXER,
593*4882a593Smuzhiyun RT5640_M_DAC_R2_DAC_R_SFT, 1, 1),
594*4882a593Smuzhiyun };
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun /* Analog Input Mixer */
597*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_rec_l_mix[] = {
598*4882a593Smuzhiyun SOC_DAPM_SINGLE("HPOL Switch", RT5640_REC_L2_MIXER,
599*4882a593Smuzhiyun RT5640_M_HP_L_RM_L_SFT, 1, 1),
600*4882a593Smuzhiyun SOC_DAPM_SINGLE("INL Switch", RT5640_REC_L2_MIXER,
601*4882a593Smuzhiyun RT5640_M_IN_L_RM_L_SFT, 1, 1),
602*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST3 Switch", RT5640_REC_L2_MIXER,
603*4882a593Smuzhiyun RT5640_M_BST2_RM_L_SFT, 1, 1),
604*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_L2_MIXER,
605*4882a593Smuzhiyun RT5640_M_BST4_RM_L_SFT, 1, 1),
606*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_L2_MIXER,
607*4882a593Smuzhiyun RT5640_M_BST1_RM_L_SFT, 1, 1),
608*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_REC_L2_MIXER,
609*4882a593Smuzhiyun RT5640_M_OM_L_RM_L_SFT, 1, 1),
610*4882a593Smuzhiyun };
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_rec_r_mix[] = {
613*4882a593Smuzhiyun SOC_DAPM_SINGLE("HPOR Switch", RT5640_REC_R2_MIXER,
614*4882a593Smuzhiyun RT5640_M_HP_R_RM_R_SFT, 1, 1),
615*4882a593Smuzhiyun SOC_DAPM_SINGLE("INR Switch", RT5640_REC_R2_MIXER,
616*4882a593Smuzhiyun RT5640_M_IN_R_RM_R_SFT, 1, 1),
617*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST3 Switch", RT5640_REC_R2_MIXER,
618*4882a593Smuzhiyun RT5640_M_BST2_RM_R_SFT, 1, 1),
619*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_R2_MIXER,
620*4882a593Smuzhiyun RT5640_M_BST4_RM_R_SFT, 1, 1),
621*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_R2_MIXER,
622*4882a593Smuzhiyun RT5640_M_BST1_RM_R_SFT, 1, 1),
623*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_REC_R2_MIXER,
624*4882a593Smuzhiyun RT5640_M_OM_R_RM_R_SFT, 1, 1),
625*4882a593Smuzhiyun };
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun /* Analog Output Mixer */
628*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_spk_l_mix[] = {
629*4882a593Smuzhiyun SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_SPK_L_MIXER,
630*4882a593Smuzhiyun RT5640_M_RM_L_SM_L_SFT, 1, 1),
631*4882a593Smuzhiyun SOC_DAPM_SINGLE("INL Switch", RT5640_SPK_L_MIXER,
632*4882a593Smuzhiyun RT5640_M_IN_L_SM_L_SFT, 1, 1),
633*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPK_L_MIXER,
634*4882a593Smuzhiyun RT5640_M_DAC_L1_SM_L_SFT, 1, 1),
635*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_SPK_L_MIXER,
636*4882a593Smuzhiyun RT5640_M_DAC_L2_SM_L_SFT, 1, 1),
637*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_SPK_L_MIXER,
638*4882a593Smuzhiyun RT5640_M_OM_L_SM_L_SFT, 1, 1),
639*4882a593Smuzhiyun };
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_spk_r_mix[] = {
642*4882a593Smuzhiyun SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_SPK_R_MIXER,
643*4882a593Smuzhiyun RT5640_M_RM_R_SM_R_SFT, 1, 1),
644*4882a593Smuzhiyun SOC_DAPM_SINGLE("INR Switch", RT5640_SPK_R_MIXER,
645*4882a593Smuzhiyun RT5640_M_IN_R_SM_R_SFT, 1, 1),
646*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPK_R_MIXER,
647*4882a593Smuzhiyun RT5640_M_DAC_R1_SM_R_SFT, 1, 1),
648*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_SPK_R_MIXER,
649*4882a593Smuzhiyun RT5640_M_DAC_R2_SM_R_SFT, 1, 1),
650*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_SPK_R_MIXER,
651*4882a593Smuzhiyun RT5640_M_OM_R_SM_R_SFT, 1, 1),
652*4882a593Smuzhiyun };
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_out_l_mix[] = {
655*4882a593Smuzhiyun SOC_DAPM_SINGLE("SPK MIXL Switch", RT5640_OUT_L3_MIXER,
656*4882a593Smuzhiyun RT5640_M_SM_L_OM_L_SFT, 1, 1),
657*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
658*4882a593Smuzhiyun RT5640_M_BST1_OM_L_SFT, 1, 1),
659*4882a593Smuzhiyun SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
660*4882a593Smuzhiyun RT5640_M_IN_L_OM_L_SFT, 1, 1),
661*4882a593Smuzhiyun SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
662*4882a593Smuzhiyun RT5640_M_RM_L_OM_L_SFT, 1, 1),
663*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_L3_MIXER,
664*4882a593Smuzhiyun RT5640_M_DAC_R2_OM_L_SFT, 1, 1),
665*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_L3_MIXER,
666*4882a593Smuzhiyun RT5640_M_DAC_L2_OM_L_SFT, 1, 1),
667*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
668*4882a593Smuzhiyun RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
669*4882a593Smuzhiyun };
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_out_r_mix[] = {
672*4882a593Smuzhiyun SOC_DAPM_SINGLE("SPK MIXR Switch", RT5640_OUT_R3_MIXER,
673*4882a593Smuzhiyun RT5640_M_SM_L_OM_R_SFT, 1, 1),
674*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
675*4882a593Smuzhiyun RT5640_M_BST4_OM_R_SFT, 1, 1),
676*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
677*4882a593Smuzhiyun RT5640_M_BST1_OM_R_SFT, 1, 1),
678*4882a593Smuzhiyun SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
679*4882a593Smuzhiyun RT5640_M_IN_R_OM_R_SFT, 1, 1),
680*4882a593Smuzhiyun SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
681*4882a593Smuzhiyun RT5640_M_RM_R_OM_R_SFT, 1, 1),
682*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_R3_MIXER,
683*4882a593Smuzhiyun RT5640_M_DAC_L2_OM_R_SFT, 1, 1),
684*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_R3_MIXER,
685*4882a593Smuzhiyun RT5640_M_DAC_R2_OM_R_SFT, 1, 1),
686*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
687*4882a593Smuzhiyun RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
688*4882a593Smuzhiyun };
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5639_out_l_mix[] = {
691*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
692*4882a593Smuzhiyun RT5640_M_BST1_OM_L_SFT, 1, 1),
693*4882a593Smuzhiyun SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
694*4882a593Smuzhiyun RT5640_M_IN_L_OM_L_SFT, 1, 1),
695*4882a593Smuzhiyun SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
696*4882a593Smuzhiyun RT5640_M_RM_L_OM_L_SFT, 1, 1),
697*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
698*4882a593Smuzhiyun RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
699*4882a593Smuzhiyun };
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5639_out_r_mix[] = {
702*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
703*4882a593Smuzhiyun RT5640_M_BST4_OM_R_SFT, 1, 1),
704*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
705*4882a593Smuzhiyun RT5640_M_BST1_OM_R_SFT, 1, 1),
706*4882a593Smuzhiyun SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
707*4882a593Smuzhiyun RT5640_M_IN_R_OM_R_SFT, 1, 1),
708*4882a593Smuzhiyun SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
709*4882a593Smuzhiyun RT5640_M_RM_R_OM_R_SFT, 1, 1),
710*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
711*4882a593Smuzhiyun RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
712*4882a593Smuzhiyun };
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_spo_l_mix[] = {
715*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_L_MIXER,
716*4882a593Smuzhiyun RT5640_M_DAC_R1_SPM_L_SFT, 1, 1),
717*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPO_L_MIXER,
718*4882a593Smuzhiyun RT5640_M_DAC_L1_SPM_L_SFT, 1, 1),
719*4882a593Smuzhiyun SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_L_MIXER,
720*4882a593Smuzhiyun RT5640_M_SV_R_SPM_L_SFT, 1, 1),
721*4882a593Smuzhiyun SOC_DAPM_SINGLE("SPKVOL L Switch", RT5640_SPO_L_MIXER,
722*4882a593Smuzhiyun RT5640_M_SV_L_SPM_L_SFT, 1, 1),
723*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_L_MIXER,
724*4882a593Smuzhiyun RT5640_M_BST1_SPM_L_SFT, 1, 1),
725*4882a593Smuzhiyun };
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_spo_r_mix[] = {
728*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_R_MIXER,
729*4882a593Smuzhiyun RT5640_M_DAC_R1_SPM_R_SFT, 1, 1),
730*4882a593Smuzhiyun SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_R_MIXER,
731*4882a593Smuzhiyun RT5640_M_SV_R_SPM_R_SFT, 1, 1),
732*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_R_MIXER,
733*4882a593Smuzhiyun RT5640_M_BST1_SPM_R_SFT, 1, 1),
734*4882a593Smuzhiyun };
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_hpo_mix[] = {
737*4882a593Smuzhiyun SOC_DAPM_SINGLE("HPO MIX DAC2 Switch", RT5640_HPO_MIXER,
738*4882a593Smuzhiyun RT5640_M_DAC2_HM_SFT, 1, 1),
739*4882a593Smuzhiyun SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5640_HPO_MIXER,
740*4882a593Smuzhiyun RT5640_M_DAC1_HM_SFT, 1, 1),
741*4882a593Smuzhiyun SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5640_HPO_MIXER,
742*4882a593Smuzhiyun RT5640_M_HPVOL_HM_SFT, 1, 1),
743*4882a593Smuzhiyun };
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5639_hpo_mix[] = {
746*4882a593Smuzhiyun SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5640_HPO_MIXER,
747*4882a593Smuzhiyun RT5640_M_DAC1_HM_SFT, 1, 1),
748*4882a593Smuzhiyun SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5640_HPO_MIXER,
749*4882a593Smuzhiyun RT5640_M_HPVOL_HM_SFT, 1, 1),
750*4882a593Smuzhiyun };
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_lout_mix[] = {
753*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_LOUT_MIXER,
754*4882a593Smuzhiyun RT5640_M_DAC_L1_LM_SFT, 1, 1),
755*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_LOUT_MIXER,
756*4882a593Smuzhiyun RT5640_M_DAC_R1_LM_SFT, 1, 1),
757*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_LOUT_MIXER,
758*4882a593Smuzhiyun RT5640_M_OV_L_LM_SFT, 1, 1),
759*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_LOUT_MIXER,
760*4882a593Smuzhiyun RT5640_M_OV_R_LM_SFT, 1, 1),
761*4882a593Smuzhiyun };
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_mono_mix[] = {
764*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_MIXER,
765*4882a593Smuzhiyun RT5640_M_DAC_R2_MM_SFT, 1, 1),
766*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_MIXER,
767*4882a593Smuzhiyun RT5640_M_DAC_L2_MM_SFT, 1, 1),
768*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_MONO_MIXER,
769*4882a593Smuzhiyun RT5640_M_OV_R_MM_SFT, 1, 1),
770*4882a593Smuzhiyun SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_MONO_MIXER,
771*4882a593Smuzhiyun RT5640_M_OV_L_MM_SFT, 1, 1),
772*4882a593Smuzhiyun SOC_DAPM_SINGLE("BST1 Switch", RT5640_MONO_MIXER,
773*4882a593Smuzhiyun RT5640_M_BST1_MM_SFT, 1, 1),
774*4882a593Smuzhiyun };
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun static const struct snd_kcontrol_new spk_l_enable_control =
777*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_SPK_VOL,
778*4882a593Smuzhiyun RT5640_L_MUTE_SFT, 1, 1);
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun static const struct snd_kcontrol_new spk_r_enable_control =
781*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_SPK_VOL,
782*4882a593Smuzhiyun RT5640_R_MUTE_SFT, 1, 1);
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun static const struct snd_kcontrol_new hp_l_enable_control =
785*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_HP_VOL,
786*4882a593Smuzhiyun RT5640_L_MUTE_SFT, 1, 1);
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun static const struct snd_kcontrol_new hp_r_enable_control =
789*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_HP_VOL,
790*4882a593Smuzhiyun RT5640_R_MUTE_SFT, 1, 1);
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun /* Stereo ADC source */
793*4882a593Smuzhiyun static const char * const rt5640_stereo_adc1_src[] = {
794*4882a593Smuzhiyun "DIG MIX", "ADC"
795*4882a593Smuzhiyun };
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_stereo_adc1_enum, RT5640_STO_ADC_MIXER,
798*4882a593Smuzhiyun RT5640_ADC_1_SRC_SFT, rt5640_stereo_adc1_src);
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_sto_adc_1_mux =
801*4882a593Smuzhiyun SOC_DAPM_ENUM("Stereo ADC1 Mux", rt5640_stereo_adc1_enum);
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun static const char * const rt5640_stereo_adc2_src[] = {
804*4882a593Smuzhiyun "DMIC1", "DMIC2", "DIG MIX"
805*4882a593Smuzhiyun };
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_stereo_adc2_enum, RT5640_STO_ADC_MIXER,
808*4882a593Smuzhiyun RT5640_ADC_2_SRC_SFT, rt5640_stereo_adc2_src);
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_sto_adc_2_mux =
811*4882a593Smuzhiyun SOC_DAPM_ENUM("Stereo ADC2 Mux", rt5640_stereo_adc2_enum);
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun /* Mono ADC source */
814*4882a593Smuzhiyun static const char * const rt5640_mono_adc_l1_src[] = {
815*4882a593Smuzhiyun "Mono DAC MIXL", "ADCL"
816*4882a593Smuzhiyun };
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_l1_enum, RT5640_MONO_ADC_MIXER,
819*4882a593Smuzhiyun RT5640_MONO_ADC_L1_SRC_SFT, rt5640_mono_adc_l1_src);
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_mono_adc_l1_mux =
822*4882a593Smuzhiyun SOC_DAPM_ENUM("Mono ADC1 left source", rt5640_mono_adc_l1_enum);
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun static const char * const rt5640_mono_adc_l2_src[] = {
825*4882a593Smuzhiyun "DMIC L1", "DMIC L2", "Mono DAC MIXL"
826*4882a593Smuzhiyun };
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_l2_enum, RT5640_MONO_ADC_MIXER,
829*4882a593Smuzhiyun RT5640_MONO_ADC_L2_SRC_SFT, rt5640_mono_adc_l2_src);
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_mono_adc_l2_mux =
832*4882a593Smuzhiyun SOC_DAPM_ENUM("Mono ADC2 left source", rt5640_mono_adc_l2_enum);
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun static const char * const rt5640_mono_adc_r1_src[] = {
835*4882a593Smuzhiyun "Mono DAC MIXR", "ADCR"
836*4882a593Smuzhiyun };
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_r1_enum, RT5640_MONO_ADC_MIXER,
839*4882a593Smuzhiyun RT5640_MONO_ADC_R1_SRC_SFT, rt5640_mono_adc_r1_src);
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_mono_adc_r1_mux =
842*4882a593Smuzhiyun SOC_DAPM_ENUM("Mono ADC1 right source", rt5640_mono_adc_r1_enum);
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun static const char * const rt5640_mono_adc_r2_src[] = {
845*4882a593Smuzhiyun "DMIC R1", "DMIC R2", "Mono DAC MIXR"
846*4882a593Smuzhiyun };
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_r2_enum, RT5640_MONO_ADC_MIXER,
849*4882a593Smuzhiyun RT5640_MONO_ADC_R2_SRC_SFT, rt5640_mono_adc_r2_src);
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_mono_adc_r2_mux =
852*4882a593Smuzhiyun SOC_DAPM_ENUM("Mono ADC2 right source", rt5640_mono_adc_r2_enum);
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun /* DAC2 channel source */
855*4882a593Smuzhiyun static const char * const rt5640_dac_l2_src[] = {
856*4882a593Smuzhiyun "IF2", "Base L/R"
857*4882a593Smuzhiyun };
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun static int rt5640_dac_l2_values[] = {
860*4882a593Smuzhiyun 0,
861*4882a593Smuzhiyun 3,
862*4882a593Smuzhiyun };
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dac_l2_enum,
865*4882a593Smuzhiyun RT5640_DSP_PATH2, RT5640_DAC_L2_SEL_SFT,
866*4882a593Smuzhiyun 0x3, rt5640_dac_l2_src, rt5640_dac_l2_values);
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_dac_l2_mux =
869*4882a593Smuzhiyun SOC_DAPM_ENUM("DAC2 left channel source", rt5640_dac_l2_enum);
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun static const char * const rt5640_dac_r2_src[] = {
872*4882a593Smuzhiyun "IF2",
873*4882a593Smuzhiyun };
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun static int rt5640_dac_r2_values[] = {
876*4882a593Smuzhiyun 0,
877*4882a593Smuzhiyun };
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dac_r2_enum,
880*4882a593Smuzhiyun RT5640_DSP_PATH2, RT5640_DAC_R2_SEL_SFT,
881*4882a593Smuzhiyun 0x3, rt5640_dac_r2_src, rt5640_dac_r2_values);
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_dac_r2_mux =
884*4882a593Smuzhiyun SOC_DAPM_ENUM("DAC2 right channel source", rt5640_dac_r2_enum);
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun /* digital interface and iis interface map */
887*4882a593Smuzhiyun static const char * const rt5640_dai_iis_map[] = {
888*4882a593Smuzhiyun "1:1|2:2", "1:2|2:1", "1:1|2:1", "1:2|2:2"
889*4882a593Smuzhiyun };
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun static int rt5640_dai_iis_map_values[] = {
892*4882a593Smuzhiyun 0,
893*4882a593Smuzhiyun 5,
894*4882a593Smuzhiyun 6,
895*4882a593Smuzhiyun 7,
896*4882a593Smuzhiyun };
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dai_iis_map_enum,
899*4882a593Smuzhiyun RT5640_I2S1_SDP, RT5640_I2S_IF_SFT,
900*4882a593Smuzhiyun 0x7, rt5640_dai_iis_map,
901*4882a593Smuzhiyun rt5640_dai_iis_map_values);
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_dai_mux =
904*4882a593Smuzhiyun SOC_DAPM_ENUM("DAI select", rt5640_dai_iis_map_enum);
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun /* SDI select */
907*4882a593Smuzhiyun static const char * const rt5640_sdi_sel[] = {
908*4882a593Smuzhiyun "IF1", "IF2"
909*4882a593Smuzhiyun };
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5640_sdi_sel_enum, RT5640_I2S2_SDP,
912*4882a593Smuzhiyun RT5640_I2S2_SDI_SFT, rt5640_sdi_sel);
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5640_sdi_mux =
915*4882a593Smuzhiyun SOC_DAPM_ENUM("SDI select", rt5640_sdi_sel_enum);
916*4882a593Smuzhiyun
hp_amp_power_on(struct snd_soc_component * component)917*4882a593Smuzhiyun static void hp_amp_power_on(struct snd_soc_component *component)
918*4882a593Smuzhiyun {
919*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun /* depop parameters */
922*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_PR_BASE +
923*4882a593Smuzhiyun RT5640_CHPUMP_INT_REG1, 0x0700, 0x0200);
924*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M2,
925*4882a593Smuzhiyun RT5640_DEPOP_MASK, RT5640_DEPOP_MAN);
926*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M1,
927*4882a593Smuzhiyun RT5640_HP_CP_MASK | RT5640_HP_SG_MASK | RT5640_HP_CB_MASK,
928*4882a593Smuzhiyun RT5640_HP_CP_PU | RT5640_HP_SG_DIS | RT5640_HP_CB_PU);
929*4882a593Smuzhiyun regmap_write(rt5640->regmap, RT5640_PR_BASE + RT5640_HP_DCC_INT1,
930*4882a593Smuzhiyun 0x9f00);
931*4882a593Smuzhiyun /* headphone amp power on */
932*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_PWR_ANLG1,
933*4882a593Smuzhiyun RT5640_PWR_FV1 | RT5640_PWR_FV2, 0);
934*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_PWR_ANLG1,
935*4882a593Smuzhiyun RT5640_PWR_HA,
936*4882a593Smuzhiyun RT5640_PWR_HA);
937*4882a593Smuzhiyun usleep_range(10000, 15000);
938*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_PWR_ANLG1,
939*4882a593Smuzhiyun RT5640_PWR_FV1 | RT5640_PWR_FV2 ,
940*4882a593Smuzhiyun RT5640_PWR_FV1 | RT5640_PWR_FV2);
941*4882a593Smuzhiyun }
942*4882a593Smuzhiyun
rt5640_pmu_depop(struct snd_soc_component * component)943*4882a593Smuzhiyun static void rt5640_pmu_depop(struct snd_soc_component *component)
944*4882a593Smuzhiyun {
945*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M2,
948*4882a593Smuzhiyun RT5640_DEPOP_MASK | RT5640_DIG_DP_MASK,
949*4882a593Smuzhiyun RT5640_DEPOP_AUTO | RT5640_DIG_DP_EN);
950*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_CHARGE_PUMP,
951*4882a593Smuzhiyun RT5640_PM_HP_MASK, RT5640_PM_HP_HV);
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M3,
954*4882a593Smuzhiyun RT5640_CP_FQ1_MASK | RT5640_CP_FQ2_MASK | RT5640_CP_FQ3_MASK,
955*4882a593Smuzhiyun (RT5640_CP_FQ_192_KHZ << RT5640_CP_FQ1_SFT) |
956*4882a593Smuzhiyun (RT5640_CP_FQ_12_KHZ << RT5640_CP_FQ2_SFT) |
957*4882a593Smuzhiyun (RT5640_CP_FQ_192_KHZ << RT5640_CP_FQ3_SFT));
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun regmap_write(rt5640->regmap, RT5640_PR_BASE +
960*4882a593Smuzhiyun RT5640_MAMP_INT_REG2, 0x1c00);
961*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M1,
962*4882a593Smuzhiyun RT5640_HP_CP_MASK | RT5640_HP_SG_MASK,
963*4882a593Smuzhiyun RT5640_HP_CP_PD | RT5640_HP_SG_EN);
964*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_PR_BASE +
965*4882a593Smuzhiyun RT5640_CHPUMP_INT_REG1, 0x0700, 0x0400);
966*4882a593Smuzhiyun }
967*4882a593Smuzhiyun
rt5640_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)968*4882a593Smuzhiyun static int rt5640_hp_event(struct snd_soc_dapm_widget *w,
969*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
970*4882a593Smuzhiyun {
971*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
972*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun switch (event) {
975*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
976*4882a593Smuzhiyun rt5640_pmu_depop(component);
977*4882a593Smuzhiyun rt5640->hp_mute = false;
978*4882a593Smuzhiyun break;
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
981*4882a593Smuzhiyun rt5640->hp_mute = true;
982*4882a593Smuzhiyun msleep(70);
983*4882a593Smuzhiyun break;
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun default:
986*4882a593Smuzhiyun return 0;
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun return 0;
990*4882a593Smuzhiyun }
991*4882a593Smuzhiyun
rt5640_lout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)992*4882a593Smuzhiyun static int rt5640_lout_event(struct snd_soc_dapm_widget *w,
993*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
994*4882a593Smuzhiyun {
995*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun switch (event) {
998*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
999*4882a593Smuzhiyun hp_amp_power_on(component);
1000*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
1001*4882a593Smuzhiyun RT5640_PWR_LM, RT5640_PWR_LM);
1002*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_OUTPUT,
1003*4882a593Smuzhiyun RT5640_L_MUTE | RT5640_R_MUTE, 0);
1004*4882a593Smuzhiyun break;
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
1007*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_OUTPUT,
1008*4882a593Smuzhiyun RT5640_L_MUTE | RT5640_R_MUTE,
1009*4882a593Smuzhiyun RT5640_L_MUTE | RT5640_R_MUTE);
1010*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
1011*4882a593Smuzhiyun RT5640_PWR_LM, 0);
1012*4882a593Smuzhiyun break;
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun default:
1015*4882a593Smuzhiyun return 0;
1016*4882a593Smuzhiyun }
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun return 0;
1019*4882a593Smuzhiyun }
1020*4882a593Smuzhiyun
rt5640_hp_power_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1021*4882a593Smuzhiyun static int rt5640_hp_power_event(struct snd_soc_dapm_widget *w,
1022*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
1023*4882a593Smuzhiyun {
1024*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun switch (event) {
1027*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
1028*4882a593Smuzhiyun hp_amp_power_on(component);
1029*4882a593Smuzhiyun break;
1030*4882a593Smuzhiyun default:
1031*4882a593Smuzhiyun return 0;
1032*4882a593Smuzhiyun }
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun return 0;
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun
rt5640_hp_post_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1037*4882a593Smuzhiyun static int rt5640_hp_post_event(struct snd_soc_dapm_widget *w,
1038*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
1039*4882a593Smuzhiyun {
1040*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1041*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun switch (event) {
1044*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
1045*4882a593Smuzhiyun if (!rt5640->hp_mute)
1046*4882a593Smuzhiyun msleep(80);
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun break;
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun default:
1051*4882a593Smuzhiyun return 0;
1052*4882a593Smuzhiyun }
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun return 0;
1055*4882a593Smuzhiyun }
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
1058*4882a593Smuzhiyun /* ASRC */
1059*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("Stereo Filter ASRC", 1, RT5640_ASRC_1,
1060*4882a593Smuzhiyun 15, 0, NULL, 0),
1061*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("I2S2 Filter ASRC", 1, RT5640_ASRC_1,
1062*4882a593Smuzhiyun 12, 0, NULL, 0),
1063*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5640_ASRC_1,
1064*4882a593Smuzhiyun 11, 0, NULL, 0),
1065*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("DMIC1 ASRC", 1, RT5640_ASRC_1,
1066*4882a593Smuzhiyun 9, 0, NULL, 0),
1067*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("DMIC2 ASRC", 1, RT5640_ASRC_1,
1068*4882a593Smuzhiyun 8, 0, NULL, 0),
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun /* Input Side */
1072*4882a593Smuzhiyun /* micbias */
1073*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("LDO2", RT5640_PWR_ANLG1,
1074*4882a593Smuzhiyun RT5640_PWR_LDO2_BIT, 0, NULL, 0),
1075*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5640_PWR_ANLG2,
1076*4882a593Smuzhiyun RT5640_PWR_MB1_BIT, 0, NULL, 0),
1077*4882a593Smuzhiyun /* Input Lines */
1078*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC1"),
1079*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC2"),
1080*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1P"),
1081*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1N"),
1082*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2P"),
1083*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2N"),
1084*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN3P"),
1085*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN3N"),
1086*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DMIC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
1087*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DMIC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
1088*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DMIC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
1089*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DMIC R2", SND_SOC_NOPM, 0, 0, NULL, 0),
1090*4882a593Smuzhiyun
1091*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1092*4882a593Smuzhiyun set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1093*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5640_DMIC, RT5640_DMIC_1_EN_SFT, 0,
1094*4882a593Smuzhiyun NULL, 0),
1095*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5640_DMIC, RT5640_DMIC_2_EN_SFT, 0,
1096*4882a593Smuzhiyun NULL, 0),
1097*4882a593Smuzhiyun /* Boost */
1098*4882a593Smuzhiyun SND_SOC_DAPM_PGA("BST1", RT5640_PWR_ANLG2,
1099*4882a593Smuzhiyun RT5640_PWR_BST1_BIT, 0, NULL, 0),
1100*4882a593Smuzhiyun SND_SOC_DAPM_PGA("BST2", RT5640_PWR_ANLG2,
1101*4882a593Smuzhiyun RT5640_PWR_BST4_BIT, 0, NULL, 0),
1102*4882a593Smuzhiyun SND_SOC_DAPM_PGA("BST3", RT5640_PWR_ANLG2,
1103*4882a593Smuzhiyun RT5640_PWR_BST2_BIT, 0, NULL, 0),
1104*4882a593Smuzhiyun /* Input Volume */
1105*4882a593Smuzhiyun SND_SOC_DAPM_PGA("INL VOL", RT5640_PWR_VOL,
1106*4882a593Smuzhiyun RT5640_PWR_IN_L_BIT, 0, NULL, 0),
1107*4882a593Smuzhiyun SND_SOC_DAPM_PGA("INR VOL", RT5640_PWR_VOL,
1108*4882a593Smuzhiyun RT5640_PWR_IN_R_BIT, 0, NULL, 0),
1109*4882a593Smuzhiyun /* REC Mixer */
1110*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("RECMIXL", RT5640_PWR_MIXER, RT5640_PWR_RM_L_BIT, 0,
1111*4882a593Smuzhiyun rt5640_rec_l_mix, ARRAY_SIZE(rt5640_rec_l_mix)),
1112*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("RECMIXR", RT5640_PWR_MIXER, RT5640_PWR_RM_R_BIT, 0,
1113*4882a593Smuzhiyun rt5640_rec_r_mix, ARRAY_SIZE(rt5640_rec_r_mix)),
1114*4882a593Smuzhiyun /* ADCs */
1115*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC L", NULL, RT5640_PWR_DIG1,
1116*4882a593Smuzhiyun RT5640_PWR_ADC_L_BIT, 0),
1117*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC R", NULL, RT5640_PWR_DIG1,
1118*4882a593Smuzhiyun RT5640_PWR_ADC_R_BIT, 0),
1119*4882a593Smuzhiyun /* ADC Mux */
1120*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1121*4882a593Smuzhiyun &rt5640_sto_adc_2_mux),
1122*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1123*4882a593Smuzhiyun &rt5640_sto_adc_2_mux),
1124*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1125*4882a593Smuzhiyun &rt5640_sto_adc_1_mux),
1126*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1127*4882a593Smuzhiyun &rt5640_sto_adc_1_mux),
1128*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1129*4882a593Smuzhiyun &rt5640_mono_adc_l2_mux),
1130*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1131*4882a593Smuzhiyun &rt5640_mono_adc_l1_mux),
1132*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1133*4882a593Smuzhiyun &rt5640_mono_adc_r1_mux),
1134*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1135*4882a593Smuzhiyun &rt5640_mono_adc_r2_mux),
1136*4882a593Smuzhiyun /* ADC Mixer */
1137*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Stereo Filter", RT5640_PWR_DIG2,
1138*4882a593Smuzhiyun RT5640_PWR_ADC_SF_BIT, 0, NULL, 0),
1139*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
1140*4882a593Smuzhiyun rt5640_sto_adc_l_mix, ARRAY_SIZE(rt5640_sto_adc_l_mix)),
1141*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
1142*4882a593Smuzhiyun rt5640_sto_adc_r_mix, ARRAY_SIZE(rt5640_sto_adc_r_mix)),
1143*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mono Left Filter", RT5640_PWR_DIG2,
1144*4882a593Smuzhiyun RT5640_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1145*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1146*4882a593Smuzhiyun rt5640_mono_adc_l_mix, ARRAY_SIZE(rt5640_mono_adc_l_mix)),
1147*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mono Right Filter", RT5640_PWR_DIG2,
1148*4882a593Smuzhiyun RT5640_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1149*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1150*4882a593Smuzhiyun rt5640_mono_adc_r_mix, ARRAY_SIZE(rt5640_mono_adc_r_mix)),
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun /* Digital Interface */
1153*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("I2S1", RT5640_PWR_DIG1,
1154*4882a593Smuzhiyun RT5640_PWR_I2S1_BIT, 0, NULL, 0),
1155*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1156*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1157*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1158*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1159*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1160*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1161*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("I2S2", RT5640_PWR_DIG1,
1162*4882a593Smuzhiyun RT5640_PWR_I2S2_BIT, 0, NULL, 0),
1163*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1164*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1165*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1166*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1167*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1168*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1169*4882a593Smuzhiyun /* Digital Interface Select */
1170*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1171*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1172*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1173*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1174*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
1175*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1176*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1177*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1178*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1179*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
1180*4882a593Smuzhiyun /* Audio Interface */
1181*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1182*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1183*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1184*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1185*4882a593Smuzhiyun
1186*4882a593Smuzhiyun /* Output Side */
1187*4882a593Smuzhiyun /* DAC mixer before sound effect */
1188*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1189*4882a593Smuzhiyun rt5640_dac_l_mix, ARRAY_SIZE(rt5640_dac_l_mix)),
1190*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1191*4882a593Smuzhiyun rt5640_dac_r_mix, ARRAY_SIZE(rt5640_dac_r_mix)),
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun /* DAC Mixer */
1194*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1195*4882a593Smuzhiyun rt5640_mono_dac_l_mix, ARRAY_SIZE(rt5640_mono_dac_l_mix)),
1196*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1197*4882a593Smuzhiyun rt5640_mono_dac_r_mix, ARRAY_SIZE(rt5640_mono_dac_r_mix)),
1198*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
1199*4882a593Smuzhiyun rt5640_dig_l_mix, ARRAY_SIZE(rt5640_dig_l_mix)),
1200*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
1201*4882a593Smuzhiyun rt5640_dig_r_mix, ARRAY_SIZE(rt5640_dig_r_mix)),
1202*4882a593Smuzhiyun /* DACs */
1203*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM,
1204*4882a593Smuzhiyun 0, 0),
1205*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM,
1206*4882a593Smuzhiyun 0, 0),
1207*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5640_PWR_DIG1,
1208*4882a593Smuzhiyun RT5640_PWR_DAC_L1_BIT, 0, NULL, 0),
1209*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5640_PWR_DIG1,
1210*4882a593Smuzhiyun RT5640_PWR_DAC_R1_BIT, 0, NULL, 0),
1211*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5640_PWR_DIG1,
1212*4882a593Smuzhiyun RT5640_PWR_DAC_L2_BIT, 0, NULL, 0),
1213*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5640_PWR_DIG1,
1214*4882a593Smuzhiyun RT5640_PWR_DAC_R2_BIT, 0, NULL, 0),
1215*4882a593Smuzhiyun /* SPK/OUT Mixer */
1216*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("SPK MIXL", RT5640_PWR_MIXER, RT5640_PWR_SM_L_BIT,
1217*4882a593Smuzhiyun 0, rt5640_spk_l_mix, ARRAY_SIZE(rt5640_spk_l_mix)),
1218*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("SPK MIXR", RT5640_PWR_MIXER, RT5640_PWR_SM_R_BIT,
1219*4882a593Smuzhiyun 0, rt5640_spk_r_mix, ARRAY_SIZE(rt5640_spk_r_mix)),
1220*4882a593Smuzhiyun /* Ouput Volume */
1221*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPKVOL L", RT5640_PWR_VOL,
1222*4882a593Smuzhiyun RT5640_PWR_SV_L_BIT, 0, NULL, 0),
1223*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPKVOL R", RT5640_PWR_VOL,
1224*4882a593Smuzhiyun RT5640_PWR_SV_R_BIT, 0, NULL, 0),
1225*4882a593Smuzhiyun SND_SOC_DAPM_PGA("OUTVOL L", RT5640_PWR_VOL,
1226*4882a593Smuzhiyun RT5640_PWR_OV_L_BIT, 0, NULL, 0),
1227*4882a593Smuzhiyun SND_SOC_DAPM_PGA("OUTVOL R", RT5640_PWR_VOL,
1228*4882a593Smuzhiyun RT5640_PWR_OV_R_BIT, 0, NULL, 0),
1229*4882a593Smuzhiyun SND_SOC_DAPM_PGA("HPOVOL L", RT5640_PWR_VOL,
1230*4882a593Smuzhiyun RT5640_PWR_HV_L_BIT, 0, NULL, 0),
1231*4882a593Smuzhiyun SND_SOC_DAPM_PGA("HPOVOL R", RT5640_PWR_VOL,
1232*4882a593Smuzhiyun RT5640_PWR_HV_R_BIT, 0, NULL, 0),
1233*4882a593Smuzhiyun /* SPO/HPO/LOUT/Mono Mixer */
1234*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
1235*4882a593Smuzhiyun 0, rt5640_spo_l_mix, ARRAY_SIZE(rt5640_spo_l_mix)),
1236*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
1237*4882a593Smuzhiyun 0, rt5640_spo_r_mix, ARRAY_SIZE(rt5640_spo_r_mix)),
1238*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
1239*4882a593Smuzhiyun rt5640_lout_mix, ARRAY_SIZE(rt5640_lout_mix)),
1240*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM,
1241*4882a593Smuzhiyun 0, 0, rt5640_hp_power_event, SND_SOC_DAPM_POST_PMU),
1242*4882a593Smuzhiyun SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
1243*4882a593Smuzhiyun rt5640_hp_event,
1244*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1245*4882a593Smuzhiyun SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
1246*4882a593Smuzhiyun rt5640_lout_event,
1247*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1248*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("HP L Amp", RT5640_PWR_ANLG1,
1249*4882a593Smuzhiyun RT5640_PWR_HP_L_BIT, 0, NULL, 0),
1250*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("HP R Amp", RT5640_PWR_ANLG1,
1251*4882a593Smuzhiyun RT5640_PWR_HP_R_BIT, 0, NULL, 0),
1252*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Improve SPK Amp Drv", RT5640_PWR_DIG1,
1253*4882a593Smuzhiyun RT5640_PWR_CLS_D_BIT, 0, NULL, 0),
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun /* Output Switch */
1256*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("Speaker L Playback", SND_SOC_NOPM, 0, 0,
1257*4882a593Smuzhiyun &spk_l_enable_control),
1258*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("Speaker R Playback", SND_SOC_NOPM, 0, 0,
1259*4882a593Smuzhiyun &spk_r_enable_control),
1260*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("HP L Playback", SND_SOC_NOPM, 0, 0,
1261*4882a593Smuzhiyun &hp_l_enable_control),
1262*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("HP R Playback", SND_SOC_NOPM, 0, 0,
1263*4882a593Smuzhiyun &hp_r_enable_control),
1264*4882a593Smuzhiyun SND_SOC_DAPM_POST("HP Post", rt5640_hp_post_event),
1265*4882a593Smuzhiyun /* Output Lines */
1266*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPOLP"),
1267*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPOLN"),
1268*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPORP"),
1269*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPORN"),
1270*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOL"),
1271*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOR"),
1272*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LOUTL"),
1273*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LOUTR"),
1274*4882a593Smuzhiyun };
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun static const struct snd_soc_dapm_widget rt5640_specific_dapm_widgets[] = {
1277*4882a593Smuzhiyun /* Audio DSP */
1278*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1279*4882a593Smuzhiyun /* ANC */
1280*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun /* DAC2 channel Mux */
1283*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dac_l2_mux),
1284*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dac_r2_mux),
1285*4882a593Smuzhiyun
1286*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1287*4882a593Smuzhiyun rt5640_sto_dac_l_mix, ARRAY_SIZE(rt5640_sto_dac_l_mix)),
1288*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1289*4882a593Smuzhiyun rt5640_sto_dac_r_mix, ARRAY_SIZE(rt5640_sto_dac_r_mix)),
1290*4882a593Smuzhiyun
1291*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0,
1292*4882a593Smuzhiyun 0),
1293*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0,
1294*4882a593Smuzhiyun 0),
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
1297*4882a593Smuzhiyun 0, rt5640_out_l_mix, ARRAY_SIZE(rt5640_out_l_mix)),
1298*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
1299*4882a593Smuzhiyun 0, rt5640_out_r_mix, ARRAY_SIZE(rt5640_out_r_mix)),
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("HPO MIX L", SND_SOC_NOPM, 0, 0,
1302*4882a593Smuzhiyun rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1303*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("HPO MIX R", SND_SOC_NOPM, 0, 0,
1304*4882a593Smuzhiyun rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mono MIX", RT5640_PWR_ANLG1, RT5640_PWR_MM_BIT, 0,
1307*4882a593Smuzhiyun rt5640_mono_mix, ARRAY_SIZE(rt5640_mono_mix)),
1308*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Improve MONO Amp Drv", RT5640_PWR_ANLG1,
1309*4882a593Smuzhiyun RT5640_PWR_MA_BIT, 0, NULL, 0),
1310*4882a593Smuzhiyun
1311*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MONOP"),
1312*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MONON"),
1313*4882a593Smuzhiyun };
1314*4882a593Smuzhiyun
1315*4882a593Smuzhiyun static const struct snd_soc_dapm_widget rt5639_specific_dapm_widgets[] = {
1316*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1317*4882a593Smuzhiyun rt5639_sto_dac_l_mix, ARRAY_SIZE(rt5639_sto_dac_l_mix)),
1318*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1319*4882a593Smuzhiyun rt5639_sto_dac_r_mix, ARRAY_SIZE(rt5639_sto_dac_r_mix)),
1320*4882a593Smuzhiyun
1321*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
1322*4882a593Smuzhiyun 0, rt5639_out_l_mix, ARRAY_SIZE(rt5639_out_l_mix)),
1323*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
1324*4882a593Smuzhiyun 0, rt5639_out_r_mix, ARRAY_SIZE(rt5639_out_r_mix)),
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("HPO MIX L", SND_SOC_NOPM, 0, 0,
1327*4882a593Smuzhiyun rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
1328*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("HPO MIX R", SND_SOC_NOPM, 0, 0,
1329*4882a593Smuzhiyun rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
1330*4882a593Smuzhiyun };
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
1333*4882a593Smuzhiyun { "I2S1", NULL, "Stereo Filter ASRC", is_using_asrc },
1334*4882a593Smuzhiyun { "I2S2", NULL, "I2S2 ASRC", is_using_asrc },
1335*4882a593Smuzhiyun { "I2S2", NULL, "I2S2 Filter ASRC", is_using_asrc },
1336*4882a593Smuzhiyun { "DMIC1", NULL, "DMIC1 ASRC", is_using_asrc },
1337*4882a593Smuzhiyun { "DMIC2", NULL, "DMIC2 ASRC", is_using_asrc },
1338*4882a593Smuzhiyun {"IN1P", NULL, "MICBIAS1"},
1339*4882a593Smuzhiyun {"IN2P", NULL, "MICBIAS1"},
1340*4882a593Smuzhiyun {"IN3P", NULL, "MICBIAS1"},
1341*4882a593Smuzhiyun {"IN1P", NULL, "LDO2"},
1342*4882a593Smuzhiyun {"IN2P", NULL, "LDO2"},
1343*4882a593Smuzhiyun {"IN3P", NULL, "LDO2"},
1344*4882a593Smuzhiyun
1345*4882a593Smuzhiyun {"DMIC L1", NULL, "DMIC1"},
1346*4882a593Smuzhiyun {"DMIC R1", NULL, "DMIC1"},
1347*4882a593Smuzhiyun {"DMIC L2", NULL, "DMIC2"},
1348*4882a593Smuzhiyun {"DMIC R2", NULL, "DMIC2"},
1349*4882a593Smuzhiyun
1350*4882a593Smuzhiyun {"BST1", NULL, "IN1P"},
1351*4882a593Smuzhiyun {"BST1", NULL, "IN1N"},
1352*4882a593Smuzhiyun {"BST2", NULL, "IN2P"},
1353*4882a593Smuzhiyun {"BST2", NULL, "IN2N"},
1354*4882a593Smuzhiyun {"BST3", NULL, "IN3P"},
1355*4882a593Smuzhiyun {"BST3", NULL, "IN3N"},
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun {"INL VOL", NULL, "IN2P"},
1358*4882a593Smuzhiyun {"INR VOL", NULL, "IN2N"},
1359*4882a593Smuzhiyun
1360*4882a593Smuzhiyun {"RECMIXL", "HPOL Switch", "HPOL"},
1361*4882a593Smuzhiyun {"RECMIXL", "INL Switch", "INL VOL"},
1362*4882a593Smuzhiyun {"RECMIXL", "BST3 Switch", "BST3"},
1363*4882a593Smuzhiyun {"RECMIXL", "BST2 Switch", "BST2"},
1364*4882a593Smuzhiyun {"RECMIXL", "BST1 Switch", "BST1"},
1365*4882a593Smuzhiyun {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun {"RECMIXR", "HPOR Switch", "HPOR"},
1368*4882a593Smuzhiyun {"RECMIXR", "INR Switch", "INR VOL"},
1369*4882a593Smuzhiyun {"RECMIXR", "BST3 Switch", "BST3"},
1370*4882a593Smuzhiyun {"RECMIXR", "BST2 Switch", "BST2"},
1371*4882a593Smuzhiyun {"RECMIXR", "BST1 Switch", "BST1"},
1372*4882a593Smuzhiyun {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
1373*4882a593Smuzhiyun
1374*4882a593Smuzhiyun {"ADC L", NULL, "RECMIXL"},
1375*4882a593Smuzhiyun {"ADC R", NULL, "RECMIXR"},
1376*4882a593Smuzhiyun
1377*4882a593Smuzhiyun {"DMIC L1", NULL, "DMIC CLK"},
1378*4882a593Smuzhiyun {"DMIC L1", NULL, "DMIC1 Power"},
1379*4882a593Smuzhiyun {"DMIC R1", NULL, "DMIC CLK"},
1380*4882a593Smuzhiyun {"DMIC R1", NULL, "DMIC1 Power"},
1381*4882a593Smuzhiyun {"DMIC L2", NULL, "DMIC CLK"},
1382*4882a593Smuzhiyun {"DMIC L2", NULL, "DMIC2 Power"},
1383*4882a593Smuzhiyun {"DMIC R2", NULL, "DMIC CLK"},
1384*4882a593Smuzhiyun {"DMIC R2", NULL, "DMIC2 Power"},
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
1387*4882a593Smuzhiyun {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
1388*4882a593Smuzhiyun {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
1389*4882a593Smuzhiyun {"Stereo ADC L1 Mux", "ADC", "ADC L"},
1390*4882a593Smuzhiyun {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun {"Stereo ADC R1 Mux", "ADC", "ADC R"},
1393*4882a593Smuzhiyun {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
1394*4882a593Smuzhiyun {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
1395*4882a593Smuzhiyun {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
1396*4882a593Smuzhiyun {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
1397*4882a593Smuzhiyun
1398*4882a593Smuzhiyun {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
1399*4882a593Smuzhiyun {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
1400*4882a593Smuzhiyun {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1401*4882a593Smuzhiyun {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1402*4882a593Smuzhiyun {"Mono ADC L1 Mux", "ADCL", "ADC L"},
1403*4882a593Smuzhiyun
1404*4882a593Smuzhiyun {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1405*4882a593Smuzhiyun {"Mono ADC R1 Mux", "ADCR", "ADC R"},
1406*4882a593Smuzhiyun {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
1407*4882a593Smuzhiyun {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
1408*4882a593Smuzhiyun {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
1411*4882a593Smuzhiyun {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
1412*4882a593Smuzhiyun {"Stereo ADC MIXL", NULL, "Stereo Filter"},
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
1415*4882a593Smuzhiyun {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
1416*4882a593Smuzhiyun {"Stereo ADC MIXR", NULL, "Stereo Filter"},
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
1419*4882a593Smuzhiyun {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
1420*4882a593Smuzhiyun {"Mono ADC MIXL", NULL, "Mono Left Filter"},
1421*4882a593Smuzhiyun
1422*4882a593Smuzhiyun {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
1423*4882a593Smuzhiyun {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
1424*4882a593Smuzhiyun {"Mono ADC MIXR", NULL, "Mono Right Filter"},
1425*4882a593Smuzhiyun
1426*4882a593Smuzhiyun {"IF2 ADC L", NULL, "Mono ADC MIXL"},
1427*4882a593Smuzhiyun {"IF2 ADC R", NULL, "Mono ADC MIXR"},
1428*4882a593Smuzhiyun {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
1429*4882a593Smuzhiyun {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun {"IF1 ADC", NULL, "I2S1"},
1432*4882a593Smuzhiyun {"IF1 ADC", NULL, "IF1 ADC L"},
1433*4882a593Smuzhiyun {"IF1 ADC", NULL, "IF1 ADC R"},
1434*4882a593Smuzhiyun {"IF2 ADC", NULL, "I2S2"},
1435*4882a593Smuzhiyun {"IF2 ADC", NULL, "IF2 ADC L"},
1436*4882a593Smuzhiyun {"IF2 ADC", NULL, "IF2 ADC R"},
1437*4882a593Smuzhiyun
1438*4882a593Smuzhiyun {"DAI1 TX Mux", "1:1|2:2", "IF1 ADC"},
1439*4882a593Smuzhiyun {"DAI1 TX Mux", "1:2|2:1", "IF2 ADC"},
1440*4882a593Smuzhiyun {"DAI1 IF1 Mux", "1:1|2:1", "IF1 ADC"},
1441*4882a593Smuzhiyun {"DAI1 IF2 Mux", "1:1|2:1", "IF2 ADC"},
1442*4882a593Smuzhiyun {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
1443*4882a593Smuzhiyun {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
1444*4882a593Smuzhiyun
1445*4882a593Smuzhiyun {"DAI2 TX Mux", "1:2|2:1", "IF1 ADC"},
1446*4882a593Smuzhiyun {"DAI2 TX Mux", "1:1|2:2", "IF2 ADC"},
1447*4882a593Smuzhiyun {"DAI2 IF1 Mux", "1:2|2:2", "IF1 ADC"},
1448*4882a593Smuzhiyun {"DAI2 IF2 Mux", "1:2|2:2", "IF2 ADC"},
1449*4882a593Smuzhiyun {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
1450*4882a593Smuzhiyun {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
1451*4882a593Smuzhiyun
1452*4882a593Smuzhiyun {"AIF1TX", NULL, "DAI1 TX Mux"},
1453*4882a593Smuzhiyun {"AIF1TX", NULL, "SDI1 TX Mux"},
1454*4882a593Smuzhiyun {"AIF2TX", NULL, "DAI2 TX Mux"},
1455*4882a593Smuzhiyun {"AIF2TX", NULL, "SDI2 TX Mux"},
1456*4882a593Smuzhiyun
1457*4882a593Smuzhiyun {"DAI1 RX Mux", "1:1|2:2", "AIF1RX"},
1458*4882a593Smuzhiyun {"DAI1 RX Mux", "1:1|2:1", "AIF1RX"},
1459*4882a593Smuzhiyun {"DAI1 RX Mux", "1:2|2:1", "AIF2RX"},
1460*4882a593Smuzhiyun {"DAI1 RX Mux", "1:2|2:2", "AIF2RX"},
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun {"DAI2 RX Mux", "1:2|2:1", "AIF1RX"},
1463*4882a593Smuzhiyun {"DAI2 RX Mux", "1:1|2:1", "AIF1RX"},
1464*4882a593Smuzhiyun {"DAI2 RX Mux", "1:1|2:2", "AIF2RX"},
1465*4882a593Smuzhiyun {"DAI2 RX Mux", "1:2|2:2", "AIF2RX"},
1466*4882a593Smuzhiyun
1467*4882a593Smuzhiyun {"IF1 DAC", NULL, "I2S1"},
1468*4882a593Smuzhiyun {"IF1 DAC", NULL, "DAI1 RX Mux"},
1469*4882a593Smuzhiyun {"IF2 DAC", NULL, "I2S2"},
1470*4882a593Smuzhiyun {"IF2 DAC", NULL, "DAI2 RX Mux"},
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun {"IF1 DAC L", NULL, "IF1 DAC"},
1473*4882a593Smuzhiyun {"IF1 DAC R", NULL, "IF1 DAC"},
1474*4882a593Smuzhiyun {"IF2 DAC L", NULL, "IF2 DAC"},
1475*4882a593Smuzhiyun {"IF2 DAC R", NULL, "IF2 DAC"},
1476*4882a593Smuzhiyun
1477*4882a593Smuzhiyun {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
1478*4882a593Smuzhiyun {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
1479*4882a593Smuzhiyun {"DAC MIXL", NULL, "DAC L1 Power"},
1480*4882a593Smuzhiyun {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
1481*4882a593Smuzhiyun {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
1482*4882a593Smuzhiyun {"DAC MIXR", NULL, "DAC R1 Power"},
1483*4882a593Smuzhiyun
1484*4882a593Smuzhiyun {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
1485*4882a593Smuzhiyun {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
1488*4882a593Smuzhiyun {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1489*4882a593Smuzhiyun
1490*4882a593Smuzhiyun {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
1491*4882a593Smuzhiyun {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun {"DAC L1", NULL, "Stereo DAC MIXL"},
1494*4882a593Smuzhiyun {"DAC L1", NULL, "DAC L1 Power"},
1495*4882a593Smuzhiyun {"DAC R1", NULL, "Stereo DAC MIXR"},
1496*4882a593Smuzhiyun {"DAC R1", NULL, "DAC R1 Power"},
1497*4882a593Smuzhiyun
1498*4882a593Smuzhiyun {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
1499*4882a593Smuzhiyun {"SPK MIXL", "INL Switch", "INL VOL"},
1500*4882a593Smuzhiyun {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
1501*4882a593Smuzhiyun {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
1502*4882a593Smuzhiyun {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
1503*4882a593Smuzhiyun {"SPK MIXR", "INR Switch", "INR VOL"},
1504*4882a593Smuzhiyun {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
1505*4882a593Smuzhiyun {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun {"OUT MIXL", "BST1 Switch", "BST1"},
1508*4882a593Smuzhiyun {"OUT MIXL", "INL Switch", "INL VOL"},
1509*4882a593Smuzhiyun {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1510*4882a593Smuzhiyun {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1511*4882a593Smuzhiyun
1512*4882a593Smuzhiyun {"OUT MIXR", "BST2 Switch", "BST2"},
1513*4882a593Smuzhiyun {"OUT MIXR", "BST1 Switch", "BST1"},
1514*4882a593Smuzhiyun {"OUT MIXR", "INR Switch", "INR VOL"},
1515*4882a593Smuzhiyun {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1516*4882a593Smuzhiyun {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun {"SPKVOL L", NULL, "SPK MIXL"},
1519*4882a593Smuzhiyun {"SPKVOL R", NULL, "SPK MIXR"},
1520*4882a593Smuzhiyun {"HPOVOL L", NULL, "OUT MIXL"},
1521*4882a593Smuzhiyun {"HPOVOL R", NULL, "OUT MIXR"},
1522*4882a593Smuzhiyun {"OUTVOL L", NULL, "OUT MIXL"},
1523*4882a593Smuzhiyun {"OUTVOL R", NULL, "OUT MIXR"},
1524*4882a593Smuzhiyun
1525*4882a593Smuzhiyun {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
1526*4882a593Smuzhiyun {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
1527*4882a593Smuzhiyun {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
1528*4882a593Smuzhiyun {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
1529*4882a593Smuzhiyun {"SPOL MIX", "BST1 Switch", "BST1"},
1530*4882a593Smuzhiyun {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
1531*4882a593Smuzhiyun {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
1532*4882a593Smuzhiyun {"SPOR MIX", "BST1 Switch", "BST1"},
1533*4882a593Smuzhiyun
1534*4882a593Smuzhiyun {"HPO MIX L", "HPO MIX DAC1 Switch", "DAC L1"},
1535*4882a593Smuzhiyun {"HPO MIX L", "HPO MIX HPVOL Switch", "HPOVOL L"},
1536*4882a593Smuzhiyun {"HPO MIX L", NULL, "HP L Amp"},
1537*4882a593Smuzhiyun {"HPO MIX R", "HPO MIX DAC1 Switch", "DAC R1"},
1538*4882a593Smuzhiyun {"HPO MIX R", "HPO MIX HPVOL Switch", "HPOVOL R"},
1539*4882a593Smuzhiyun {"HPO MIX R", NULL, "HP R Amp"},
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1542*4882a593Smuzhiyun {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1543*4882a593Smuzhiyun {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1544*4882a593Smuzhiyun {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1545*4882a593Smuzhiyun
1546*4882a593Smuzhiyun {"HP Amp", NULL, "HPO MIX L"},
1547*4882a593Smuzhiyun {"HP Amp", NULL, "HPO MIX R"},
1548*4882a593Smuzhiyun
1549*4882a593Smuzhiyun {"Speaker L Playback", "Switch", "SPOL MIX"},
1550*4882a593Smuzhiyun {"Speaker R Playback", "Switch", "SPOR MIX"},
1551*4882a593Smuzhiyun {"SPOLP", NULL, "Speaker L Playback"},
1552*4882a593Smuzhiyun {"SPOLN", NULL, "Speaker L Playback"},
1553*4882a593Smuzhiyun {"SPORP", NULL, "Speaker R Playback"},
1554*4882a593Smuzhiyun {"SPORN", NULL, "Speaker R Playback"},
1555*4882a593Smuzhiyun
1556*4882a593Smuzhiyun {"SPOLP", NULL, "Improve SPK Amp Drv"},
1557*4882a593Smuzhiyun {"SPOLN", NULL, "Improve SPK Amp Drv"},
1558*4882a593Smuzhiyun {"SPORP", NULL, "Improve SPK Amp Drv"},
1559*4882a593Smuzhiyun {"SPORN", NULL, "Improve SPK Amp Drv"},
1560*4882a593Smuzhiyun
1561*4882a593Smuzhiyun {"HPOL", NULL, "Improve HP Amp Drv"},
1562*4882a593Smuzhiyun {"HPOR", NULL, "Improve HP Amp Drv"},
1563*4882a593Smuzhiyun
1564*4882a593Smuzhiyun {"HP L Playback", "Switch", "HP Amp"},
1565*4882a593Smuzhiyun {"HP R Playback", "Switch", "HP Amp"},
1566*4882a593Smuzhiyun {"HPOL", NULL, "HP L Playback"},
1567*4882a593Smuzhiyun {"HPOR", NULL, "HP R Playback"},
1568*4882a593Smuzhiyun
1569*4882a593Smuzhiyun {"LOUT amp", NULL, "LOUT MIX"},
1570*4882a593Smuzhiyun {"LOUTL", NULL, "LOUT amp"},
1571*4882a593Smuzhiyun {"LOUTR", NULL, "LOUT amp"},
1572*4882a593Smuzhiyun };
1573*4882a593Smuzhiyun
1574*4882a593Smuzhiyun static const struct snd_soc_dapm_route rt5640_specific_dapm_routes[] = {
1575*4882a593Smuzhiyun {"ANC", NULL, "Stereo ADC MIXL"},
1576*4882a593Smuzhiyun {"ANC", NULL, "Stereo ADC MIXR"},
1577*4882a593Smuzhiyun
1578*4882a593Smuzhiyun {"Audio DSP", NULL, "DAC MIXL"},
1579*4882a593Smuzhiyun {"Audio DSP", NULL, "DAC MIXR"},
1580*4882a593Smuzhiyun
1581*4882a593Smuzhiyun {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1582*4882a593Smuzhiyun {"DAC L2 Mux", "Base L/R", "Audio DSP"},
1583*4882a593Smuzhiyun {"DAC L2 Mux", NULL, "DAC L2 Power"},
1584*4882a593Smuzhiyun {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1585*4882a593Smuzhiyun {"DAC R2 Mux", NULL, "DAC R2 Power"},
1586*4882a593Smuzhiyun
1587*4882a593Smuzhiyun {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1588*4882a593Smuzhiyun {"Stereo DAC MIXL", "ANC Switch", "ANC"},
1589*4882a593Smuzhiyun {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1590*4882a593Smuzhiyun {"Stereo DAC MIXR", "ANC Switch", "ANC"},
1591*4882a593Smuzhiyun
1592*4882a593Smuzhiyun {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1593*4882a593Smuzhiyun {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
1594*4882a593Smuzhiyun
1595*4882a593Smuzhiyun {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1596*4882a593Smuzhiyun {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
1597*4882a593Smuzhiyun
1598*4882a593Smuzhiyun {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1599*4882a593Smuzhiyun {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1600*4882a593Smuzhiyun
1601*4882a593Smuzhiyun {"DAC L2", NULL, "Mono DAC MIXL"},
1602*4882a593Smuzhiyun {"DAC L2", NULL, "DAC L2 Power"},
1603*4882a593Smuzhiyun {"DAC R2", NULL, "Mono DAC MIXR"},
1604*4882a593Smuzhiyun {"DAC R2", NULL, "DAC R2 Power"},
1605*4882a593Smuzhiyun
1606*4882a593Smuzhiyun {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
1607*4882a593Smuzhiyun {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
1608*4882a593Smuzhiyun
1609*4882a593Smuzhiyun {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
1610*4882a593Smuzhiyun {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
1613*4882a593Smuzhiyun {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
1614*4882a593Smuzhiyun
1615*4882a593Smuzhiyun {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
1616*4882a593Smuzhiyun {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
1617*4882a593Smuzhiyun
1618*4882a593Smuzhiyun {"HPO MIX L", "HPO MIX DAC2 Switch", "DAC L2"},
1619*4882a593Smuzhiyun {"HPO MIX R", "HPO MIX DAC2 Switch", "DAC R2"},
1620*4882a593Smuzhiyun
1621*4882a593Smuzhiyun {"Mono MIX", "DAC R2 Switch", "DAC R2"},
1622*4882a593Smuzhiyun {"Mono MIX", "DAC L2 Switch", "DAC L2"},
1623*4882a593Smuzhiyun {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
1624*4882a593Smuzhiyun {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
1625*4882a593Smuzhiyun {"Mono MIX", "BST1 Switch", "BST1"},
1626*4882a593Smuzhiyun
1627*4882a593Smuzhiyun {"MONOP", NULL, "Mono MIX"},
1628*4882a593Smuzhiyun {"MONON", NULL, "Mono MIX"},
1629*4882a593Smuzhiyun {"MONOP", NULL, "Improve MONO Amp Drv"},
1630*4882a593Smuzhiyun };
1631*4882a593Smuzhiyun
1632*4882a593Smuzhiyun static const struct snd_soc_dapm_route rt5639_specific_dapm_routes[] = {
1633*4882a593Smuzhiyun {"Stereo DAC MIXL", "DAC L2 Switch", "IF2 DAC L"},
1634*4882a593Smuzhiyun {"Stereo DAC MIXR", "DAC R2 Switch", "IF2 DAC R"},
1635*4882a593Smuzhiyun
1636*4882a593Smuzhiyun {"Mono DAC MIXL", "DAC L2 Switch", "IF2 DAC L"},
1637*4882a593Smuzhiyun {"Mono DAC MIXL", "DAC R2 Switch", "IF2 DAC R"},
1638*4882a593Smuzhiyun
1639*4882a593Smuzhiyun {"Mono DAC MIXR", "DAC R2 Switch", "IF2 DAC R"},
1640*4882a593Smuzhiyun {"Mono DAC MIXR", "DAC L2 Switch", "IF2 DAC L"},
1641*4882a593Smuzhiyun
1642*4882a593Smuzhiyun {"DIG MIXL", "DAC L2 Switch", "IF2 DAC L"},
1643*4882a593Smuzhiyun {"DIG MIXR", "DAC R2 Switch", "IF2 DAC R"},
1644*4882a593Smuzhiyun
1645*4882a593Smuzhiyun {"IF2 DAC L", NULL, "DAC L2 Power"},
1646*4882a593Smuzhiyun {"IF2 DAC R", NULL, "DAC R2 Power"},
1647*4882a593Smuzhiyun };
1648*4882a593Smuzhiyun
get_sdp_info(struct snd_soc_component * component,int dai_id)1649*4882a593Smuzhiyun static int get_sdp_info(struct snd_soc_component *component, int dai_id)
1650*4882a593Smuzhiyun {
1651*4882a593Smuzhiyun int ret = 0, val;
1652*4882a593Smuzhiyun
1653*4882a593Smuzhiyun if (component == NULL)
1654*4882a593Smuzhiyun return -EINVAL;
1655*4882a593Smuzhiyun
1656*4882a593Smuzhiyun val = snd_soc_component_read(component, RT5640_I2S1_SDP);
1657*4882a593Smuzhiyun val = (val & RT5640_I2S_IF_MASK) >> RT5640_I2S_IF_SFT;
1658*4882a593Smuzhiyun switch (dai_id) {
1659*4882a593Smuzhiyun case RT5640_AIF1:
1660*4882a593Smuzhiyun switch (val) {
1661*4882a593Smuzhiyun case RT5640_IF_123:
1662*4882a593Smuzhiyun case RT5640_IF_132:
1663*4882a593Smuzhiyun ret |= RT5640_U_IF1;
1664*4882a593Smuzhiyun break;
1665*4882a593Smuzhiyun case RT5640_IF_113:
1666*4882a593Smuzhiyun ret |= RT5640_U_IF1;
1667*4882a593Smuzhiyun fallthrough;
1668*4882a593Smuzhiyun case RT5640_IF_312:
1669*4882a593Smuzhiyun case RT5640_IF_213:
1670*4882a593Smuzhiyun ret |= RT5640_U_IF2;
1671*4882a593Smuzhiyun break;
1672*4882a593Smuzhiyun }
1673*4882a593Smuzhiyun break;
1674*4882a593Smuzhiyun
1675*4882a593Smuzhiyun case RT5640_AIF2:
1676*4882a593Smuzhiyun switch (val) {
1677*4882a593Smuzhiyun case RT5640_IF_231:
1678*4882a593Smuzhiyun case RT5640_IF_213:
1679*4882a593Smuzhiyun ret |= RT5640_U_IF1;
1680*4882a593Smuzhiyun break;
1681*4882a593Smuzhiyun case RT5640_IF_223:
1682*4882a593Smuzhiyun ret |= RT5640_U_IF1;
1683*4882a593Smuzhiyun fallthrough;
1684*4882a593Smuzhiyun case RT5640_IF_123:
1685*4882a593Smuzhiyun case RT5640_IF_321:
1686*4882a593Smuzhiyun ret |= RT5640_U_IF2;
1687*4882a593Smuzhiyun break;
1688*4882a593Smuzhiyun }
1689*4882a593Smuzhiyun break;
1690*4882a593Smuzhiyun
1691*4882a593Smuzhiyun default:
1692*4882a593Smuzhiyun ret = -EINVAL;
1693*4882a593Smuzhiyun break;
1694*4882a593Smuzhiyun }
1695*4882a593Smuzhiyun
1696*4882a593Smuzhiyun return ret;
1697*4882a593Smuzhiyun }
1698*4882a593Smuzhiyun
rt5640_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1699*4882a593Smuzhiyun static int rt5640_hw_params(struct snd_pcm_substream *substream,
1700*4882a593Smuzhiyun struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1701*4882a593Smuzhiyun {
1702*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
1703*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
1704*4882a593Smuzhiyun unsigned int val_len = 0, val_clk, mask_clk;
1705*4882a593Smuzhiyun int dai_sel, pre_div, bclk_ms, frame_size;
1706*4882a593Smuzhiyun
1707*4882a593Smuzhiyun rt5640->lrck[dai->id] = params_rate(params);
1708*4882a593Smuzhiyun pre_div = rl6231_get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]);
1709*4882a593Smuzhiyun if (pre_div < 0) {
1710*4882a593Smuzhiyun dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
1711*4882a593Smuzhiyun rt5640->lrck[dai->id], dai->id);
1712*4882a593Smuzhiyun return -EINVAL;
1713*4882a593Smuzhiyun }
1714*4882a593Smuzhiyun frame_size = snd_soc_params_to_frame_size(params);
1715*4882a593Smuzhiyun if (frame_size < 0) {
1716*4882a593Smuzhiyun dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
1717*4882a593Smuzhiyun return frame_size;
1718*4882a593Smuzhiyun }
1719*4882a593Smuzhiyun if (frame_size > 32)
1720*4882a593Smuzhiyun bclk_ms = 1;
1721*4882a593Smuzhiyun else
1722*4882a593Smuzhiyun bclk_ms = 0;
1723*4882a593Smuzhiyun rt5640->bclk[dai->id] = rt5640->lrck[dai->id] * (32 << bclk_ms);
1724*4882a593Smuzhiyun
1725*4882a593Smuzhiyun dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1726*4882a593Smuzhiyun rt5640->bclk[dai->id], rt5640->lrck[dai->id]);
1727*4882a593Smuzhiyun dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1728*4882a593Smuzhiyun bclk_ms, pre_div, dai->id);
1729*4882a593Smuzhiyun
1730*4882a593Smuzhiyun switch (params_width(params)) {
1731*4882a593Smuzhiyun case 16:
1732*4882a593Smuzhiyun break;
1733*4882a593Smuzhiyun case 20:
1734*4882a593Smuzhiyun val_len |= RT5640_I2S_DL_20;
1735*4882a593Smuzhiyun break;
1736*4882a593Smuzhiyun case 24:
1737*4882a593Smuzhiyun val_len |= RT5640_I2S_DL_24;
1738*4882a593Smuzhiyun break;
1739*4882a593Smuzhiyun case 8:
1740*4882a593Smuzhiyun val_len |= RT5640_I2S_DL_8;
1741*4882a593Smuzhiyun break;
1742*4882a593Smuzhiyun default:
1743*4882a593Smuzhiyun return -EINVAL;
1744*4882a593Smuzhiyun }
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun dai_sel = get_sdp_info(component, dai->id);
1747*4882a593Smuzhiyun if (dai_sel < 0) {
1748*4882a593Smuzhiyun dev_err(component->dev, "Failed to get sdp info: %d\n", dai_sel);
1749*4882a593Smuzhiyun return -EINVAL;
1750*4882a593Smuzhiyun }
1751*4882a593Smuzhiyun if (dai_sel & RT5640_U_IF1) {
1752*4882a593Smuzhiyun mask_clk = RT5640_I2S_BCLK_MS1_MASK | RT5640_I2S_PD1_MASK;
1753*4882a593Smuzhiyun val_clk = bclk_ms << RT5640_I2S_BCLK_MS1_SFT |
1754*4882a593Smuzhiyun pre_div << RT5640_I2S_PD1_SFT;
1755*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_I2S1_SDP,
1756*4882a593Smuzhiyun RT5640_I2S_DL_MASK, val_len);
1757*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_ADDA_CLK1, mask_clk, val_clk);
1758*4882a593Smuzhiyun }
1759*4882a593Smuzhiyun if (dai_sel & RT5640_U_IF2) {
1760*4882a593Smuzhiyun mask_clk = RT5640_I2S_BCLK_MS2_MASK | RT5640_I2S_PD2_MASK;
1761*4882a593Smuzhiyun val_clk = bclk_ms << RT5640_I2S_BCLK_MS2_SFT |
1762*4882a593Smuzhiyun pre_div << RT5640_I2S_PD2_SFT;
1763*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_I2S2_SDP,
1764*4882a593Smuzhiyun RT5640_I2S_DL_MASK, val_len);
1765*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_ADDA_CLK1, mask_clk, val_clk);
1766*4882a593Smuzhiyun }
1767*4882a593Smuzhiyun
1768*4882a593Smuzhiyun return 0;
1769*4882a593Smuzhiyun }
1770*4882a593Smuzhiyun
rt5640_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)1771*4882a593Smuzhiyun static int rt5640_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1772*4882a593Smuzhiyun {
1773*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
1774*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
1775*4882a593Smuzhiyun unsigned int reg_val = 0;
1776*4882a593Smuzhiyun int dai_sel;
1777*4882a593Smuzhiyun
1778*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1779*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
1780*4882a593Smuzhiyun rt5640->master[dai->id] = 1;
1781*4882a593Smuzhiyun break;
1782*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
1783*4882a593Smuzhiyun reg_val |= RT5640_I2S_MS_S;
1784*4882a593Smuzhiyun rt5640->master[dai->id] = 0;
1785*4882a593Smuzhiyun break;
1786*4882a593Smuzhiyun default:
1787*4882a593Smuzhiyun return -EINVAL;
1788*4882a593Smuzhiyun }
1789*4882a593Smuzhiyun
1790*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1791*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
1792*4882a593Smuzhiyun break;
1793*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
1794*4882a593Smuzhiyun reg_val |= RT5640_I2S_BP_INV;
1795*4882a593Smuzhiyun break;
1796*4882a593Smuzhiyun default:
1797*4882a593Smuzhiyun return -EINVAL;
1798*4882a593Smuzhiyun }
1799*4882a593Smuzhiyun
1800*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1801*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
1802*4882a593Smuzhiyun break;
1803*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
1804*4882a593Smuzhiyun reg_val |= RT5640_I2S_DF_LEFT;
1805*4882a593Smuzhiyun break;
1806*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
1807*4882a593Smuzhiyun reg_val |= RT5640_I2S_DF_PCM_A;
1808*4882a593Smuzhiyun break;
1809*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
1810*4882a593Smuzhiyun reg_val |= RT5640_I2S_DF_PCM_B;
1811*4882a593Smuzhiyun break;
1812*4882a593Smuzhiyun default:
1813*4882a593Smuzhiyun return -EINVAL;
1814*4882a593Smuzhiyun }
1815*4882a593Smuzhiyun
1816*4882a593Smuzhiyun dai_sel = get_sdp_info(component, dai->id);
1817*4882a593Smuzhiyun if (dai_sel < 0) {
1818*4882a593Smuzhiyun dev_err(component->dev, "Failed to get sdp info: %d\n", dai_sel);
1819*4882a593Smuzhiyun return -EINVAL;
1820*4882a593Smuzhiyun }
1821*4882a593Smuzhiyun if (dai_sel & RT5640_U_IF1) {
1822*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_I2S1_SDP,
1823*4882a593Smuzhiyun RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
1824*4882a593Smuzhiyun RT5640_I2S_DF_MASK, reg_val);
1825*4882a593Smuzhiyun }
1826*4882a593Smuzhiyun if (dai_sel & RT5640_U_IF2) {
1827*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_I2S2_SDP,
1828*4882a593Smuzhiyun RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
1829*4882a593Smuzhiyun RT5640_I2S_DF_MASK, reg_val);
1830*4882a593Smuzhiyun }
1831*4882a593Smuzhiyun
1832*4882a593Smuzhiyun return 0;
1833*4882a593Smuzhiyun }
1834*4882a593Smuzhiyun
rt5640_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1835*4882a593Smuzhiyun static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
1836*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
1837*4882a593Smuzhiyun {
1838*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
1839*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
1840*4882a593Smuzhiyun unsigned int reg_val = 0;
1841*4882a593Smuzhiyun unsigned int pll_bit = 0;
1842*4882a593Smuzhiyun
1843*4882a593Smuzhiyun if (freq == rt5640->sysclk && clk_id == rt5640->sysclk_src)
1844*4882a593Smuzhiyun return 0;
1845*4882a593Smuzhiyun
1846*4882a593Smuzhiyun switch (clk_id) {
1847*4882a593Smuzhiyun case RT5640_SCLK_S_MCLK:
1848*4882a593Smuzhiyun reg_val |= RT5640_SCLK_SRC_MCLK;
1849*4882a593Smuzhiyun break;
1850*4882a593Smuzhiyun case RT5640_SCLK_S_PLL1:
1851*4882a593Smuzhiyun reg_val |= RT5640_SCLK_SRC_PLL1;
1852*4882a593Smuzhiyun pll_bit |= RT5640_PWR_PLL;
1853*4882a593Smuzhiyun break;
1854*4882a593Smuzhiyun case RT5640_SCLK_S_RCCLK:
1855*4882a593Smuzhiyun reg_val |= RT5640_SCLK_SRC_RCCLK;
1856*4882a593Smuzhiyun break;
1857*4882a593Smuzhiyun default:
1858*4882a593Smuzhiyun dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
1859*4882a593Smuzhiyun return -EINVAL;
1860*4882a593Smuzhiyun }
1861*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_PWR_ANLG2,
1862*4882a593Smuzhiyun RT5640_PWR_PLL, pll_bit);
1863*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_GLB_CLK,
1864*4882a593Smuzhiyun RT5640_SCLK_SRC_MASK, reg_val);
1865*4882a593Smuzhiyun rt5640->sysclk = freq;
1866*4882a593Smuzhiyun rt5640->sysclk_src = clk_id;
1867*4882a593Smuzhiyun
1868*4882a593Smuzhiyun dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1869*4882a593Smuzhiyun return 0;
1870*4882a593Smuzhiyun }
1871*4882a593Smuzhiyun
rt5640_set_dai_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)1872*4882a593Smuzhiyun static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1873*4882a593Smuzhiyun unsigned int freq_in, unsigned int freq_out)
1874*4882a593Smuzhiyun {
1875*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
1876*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
1877*4882a593Smuzhiyun struct rl6231_pll_code pll_code;
1878*4882a593Smuzhiyun int ret;
1879*4882a593Smuzhiyun
1880*4882a593Smuzhiyun if (source == rt5640->pll_src && freq_in == rt5640->pll_in &&
1881*4882a593Smuzhiyun freq_out == rt5640->pll_out)
1882*4882a593Smuzhiyun return 0;
1883*4882a593Smuzhiyun
1884*4882a593Smuzhiyun if (!freq_in || !freq_out) {
1885*4882a593Smuzhiyun dev_dbg(component->dev, "PLL disabled\n");
1886*4882a593Smuzhiyun
1887*4882a593Smuzhiyun rt5640->pll_in = 0;
1888*4882a593Smuzhiyun rt5640->pll_out = 0;
1889*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_GLB_CLK,
1890*4882a593Smuzhiyun RT5640_SCLK_SRC_MASK, RT5640_SCLK_SRC_MCLK);
1891*4882a593Smuzhiyun return 0;
1892*4882a593Smuzhiyun }
1893*4882a593Smuzhiyun
1894*4882a593Smuzhiyun switch (source) {
1895*4882a593Smuzhiyun case RT5640_PLL1_S_MCLK:
1896*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_GLB_CLK,
1897*4882a593Smuzhiyun RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_MCLK);
1898*4882a593Smuzhiyun break;
1899*4882a593Smuzhiyun case RT5640_PLL1_S_BCLK1:
1900*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_GLB_CLK,
1901*4882a593Smuzhiyun RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK1);
1902*4882a593Smuzhiyun break;
1903*4882a593Smuzhiyun case RT5640_PLL1_S_BCLK2:
1904*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_GLB_CLK,
1905*4882a593Smuzhiyun RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK2);
1906*4882a593Smuzhiyun break;
1907*4882a593Smuzhiyun default:
1908*4882a593Smuzhiyun dev_err(component->dev, "Unknown PLL source %d\n", source);
1909*4882a593Smuzhiyun return -EINVAL;
1910*4882a593Smuzhiyun }
1911*4882a593Smuzhiyun
1912*4882a593Smuzhiyun ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1913*4882a593Smuzhiyun if (ret < 0) {
1914*4882a593Smuzhiyun dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
1915*4882a593Smuzhiyun return ret;
1916*4882a593Smuzhiyun }
1917*4882a593Smuzhiyun
1918*4882a593Smuzhiyun dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
1919*4882a593Smuzhiyun pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1920*4882a593Smuzhiyun pll_code.n_code, pll_code.k_code);
1921*4882a593Smuzhiyun
1922*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_PLL_CTRL1,
1923*4882a593Smuzhiyun pll_code.n_code << RT5640_PLL_N_SFT | pll_code.k_code);
1924*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_PLL_CTRL2,
1925*4882a593Smuzhiyun (pll_code.m_bp ? 0 : pll_code.m_code) << RT5640_PLL_M_SFT |
1926*4882a593Smuzhiyun pll_code.m_bp << RT5640_PLL_M_BP_SFT);
1927*4882a593Smuzhiyun
1928*4882a593Smuzhiyun rt5640->pll_in = freq_in;
1929*4882a593Smuzhiyun rt5640->pll_out = freq_out;
1930*4882a593Smuzhiyun rt5640->pll_src = source;
1931*4882a593Smuzhiyun
1932*4882a593Smuzhiyun return 0;
1933*4882a593Smuzhiyun }
1934*4882a593Smuzhiyun
rt5640_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1935*4882a593Smuzhiyun static int rt5640_set_bias_level(struct snd_soc_component *component,
1936*4882a593Smuzhiyun enum snd_soc_bias_level level)
1937*4882a593Smuzhiyun {
1938*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
1939*4882a593Smuzhiyun int ret;
1940*4882a593Smuzhiyun
1941*4882a593Smuzhiyun switch (level) {
1942*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
1943*4882a593Smuzhiyun break;
1944*4882a593Smuzhiyun
1945*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
1946*4882a593Smuzhiyun /*
1947*4882a593Smuzhiyun * SND_SOC_BIAS_PREPARE is called while preparing for a
1948*4882a593Smuzhiyun * transition to ON or away from ON. If current bias_level
1949*4882a593Smuzhiyun * is SND_SOC_BIAS_ON, then it is preparing for a transition
1950*4882a593Smuzhiyun * away from ON. Disable the clock in that case, otherwise
1951*4882a593Smuzhiyun * enable it.
1952*4882a593Smuzhiyun */
1953*4882a593Smuzhiyun if (IS_ERR(rt5640->mclk))
1954*4882a593Smuzhiyun break;
1955*4882a593Smuzhiyun
1956*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1957*4882a593Smuzhiyun clk_disable_unprepare(rt5640->mclk);
1958*4882a593Smuzhiyun } else {
1959*4882a593Smuzhiyun ret = clk_prepare_enable(rt5640->mclk);
1960*4882a593Smuzhiyun if (ret)
1961*4882a593Smuzhiyun return ret;
1962*4882a593Smuzhiyun }
1963*4882a593Smuzhiyun break;
1964*4882a593Smuzhiyun
1965*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
1966*4882a593Smuzhiyun if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
1967*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
1968*4882a593Smuzhiyun RT5640_PWR_VREF1 | RT5640_PWR_MB |
1969*4882a593Smuzhiyun RT5640_PWR_BG | RT5640_PWR_VREF2,
1970*4882a593Smuzhiyun RT5640_PWR_VREF1 | RT5640_PWR_MB |
1971*4882a593Smuzhiyun RT5640_PWR_BG | RT5640_PWR_VREF2);
1972*4882a593Smuzhiyun usleep_range(10000, 15000);
1973*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
1974*4882a593Smuzhiyun RT5640_PWR_FV1 | RT5640_PWR_FV2,
1975*4882a593Smuzhiyun RT5640_PWR_FV1 | RT5640_PWR_FV2);
1976*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_DUMMY1,
1977*4882a593Smuzhiyun 0x0301, 0x0301);
1978*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_MICBIAS,
1979*4882a593Smuzhiyun 0x0030, 0x0030);
1980*4882a593Smuzhiyun }
1981*4882a593Smuzhiyun break;
1982*4882a593Smuzhiyun
1983*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
1984*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_DEPOP_M1, 0x0004);
1985*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_DEPOP_M2, 0x1100);
1986*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_DUMMY1, 0x1, 0);
1987*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_PWR_DIG1, 0x0000);
1988*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_PWR_DIG2, 0x0000);
1989*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_PWR_VOL, 0x0000);
1990*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_PWR_MIXER, 0x0000);
1991*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_PWR_ANLG1, 0x0000);
1992*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_PWR_ANLG2, 0x0000);
1993*4882a593Smuzhiyun break;
1994*4882a593Smuzhiyun
1995*4882a593Smuzhiyun default:
1996*4882a593Smuzhiyun break;
1997*4882a593Smuzhiyun }
1998*4882a593Smuzhiyun
1999*4882a593Smuzhiyun return 0;
2000*4882a593Smuzhiyun }
2001*4882a593Smuzhiyun
rt5640_dmic_enable(struct snd_soc_component * component,bool dmic1_data_pin,bool dmic2_data_pin)2002*4882a593Smuzhiyun int rt5640_dmic_enable(struct snd_soc_component *component,
2003*4882a593Smuzhiyun bool dmic1_data_pin, bool dmic2_data_pin)
2004*4882a593Smuzhiyun {
2005*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2006*4882a593Smuzhiyun
2007*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
2008*4882a593Smuzhiyun RT5640_GP2_PIN_MASK, RT5640_GP2_PIN_DMIC1_SCL);
2009*4882a593Smuzhiyun
2010*4882a593Smuzhiyun if (dmic1_data_pin) {
2011*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_DMIC,
2012*4882a593Smuzhiyun RT5640_DMIC_1_DP_MASK, RT5640_DMIC_1_DP_GPIO3);
2013*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
2014*4882a593Smuzhiyun RT5640_GP3_PIN_MASK, RT5640_GP3_PIN_DMIC1_SDA);
2015*4882a593Smuzhiyun }
2016*4882a593Smuzhiyun
2017*4882a593Smuzhiyun if (dmic2_data_pin) {
2018*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_DMIC,
2019*4882a593Smuzhiyun RT5640_DMIC_2_DP_MASK, RT5640_DMIC_2_DP_GPIO4);
2020*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
2021*4882a593Smuzhiyun RT5640_GP4_PIN_MASK, RT5640_GP4_PIN_DMIC2_SDA);
2022*4882a593Smuzhiyun }
2023*4882a593Smuzhiyun
2024*4882a593Smuzhiyun return 0;
2025*4882a593Smuzhiyun }
2026*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt5640_dmic_enable);
2027*4882a593Smuzhiyun
rt5640_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)2028*4882a593Smuzhiyun int rt5640_sel_asrc_clk_src(struct snd_soc_component *component,
2029*4882a593Smuzhiyun unsigned int filter_mask, unsigned int clk_src)
2030*4882a593Smuzhiyun {
2031*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2032*4882a593Smuzhiyun unsigned int asrc2_mask = 0;
2033*4882a593Smuzhiyun unsigned int asrc2_value = 0;
2034*4882a593Smuzhiyun
2035*4882a593Smuzhiyun switch (clk_src) {
2036*4882a593Smuzhiyun case RT5640_CLK_SEL_SYS:
2037*4882a593Smuzhiyun case RT5640_CLK_SEL_ASRC:
2038*4882a593Smuzhiyun break;
2039*4882a593Smuzhiyun
2040*4882a593Smuzhiyun default:
2041*4882a593Smuzhiyun return -EINVAL;
2042*4882a593Smuzhiyun }
2043*4882a593Smuzhiyun
2044*4882a593Smuzhiyun if (!filter_mask)
2045*4882a593Smuzhiyun return -EINVAL;
2046*4882a593Smuzhiyun
2047*4882a593Smuzhiyun if (filter_mask & RT5640_DA_STEREO_FILTER) {
2048*4882a593Smuzhiyun asrc2_mask |= RT5640_STO_DAC_M_MASK;
2049*4882a593Smuzhiyun asrc2_value = (asrc2_value & ~RT5640_STO_DAC_M_MASK)
2050*4882a593Smuzhiyun | (clk_src << RT5640_STO_DAC_M_SFT);
2051*4882a593Smuzhiyun }
2052*4882a593Smuzhiyun
2053*4882a593Smuzhiyun if (filter_mask & RT5640_DA_MONO_L_FILTER) {
2054*4882a593Smuzhiyun asrc2_mask |= RT5640_MDA_L_M_MASK;
2055*4882a593Smuzhiyun asrc2_value = (asrc2_value & ~RT5640_MDA_L_M_MASK)
2056*4882a593Smuzhiyun | (clk_src << RT5640_MDA_L_M_SFT);
2057*4882a593Smuzhiyun }
2058*4882a593Smuzhiyun
2059*4882a593Smuzhiyun if (filter_mask & RT5640_DA_MONO_R_FILTER) {
2060*4882a593Smuzhiyun asrc2_mask |= RT5640_MDA_R_M_MASK;
2061*4882a593Smuzhiyun asrc2_value = (asrc2_value & ~RT5640_MDA_R_M_MASK)
2062*4882a593Smuzhiyun | (clk_src << RT5640_MDA_R_M_SFT);
2063*4882a593Smuzhiyun }
2064*4882a593Smuzhiyun
2065*4882a593Smuzhiyun if (filter_mask & RT5640_AD_STEREO_FILTER) {
2066*4882a593Smuzhiyun asrc2_mask |= RT5640_ADC_M_MASK;
2067*4882a593Smuzhiyun asrc2_value = (asrc2_value & ~RT5640_ADC_M_MASK)
2068*4882a593Smuzhiyun | (clk_src << RT5640_ADC_M_SFT);
2069*4882a593Smuzhiyun }
2070*4882a593Smuzhiyun
2071*4882a593Smuzhiyun if (filter_mask & RT5640_AD_MONO_L_FILTER) {
2072*4882a593Smuzhiyun asrc2_mask |= RT5640_MAD_L_M_MASK;
2073*4882a593Smuzhiyun asrc2_value = (asrc2_value & ~RT5640_MAD_L_M_MASK)
2074*4882a593Smuzhiyun | (clk_src << RT5640_MAD_L_M_SFT);
2075*4882a593Smuzhiyun }
2076*4882a593Smuzhiyun
2077*4882a593Smuzhiyun if (filter_mask & RT5640_AD_MONO_R_FILTER) {
2078*4882a593Smuzhiyun asrc2_mask |= RT5640_MAD_R_M_MASK;
2079*4882a593Smuzhiyun asrc2_value = (asrc2_value & ~RT5640_MAD_R_M_MASK)
2080*4882a593Smuzhiyun | (clk_src << RT5640_MAD_R_M_SFT);
2081*4882a593Smuzhiyun }
2082*4882a593Smuzhiyun
2083*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_ASRC_2,
2084*4882a593Smuzhiyun asrc2_mask, asrc2_value);
2085*4882a593Smuzhiyun
2086*4882a593Smuzhiyun if (snd_soc_component_read(component, RT5640_ASRC_2)) {
2087*4882a593Smuzhiyun rt5640->asrc_en = true;
2088*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_JD_CTRL, 0x3, 0x3);
2089*4882a593Smuzhiyun } else {
2090*4882a593Smuzhiyun rt5640->asrc_en = false;
2091*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_JD_CTRL, 0x3, 0x0);
2092*4882a593Smuzhiyun }
2093*4882a593Smuzhiyun
2094*4882a593Smuzhiyun return 0;
2095*4882a593Smuzhiyun }
2096*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt5640_sel_asrc_clk_src);
2097*4882a593Smuzhiyun
rt5640_enable_micbias1_for_ovcd(struct snd_soc_component * component)2098*4882a593Smuzhiyun static void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component)
2099*4882a593Smuzhiyun {
2100*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2101*4882a593Smuzhiyun
2102*4882a593Smuzhiyun snd_soc_dapm_mutex_lock(dapm);
2103*4882a593Smuzhiyun snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2");
2104*4882a593Smuzhiyun snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS1");
2105*4882a593Smuzhiyun /* OVCD is unreliable when used with RCCLK as sysclk-source */
2106*4882a593Smuzhiyun snd_soc_dapm_force_enable_pin_unlocked(dapm, "Platform Clock");
2107*4882a593Smuzhiyun snd_soc_dapm_sync_unlocked(dapm);
2108*4882a593Smuzhiyun snd_soc_dapm_mutex_unlock(dapm);
2109*4882a593Smuzhiyun }
2110*4882a593Smuzhiyun
rt5640_disable_micbias1_for_ovcd(struct snd_soc_component * component)2111*4882a593Smuzhiyun static void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component)
2112*4882a593Smuzhiyun {
2113*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2114*4882a593Smuzhiyun
2115*4882a593Smuzhiyun snd_soc_dapm_mutex_lock(dapm);
2116*4882a593Smuzhiyun snd_soc_dapm_disable_pin_unlocked(dapm, "Platform Clock");
2117*4882a593Smuzhiyun snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS1");
2118*4882a593Smuzhiyun snd_soc_dapm_disable_pin_unlocked(dapm, "LDO2");
2119*4882a593Smuzhiyun snd_soc_dapm_sync_unlocked(dapm);
2120*4882a593Smuzhiyun snd_soc_dapm_mutex_unlock(dapm);
2121*4882a593Smuzhiyun }
2122*4882a593Smuzhiyun
rt5640_enable_micbias1_ovcd_irq(struct snd_soc_component * component)2123*4882a593Smuzhiyun static void rt5640_enable_micbias1_ovcd_irq(struct snd_soc_component *component)
2124*4882a593Smuzhiyun {
2125*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2126*4882a593Smuzhiyun
2127*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
2128*4882a593Smuzhiyun RT5640_IRQ_MB1_OC_MASK, RT5640_IRQ_MB1_OC_NOR);
2129*4882a593Smuzhiyun rt5640->ovcd_irq_enabled = true;
2130*4882a593Smuzhiyun }
2131*4882a593Smuzhiyun
rt5640_disable_micbias1_ovcd_irq(struct snd_soc_component * component)2132*4882a593Smuzhiyun static void rt5640_disable_micbias1_ovcd_irq(struct snd_soc_component *component)
2133*4882a593Smuzhiyun {
2134*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2135*4882a593Smuzhiyun
2136*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
2137*4882a593Smuzhiyun RT5640_IRQ_MB1_OC_MASK, RT5640_IRQ_MB1_OC_BP);
2138*4882a593Smuzhiyun rt5640->ovcd_irq_enabled = false;
2139*4882a593Smuzhiyun }
2140*4882a593Smuzhiyun
rt5640_clear_micbias1_ovcd(struct snd_soc_component * component)2141*4882a593Smuzhiyun static void rt5640_clear_micbias1_ovcd(struct snd_soc_component *component)
2142*4882a593Smuzhiyun {
2143*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
2144*4882a593Smuzhiyun RT5640_MB1_OC_STATUS, 0);
2145*4882a593Smuzhiyun }
2146*4882a593Smuzhiyun
rt5640_micbias1_ovcd(struct snd_soc_component * component)2147*4882a593Smuzhiyun static bool rt5640_micbias1_ovcd(struct snd_soc_component *component)
2148*4882a593Smuzhiyun {
2149*4882a593Smuzhiyun int val;
2150*4882a593Smuzhiyun
2151*4882a593Smuzhiyun val = snd_soc_component_read(component, RT5640_IRQ_CTRL2);
2152*4882a593Smuzhiyun dev_dbg(component->dev, "irq ctrl2 %#04x\n", val);
2153*4882a593Smuzhiyun
2154*4882a593Smuzhiyun return (val & RT5640_MB1_OC_STATUS);
2155*4882a593Smuzhiyun }
2156*4882a593Smuzhiyun
rt5640_jack_inserted(struct snd_soc_component * component)2157*4882a593Smuzhiyun static bool rt5640_jack_inserted(struct snd_soc_component *component)
2158*4882a593Smuzhiyun {
2159*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2160*4882a593Smuzhiyun int val;
2161*4882a593Smuzhiyun
2162*4882a593Smuzhiyun val = snd_soc_component_read(component, RT5640_INT_IRQ_ST);
2163*4882a593Smuzhiyun dev_dbg(component->dev, "irq status %#04x\n", val);
2164*4882a593Smuzhiyun
2165*4882a593Smuzhiyun if (rt5640->jd_inverted)
2166*4882a593Smuzhiyun return !(val & RT5640_JD_STATUS);
2167*4882a593Smuzhiyun else
2168*4882a593Smuzhiyun return (val & RT5640_JD_STATUS);
2169*4882a593Smuzhiyun }
2170*4882a593Smuzhiyun
2171*4882a593Smuzhiyun /* Jack detect and button-press timings */
2172*4882a593Smuzhiyun #define JACK_SETTLE_TIME 100 /* milli seconds */
2173*4882a593Smuzhiyun #define JACK_DETECT_COUNT 5
2174*4882a593Smuzhiyun #define JACK_DETECT_MAXCOUNT 20 /* Aprox. 2 seconds worth of tries */
2175*4882a593Smuzhiyun #define JACK_UNPLUG_TIME 80 /* milli seconds */
2176*4882a593Smuzhiyun #define BP_POLL_TIME 10 /* milli seconds */
2177*4882a593Smuzhiyun #define BP_POLL_MAXCOUNT 200 /* assume something is wrong after this */
2178*4882a593Smuzhiyun #define BP_THRESHOLD 3
2179*4882a593Smuzhiyun
rt5640_start_button_press_work(struct snd_soc_component * component)2180*4882a593Smuzhiyun static void rt5640_start_button_press_work(struct snd_soc_component *component)
2181*4882a593Smuzhiyun {
2182*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2183*4882a593Smuzhiyun
2184*4882a593Smuzhiyun rt5640->poll_count = 0;
2185*4882a593Smuzhiyun rt5640->press_count = 0;
2186*4882a593Smuzhiyun rt5640->release_count = 0;
2187*4882a593Smuzhiyun rt5640->pressed = false;
2188*4882a593Smuzhiyun rt5640->press_reported = false;
2189*4882a593Smuzhiyun rt5640_clear_micbias1_ovcd(component);
2190*4882a593Smuzhiyun schedule_delayed_work(&rt5640->bp_work, msecs_to_jiffies(BP_POLL_TIME));
2191*4882a593Smuzhiyun }
2192*4882a593Smuzhiyun
rt5640_button_press_work(struct work_struct * work)2193*4882a593Smuzhiyun static void rt5640_button_press_work(struct work_struct *work)
2194*4882a593Smuzhiyun {
2195*4882a593Smuzhiyun struct rt5640_priv *rt5640 =
2196*4882a593Smuzhiyun container_of(work, struct rt5640_priv, bp_work.work);
2197*4882a593Smuzhiyun struct snd_soc_component *component = rt5640->component;
2198*4882a593Smuzhiyun
2199*4882a593Smuzhiyun /* Check the jack was not removed underneath us */
2200*4882a593Smuzhiyun if (!rt5640_jack_inserted(component))
2201*4882a593Smuzhiyun return;
2202*4882a593Smuzhiyun
2203*4882a593Smuzhiyun if (rt5640_micbias1_ovcd(component)) {
2204*4882a593Smuzhiyun rt5640->release_count = 0;
2205*4882a593Smuzhiyun rt5640->press_count++;
2206*4882a593Smuzhiyun /* Remember till after JACK_UNPLUG_TIME wait */
2207*4882a593Smuzhiyun if (rt5640->press_count >= BP_THRESHOLD)
2208*4882a593Smuzhiyun rt5640->pressed = true;
2209*4882a593Smuzhiyun rt5640_clear_micbias1_ovcd(component);
2210*4882a593Smuzhiyun } else {
2211*4882a593Smuzhiyun rt5640->press_count = 0;
2212*4882a593Smuzhiyun rt5640->release_count++;
2213*4882a593Smuzhiyun }
2214*4882a593Smuzhiyun
2215*4882a593Smuzhiyun /*
2216*4882a593Smuzhiyun * The pins get temporarily shorted on jack unplug, so we poll for
2217*4882a593Smuzhiyun * at least JACK_UNPLUG_TIME milli-seconds before reporting a press.
2218*4882a593Smuzhiyun */
2219*4882a593Smuzhiyun rt5640->poll_count++;
2220*4882a593Smuzhiyun if (rt5640->poll_count < (JACK_UNPLUG_TIME / BP_POLL_TIME)) {
2221*4882a593Smuzhiyun schedule_delayed_work(&rt5640->bp_work,
2222*4882a593Smuzhiyun msecs_to_jiffies(BP_POLL_TIME));
2223*4882a593Smuzhiyun return;
2224*4882a593Smuzhiyun }
2225*4882a593Smuzhiyun
2226*4882a593Smuzhiyun if (rt5640->pressed && !rt5640->press_reported) {
2227*4882a593Smuzhiyun dev_dbg(component->dev, "headset button press\n");
2228*4882a593Smuzhiyun snd_soc_jack_report(rt5640->jack, SND_JACK_BTN_0,
2229*4882a593Smuzhiyun SND_JACK_BTN_0);
2230*4882a593Smuzhiyun rt5640->press_reported = true;
2231*4882a593Smuzhiyun }
2232*4882a593Smuzhiyun
2233*4882a593Smuzhiyun if (rt5640->release_count >= BP_THRESHOLD) {
2234*4882a593Smuzhiyun if (rt5640->press_reported) {
2235*4882a593Smuzhiyun dev_dbg(component->dev, "headset button release\n");
2236*4882a593Smuzhiyun snd_soc_jack_report(rt5640->jack, 0, SND_JACK_BTN_0);
2237*4882a593Smuzhiyun }
2238*4882a593Smuzhiyun /* Re-enable OVCD IRQ to detect next press */
2239*4882a593Smuzhiyun rt5640_enable_micbias1_ovcd_irq(component);
2240*4882a593Smuzhiyun return; /* Stop polling */
2241*4882a593Smuzhiyun }
2242*4882a593Smuzhiyun
2243*4882a593Smuzhiyun schedule_delayed_work(&rt5640->bp_work, msecs_to_jiffies(BP_POLL_TIME));
2244*4882a593Smuzhiyun }
2245*4882a593Smuzhiyun
rt5640_detect_headset(struct snd_soc_component * component)2246*4882a593Smuzhiyun static int rt5640_detect_headset(struct snd_soc_component *component)
2247*4882a593Smuzhiyun {
2248*4882a593Smuzhiyun int i, headset_count = 0, headphone_count = 0;
2249*4882a593Smuzhiyun
2250*4882a593Smuzhiyun /*
2251*4882a593Smuzhiyun * We get the insertion event before the jack is fully inserted at which
2252*4882a593Smuzhiyun * point the second ring on a TRRS connector may short the 2nd ring and
2253*4882a593Smuzhiyun * sleeve contacts, also the overcurrent detection is not entirely
2254*4882a593Smuzhiyun * reliable. So we try several times with a wait in between until we
2255*4882a593Smuzhiyun * detect the same type JACK_DETECT_COUNT times in a row.
2256*4882a593Smuzhiyun */
2257*4882a593Smuzhiyun for (i = 0; i < JACK_DETECT_MAXCOUNT; i++) {
2258*4882a593Smuzhiyun /* Clear any previous over-current status flag */
2259*4882a593Smuzhiyun rt5640_clear_micbias1_ovcd(component);
2260*4882a593Smuzhiyun
2261*4882a593Smuzhiyun msleep(JACK_SETTLE_TIME);
2262*4882a593Smuzhiyun
2263*4882a593Smuzhiyun /* Check the jack is still connected before checking ovcd */
2264*4882a593Smuzhiyun if (!rt5640_jack_inserted(component))
2265*4882a593Smuzhiyun return 0;
2266*4882a593Smuzhiyun
2267*4882a593Smuzhiyun if (rt5640_micbias1_ovcd(component)) {
2268*4882a593Smuzhiyun /*
2269*4882a593Smuzhiyun * Over current detected, there is a short between the
2270*4882a593Smuzhiyun * 2nd ring contact and the ground, so a TRS connector
2271*4882a593Smuzhiyun * without a mic contact and thus plain headphones.
2272*4882a593Smuzhiyun */
2273*4882a593Smuzhiyun dev_dbg(component->dev, "jack mic-gnd shorted\n");
2274*4882a593Smuzhiyun headset_count = 0;
2275*4882a593Smuzhiyun headphone_count++;
2276*4882a593Smuzhiyun if (headphone_count == JACK_DETECT_COUNT)
2277*4882a593Smuzhiyun return SND_JACK_HEADPHONE;
2278*4882a593Smuzhiyun } else {
2279*4882a593Smuzhiyun dev_dbg(component->dev, "jack mic-gnd open\n");
2280*4882a593Smuzhiyun headphone_count = 0;
2281*4882a593Smuzhiyun headset_count++;
2282*4882a593Smuzhiyun if (headset_count == JACK_DETECT_COUNT)
2283*4882a593Smuzhiyun return SND_JACK_HEADSET;
2284*4882a593Smuzhiyun }
2285*4882a593Smuzhiyun }
2286*4882a593Smuzhiyun
2287*4882a593Smuzhiyun dev_err(component->dev, "Error detecting headset vs headphones, bad contact?, assuming headphones\n");
2288*4882a593Smuzhiyun return SND_JACK_HEADPHONE;
2289*4882a593Smuzhiyun }
2290*4882a593Smuzhiyun
rt5640_jack_work(struct work_struct * work)2291*4882a593Smuzhiyun static void rt5640_jack_work(struct work_struct *work)
2292*4882a593Smuzhiyun {
2293*4882a593Smuzhiyun struct rt5640_priv *rt5640 =
2294*4882a593Smuzhiyun container_of(work, struct rt5640_priv, jack_work);
2295*4882a593Smuzhiyun struct snd_soc_component *component = rt5640->component;
2296*4882a593Smuzhiyun int status;
2297*4882a593Smuzhiyun
2298*4882a593Smuzhiyun if (!rt5640_jack_inserted(component)) {
2299*4882a593Smuzhiyun /* Jack removed, or spurious IRQ? */
2300*4882a593Smuzhiyun if (rt5640->jack->status & SND_JACK_HEADPHONE) {
2301*4882a593Smuzhiyun if (rt5640->jack->status & SND_JACK_MICROPHONE) {
2302*4882a593Smuzhiyun cancel_delayed_work_sync(&rt5640->bp_work);
2303*4882a593Smuzhiyun rt5640_disable_micbias1_ovcd_irq(component);
2304*4882a593Smuzhiyun rt5640_disable_micbias1_for_ovcd(component);
2305*4882a593Smuzhiyun }
2306*4882a593Smuzhiyun snd_soc_jack_report(rt5640->jack, 0,
2307*4882a593Smuzhiyun SND_JACK_HEADSET | SND_JACK_BTN_0);
2308*4882a593Smuzhiyun dev_dbg(component->dev, "jack unplugged\n");
2309*4882a593Smuzhiyun }
2310*4882a593Smuzhiyun } else if (!(rt5640->jack->status & SND_JACK_HEADPHONE)) {
2311*4882a593Smuzhiyun /* Jack inserted */
2312*4882a593Smuzhiyun WARN_ON(rt5640->ovcd_irq_enabled);
2313*4882a593Smuzhiyun rt5640_enable_micbias1_for_ovcd(component);
2314*4882a593Smuzhiyun status = rt5640_detect_headset(component);
2315*4882a593Smuzhiyun if (status == SND_JACK_HEADSET) {
2316*4882a593Smuzhiyun /* Enable ovcd IRQ for button press detect. */
2317*4882a593Smuzhiyun rt5640_enable_micbias1_ovcd_irq(component);
2318*4882a593Smuzhiyun } else {
2319*4882a593Smuzhiyun /* No more need for overcurrent detect. */
2320*4882a593Smuzhiyun rt5640_disable_micbias1_for_ovcd(component);
2321*4882a593Smuzhiyun }
2322*4882a593Smuzhiyun dev_dbg(component->dev, "detect status %#02x\n", status);
2323*4882a593Smuzhiyun snd_soc_jack_report(rt5640->jack, status, SND_JACK_HEADSET);
2324*4882a593Smuzhiyun } else if (rt5640->ovcd_irq_enabled && rt5640_micbias1_ovcd(component)) {
2325*4882a593Smuzhiyun dev_dbg(component->dev, "OVCD IRQ\n");
2326*4882a593Smuzhiyun
2327*4882a593Smuzhiyun /*
2328*4882a593Smuzhiyun * The ovcd IRQ keeps firing while the button is pressed, so
2329*4882a593Smuzhiyun * we disable it and start polling the button until released.
2330*4882a593Smuzhiyun *
2331*4882a593Smuzhiyun * The disable will make the IRQ pin 0 again and since we get
2332*4882a593Smuzhiyun * IRQs on both edges (so as to detect both jack plugin and
2333*4882a593Smuzhiyun * unplug) this means we will immediately get another IRQ.
2334*4882a593Smuzhiyun * The ovcd_irq_enabled check above makes the 2ND IRQ a NOP.
2335*4882a593Smuzhiyun */
2336*4882a593Smuzhiyun rt5640_disable_micbias1_ovcd_irq(component);
2337*4882a593Smuzhiyun rt5640_start_button_press_work(component);
2338*4882a593Smuzhiyun
2339*4882a593Smuzhiyun /*
2340*4882a593Smuzhiyun * If the jack-detect IRQ flag goes high (unplug) after our
2341*4882a593Smuzhiyun * above rt5640_jack_inserted() check and before we have
2342*4882a593Smuzhiyun * disabled the OVCD IRQ, the IRQ pin will stay high and as
2343*4882a593Smuzhiyun * we react to edges, we miss the unplug event -> recheck.
2344*4882a593Smuzhiyun */
2345*4882a593Smuzhiyun queue_work(system_long_wq, &rt5640->jack_work);
2346*4882a593Smuzhiyun }
2347*4882a593Smuzhiyun }
2348*4882a593Smuzhiyun
rt5640_irq(int irq,void * data)2349*4882a593Smuzhiyun static irqreturn_t rt5640_irq(int irq, void *data)
2350*4882a593Smuzhiyun {
2351*4882a593Smuzhiyun struct rt5640_priv *rt5640 = data;
2352*4882a593Smuzhiyun
2353*4882a593Smuzhiyun if (rt5640->jack)
2354*4882a593Smuzhiyun queue_work(system_long_wq, &rt5640->jack_work);
2355*4882a593Smuzhiyun
2356*4882a593Smuzhiyun return IRQ_HANDLED;
2357*4882a593Smuzhiyun }
2358*4882a593Smuzhiyun
rt5640_cancel_work(void * data)2359*4882a593Smuzhiyun static void rt5640_cancel_work(void *data)
2360*4882a593Smuzhiyun {
2361*4882a593Smuzhiyun struct rt5640_priv *rt5640 = data;
2362*4882a593Smuzhiyun
2363*4882a593Smuzhiyun cancel_work_sync(&rt5640->jack_work);
2364*4882a593Smuzhiyun cancel_delayed_work_sync(&rt5640->bp_work);
2365*4882a593Smuzhiyun }
2366*4882a593Smuzhiyun
rt5640_enable_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * jack)2367*4882a593Smuzhiyun static void rt5640_enable_jack_detect(struct snd_soc_component *component,
2368*4882a593Smuzhiyun struct snd_soc_jack *jack)
2369*4882a593Smuzhiyun {
2370*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2371*4882a593Smuzhiyun
2372*4882a593Smuzhiyun /* Select JD-source */
2373*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_JD_CTRL,
2374*4882a593Smuzhiyun RT5640_JD_MASK, rt5640->jd_src);
2375*4882a593Smuzhiyun
2376*4882a593Smuzhiyun /* Selecting GPIO01 as an interrupt */
2377*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_GPIO_CTRL1,
2378*4882a593Smuzhiyun RT5640_GP1_PIN_MASK, RT5640_GP1_PIN_IRQ);
2379*4882a593Smuzhiyun
2380*4882a593Smuzhiyun /* Set GPIO1 output */
2381*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_GPIO_CTRL3,
2382*4882a593Smuzhiyun RT5640_GP1_PF_MASK, RT5640_GP1_PF_OUT);
2383*4882a593Smuzhiyun
2384*4882a593Smuzhiyun /* Enabling jd2 in general control 1 */
2385*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_DUMMY1, 0x3f41);
2386*4882a593Smuzhiyun
2387*4882a593Smuzhiyun /* Enabling jd2 in general control 2 */
2388*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_DUMMY2, 0x4001);
2389*4882a593Smuzhiyun
2390*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_PR_BASE + RT5640_BIAS_CUR4,
2391*4882a593Smuzhiyun 0xa800 | rt5640->ovcd_sf);
2392*4882a593Smuzhiyun
2393*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_MICBIAS,
2394*4882a593Smuzhiyun RT5640_MIC1_OVTH_MASK | RT5640_MIC1_OVCD_MASK,
2395*4882a593Smuzhiyun rt5640->ovcd_th | RT5640_MIC1_OVCD_EN);
2396*4882a593Smuzhiyun
2397*4882a593Smuzhiyun /*
2398*4882a593Smuzhiyun * The over-current-detect is only reliable in detecting the absence
2399*4882a593Smuzhiyun * of over-current, when the mic-contact in the jack is short-circuited,
2400*4882a593Smuzhiyun * the hardware periodically retries if it can apply the bias-current
2401*4882a593Smuzhiyun * leading to the ovcd status flip-flopping 1-0-1 with it being 0 about
2402*4882a593Smuzhiyun * 10% of the time, as we poll the ovcd status bit we might hit that
2403*4882a593Smuzhiyun * 10%, so we enable sticky mode and when checking OVCD we clear the
2404*4882a593Smuzhiyun * status, msleep() a bit and then check to get a reliable reading.
2405*4882a593Smuzhiyun */
2406*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
2407*4882a593Smuzhiyun RT5640_MB1_OC_STKY_MASK, RT5640_MB1_OC_STKY_EN);
2408*4882a593Smuzhiyun
2409*4882a593Smuzhiyun /*
2410*4882a593Smuzhiyun * All IRQs get or-ed together, so we need the jack IRQ to report 0
2411*4882a593Smuzhiyun * when a jack is inserted so that the OVCD IRQ then toggles the IRQ
2412*4882a593Smuzhiyun * pin 0/1 instead of it being stuck to 1. So we invert the JD polarity
2413*4882a593Smuzhiyun * on systems where the hardware does not already do this.
2414*4882a593Smuzhiyun */
2415*4882a593Smuzhiyun if (rt5640->jd_inverted)
2416*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_IRQ_CTRL1,
2417*4882a593Smuzhiyun RT5640_IRQ_JD_NOR);
2418*4882a593Smuzhiyun else
2419*4882a593Smuzhiyun snd_soc_component_write(component, RT5640_IRQ_CTRL1,
2420*4882a593Smuzhiyun RT5640_IRQ_JD_NOR | RT5640_JD_P_INV);
2421*4882a593Smuzhiyun
2422*4882a593Smuzhiyun rt5640->jack = jack;
2423*4882a593Smuzhiyun if (rt5640->jack->status & SND_JACK_MICROPHONE) {
2424*4882a593Smuzhiyun rt5640_enable_micbias1_for_ovcd(component);
2425*4882a593Smuzhiyun rt5640_enable_micbias1_ovcd_irq(component);
2426*4882a593Smuzhiyun }
2427*4882a593Smuzhiyun
2428*4882a593Smuzhiyun enable_irq(rt5640->irq);
2429*4882a593Smuzhiyun /* sync initial jack state */
2430*4882a593Smuzhiyun queue_work(system_long_wq, &rt5640->jack_work);
2431*4882a593Smuzhiyun }
2432*4882a593Smuzhiyun
rt5640_disable_jack_detect(struct snd_soc_component * component)2433*4882a593Smuzhiyun static void rt5640_disable_jack_detect(struct snd_soc_component *component)
2434*4882a593Smuzhiyun {
2435*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2436*4882a593Smuzhiyun
2437*4882a593Smuzhiyun /*
2438*4882a593Smuzhiyun * soc_remove_component() force-disables jack and thus rt5640->jack
2439*4882a593Smuzhiyun * could be NULL at the time of driver's module unloading.
2440*4882a593Smuzhiyun */
2441*4882a593Smuzhiyun if (!rt5640->jack)
2442*4882a593Smuzhiyun return;
2443*4882a593Smuzhiyun
2444*4882a593Smuzhiyun disable_irq(rt5640->irq);
2445*4882a593Smuzhiyun rt5640_cancel_work(rt5640);
2446*4882a593Smuzhiyun
2447*4882a593Smuzhiyun if (rt5640->jack->status & SND_JACK_MICROPHONE) {
2448*4882a593Smuzhiyun rt5640_disable_micbias1_ovcd_irq(component);
2449*4882a593Smuzhiyun rt5640_disable_micbias1_for_ovcd(component);
2450*4882a593Smuzhiyun snd_soc_jack_report(rt5640->jack, 0, SND_JACK_BTN_0);
2451*4882a593Smuzhiyun }
2452*4882a593Smuzhiyun
2453*4882a593Smuzhiyun rt5640->jack = NULL;
2454*4882a593Smuzhiyun }
2455*4882a593Smuzhiyun
rt5640_set_jack(struct snd_soc_component * component,struct snd_soc_jack * jack,void * data)2456*4882a593Smuzhiyun static int rt5640_set_jack(struct snd_soc_component *component,
2457*4882a593Smuzhiyun struct snd_soc_jack *jack, void *data)
2458*4882a593Smuzhiyun {
2459*4882a593Smuzhiyun if (jack)
2460*4882a593Smuzhiyun rt5640_enable_jack_detect(component, jack);
2461*4882a593Smuzhiyun else
2462*4882a593Smuzhiyun rt5640_disable_jack_detect(component);
2463*4882a593Smuzhiyun
2464*4882a593Smuzhiyun return 0;
2465*4882a593Smuzhiyun }
2466*4882a593Smuzhiyun
rt5640_probe(struct snd_soc_component * component)2467*4882a593Smuzhiyun static int rt5640_probe(struct snd_soc_component *component)
2468*4882a593Smuzhiyun {
2469*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2470*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2471*4882a593Smuzhiyun u32 dmic1_data_pin = 0;
2472*4882a593Smuzhiyun u32 dmic2_data_pin = 0;
2473*4882a593Smuzhiyun bool dmic_en = false;
2474*4882a593Smuzhiyun u32 val;
2475*4882a593Smuzhiyun
2476*4882a593Smuzhiyun /* Check if MCLK provided */
2477*4882a593Smuzhiyun rt5640->mclk = devm_clk_get(component->dev, "mclk");
2478*4882a593Smuzhiyun if (PTR_ERR(rt5640->mclk) == -EPROBE_DEFER)
2479*4882a593Smuzhiyun return -EPROBE_DEFER;
2480*4882a593Smuzhiyun
2481*4882a593Smuzhiyun rt5640->component = component;
2482*4882a593Smuzhiyun
2483*4882a593Smuzhiyun snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
2484*4882a593Smuzhiyun
2485*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_DUMMY1, 0x0301, 0x0301);
2486*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_MICBIAS, 0x0030, 0x0030);
2487*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_DSP_PATH2, 0xfc00, 0x0c00);
2488*4882a593Smuzhiyun
2489*4882a593Smuzhiyun switch (snd_soc_component_read(component, RT5640_RESET) & RT5640_ID_MASK) {
2490*4882a593Smuzhiyun case RT5640_ID_5640:
2491*4882a593Smuzhiyun case RT5640_ID_5642:
2492*4882a593Smuzhiyun snd_soc_add_component_controls(component,
2493*4882a593Smuzhiyun rt5640_specific_snd_controls,
2494*4882a593Smuzhiyun ARRAY_SIZE(rt5640_specific_snd_controls));
2495*4882a593Smuzhiyun snd_soc_dapm_new_controls(dapm,
2496*4882a593Smuzhiyun rt5640_specific_dapm_widgets,
2497*4882a593Smuzhiyun ARRAY_SIZE(rt5640_specific_dapm_widgets));
2498*4882a593Smuzhiyun snd_soc_dapm_add_routes(dapm,
2499*4882a593Smuzhiyun rt5640_specific_dapm_routes,
2500*4882a593Smuzhiyun ARRAY_SIZE(rt5640_specific_dapm_routes));
2501*4882a593Smuzhiyun break;
2502*4882a593Smuzhiyun case RT5640_ID_5639:
2503*4882a593Smuzhiyun snd_soc_dapm_new_controls(dapm,
2504*4882a593Smuzhiyun rt5639_specific_dapm_widgets,
2505*4882a593Smuzhiyun ARRAY_SIZE(rt5639_specific_dapm_widgets));
2506*4882a593Smuzhiyun snd_soc_dapm_add_routes(dapm,
2507*4882a593Smuzhiyun rt5639_specific_dapm_routes,
2508*4882a593Smuzhiyun ARRAY_SIZE(rt5639_specific_dapm_routes));
2509*4882a593Smuzhiyun break;
2510*4882a593Smuzhiyun default:
2511*4882a593Smuzhiyun dev_err(component->dev,
2512*4882a593Smuzhiyun "The driver is for RT5639 RT5640 or RT5642 only\n");
2513*4882a593Smuzhiyun return -ENODEV;
2514*4882a593Smuzhiyun }
2515*4882a593Smuzhiyun
2516*4882a593Smuzhiyun /*
2517*4882a593Smuzhiyun * Note on some platforms the platform code may need to add device-props
2518*4882a593Smuzhiyun * rather then relying only on properties set by the firmware.
2519*4882a593Smuzhiyun * Therefor the property parsing MUST be done here, rather then from
2520*4882a593Smuzhiyun * rt5640_i2c_probe(), so that the platform-code can attach extra
2521*4882a593Smuzhiyun * properties before calling snd_soc_register_card().
2522*4882a593Smuzhiyun */
2523*4882a593Smuzhiyun if (device_property_read_bool(component->dev, "realtek,in1-differential"))
2524*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_IN1_IN2,
2525*4882a593Smuzhiyun RT5640_IN_DF1, RT5640_IN_DF1);
2526*4882a593Smuzhiyun
2527*4882a593Smuzhiyun if (device_property_read_bool(component->dev, "realtek,in2-differential"))
2528*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_IN3_IN4,
2529*4882a593Smuzhiyun RT5640_IN_DF2, RT5640_IN_DF2);
2530*4882a593Smuzhiyun
2531*4882a593Smuzhiyun if (device_property_read_bool(component->dev, "realtek,in3-differential"))
2532*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT5640_IN1_IN2,
2533*4882a593Smuzhiyun RT5640_IN_DF2, RT5640_IN_DF2);
2534*4882a593Smuzhiyun
2535*4882a593Smuzhiyun if (device_property_read_u32(component->dev, "realtek,dmic1-data-pin",
2536*4882a593Smuzhiyun &val) == 0 && val) {
2537*4882a593Smuzhiyun dmic1_data_pin = val - 1;
2538*4882a593Smuzhiyun dmic_en = true;
2539*4882a593Smuzhiyun }
2540*4882a593Smuzhiyun
2541*4882a593Smuzhiyun if (device_property_read_u32(component->dev, "realtek,dmic2-data-pin",
2542*4882a593Smuzhiyun &val) == 0 && val) {
2543*4882a593Smuzhiyun dmic2_data_pin = val - 1;
2544*4882a593Smuzhiyun dmic_en = true;
2545*4882a593Smuzhiyun }
2546*4882a593Smuzhiyun
2547*4882a593Smuzhiyun if (dmic_en)
2548*4882a593Smuzhiyun rt5640_dmic_enable(component, dmic1_data_pin, dmic2_data_pin);
2549*4882a593Smuzhiyun
2550*4882a593Smuzhiyun if (device_property_read_u32(component->dev,
2551*4882a593Smuzhiyun "realtek,jack-detect-source", &val) == 0) {
2552*4882a593Smuzhiyun if (val <= RT5640_JD_SRC_GPIO4)
2553*4882a593Smuzhiyun rt5640->jd_src = val << RT5640_JD_SFT;
2554*4882a593Smuzhiyun else
2555*4882a593Smuzhiyun dev_warn(component->dev, "Warning: Invalid jack-detect-source value: %d, leaving jack-detect disabled\n",
2556*4882a593Smuzhiyun val);
2557*4882a593Smuzhiyun }
2558*4882a593Smuzhiyun
2559*4882a593Smuzhiyun if (!device_property_read_bool(component->dev, "realtek,jack-detect-not-inverted"))
2560*4882a593Smuzhiyun rt5640->jd_inverted = true;
2561*4882a593Smuzhiyun
2562*4882a593Smuzhiyun /*
2563*4882a593Smuzhiyun * Testing on various boards has shown that good defaults for the OVCD
2564*4882a593Smuzhiyun * threshold and scale-factor are 2000µA and 0.75. For an effective
2565*4882a593Smuzhiyun * limit of 1500µA, this seems to be more reliable then 1500µA and 1.0.
2566*4882a593Smuzhiyun */
2567*4882a593Smuzhiyun rt5640->ovcd_th = RT5640_MIC1_OVTH_2000UA;
2568*4882a593Smuzhiyun rt5640->ovcd_sf = RT5640_MIC_OVCD_SF_0P75;
2569*4882a593Smuzhiyun
2570*4882a593Smuzhiyun if (device_property_read_u32(component->dev,
2571*4882a593Smuzhiyun "realtek,over-current-threshold-microamp", &val) == 0) {
2572*4882a593Smuzhiyun switch (val) {
2573*4882a593Smuzhiyun case 600:
2574*4882a593Smuzhiyun rt5640->ovcd_th = RT5640_MIC1_OVTH_600UA;
2575*4882a593Smuzhiyun break;
2576*4882a593Smuzhiyun case 1500:
2577*4882a593Smuzhiyun rt5640->ovcd_th = RT5640_MIC1_OVTH_1500UA;
2578*4882a593Smuzhiyun break;
2579*4882a593Smuzhiyun case 2000:
2580*4882a593Smuzhiyun rt5640->ovcd_th = RT5640_MIC1_OVTH_2000UA;
2581*4882a593Smuzhiyun break;
2582*4882a593Smuzhiyun default:
2583*4882a593Smuzhiyun dev_warn(component->dev, "Warning: Invalid over-current-threshold-microamp value: %d, defaulting to 2000uA\n",
2584*4882a593Smuzhiyun val);
2585*4882a593Smuzhiyun }
2586*4882a593Smuzhiyun }
2587*4882a593Smuzhiyun
2588*4882a593Smuzhiyun if (device_property_read_u32(component->dev,
2589*4882a593Smuzhiyun "realtek,over-current-scale-factor", &val) == 0) {
2590*4882a593Smuzhiyun if (val <= RT5640_OVCD_SF_1P5)
2591*4882a593Smuzhiyun rt5640->ovcd_sf = val << RT5640_MIC_OVCD_SF_SFT;
2592*4882a593Smuzhiyun else
2593*4882a593Smuzhiyun dev_warn(component->dev, "Warning: Invalid over-current-scale-factor value: %d, defaulting to 0.75\n",
2594*4882a593Smuzhiyun val);
2595*4882a593Smuzhiyun }
2596*4882a593Smuzhiyun
2597*4882a593Smuzhiyun return 0;
2598*4882a593Smuzhiyun }
2599*4882a593Smuzhiyun
rt5640_remove(struct snd_soc_component * component)2600*4882a593Smuzhiyun static void rt5640_remove(struct snd_soc_component *component)
2601*4882a593Smuzhiyun {
2602*4882a593Smuzhiyun rt5640_reset(component);
2603*4882a593Smuzhiyun }
2604*4882a593Smuzhiyun
2605*4882a593Smuzhiyun #ifdef CONFIG_PM
rt5640_suspend(struct snd_soc_component * component)2606*4882a593Smuzhiyun static int rt5640_suspend(struct snd_soc_component *component)
2607*4882a593Smuzhiyun {
2608*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2609*4882a593Smuzhiyun
2610*4882a593Smuzhiyun snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
2611*4882a593Smuzhiyun rt5640_reset(component);
2612*4882a593Smuzhiyun regcache_cache_only(rt5640->regmap, true);
2613*4882a593Smuzhiyun regcache_mark_dirty(rt5640->regmap);
2614*4882a593Smuzhiyun if (gpio_is_valid(rt5640->ldo1_en))
2615*4882a593Smuzhiyun gpio_set_value_cansleep(rt5640->ldo1_en, 0);
2616*4882a593Smuzhiyun
2617*4882a593Smuzhiyun return 0;
2618*4882a593Smuzhiyun }
2619*4882a593Smuzhiyun
rt5640_resume(struct snd_soc_component * component)2620*4882a593Smuzhiyun static int rt5640_resume(struct snd_soc_component *component)
2621*4882a593Smuzhiyun {
2622*4882a593Smuzhiyun struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2623*4882a593Smuzhiyun
2624*4882a593Smuzhiyun if (gpio_is_valid(rt5640->ldo1_en)) {
2625*4882a593Smuzhiyun gpio_set_value_cansleep(rt5640->ldo1_en, 1);
2626*4882a593Smuzhiyun msleep(400);
2627*4882a593Smuzhiyun }
2628*4882a593Smuzhiyun
2629*4882a593Smuzhiyun regcache_cache_only(rt5640->regmap, false);
2630*4882a593Smuzhiyun regcache_sync(rt5640->regmap);
2631*4882a593Smuzhiyun
2632*4882a593Smuzhiyun return 0;
2633*4882a593Smuzhiyun }
2634*4882a593Smuzhiyun #else
2635*4882a593Smuzhiyun #define rt5640_suspend NULL
2636*4882a593Smuzhiyun #define rt5640_resume NULL
2637*4882a593Smuzhiyun #endif
2638*4882a593Smuzhiyun
2639*4882a593Smuzhiyun #define RT5640_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2640*4882a593Smuzhiyun #define RT5640_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2641*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2642*4882a593Smuzhiyun
2643*4882a593Smuzhiyun static const struct snd_soc_dai_ops rt5640_aif_dai_ops = {
2644*4882a593Smuzhiyun .hw_params = rt5640_hw_params,
2645*4882a593Smuzhiyun .set_fmt = rt5640_set_dai_fmt,
2646*4882a593Smuzhiyun .set_sysclk = rt5640_set_dai_sysclk,
2647*4882a593Smuzhiyun .set_pll = rt5640_set_dai_pll,
2648*4882a593Smuzhiyun };
2649*4882a593Smuzhiyun
2650*4882a593Smuzhiyun static struct snd_soc_dai_driver rt5640_dai[] = {
2651*4882a593Smuzhiyun {
2652*4882a593Smuzhiyun .name = "rt5640-aif1",
2653*4882a593Smuzhiyun .id = RT5640_AIF1,
2654*4882a593Smuzhiyun .playback = {
2655*4882a593Smuzhiyun .stream_name = "AIF1 Playback",
2656*4882a593Smuzhiyun .channels_min = 1,
2657*4882a593Smuzhiyun .channels_max = 2,
2658*4882a593Smuzhiyun .rates = RT5640_STEREO_RATES,
2659*4882a593Smuzhiyun .formats = RT5640_FORMATS,
2660*4882a593Smuzhiyun },
2661*4882a593Smuzhiyun .capture = {
2662*4882a593Smuzhiyun .stream_name = "AIF1 Capture",
2663*4882a593Smuzhiyun .channels_min = 1,
2664*4882a593Smuzhiyun .channels_max = 2,
2665*4882a593Smuzhiyun .rates = RT5640_STEREO_RATES,
2666*4882a593Smuzhiyun .formats = RT5640_FORMATS,
2667*4882a593Smuzhiyun },
2668*4882a593Smuzhiyun .ops = &rt5640_aif_dai_ops,
2669*4882a593Smuzhiyun },
2670*4882a593Smuzhiyun {
2671*4882a593Smuzhiyun .name = "rt5640-aif2",
2672*4882a593Smuzhiyun .id = RT5640_AIF2,
2673*4882a593Smuzhiyun .playback = {
2674*4882a593Smuzhiyun .stream_name = "AIF2 Playback",
2675*4882a593Smuzhiyun .channels_min = 1,
2676*4882a593Smuzhiyun .channels_max = 2,
2677*4882a593Smuzhiyun .rates = RT5640_STEREO_RATES,
2678*4882a593Smuzhiyun .formats = RT5640_FORMATS,
2679*4882a593Smuzhiyun },
2680*4882a593Smuzhiyun .capture = {
2681*4882a593Smuzhiyun .stream_name = "AIF2 Capture",
2682*4882a593Smuzhiyun .channels_min = 1,
2683*4882a593Smuzhiyun .channels_max = 2,
2684*4882a593Smuzhiyun .rates = RT5640_STEREO_RATES,
2685*4882a593Smuzhiyun .formats = RT5640_FORMATS,
2686*4882a593Smuzhiyun },
2687*4882a593Smuzhiyun .ops = &rt5640_aif_dai_ops,
2688*4882a593Smuzhiyun },
2689*4882a593Smuzhiyun };
2690*4882a593Smuzhiyun
2691*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_rt5640 = {
2692*4882a593Smuzhiyun .probe = rt5640_probe,
2693*4882a593Smuzhiyun .remove = rt5640_remove,
2694*4882a593Smuzhiyun .suspend = rt5640_suspend,
2695*4882a593Smuzhiyun .resume = rt5640_resume,
2696*4882a593Smuzhiyun .set_bias_level = rt5640_set_bias_level,
2697*4882a593Smuzhiyun .set_jack = rt5640_set_jack,
2698*4882a593Smuzhiyun .controls = rt5640_snd_controls,
2699*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(rt5640_snd_controls),
2700*4882a593Smuzhiyun .dapm_widgets = rt5640_dapm_widgets,
2701*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(rt5640_dapm_widgets),
2702*4882a593Smuzhiyun .dapm_routes = rt5640_dapm_routes,
2703*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(rt5640_dapm_routes),
2704*4882a593Smuzhiyun .use_pmdown_time = 1,
2705*4882a593Smuzhiyun .endianness = 1,
2706*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
2707*4882a593Smuzhiyun
2708*4882a593Smuzhiyun };
2709*4882a593Smuzhiyun
2710*4882a593Smuzhiyun static const struct regmap_config rt5640_regmap = {
2711*4882a593Smuzhiyun .reg_bits = 8,
2712*4882a593Smuzhiyun .val_bits = 16,
2713*4882a593Smuzhiyun .use_single_read = true,
2714*4882a593Smuzhiyun .use_single_write = true,
2715*4882a593Smuzhiyun
2716*4882a593Smuzhiyun .max_register = RT5640_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5640_ranges) *
2717*4882a593Smuzhiyun RT5640_PR_SPACING),
2718*4882a593Smuzhiyun .volatile_reg = rt5640_volatile_register,
2719*4882a593Smuzhiyun .readable_reg = rt5640_readable_register,
2720*4882a593Smuzhiyun
2721*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
2722*4882a593Smuzhiyun .reg_defaults = rt5640_reg,
2723*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(rt5640_reg),
2724*4882a593Smuzhiyun .ranges = rt5640_ranges,
2725*4882a593Smuzhiyun .num_ranges = ARRAY_SIZE(rt5640_ranges),
2726*4882a593Smuzhiyun };
2727*4882a593Smuzhiyun
2728*4882a593Smuzhiyun static const struct i2c_device_id rt5640_i2c_id[] = {
2729*4882a593Smuzhiyun { "rt5640", 0 },
2730*4882a593Smuzhiyun { "rt5639", 0 },
2731*4882a593Smuzhiyun { "rt5642", 0 },
2732*4882a593Smuzhiyun { }
2733*4882a593Smuzhiyun };
2734*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, rt5640_i2c_id);
2735*4882a593Smuzhiyun
2736*4882a593Smuzhiyun #if defined(CONFIG_OF)
2737*4882a593Smuzhiyun static const struct of_device_id rt5640_of_match[] = {
2738*4882a593Smuzhiyun { .compatible = "realtek,rt5639", },
2739*4882a593Smuzhiyun { .compatible = "realtek,rt5640", },
2740*4882a593Smuzhiyun {},
2741*4882a593Smuzhiyun };
2742*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rt5640_of_match);
2743*4882a593Smuzhiyun #endif
2744*4882a593Smuzhiyun
2745*4882a593Smuzhiyun #ifdef CONFIG_ACPI
2746*4882a593Smuzhiyun static const struct acpi_device_id rt5640_acpi_match[] = {
2747*4882a593Smuzhiyun { "INT33CA", 0 },
2748*4882a593Smuzhiyun { "10EC3276", 0 },
2749*4882a593Smuzhiyun { "10EC5640", 0 },
2750*4882a593Smuzhiyun { "10EC5642", 0 },
2751*4882a593Smuzhiyun { "INTCCFFD", 0 },
2752*4882a593Smuzhiyun { },
2753*4882a593Smuzhiyun };
2754*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, rt5640_acpi_match);
2755*4882a593Smuzhiyun #endif
2756*4882a593Smuzhiyun
rt5640_parse_dt(struct rt5640_priv * rt5640,struct device_node * np)2757*4882a593Smuzhiyun static int rt5640_parse_dt(struct rt5640_priv *rt5640, struct device_node *np)
2758*4882a593Smuzhiyun {
2759*4882a593Smuzhiyun rt5640->ldo1_en = of_get_named_gpio(np, "realtek,ldo1-en-gpios", 0);
2760*4882a593Smuzhiyun /*
2761*4882a593Smuzhiyun * LDO1_EN is optional (it may be statically tied on the board).
2762*4882a593Smuzhiyun * -ENOENT means that the property doesn't exist, i.e. there is no
2763*4882a593Smuzhiyun * GPIO, so is not an error. Any other error code means the property
2764*4882a593Smuzhiyun * exists, but could not be parsed.
2765*4882a593Smuzhiyun */
2766*4882a593Smuzhiyun if (!gpio_is_valid(rt5640->ldo1_en) &&
2767*4882a593Smuzhiyun (rt5640->ldo1_en != -ENOENT))
2768*4882a593Smuzhiyun return rt5640->ldo1_en;
2769*4882a593Smuzhiyun
2770*4882a593Smuzhiyun return 0;
2771*4882a593Smuzhiyun }
2772*4882a593Smuzhiyun
rt5640_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)2773*4882a593Smuzhiyun static int rt5640_i2c_probe(struct i2c_client *i2c,
2774*4882a593Smuzhiyun const struct i2c_device_id *id)
2775*4882a593Smuzhiyun {
2776*4882a593Smuzhiyun struct rt5640_priv *rt5640;
2777*4882a593Smuzhiyun int ret;
2778*4882a593Smuzhiyun unsigned int val;
2779*4882a593Smuzhiyun
2780*4882a593Smuzhiyun rt5640 = devm_kzalloc(&i2c->dev,
2781*4882a593Smuzhiyun sizeof(struct rt5640_priv),
2782*4882a593Smuzhiyun GFP_KERNEL);
2783*4882a593Smuzhiyun if (NULL == rt5640)
2784*4882a593Smuzhiyun return -ENOMEM;
2785*4882a593Smuzhiyun i2c_set_clientdata(i2c, rt5640);
2786*4882a593Smuzhiyun
2787*4882a593Smuzhiyun if (i2c->dev.of_node) {
2788*4882a593Smuzhiyun ret = rt5640_parse_dt(rt5640, i2c->dev.of_node);
2789*4882a593Smuzhiyun if (ret)
2790*4882a593Smuzhiyun return ret;
2791*4882a593Smuzhiyun } else
2792*4882a593Smuzhiyun rt5640->ldo1_en = -EINVAL;
2793*4882a593Smuzhiyun
2794*4882a593Smuzhiyun rt5640->regmap = devm_regmap_init_i2c(i2c, &rt5640_regmap);
2795*4882a593Smuzhiyun if (IS_ERR(rt5640->regmap)) {
2796*4882a593Smuzhiyun ret = PTR_ERR(rt5640->regmap);
2797*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2798*4882a593Smuzhiyun ret);
2799*4882a593Smuzhiyun return ret;
2800*4882a593Smuzhiyun }
2801*4882a593Smuzhiyun
2802*4882a593Smuzhiyun if (gpio_is_valid(rt5640->ldo1_en)) {
2803*4882a593Smuzhiyun ret = devm_gpio_request_one(&i2c->dev, rt5640->ldo1_en,
2804*4882a593Smuzhiyun GPIOF_OUT_INIT_HIGH,
2805*4882a593Smuzhiyun "RT5640 LDO1_EN");
2806*4882a593Smuzhiyun if (ret < 0) {
2807*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to request LDO1_EN %d: %d\n",
2808*4882a593Smuzhiyun rt5640->ldo1_en, ret);
2809*4882a593Smuzhiyun return ret;
2810*4882a593Smuzhiyun }
2811*4882a593Smuzhiyun msleep(400);
2812*4882a593Smuzhiyun }
2813*4882a593Smuzhiyun
2814*4882a593Smuzhiyun regmap_read(rt5640->regmap, RT5640_VENDOR_ID2, &val);
2815*4882a593Smuzhiyun if (val != RT5640_DEVICE_ID) {
2816*4882a593Smuzhiyun dev_err(&i2c->dev,
2817*4882a593Smuzhiyun "Device with ID register %#x is not rt5640/39\n", val);
2818*4882a593Smuzhiyun return -ENODEV;
2819*4882a593Smuzhiyun }
2820*4882a593Smuzhiyun
2821*4882a593Smuzhiyun regmap_write(rt5640->regmap, RT5640_RESET, 0);
2822*4882a593Smuzhiyun
2823*4882a593Smuzhiyun ret = regmap_register_patch(rt5640->regmap, init_list,
2824*4882a593Smuzhiyun ARRAY_SIZE(init_list));
2825*4882a593Smuzhiyun if (ret != 0)
2826*4882a593Smuzhiyun dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2827*4882a593Smuzhiyun
2828*4882a593Smuzhiyun regmap_update_bits(rt5640->regmap, RT5640_DUMMY1,
2829*4882a593Smuzhiyun RT5640_MCLK_DET, RT5640_MCLK_DET);
2830*4882a593Smuzhiyun
2831*4882a593Smuzhiyun rt5640->hp_mute = true;
2832*4882a593Smuzhiyun rt5640->irq = i2c->irq;
2833*4882a593Smuzhiyun INIT_DELAYED_WORK(&rt5640->bp_work, rt5640_button_press_work);
2834*4882a593Smuzhiyun INIT_WORK(&rt5640->jack_work, rt5640_jack_work);
2835*4882a593Smuzhiyun
2836*4882a593Smuzhiyun /* Make sure work is stopped on probe-error / remove */
2837*4882a593Smuzhiyun ret = devm_add_action_or_reset(&i2c->dev, rt5640_cancel_work, rt5640);
2838*4882a593Smuzhiyun if (ret)
2839*4882a593Smuzhiyun return ret;
2840*4882a593Smuzhiyun
2841*4882a593Smuzhiyun ret = devm_request_irq(&i2c->dev, rt5640->irq, rt5640_irq,
2842*4882a593Smuzhiyun IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2843*4882a593Smuzhiyun | IRQF_ONESHOT, "rt5640", rt5640);
2844*4882a593Smuzhiyun if (ret == 0) {
2845*4882a593Smuzhiyun /* Gets re-enabled by rt5640_set_jack() */
2846*4882a593Smuzhiyun disable_irq(rt5640->irq);
2847*4882a593Smuzhiyun } else {
2848*4882a593Smuzhiyun dev_warn(&i2c->dev, "Failed to reguest IRQ %d: %d\n",
2849*4882a593Smuzhiyun rt5640->irq, ret);
2850*4882a593Smuzhiyun rt5640->irq = -ENXIO;
2851*4882a593Smuzhiyun }
2852*4882a593Smuzhiyun
2853*4882a593Smuzhiyun return devm_snd_soc_register_component(&i2c->dev,
2854*4882a593Smuzhiyun &soc_component_dev_rt5640,
2855*4882a593Smuzhiyun rt5640_dai, ARRAY_SIZE(rt5640_dai));
2856*4882a593Smuzhiyun }
2857*4882a593Smuzhiyun
2858*4882a593Smuzhiyun static struct i2c_driver rt5640_i2c_driver = {
2859*4882a593Smuzhiyun .driver = {
2860*4882a593Smuzhiyun .name = "rt5640",
2861*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(rt5640_acpi_match),
2862*4882a593Smuzhiyun .of_match_table = of_match_ptr(rt5640_of_match),
2863*4882a593Smuzhiyun },
2864*4882a593Smuzhiyun .probe = rt5640_i2c_probe,
2865*4882a593Smuzhiyun .id_table = rt5640_i2c_id,
2866*4882a593Smuzhiyun };
2867*4882a593Smuzhiyun module_i2c_driver(rt5640_i2c_driver);
2868*4882a593Smuzhiyun
2869*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC RT5640/RT5639 driver");
2870*4882a593Smuzhiyun MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
2871*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
2872