xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/rt5631.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * rt5631.c  --  RT5631 ALSA Soc Audio driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2011 Realtek Microelectronics
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: flove <flove@realtek.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Based on WM8753.c
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/moduleparam.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/pm.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <sound/core.h>
19*4882a593Smuzhiyun #include <sound/pcm.h>
20*4882a593Smuzhiyun #include <sound/pcm_params.h>
21*4882a593Smuzhiyun #include <sound/soc.h>
22*4882a593Smuzhiyun #include <sound/soc-dapm.h>
23*4882a593Smuzhiyun #include <sound/initval.h>
24*4882a593Smuzhiyun #include <sound/tlv.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include "rt5631.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun struct rt5631_priv {
29*4882a593Smuzhiyun 	struct regmap *regmap;
30*4882a593Smuzhiyun 	int codec_version;
31*4882a593Smuzhiyun 	int master;
32*4882a593Smuzhiyun 	int sysclk;
33*4882a593Smuzhiyun 	int rx_rate;
34*4882a593Smuzhiyun 	int bclk_rate;
35*4882a593Smuzhiyun 	int dmic_used_flag;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun static const struct reg_default rt5631_reg[] = {
39*4882a593Smuzhiyun 	{ RT5631_SPK_OUT_VOL, 0x8888 },
40*4882a593Smuzhiyun 	{ RT5631_HP_OUT_VOL, 0x8080 },
41*4882a593Smuzhiyun 	{ RT5631_MONO_AXO_1_2_VOL, 0xa080 },
42*4882a593Smuzhiyun 	{ RT5631_AUX_IN_VOL, 0x0808 },
43*4882a593Smuzhiyun 	{ RT5631_ADC_REC_MIXER, 0xf0f0 },
44*4882a593Smuzhiyun 	{ RT5631_VDAC_DIG_VOL, 0x0010 },
45*4882a593Smuzhiyun 	{ RT5631_OUTMIXER_L_CTRL, 0xffc0 },
46*4882a593Smuzhiyun 	{ RT5631_OUTMIXER_R_CTRL, 0xffc0 },
47*4882a593Smuzhiyun 	{ RT5631_AXO1MIXER_CTRL, 0x88c0 },
48*4882a593Smuzhiyun 	{ RT5631_AXO2MIXER_CTRL, 0x88c0 },
49*4882a593Smuzhiyun 	{ RT5631_DIG_MIC_CTRL, 0x3000 },
50*4882a593Smuzhiyun 	{ RT5631_MONO_INPUT_VOL, 0x8808 },
51*4882a593Smuzhiyun 	{ RT5631_SPK_MIXER_CTRL, 0xf8f8 },
52*4882a593Smuzhiyun 	{ RT5631_SPK_MONO_OUT_CTRL, 0xfc00 },
53*4882a593Smuzhiyun 	{ RT5631_SPK_MONO_HP_OUT_CTRL, 0x4440 },
54*4882a593Smuzhiyun 	{ RT5631_SDP_CTRL, 0x8000 },
55*4882a593Smuzhiyun 	{ RT5631_MONO_SDP_CTRL, 0x8000 },
56*4882a593Smuzhiyun 	{ RT5631_STEREO_AD_DA_CLK_CTRL, 0x2010 },
57*4882a593Smuzhiyun 	{ RT5631_GEN_PUR_CTRL_REG, 0x0e00 },
58*4882a593Smuzhiyun 	{ RT5631_INT_ST_IRQ_CTRL_2, 0x071a },
59*4882a593Smuzhiyun 	{ RT5631_MISC_CTRL, 0x2040 },
60*4882a593Smuzhiyun 	{ RT5631_DEPOP_FUN_CTRL_2, 0x8000 },
61*4882a593Smuzhiyun 	{ RT5631_SOFT_VOL_CTRL, 0x07e0 },
62*4882a593Smuzhiyun 	{ RT5631_ALC_CTRL_1, 0x0206 },
63*4882a593Smuzhiyun 	{ RT5631_ALC_CTRL_3, 0x2000 },
64*4882a593Smuzhiyun 	{ RT5631_PSEUDO_SPATL_CTRL, 0x0553 },
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /*
68*4882a593Smuzhiyun  * rt5631_write_index - write index register of 2nd layer
69*4882a593Smuzhiyun  */
rt5631_write_index(struct snd_soc_component * component,unsigned int reg,unsigned int value)70*4882a593Smuzhiyun static void rt5631_write_index(struct snd_soc_component *component,
71*4882a593Smuzhiyun 		unsigned int reg, unsigned int value)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INDEX_ADD, reg);
74*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INDEX_DATA, value);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun  * rt5631_read_index - read index register of 2nd layer
79*4882a593Smuzhiyun  */
rt5631_read_index(struct snd_soc_component * component,unsigned int reg)80*4882a593Smuzhiyun static unsigned int rt5631_read_index(struct snd_soc_component *component,
81*4882a593Smuzhiyun 				unsigned int reg)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun 	unsigned int value;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INDEX_ADD, reg);
86*4882a593Smuzhiyun 	value = snd_soc_component_read(component, RT5631_INDEX_DATA);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	return value;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
rt5631_reset(struct snd_soc_component * component)91*4882a593Smuzhiyun static int rt5631_reset(struct snd_soc_component *component)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	return snd_soc_component_write(component, RT5631_RESET, 0);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
rt5631_volatile_register(struct device * dev,unsigned int reg)96*4882a593Smuzhiyun static bool rt5631_volatile_register(struct device *dev, unsigned int reg)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	switch (reg) {
99*4882a593Smuzhiyun 	case RT5631_RESET:
100*4882a593Smuzhiyun 	case RT5631_INT_ST_IRQ_CTRL_2:
101*4882a593Smuzhiyun 	case RT5631_INDEX_ADD:
102*4882a593Smuzhiyun 	case RT5631_INDEX_DATA:
103*4882a593Smuzhiyun 	case RT5631_EQ_CTRL:
104*4882a593Smuzhiyun 		return true;
105*4882a593Smuzhiyun 	default:
106*4882a593Smuzhiyun 		return false;
107*4882a593Smuzhiyun 	}
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
rt5631_readable_register(struct device * dev,unsigned int reg)110*4882a593Smuzhiyun static bool rt5631_readable_register(struct device *dev, unsigned int reg)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	switch (reg) {
113*4882a593Smuzhiyun 	case RT5631_RESET:
114*4882a593Smuzhiyun 	case RT5631_SPK_OUT_VOL:
115*4882a593Smuzhiyun 	case RT5631_HP_OUT_VOL:
116*4882a593Smuzhiyun 	case RT5631_MONO_AXO_1_2_VOL:
117*4882a593Smuzhiyun 	case RT5631_AUX_IN_VOL:
118*4882a593Smuzhiyun 	case RT5631_STEREO_DAC_VOL_1:
119*4882a593Smuzhiyun 	case RT5631_MIC_CTRL_1:
120*4882a593Smuzhiyun 	case RT5631_STEREO_DAC_VOL_2:
121*4882a593Smuzhiyun 	case RT5631_ADC_CTRL_1:
122*4882a593Smuzhiyun 	case RT5631_ADC_REC_MIXER:
123*4882a593Smuzhiyun 	case RT5631_ADC_CTRL_2:
124*4882a593Smuzhiyun 	case RT5631_VDAC_DIG_VOL:
125*4882a593Smuzhiyun 	case RT5631_OUTMIXER_L_CTRL:
126*4882a593Smuzhiyun 	case RT5631_OUTMIXER_R_CTRL:
127*4882a593Smuzhiyun 	case RT5631_AXO1MIXER_CTRL:
128*4882a593Smuzhiyun 	case RT5631_AXO2MIXER_CTRL:
129*4882a593Smuzhiyun 	case RT5631_MIC_CTRL_2:
130*4882a593Smuzhiyun 	case RT5631_DIG_MIC_CTRL:
131*4882a593Smuzhiyun 	case RT5631_MONO_INPUT_VOL:
132*4882a593Smuzhiyun 	case RT5631_SPK_MIXER_CTRL:
133*4882a593Smuzhiyun 	case RT5631_SPK_MONO_OUT_CTRL:
134*4882a593Smuzhiyun 	case RT5631_SPK_MONO_HP_OUT_CTRL:
135*4882a593Smuzhiyun 	case RT5631_SDP_CTRL:
136*4882a593Smuzhiyun 	case RT5631_MONO_SDP_CTRL:
137*4882a593Smuzhiyun 	case RT5631_STEREO_AD_DA_CLK_CTRL:
138*4882a593Smuzhiyun 	case RT5631_PWR_MANAG_ADD1:
139*4882a593Smuzhiyun 	case RT5631_PWR_MANAG_ADD2:
140*4882a593Smuzhiyun 	case RT5631_PWR_MANAG_ADD3:
141*4882a593Smuzhiyun 	case RT5631_PWR_MANAG_ADD4:
142*4882a593Smuzhiyun 	case RT5631_GEN_PUR_CTRL_REG:
143*4882a593Smuzhiyun 	case RT5631_GLOBAL_CLK_CTRL:
144*4882a593Smuzhiyun 	case RT5631_PLL_CTRL:
145*4882a593Smuzhiyun 	case RT5631_INT_ST_IRQ_CTRL_1:
146*4882a593Smuzhiyun 	case RT5631_INT_ST_IRQ_CTRL_2:
147*4882a593Smuzhiyun 	case RT5631_GPIO_CTRL:
148*4882a593Smuzhiyun 	case RT5631_MISC_CTRL:
149*4882a593Smuzhiyun 	case RT5631_DEPOP_FUN_CTRL_1:
150*4882a593Smuzhiyun 	case RT5631_DEPOP_FUN_CTRL_2:
151*4882a593Smuzhiyun 	case RT5631_JACK_DET_CTRL:
152*4882a593Smuzhiyun 	case RT5631_SOFT_VOL_CTRL:
153*4882a593Smuzhiyun 	case RT5631_ALC_CTRL_1:
154*4882a593Smuzhiyun 	case RT5631_ALC_CTRL_2:
155*4882a593Smuzhiyun 	case RT5631_ALC_CTRL_3:
156*4882a593Smuzhiyun 	case RT5631_PSEUDO_SPATL_CTRL:
157*4882a593Smuzhiyun 	case RT5631_INDEX_ADD:
158*4882a593Smuzhiyun 	case RT5631_INDEX_DATA:
159*4882a593Smuzhiyun 	case RT5631_EQ_CTRL:
160*4882a593Smuzhiyun 	case RT5631_VENDOR_ID:
161*4882a593Smuzhiyun 	case RT5631_VENDOR_ID1:
162*4882a593Smuzhiyun 	case RT5631_VENDOR_ID2:
163*4882a593Smuzhiyun 		return true;
164*4882a593Smuzhiyun 	default:
165*4882a593Smuzhiyun 		return false;
166*4882a593Smuzhiyun 	}
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
170*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -95625, 375, 0);
171*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
172*4882a593Smuzhiyun /* {0, +20, +24, +30, +35, +40, +44, +50, +52}dB */
173*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(mic_bst_tlv,
174*4882a593Smuzhiyun 	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
175*4882a593Smuzhiyun 	1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
176*4882a593Smuzhiyun 	2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
177*4882a593Smuzhiyun 	3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
178*4882a593Smuzhiyun 	6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
179*4882a593Smuzhiyun 	7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
180*4882a593Smuzhiyun 	8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
181*4882a593Smuzhiyun );
182*4882a593Smuzhiyun 
rt5631_dmic_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)183*4882a593Smuzhiyun static int rt5631_dmic_get(struct snd_kcontrol *kcontrol,
184*4882a593Smuzhiyun 		struct snd_ctl_elem_value *ucontrol)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
187*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = rt5631->dmic_used_flag;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	return 0;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
rt5631_dmic_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)194*4882a593Smuzhiyun static int rt5631_dmic_put(struct snd_kcontrol *kcontrol,
195*4882a593Smuzhiyun 		struct snd_ctl_elem_value *ucontrol)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
198*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	rt5631->dmic_used_flag = ucontrol->value.integer.value[0];
201*4882a593Smuzhiyun 	return 0;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun /* MIC Input Type */
205*4882a593Smuzhiyun static const char *rt5631_input_mode[] = {
206*4882a593Smuzhiyun 	"Single ended", "Differential"};
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_mic1_mode_enum, RT5631_MIC_CTRL_1,
209*4882a593Smuzhiyun 			    RT5631_MIC1_DIFF_INPUT_SHIFT, rt5631_input_mode);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_mic2_mode_enum, RT5631_MIC_CTRL_1,
212*4882a593Smuzhiyun 			    RT5631_MIC2_DIFF_INPUT_SHIFT, rt5631_input_mode);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun /* MONO Input Type */
215*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_monoin_mode_enum, RT5631_MONO_INPUT_VOL,
216*4882a593Smuzhiyun 			    RT5631_MONO_DIFF_INPUT_SHIFT, rt5631_input_mode);
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun /* SPK Ratio Gain Control */
219*4882a593Smuzhiyun static const char *rt5631_spk_ratio[] = {"1.00x", "1.09x", "1.27x", "1.44x",
220*4882a593Smuzhiyun 			"1.56x", "1.68x", "1.99x", "2.34x"};
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_spk_ratio_enum, RT5631_GEN_PUR_CTRL_REG,
223*4882a593Smuzhiyun 			    RT5631_SPK_AMP_RATIO_CTRL_SHIFT, rt5631_spk_ratio);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_snd_controls[] = {
226*4882a593Smuzhiyun 	/* MIC */
227*4882a593Smuzhiyun 	SOC_ENUM("MIC1 Mode Control",  rt5631_mic1_mode_enum),
228*4882a593Smuzhiyun 	SOC_SINGLE_TLV("MIC1 Boost Volume", RT5631_MIC_CTRL_2,
229*4882a593Smuzhiyun 		RT5631_MIC1_BOOST_SHIFT, 8, 0, mic_bst_tlv),
230*4882a593Smuzhiyun 	SOC_ENUM("MIC2 Mode Control", rt5631_mic2_mode_enum),
231*4882a593Smuzhiyun 	SOC_SINGLE_TLV("MIC2 Boost Volume", RT5631_MIC_CTRL_2,
232*4882a593Smuzhiyun 		RT5631_MIC2_BOOST_SHIFT, 8, 0, mic_bst_tlv),
233*4882a593Smuzhiyun 	/* MONO IN */
234*4882a593Smuzhiyun 	SOC_ENUM("MONOIN Mode Control", rt5631_monoin_mode_enum),
235*4882a593Smuzhiyun 	SOC_DOUBLE_TLV("MONOIN_RX Capture Volume", RT5631_MONO_INPUT_VOL,
236*4882a593Smuzhiyun 			RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
237*4882a593Smuzhiyun 			RT5631_VOL_MASK, 1, in_vol_tlv),
238*4882a593Smuzhiyun 	/* AXI */
239*4882a593Smuzhiyun 	SOC_DOUBLE_TLV("AXI Capture Volume", RT5631_AUX_IN_VOL,
240*4882a593Smuzhiyun 			RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
241*4882a593Smuzhiyun 			RT5631_VOL_MASK, 1, in_vol_tlv),
242*4882a593Smuzhiyun 	/* DAC */
243*4882a593Smuzhiyun 	SOC_DOUBLE_TLV("PCM Playback Volume", RT5631_STEREO_DAC_VOL_2,
244*4882a593Smuzhiyun 			RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
245*4882a593Smuzhiyun 			RT5631_DAC_VOL_MASK, 1, dac_vol_tlv),
246*4882a593Smuzhiyun 	SOC_DOUBLE("PCM Playback Switch", RT5631_STEREO_DAC_VOL_1,
247*4882a593Smuzhiyun 			RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
248*4882a593Smuzhiyun 	/* AXO */
249*4882a593Smuzhiyun 	SOC_SINGLE("AXO1 Playback Switch", RT5631_MONO_AXO_1_2_VOL,
250*4882a593Smuzhiyun 				RT5631_L_MUTE_SHIFT, 1, 1),
251*4882a593Smuzhiyun 	SOC_SINGLE("AXO2 Playback Switch", RT5631_MONO_AXO_1_2_VOL,
252*4882a593Smuzhiyun 				RT5631_R_VOL_SHIFT, 1, 1),
253*4882a593Smuzhiyun 	/* OUTVOL */
254*4882a593Smuzhiyun 	SOC_DOUBLE("OUTVOL Channel Switch", RT5631_SPK_OUT_VOL,
255*4882a593Smuzhiyun 		RT5631_L_EN_SHIFT, RT5631_R_EN_SHIFT, 1, 0),
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	/* SPK */
258*4882a593Smuzhiyun 	SOC_DOUBLE("Speaker Playback Switch", RT5631_SPK_OUT_VOL,
259*4882a593Smuzhiyun 		RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
260*4882a593Smuzhiyun 	SOC_DOUBLE_TLV("Speaker Playback Volume", RT5631_SPK_OUT_VOL,
261*4882a593Smuzhiyun 		RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT, 39, 1, out_vol_tlv),
262*4882a593Smuzhiyun 	/* MONO OUT */
263*4882a593Smuzhiyun 	SOC_SINGLE("MONO Playback Switch", RT5631_MONO_AXO_1_2_VOL,
264*4882a593Smuzhiyun 				RT5631_MUTE_MONO_SHIFT, 1, 1),
265*4882a593Smuzhiyun 	/* HP */
266*4882a593Smuzhiyun 	SOC_DOUBLE("HP Playback Switch", RT5631_HP_OUT_VOL,
267*4882a593Smuzhiyun 		RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
268*4882a593Smuzhiyun 	SOC_DOUBLE_TLV("HP Playback Volume", RT5631_HP_OUT_VOL,
269*4882a593Smuzhiyun 		RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
270*4882a593Smuzhiyun 		RT5631_VOL_MASK, 1, out_vol_tlv),
271*4882a593Smuzhiyun 	/* DMIC */
272*4882a593Smuzhiyun 	SOC_SINGLE_EXT("DMIC Switch", 0, 0, 1, 0,
273*4882a593Smuzhiyun 		rt5631_dmic_get, rt5631_dmic_put),
274*4882a593Smuzhiyun 	SOC_DOUBLE("DMIC Capture Switch", RT5631_DIG_MIC_CTRL,
275*4882a593Smuzhiyun 		RT5631_DMIC_L_CH_MUTE_SHIFT,
276*4882a593Smuzhiyun 		RT5631_DMIC_R_CH_MUTE_SHIFT, 1, 1),
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	/* SPK Ratio Gain Control */
279*4882a593Smuzhiyun 	SOC_ENUM("SPK Ratio Control", rt5631_spk_ratio_enum),
280*4882a593Smuzhiyun };
281*4882a593Smuzhiyun 
check_sysclk1_source(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)282*4882a593Smuzhiyun static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
283*4882a593Smuzhiyun 			 struct snd_soc_dapm_widget *sink)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
286*4882a593Smuzhiyun 	unsigned int reg;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, RT5631_GLOBAL_CLK_CTRL);
289*4882a593Smuzhiyun 	return reg & RT5631_SYSCLK_SOUR_SEL_PLL;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun 
check_dmic_used(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)292*4882a593Smuzhiyun static int check_dmic_used(struct snd_soc_dapm_widget *source,
293*4882a593Smuzhiyun 			 struct snd_soc_dapm_widget *sink)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
296*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
297*4882a593Smuzhiyun 	return rt5631->dmic_used_flag;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun 
check_dacl_to_outmixl(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)300*4882a593Smuzhiyun static int check_dacl_to_outmixl(struct snd_soc_dapm_widget *source,
301*4882a593Smuzhiyun 			 struct snd_soc_dapm_widget *sink)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
304*4882a593Smuzhiyun 	unsigned int reg;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, RT5631_OUTMIXER_L_CTRL);
307*4882a593Smuzhiyun 	return !(reg & RT5631_M_DAC_L_TO_OUTMIXER_L);
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun 
check_dacr_to_outmixr(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)310*4882a593Smuzhiyun static int check_dacr_to_outmixr(struct snd_soc_dapm_widget *source,
311*4882a593Smuzhiyun 			 struct snd_soc_dapm_widget *sink)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
314*4882a593Smuzhiyun 	unsigned int reg;
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, RT5631_OUTMIXER_R_CTRL);
317*4882a593Smuzhiyun 	return !(reg & RT5631_M_DAC_R_TO_OUTMIXER_R);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun 
check_dacl_to_spkmixl(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)320*4882a593Smuzhiyun static int check_dacl_to_spkmixl(struct snd_soc_dapm_widget *source,
321*4882a593Smuzhiyun 			 struct snd_soc_dapm_widget *sink)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
324*4882a593Smuzhiyun 	unsigned int reg;
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, RT5631_SPK_MIXER_CTRL);
327*4882a593Smuzhiyun 	return !(reg & RT5631_M_DAC_L_TO_SPKMIXER_L);
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun 
check_dacr_to_spkmixr(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)330*4882a593Smuzhiyun static int check_dacr_to_spkmixr(struct snd_soc_dapm_widget *source,
331*4882a593Smuzhiyun 			 struct snd_soc_dapm_widget *sink)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
334*4882a593Smuzhiyun 	unsigned int reg;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, RT5631_SPK_MIXER_CTRL);
337*4882a593Smuzhiyun 	return !(reg & RT5631_M_DAC_R_TO_SPKMIXER_R);
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun 
check_adcl_select(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)340*4882a593Smuzhiyun static int check_adcl_select(struct snd_soc_dapm_widget *source,
341*4882a593Smuzhiyun 			 struct snd_soc_dapm_widget *sink)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
344*4882a593Smuzhiyun 	unsigned int reg;
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, RT5631_ADC_REC_MIXER);
347*4882a593Smuzhiyun 	return !(reg & RT5631_M_MIC1_TO_RECMIXER_L);
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun 
check_adcr_select(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)350*4882a593Smuzhiyun static int check_adcr_select(struct snd_soc_dapm_widget *source,
351*4882a593Smuzhiyun 			 struct snd_soc_dapm_widget *sink)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
354*4882a593Smuzhiyun 	unsigned int reg;
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, RT5631_ADC_REC_MIXER);
357*4882a593Smuzhiyun 	return !(reg & RT5631_M_MIC2_TO_RECMIXER_R);
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun /**
361*4882a593Smuzhiyun  * onebit_depop_power_stage - auto depop in power stage.
362*4882a593Smuzhiyun  * @component: ASoC component
363*4882a593Smuzhiyun  * @enable: power on/off
364*4882a593Smuzhiyun  *
365*4882a593Smuzhiyun  * When power on/off headphone, the depop sequence is done by hardware.
366*4882a593Smuzhiyun  */
onebit_depop_power_stage(struct snd_soc_component * component,int enable)367*4882a593Smuzhiyun static void onebit_depop_power_stage(struct snd_soc_component *component, int enable)
368*4882a593Smuzhiyun {
369*4882a593Smuzhiyun 	unsigned int soft_vol, hp_zc;
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	/* enable one-bit depop function */
372*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, RT5631_DEPOP_FUN_CTRL_2,
373*4882a593Smuzhiyun 				RT5631_EN_ONE_BIT_DEPOP, 0);
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	/* keep soft volume and zero crossing setting */
376*4882a593Smuzhiyun 	soft_vol = snd_soc_component_read(component, RT5631_SOFT_VOL_CTRL);
377*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, 0);
378*4882a593Smuzhiyun 	hp_zc = snd_soc_component_read(component, RT5631_INT_ST_IRQ_CTRL_2);
379*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
380*4882a593Smuzhiyun 	if (enable) {
381*4882a593Smuzhiyun 		/* config one-bit depop parameter */
382*4882a593Smuzhiyun 		rt5631_write_index(component, RT5631_TEST_MODE_CTRL, 0x84c0);
383*4882a593Smuzhiyun 		rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x309f);
384*4882a593Smuzhiyun 		rt5631_write_index(component, RT5631_CP_INTL_REG2, 0x6530);
385*4882a593Smuzhiyun 		/* power on capless block */
386*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_2,
387*4882a593Smuzhiyun 				RT5631_EN_CAP_FREE_DEPOP);
388*4882a593Smuzhiyun 	} else {
389*4882a593Smuzhiyun 		/* power off capless block */
390*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_2, 0);
391*4882a593Smuzhiyun 		msleep(100);
392*4882a593Smuzhiyun 	}
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	/* recover soft volume and zero crossing setting */
395*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, soft_vol);
396*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun /**
400*4882a593Smuzhiyun  * onebit_depop_mute_stage - auto depop in mute stage.
401*4882a593Smuzhiyun  * @component: ASoC component
402*4882a593Smuzhiyun  * @enable: mute/unmute
403*4882a593Smuzhiyun  *
404*4882a593Smuzhiyun  * When mute/unmute headphone, the depop sequence is done by hardware.
405*4882a593Smuzhiyun  */
onebit_depop_mute_stage(struct snd_soc_component * component,int enable)406*4882a593Smuzhiyun static void onebit_depop_mute_stage(struct snd_soc_component *component, int enable)
407*4882a593Smuzhiyun {
408*4882a593Smuzhiyun 	unsigned int soft_vol, hp_zc;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	/* enable one-bit depop function */
411*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, RT5631_DEPOP_FUN_CTRL_2,
412*4882a593Smuzhiyun 				RT5631_EN_ONE_BIT_DEPOP, 0);
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	/* keep soft volume and zero crossing setting */
415*4882a593Smuzhiyun 	soft_vol = snd_soc_component_read(component, RT5631_SOFT_VOL_CTRL);
416*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, 0);
417*4882a593Smuzhiyun 	hp_zc = snd_soc_component_read(component, RT5631_INT_ST_IRQ_CTRL_2);
418*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
419*4882a593Smuzhiyun 	if (enable) {
420*4882a593Smuzhiyun 		schedule_timeout_uninterruptible(msecs_to_jiffies(10));
421*4882a593Smuzhiyun 		/* config one-bit depop parameter */
422*4882a593Smuzhiyun 		rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x307f);
423*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_HP_OUT_VOL,
424*4882a593Smuzhiyun 				RT5631_L_MUTE | RT5631_R_MUTE, 0);
425*4882a593Smuzhiyun 		msleep(300);
426*4882a593Smuzhiyun 	} else {
427*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_HP_OUT_VOL,
428*4882a593Smuzhiyun 			RT5631_L_MUTE | RT5631_R_MUTE,
429*4882a593Smuzhiyun 			RT5631_L_MUTE | RT5631_R_MUTE);
430*4882a593Smuzhiyun 		msleep(100);
431*4882a593Smuzhiyun 	}
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	/* recover soft volume and zero crossing setting */
434*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, soft_vol);
435*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun /**
439*4882a593Smuzhiyun  * onebit_depop_power_stage - step by step depop sequence in power stage.
440*4882a593Smuzhiyun  * @component: ASoC component
441*4882a593Smuzhiyun  * @enable: power on/off
442*4882a593Smuzhiyun  *
443*4882a593Smuzhiyun  * When power on/off headphone, the depop sequence is done in step by step.
444*4882a593Smuzhiyun  */
depop_seq_power_stage(struct snd_soc_component * component,int enable)445*4882a593Smuzhiyun static void depop_seq_power_stage(struct snd_soc_component *component, int enable)
446*4882a593Smuzhiyun {
447*4882a593Smuzhiyun 	unsigned int soft_vol, hp_zc;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	/* depop control by register */
450*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, RT5631_DEPOP_FUN_CTRL_2,
451*4882a593Smuzhiyun 		RT5631_EN_ONE_BIT_DEPOP, RT5631_EN_ONE_BIT_DEPOP);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	/* keep soft volume and zero crossing setting */
454*4882a593Smuzhiyun 	soft_vol = snd_soc_component_read(component, RT5631_SOFT_VOL_CTRL);
455*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, 0);
456*4882a593Smuzhiyun 	hp_zc = snd_soc_component_read(component, RT5631_INT_ST_IRQ_CTRL_2);
457*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
458*4882a593Smuzhiyun 	if (enable) {
459*4882a593Smuzhiyun 		/* config depop sequence parameter */
460*4882a593Smuzhiyun 		rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x303e);
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 		/* power on headphone and charge pump */
463*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
464*4882a593Smuzhiyun 			RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
465*4882a593Smuzhiyun 			RT5631_PWR_HP_R_AMP,
466*4882a593Smuzhiyun 			RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
467*4882a593Smuzhiyun 			RT5631_PWR_HP_R_AMP);
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 		/* power on soft generator and depop mode2 */
470*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
471*4882a593Smuzhiyun 			RT5631_POW_ON_SOFT_GEN | RT5631_EN_DEPOP2_FOR_HP);
472*4882a593Smuzhiyun 		msleep(100);
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 		/* stop depop mode */
475*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
476*4882a593Smuzhiyun 			RT5631_PWR_HP_DEPOP_DIS, RT5631_PWR_HP_DEPOP_DIS);
477*4882a593Smuzhiyun 	} else {
478*4882a593Smuzhiyun 		/* config depop sequence parameter */
479*4882a593Smuzhiyun 		rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x303F);
480*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
481*4882a593Smuzhiyun 			RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
482*4882a593Smuzhiyun 			RT5631_PD_HPAMP_L_ST_UP | RT5631_PD_HPAMP_R_ST_UP);
483*4882a593Smuzhiyun 		msleep(75);
484*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
485*4882a593Smuzhiyun 			RT5631_POW_ON_SOFT_GEN | RT5631_PD_HPAMP_L_ST_UP |
486*4882a593Smuzhiyun 			RT5631_PD_HPAMP_R_ST_UP);
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 		/* start depop mode */
489*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
490*4882a593Smuzhiyun 				RT5631_PWR_HP_DEPOP_DIS, 0);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 		/* config depop sequence parameter */
493*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
494*4882a593Smuzhiyun 			RT5631_POW_ON_SOFT_GEN | RT5631_EN_DEPOP2_FOR_HP |
495*4882a593Smuzhiyun 			RT5631_PD_HPAMP_L_ST_UP | RT5631_PD_HPAMP_R_ST_UP);
496*4882a593Smuzhiyun 		msleep(80);
497*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
498*4882a593Smuzhiyun 			RT5631_POW_ON_SOFT_GEN);
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 		/* power down headphone and charge pump */
501*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
502*4882a593Smuzhiyun 			RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
503*4882a593Smuzhiyun 			RT5631_PWR_HP_R_AMP, 0);
504*4882a593Smuzhiyun 	}
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	/* recover soft volume and zero crossing setting */
507*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, soft_vol);
508*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun /**
512*4882a593Smuzhiyun  * depop_seq_mute_stage - step by step depop sequence in mute stage.
513*4882a593Smuzhiyun  * @component: ASoC component
514*4882a593Smuzhiyun  * @enable: mute/unmute
515*4882a593Smuzhiyun  *
516*4882a593Smuzhiyun  * When mute/unmute headphone, the depop sequence is done in step by step.
517*4882a593Smuzhiyun  */
depop_seq_mute_stage(struct snd_soc_component * component,int enable)518*4882a593Smuzhiyun static void depop_seq_mute_stage(struct snd_soc_component *component, int enable)
519*4882a593Smuzhiyun {
520*4882a593Smuzhiyun 	unsigned int soft_vol, hp_zc;
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	/* depop control by register */
523*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, RT5631_DEPOP_FUN_CTRL_2,
524*4882a593Smuzhiyun 		RT5631_EN_ONE_BIT_DEPOP, RT5631_EN_ONE_BIT_DEPOP);
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 	/* keep soft volume and zero crossing setting */
527*4882a593Smuzhiyun 	soft_vol = snd_soc_component_read(component, RT5631_SOFT_VOL_CTRL);
528*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, 0);
529*4882a593Smuzhiyun 	hp_zc = snd_soc_component_read(component, RT5631_INT_ST_IRQ_CTRL_2);
530*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
531*4882a593Smuzhiyun 	if (enable) {
532*4882a593Smuzhiyun 		schedule_timeout_uninterruptible(msecs_to_jiffies(10));
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 		/* config depop sequence parameter */
535*4882a593Smuzhiyun 		rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x302f);
536*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
537*4882a593Smuzhiyun 			RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
538*4882a593Smuzhiyun 			RT5631_EN_HP_R_M_UN_MUTE_DEPOP |
539*4882a593Smuzhiyun 			RT5631_EN_HP_L_M_UN_MUTE_DEPOP);
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_HP_OUT_VOL,
542*4882a593Smuzhiyun 				RT5631_L_MUTE | RT5631_R_MUTE, 0);
543*4882a593Smuzhiyun 		msleep(160);
544*4882a593Smuzhiyun 	} else {
545*4882a593Smuzhiyun 		/* config depop sequence parameter */
546*4882a593Smuzhiyun 		rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x302f);
547*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
548*4882a593Smuzhiyun 			RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
549*4882a593Smuzhiyun 			RT5631_EN_HP_R_M_UN_MUTE_DEPOP |
550*4882a593Smuzhiyun 			RT5631_EN_HP_L_M_UN_MUTE_DEPOP);
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_HP_OUT_VOL,
553*4882a593Smuzhiyun 			RT5631_L_MUTE | RT5631_R_MUTE,
554*4882a593Smuzhiyun 			RT5631_L_MUTE | RT5631_R_MUTE);
555*4882a593Smuzhiyun 		msleep(150);
556*4882a593Smuzhiyun 	}
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	/* recover soft volume and zero crossing setting */
559*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, soft_vol);
560*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun 
hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)563*4882a593Smuzhiyun static int hp_event(struct snd_soc_dapm_widget *w,
564*4882a593Smuzhiyun 	struct snd_kcontrol *kcontrol, int event)
565*4882a593Smuzhiyun {
566*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
567*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	switch (event) {
570*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMD:
571*4882a593Smuzhiyun 		if (rt5631->codec_version) {
572*4882a593Smuzhiyun 			onebit_depop_mute_stage(component, 0);
573*4882a593Smuzhiyun 			onebit_depop_power_stage(component, 0);
574*4882a593Smuzhiyun 		} else {
575*4882a593Smuzhiyun 			depop_seq_mute_stage(component, 0);
576*4882a593Smuzhiyun 			depop_seq_power_stage(component, 0);
577*4882a593Smuzhiyun 		}
578*4882a593Smuzhiyun 		break;
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMU:
581*4882a593Smuzhiyun 		if (rt5631->codec_version) {
582*4882a593Smuzhiyun 			onebit_depop_power_stage(component, 1);
583*4882a593Smuzhiyun 			onebit_depop_mute_stage(component, 1);
584*4882a593Smuzhiyun 		} else {
585*4882a593Smuzhiyun 			depop_seq_power_stage(component, 1);
586*4882a593Smuzhiyun 			depop_seq_mute_stage(component, 1);
587*4882a593Smuzhiyun 		}
588*4882a593Smuzhiyun 		break;
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	default:
591*4882a593Smuzhiyun 		break;
592*4882a593Smuzhiyun 	}
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	return 0;
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun 
set_dmic_params(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)597*4882a593Smuzhiyun static int set_dmic_params(struct snd_soc_dapm_widget *w,
598*4882a593Smuzhiyun 	struct snd_kcontrol *kcontrol, int event)
599*4882a593Smuzhiyun {
600*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
601*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 	switch (rt5631->rx_rate) {
604*4882a593Smuzhiyun 	case 44100:
605*4882a593Smuzhiyun 	case 48000:
606*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_DIG_MIC_CTRL,
607*4882a593Smuzhiyun 			RT5631_DMIC_CLK_CTRL_MASK,
608*4882a593Smuzhiyun 			RT5631_DMIC_CLK_CTRL_TO_32FS);
609*4882a593Smuzhiyun 		break;
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	case 32000:
612*4882a593Smuzhiyun 	case 22050:
613*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_DIG_MIC_CTRL,
614*4882a593Smuzhiyun 			RT5631_DMIC_CLK_CTRL_MASK,
615*4882a593Smuzhiyun 			RT5631_DMIC_CLK_CTRL_TO_64FS);
616*4882a593Smuzhiyun 		break;
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	case 16000:
619*4882a593Smuzhiyun 	case 11025:
620*4882a593Smuzhiyun 	case 8000:
621*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_DIG_MIC_CTRL,
622*4882a593Smuzhiyun 			RT5631_DMIC_CLK_CTRL_MASK,
623*4882a593Smuzhiyun 			RT5631_DMIC_CLK_CTRL_TO_128FS);
624*4882a593Smuzhiyun 		break;
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 	default:
627*4882a593Smuzhiyun 		return -EINVAL;
628*4882a593Smuzhiyun 	}
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	return 0;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun 
633*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_recmixl_mixer_controls[] = {
634*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("OUTMIXL Capture Switch", RT5631_ADC_REC_MIXER,
635*4882a593Smuzhiyun 			RT5631_M_OUTMIXL_RECMIXL_BIT, 1, 1),
636*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC1_BST1 Capture Switch", RT5631_ADC_REC_MIXER,
637*4882a593Smuzhiyun 			RT5631_M_MIC1_RECMIXL_BIT, 1, 1),
638*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AXILVOL Capture Switch", RT5631_ADC_REC_MIXER,
639*4882a593Smuzhiyun 			RT5631_M_AXIL_RECMIXL_BIT, 1, 1),
640*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MONOIN_RX Capture Switch", RT5631_ADC_REC_MIXER,
641*4882a593Smuzhiyun 			RT5631_M_MONO_IN_RECMIXL_BIT, 1, 1),
642*4882a593Smuzhiyun };
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_recmixr_mixer_controls[] = {
645*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MONOIN_RX Capture Switch", RT5631_ADC_REC_MIXER,
646*4882a593Smuzhiyun 			RT5631_M_MONO_IN_RECMIXR_BIT, 1, 1),
647*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AXIRVOL Capture Switch", RT5631_ADC_REC_MIXER,
648*4882a593Smuzhiyun 			RT5631_M_AXIR_RECMIXR_BIT, 1, 1),
649*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC2_BST2 Capture Switch", RT5631_ADC_REC_MIXER,
650*4882a593Smuzhiyun 			RT5631_M_MIC2_RECMIXR_BIT, 1, 1),
651*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("OUTMIXR Capture Switch", RT5631_ADC_REC_MIXER,
652*4882a593Smuzhiyun 			RT5631_M_OUTMIXR_RECMIXR_BIT, 1, 1),
653*4882a593Smuzhiyun };
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_spkmixl_mixer_controls[] = {
656*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_SPK_MIXER_CTRL,
657*4882a593Smuzhiyun 			RT5631_M_RECMIXL_SPKMIXL_BIT, 1, 1),
658*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC1_P Playback Switch", RT5631_SPK_MIXER_CTRL,
659*4882a593Smuzhiyun 			RT5631_M_MIC1P_SPKMIXL_BIT, 1, 1),
660*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("DACL Playback Switch", RT5631_SPK_MIXER_CTRL,
661*4882a593Smuzhiyun 			RT5631_M_DACL_SPKMIXL_BIT, 1, 1),
662*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("OUTMIXL Playback Switch", RT5631_SPK_MIXER_CTRL,
663*4882a593Smuzhiyun 			RT5631_M_OUTMIXL_SPKMIXL_BIT, 1, 1),
664*4882a593Smuzhiyun };
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_spkmixr_mixer_controls[] = {
667*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("OUTMIXR Playback Switch", RT5631_SPK_MIXER_CTRL,
668*4882a593Smuzhiyun 			RT5631_M_OUTMIXR_SPKMIXR_BIT, 1, 1),
669*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("DACR Playback Switch", RT5631_SPK_MIXER_CTRL,
670*4882a593Smuzhiyun 			RT5631_M_DACR_SPKMIXR_BIT, 1, 1),
671*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC2_P Playback Switch", RT5631_SPK_MIXER_CTRL,
672*4882a593Smuzhiyun 			RT5631_M_MIC2P_SPKMIXR_BIT, 1, 1),
673*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_SPK_MIXER_CTRL,
674*4882a593Smuzhiyun 			RT5631_M_RECMIXR_SPKMIXR_BIT, 1, 1),
675*4882a593Smuzhiyun };
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_outmixl_mixer_controls[] = {
678*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_OUTMIXER_L_CTRL,
679*4882a593Smuzhiyun 				RT5631_M_RECMIXL_OUTMIXL_BIT, 1, 1),
680*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_OUTMIXER_L_CTRL,
681*4882a593Smuzhiyun 				RT5631_M_RECMIXR_OUTMIXL_BIT, 1, 1),
682*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("DACL Playback Switch", RT5631_OUTMIXER_L_CTRL,
683*4882a593Smuzhiyun 				RT5631_M_DACL_OUTMIXL_BIT, 1, 1),
684*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_OUTMIXER_L_CTRL,
685*4882a593Smuzhiyun 				RT5631_M_MIC1_OUTMIXL_BIT, 1, 1),
686*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_OUTMIXER_L_CTRL,
687*4882a593Smuzhiyun 				RT5631_M_MIC2_OUTMIXL_BIT, 1, 1),
688*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MONOIN_RXP Playback Switch", RT5631_OUTMIXER_L_CTRL,
689*4882a593Smuzhiyun 				RT5631_M_MONO_INP_OUTMIXL_BIT, 1, 1),
690*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AXILVOL Playback Switch", RT5631_OUTMIXER_L_CTRL,
691*4882a593Smuzhiyun 				RT5631_M_AXIL_OUTMIXL_BIT, 1, 1),
692*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AXIRVOL Playback Switch", RT5631_OUTMIXER_L_CTRL,
693*4882a593Smuzhiyun 				RT5631_M_AXIR_OUTMIXL_BIT, 1, 1),
694*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("VDAC Playback Switch", RT5631_OUTMIXER_L_CTRL,
695*4882a593Smuzhiyun 				RT5631_M_VDAC_OUTMIXL_BIT, 1, 1),
696*4882a593Smuzhiyun };
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_outmixr_mixer_controls[] = {
699*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("VDAC Playback Switch", RT5631_OUTMIXER_R_CTRL,
700*4882a593Smuzhiyun 				RT5631_M_VDAC_OUTMIXR_BIT, 1, 1),
701*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AXIRVOL Playback Switch", RT5631_OUTMIXER_R_CTRL,
702*4882a593Smuzhiyun 				RT5631_M_AXIR_OUTMIXR_BIT, 1, 1),
703*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AXILVOL Playback Switch", RT5631_OUTMIXER_R_CTRL,
704*4882a593Smuzhiyun 				RT5631_M_AXIL_OUTMIXR_BIT, 1, 1),
705*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MONOIN_RXN Playback Switch", RT5631_OUTMIXER_R_CTRL,
706*4882a593Smuzhiyun 				RT5631_M_MONO_INN_OUTMIXR_BIT, 1, 1),
707*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_OUTMIXER_R_CTRL,
708*4882a593Smuzhiyun 				RT5631_M_MIC2_OUTMIXR_BIT, 1, 1),
709*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_OUTMIXER_R_CTRL,
710*4882a593Smuzhiyun 				RT5631_M_MIC1_OUTMIXR_BIT, 1, 1),
711*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("DACR Playback Switch", RT5631_OUTMIXER_R_CTRL,
712*4882a593Smuzhiyun 				RT5631_M_DACR_OUTMIXR_BIT, 1, 1),
713*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_OUTMIXER_R_CTRL,
714*4882a593Smuzhiyun 				RT5631_M_RECMIXR_OUTMIXR_BIT, 1, 1),
715*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_OUTMIXER_R_CTRL,
716*4882a593Smuzhiyun 				RT5631_M_RECMIXL_OUTMIXR_BIT, 1, 1),
717*4882a593Smuzhiyun };
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_AXO1MIX_mixer_controls[] = {
720*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_AXO1MIXER_CTRL,
721*4882a593Smuzhiyun 				RT5631_M_MIC1_AXO1MIX_BIT , 1, 1),
722*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_AXO1MIXER_CTRL,
723*4882a593Smuzhiyun 				RT5631_M_MIC2_AXO1MIX_BIT, 1, 1),
724*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_AXO1MIXER_CTRL,
725*4882a593Smuzhiyun 				RT5631_M_OUTMIXL_AXO1MIX_BIT , 1 , 1),
726*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_AXO1MIXER_CTRL,
727*4882a593Smuzhiyun 				RT5631_M_OUTMIXR_AXO1MIX_BIT, 1, 1),
728*4882a593Smuzhiyun };
729*4882a593Smuzhiyun 
730*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_AXO2MIX_mixer_controls[] = {
731*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_AXO2MIXER_CTRL,
732*4882a593Smuzhiyun 				RT5631_M_MIC1_AXO2MIX_BIT, 1, 1),
733*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_AXO2MIXER_CTRL,
734*4882a593Smuzhiyun 				RT5631_M_MIC2_AXO2MIX_BIT, 1, 1),
735*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_AXO2MIXER_CTRL,
736*4882a593Smuzhiyun 				RT5631_M_OUTMIXL_AXO2MIX_BIT, 1, 1),
737*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_AXO2MIXER_CTRL,
738*4882a593Smuzhiyun 				RT5631_M_OUTMIXR_AXO2MIX_BIT, 1 , 1),
739*4882a593Smuzhiyun };
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_spolmix_mixer_controls[] = {
742*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("SPKVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
743*4882a593Smuzhiyun 				RT5631_M_SPKVOLL_SPOLMIX_BIT, 1, 1),
744*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("SPKVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
745*4882a593Smuzhiyun 				RT5631_M_SPKVOLR_SPOLMIX_BIT, 1, 1),
746*4882a593Smuzhiyun };
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_spormix_mixer_controls[] = {
749*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("SPKVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
750*4882a593Smuzhiyun 				RT5631_M_SPKVOLL_SPORMIX_BIT, 1, 1),
751*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("SPKVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
752*4882a593Smuzhiyun 				RT5631_M_SPKVOLR_SPORMIX_BIT, 1, 1),
753*4882a593Smuzhiyun };
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_monomix_mixer_controls[] = {
756*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
757*4882a593Smuzhiyun 				RT5631_M_OUTVOLL_MONOMIX_BIT, 1, 1),
758*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
759*4882a593Smuzhiyun 				RT5631_M_OUTVOLR_MONOMIX_BIT, 1, 1),
760*4882a593Smuzhiyun };
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun /* Left SPK Volume Input */
763*4882a593Smuzhiyun static const char *rt5631_spkvoll_sel[] = {"Vmid", "SPKMIXL"};
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_spkvoll_enum, RT5631_SPK_OUT_VOL,
766*4882a593Smuzhiyun 			    RT5631_L_EN_SHIFT, rt5631_spkvoll_sel);
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_spkvoll_mux_control =
769*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Left SPKVOL SRC", rt5631_spkvoll_enum);
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun /* Left HP Volume Input */
772*4882a593Smuzhiyun static const char *rt5631_hpvoll_sel[] = {"Vmid", "OUTMIXL"};
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_hpvoll_enum, RT5631_HP_OUT_VOL,
775*4882a593Smuzhiyun 			    RT5631_L_EN_SHIFT, rt5631_hpvoll_sel);
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_hpvoll_mux_control =
778*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Left HPVOL SRC", rt5631_hpvoll_enum);
779*4882a593Smuzhiyun 
780*4882a593Smuzhiyun /* Left Out Volume Input */
781*4882a593Smuzhiyun static const char *rt5631_outvoll_sel[] = {"Vmid", "OUTMIXL"};
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_outvoll_enum, RT5631_MONO_AXO_1_2_VOL,
784*4882a593Smuzhiyun 			    RT5631_L_EN_SHIFT, rt5631_outvoll_sel);
785*4882a593Smuzhiyun 
786*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_outvoll_mux_control =
787*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Left OUTVOL SRC", rt5631_outvoll_enum);
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun /* Right Out Volume Input */
790*4882a593Smuzhiyun static const char *rt5631_outvolr_sel[] = {"Vmid", "OUTMIXR"};
791*4882a593Smuzhiyun 
792*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_outvolr_enum, RT5631_MONO_AXO_1_2_VOL,
793*4882a593Smuzhiyun 			    RT5631_R_EN_SHIFT, rt5631_outvolr_sel);
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_outvolr_mux_control =
796*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Right OUTVOL SRC", rt5631_outvolr_enum);
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun /* Right HP Volume Input */
799*4882a593Smuzhiyun static const char *rt5631_hpvolr_sel[] = {"Vmid", "OUTMIXR"};
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_hpvolr_enum, RT5631_HP_OUT_VOL,
802*4882a593Smuzhiyun 			    RT5631_R_EN_SHIFT, rt5631_hpvolr_sel);
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_hpvolr_mux_control =
805*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Right HPVOL SRC", rt5631_hpvolr_enum);
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun /* Right SPK Volume Input */
808*4882a593Smuzhiyun static const char *rt5631_spkvolr_sel[] = {"Vmid", "SPKMIXR"};
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_spkvolr_enum, RT5631_SPK_OUT_VOL,
811*4882a593Smuzhiyun 			    RT5631_R_EN_SHIFT, rt5631_spkvolr_sel);
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_spkvolr_mux_control =
814*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Right SPKVOL SRC", rt5631_spkvolr_enum);
815*4882a593Smuzhiyun 
816*4882a593Smuzhiyun /* SPO Left Channel Input */
817*4882a593Smuzhiyun static const char *rt5631_spol_src_sel[] = {
818*4882a593Smuzhiyun 	"SPOLMIX", "MONOIN_RX", "VDAC", "DACL"};
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_spol_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
821*4882a593Smuzhiyun 			    RT5631_SPK_L_MUX_SEL_SHIFT, rt5631_spol_src_sel);
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_spol_mux_control =
824*4882a593Smuzhiyun 	SOC_DAPM_ENUM("SPOL SRC", rt5631_spol_src_enum);
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun /* SPO Right Channel Input */
827*4882a593Smuzhiyun static const char *rt5631_spor_src_sel[] = {
828*4882a593Smuzhiyun 	"SPORMIX", "MONOIN_RX", "VDAC", "DACR"};
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_spor_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
831*4882a593Smuzhiyun 			    RT5631_SPK_R_MUX_SEL_SHIFT, rt5631_spor_src_sel);
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_spor_mux_control =
834*4882a593Smuzhiyun 	SOC_DAPM_ENUM("SPOR SRC", rt5631_spor_src_enum);
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun /* MONO Input */
837*4882a593Smuzhiyun static const char *rt5631_mono_src_sel[] = {"MONOMIX", "MONOIN_RX", "VDAC"};
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_mono_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
840*4882a593Smuzhiyun 			    RT5631_MONO_MUX_SEL_SHIFT, rt5631_mono_src_sel);
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_mono_mux_control =
843*4882a593Smuzhiyun 	SOC_DAPM_ENUM("MONO SRC", rt5631_mono_src_enum);
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun /* Left HPO Input */
846*4882a593Smuzhiyun static const char *rt5631_hpl_src_sel[] = {"Left HPVOL", "Left DAC"};
847*4882a593Smuzhiyun 
848*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_hpl_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
849*4882a593Smuzhiyun 			    RT5631_HP_L_MUX_SEL_SHIFT, rt5631_hpl_src_sel);
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_hpl_mux_control =
852*4882a593Smuzhiyun 	SOC_DAPM_ENUM("HPL SRC", rt5631_hpl_src_enum);
853*4882a593Smuzhiyun 
854*4882a593Smuzhiyun /* Right HPO Input */
855*4882a593Smuzhiyun static const char *rt5631_hpr_src_sel[] = {"Right HPVOL", "Right DAC"};
856*4882a593Smuzhiyun 
857*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt5631_hpr_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
858*4882a593Smuzhiyun 			    RT5631_HP_R_MUX_SEL_SHIFT, rt5631_hpr_src_sel);
859*4882a593Smuzhiyun 
860*4882a593Smuzhiyun static const struct snd_kcontrol_new rt5631_hpr_mux_control =
861*4882a593Smuzhiyun 	SOC_DAPM_ENUM("HPR SRC", rt5631_hpr_src_enum);
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun static const struct snd_soc_dapm_widget rt5631_dapm_widgets[] = {
864*4882a593Smuzhiyun 	/* Vmid */
865*4882a593Smuzhiyun 	SND_SOC_DAPM_VMID("Vmid"),
866*4882a593Smuzhiyun 	/* PLL1 */
867*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("PLL1", RT5631_PWR_MANAG_ADD2,
868*4882a593Smuzhiyun 			RT5631_PWR_PLL1_BIT, 0, NULL, 0),
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun 	/* Input Side */
871*4882a593Smuzhiyun 	/* Input Lines */
872*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("MIC1"),
873*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("MIC2"),
874*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AXIL"),
875*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AXIR"),
876*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("MONOIN_RXN"),
877*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("MONOIN_RXP"),
878*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("DMIC"),
879*4882a593Smuzhiyun 
880*4882a593Smuzhiyun 	/* MICBIAS */
881*4882a593Smuzhiyun 	SND_SOC_DAPM_MICBIAS("MIC Bias1", RT5631_PWR_MANAG_ADD2,
882*4882a593Smuzhiyun 			RT5631_PWR_MICBIAS1_VOL_BIT, 0),
883*4882a593Smuzhiyun 	SND_SOC_DAPM_MICBIAS("MIC Bias2", RT5631_PWR_MANAG_ADD2,
884*4882a593Smuzhiyun 			RT5631_PWR_MICBIAS2_VOL_BIT, 0),
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun 	/* Boost */
887*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("MIC1 Boost", RT5631_PWR_MANAG_ADD2,
888*4882a593Smuzhiyun 			RT5631_PWR_MIC1_BOOT_GAIN_BIT, 0, NULL, 0),
889*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("MIC2 Boost", RT5631_PWR_MANAG_ADD2,
890*4882a593Smuzhiyun 			RT5631_PWR_MIC2_BOOT_GAIN_BIT, 0, NULL, 0),
891*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("MONOIN_RXP Boost", RT5631_PWR_MANAG_ADD4,
892*4882a593Smuzhiyun 			RT5631_PWR_MONO_IN_P_VOL_BIT, 0, NULL, 0),
893*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("MONOIN_RXN Boost", RT5631_PWR_MANAG_ADD4,
894*4882a593Smuzhiyun 			RT5631_PWR_MONO_IN_N_VOL_BIT, 0, NULL, 0),
895*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("AXIL Boost", RT5631_PWR_MANAG_ADD4,
896*4882a593Smuzhiyun 			RT5631_PWR_AXIL_IN_VOL_BIT, 0, NULL, 0),
897*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("AXIR Boost", RT5631_PWR_MANAG_ADD4,
898*4882a593Smuzhiyun 			RT5631_PWR_AXIR_IN_VOL_BIT, 0, NULL, 0),
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun 	/* MONO In */
901*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("MONO_IN", SND_SOC_NOPM, 0, 0, NULL, 0),
902*4882a593Smuzhiyun 
903*4882a593Smuzhiyun 	/* REC Mixer */
904*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("RECMIXL Mixer", RT5631_PWR_MANAG_ADD2,
905*4882a593Smuzhiyun 		RT5631_PWR_RECMIXER_L_BIT, 0,
906*4882a593Smuzhiyun 		&rt5631_recmixl_mixer_controls[0],
907*4882a593Smuzhiyun 		ARRAY_SIZE(rt5631_recmixl_mixer_controls)),
908*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("RECMIXR Mixer", RT5631_PWR_MANAG_ADD2,
909*4882a593Smuzhiyun 		RT5631_PWR_RECMIXER_R_BIT, 0,
910*4882a593Smuzhiyun 		&rt5631_recmixr_mixer_controls[0],
911*4882a593Smuzhiyun 		ARRAY_SIZE(rt5631_recmixr_mixer_controls)),
912*4882a593Smuzhiyun 	/* Because of record duplication for L/R channel,
913*4882a593Smuzhiyun 	 * L/R ADCs need power up at the same time */
914*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("ADC Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
915*4882a593Smuzhiyun 
916*4882a593Smuzhiyun 	/* DMIC */
917*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("DMIC Supply", RT5631_DIG_MIC_CTRL,
918*4882a593Smuzhiyun 		RT5631_DMIC_ENA_SHIFT, 0,
919*4882a593Smuzhiyun 		set_dmic_params, SND_SOC_DAPM_PRE_PMU),
920*4882a593Smuzhiyun 	/* ADC Data Srouce */
921*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Left ADC Select", RT5631_INT_ST_IRQ_CTRL_2,
922*4882a593Smuzhiyun 			RT5631_ADC_DATA_SEL_MIC1_SHIFT, 0, NULL, 0),
923*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Right ADC Select", RT5631_INT_ST_IRQ_CTRL_2,
924*4882a593Smuzhiyun 			RT5631_ADC_DATA_SEL_MIC2_SHIFT, 0, NULL, 0),
925*4882a593Smuzhiyun 
926*4882a593Smuzhiyun 	/* ADCs */
927*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("Left ADC", "HIFI Capture",
928*4882a593Smuzhiyun 		RT5631_PWR_MANAG_ADD1, RT5631_PWR_ADC_L_CLK_BIT, 0),
929*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("Right ADC", "HIFI Capture",
930*4882a593Smuzhiyun 		RT5631_PWR_MANAG_ADD1, RT5631_PWR_ADC_R_CLK_BIT, 0),
931*4882a593Smuzhiyun 
932*4882a593Smuzhiyun 	/* DAC and ADC supply power */
933*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("I2S", RT5631_PWR_MANAG_ADD1,
934*4882a593Smuzhiyun 			RT5631_PWR_MAIN_I2S_BIT, 0, NULL, 0),
935*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("DAC REF", RT5631_PWR_MANAG_ADD1,
936*4882a593Smuzhiyun 			RT5631_PWR_DAC_REF_BIT, 0, NULL, 0),
937*4882a593Smuzhiyun 
938*4882a593Smuzhiyun 	/* Output Side */
939*4882a593Smuzhiyun 	/* DACs */
940*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("Left DAC", "HIFI Playback",
941*4882a593Smuzhiyun 		RT5631_PWR_MANAG_ADD1, RT5631_PWR_DAC_L_CLK_BIT, 0),
942*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("Right DAC", "HIFI Playback",
943*4882a593Smuzhiyun 		RT5631_PWR_MANAG_ADD1, RT5631_PWR_DAC_R_CLK_BIT, 0),
944*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("Voice DAC", "Voice DAC Mono Playback",
945*4882a593Smuzhiyun 				SND_SOC_NOPM, 0, 0),
946*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Voice DAC Boost", SND_SOC_NOPM, 0, 0, NULL, 0),
947*4882a593Smuzhiyun 	/* DAC supply power */
948*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Left DAC To Mixer", RT5631_PWR_MANAG_ADD1,
949*4882a593Smuzhiyun 			RT5631_PWR_DAC_L_TO_MIXER_BIT, 0, NULL, 0),
950*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Right DAC To Mixer", RT5631_PWR_MANAG_ADD1,
951*4882a593Smuzhiyun 			RT5631_PWR_DAC_R_TO_MIXER_BIT, 0, NULL, 0),
952*4882a593Smuzhiyun 
953*4882a593Smuzhiyun 	/* Left SPK Mixer */
954*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("SPKMIXL Mixer", RT5631_PWR_MANAG_ADD2,
955*4882a593Smuzhiyun 			RT5631_PWR_SPKMIXER_L_BIT, 0,
956*4882a593Smuzhiyun 			&rt5631_spkmixl_mixer_controls[0],
957*4882a593Smuzhiyun 			ARRAY_SIZE(rt5631_spkmixl_mixer_controls)),
958*4882a593Smuzhiyun 	/* Left Out Mixer */
959*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("OUTMIXL Mixer", RT5631_PWR_MANAG_ADD2,
960*4882a593Smuzhiyun 			RT5631_PWR_OUTMIXER_L_BIT, 0,
961*4882a593Smuzhiyun 			&rt5631_outmixl_mixer_controls[0],
962*4882a593Smuzhiyun 			ARRAY_SIZE(rt5631_outmixl_mixer_controls)),
963*4882a593Smuzhiyun 	/* Right Out Mixer */
964*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("OUTMIXR Mixer", RT5631_PWR_MANAG_ADD2,
965*4882a593Smuzhiyun 			RT5631_PWR_OUTMIXER_R_BIT, 0,
966*4882a593Smuzhiyun 			&rt5631_outmixr_mixer_controls[0],
967*4882a593Smuzhiyun 			ARRAY_SIZE(rt5631_outmixr_mixer_controls)),
968*4882a593Smuzhiyun 	/* Right SPK Mixer */
969*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("SPKMIXR Mixer", RT5631_PWR_MANAG_ADD2,
970*4882a593Smuzhiyun 			RT5631_PWR_SPKMIXER_R_BIT, 0,
971*4882a593Smuzhiyun 			&rt5631_spkmixr_mixer_controls[0],
972*4882a593Smuzhiyun 			ARRAY_SIZE(rt5631_spkmixr_mixer_controls)),
973*4882a593Smuzhiyun 
974*4882a593Smuzhiyun 	/* Volume Mux */
975*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("Left SPKVOL Mux", RT5631_PWR_MANAG_ADD4,
976*4882a593Smuzhiyun 			RT5631_PWR_SPK_L_VOL_BIT, 0,
977*4882a593Smuzhiyun 			&rt5631_spkvoll_mux_control),
978*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("Left HPVOL Mux", RT5631_PWR_MANAG_ADD4,
979*4882a593Smuzhiyun 			RT5631_PWR_HP_L_OUT_VOL_BIT, 0,
980*4882a593Smuzhiyun 			&rt5631_hpvoll_mux_control),
981*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("Left OUTVOL Mux", RT5631_PWR_MANAG_ADD4,
982*4882a593Smuzhiyun 			RT5631_PWR_LOUT_VOL_BIT, 0,
983*4882a593Smuzhiyun 			&rt5631_outvoll_mux_control),
984*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("Right OUTVOL Mux", RT5631_PWR_MANAG_ADD4,
985*4882a593Smuzhiyun 			RT5631_PWR_ROUT_VOL_BIT, 0,
986*4882a593Smuzhiyun 			&rt5631_outvolr_mux_control),
987*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("Right HPVOL Mux", RT5631_PWR_MANAG_ADD4,
988*4882a593Smuzhiyun 			RT5631_PWR_HP_R_OUT_VOL_BIT, 0,
989*4882a593Smuzhiyun 			&rt5631_hpvolr_mux_control),
990*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("Right SPKVOL Mux", RT5631_PWR_MANAG_ADD4,
991*4882a593Smuzhiyun 			RT5631_PWR_SPK_R_VOL_BIT, 0,
992*4882a593Smuzhiyun 			&rt5631_spkvolr_mux_control),
993*4882a593Smuzhiyun 
994*4882a593Smuzhiyun 	/* DAC To HP */
995*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_S("Left DAC_HP", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
996*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_S("Right DAC_HP", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	/* HP Depop */
999*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_S("HP Depop", 1, SND_SOC_NOPM, 0, 0,
1000*4882a593Smuzhiyun 		hp_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 	/* AXO1 Mixer */
1003*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("AXO1MIX Mixer", RT5631_PWR_MANAG_ADD3,
1004*4882a593Smuzhiyun 			RT5631_PWR_AXO1MIXER_BIT, 0,
1005*4882a593Smuzhiyun 			&rt5631_AXO1MIX_mixer_controls[0],
1006*4882a593Smuzhiyun 			ARRAY_SIZE(rt5631_AXO1MIX_mixer_controls)),
1007*4882a593Smuzhiyun 	/* SPOL Mixer */
1008*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("SPOLMIX Mixer", SND_SOC_NOPM, 0, 0,
1009*4882a593Smuzhiyun 			&rt5631_spolmix_mixer_controls[0],
1010*4882a593Smuzhiyun 			ARRAY_SIZE(rt5631_spolmix_mixer_controls)),
1011*4882a593Smuzhiyun 	/* MONO Mixer */
1012*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("MONOMIX Mixer", RT5631_PWR_MANAG_ADD3,
1013*4882a593Smuzhiyun 			RT5631_PWR_MONOMIXER_BIT, 0,
1014*4882a593Smuzhiyun 			&rt5631_monomix_mixer_controls[0],
1015*4882a593Smuzhiyun 			ARRAY_SIZE(rt5631_monomix_mixer_controls)),
1016*4882a593Smuzhiyun 	/* SPOR Mixer */
1017*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("SPORMIX Mixer", SND_SOC_NOPM, 0, 0,
1018*4882a593Smuzhiyun 			&rt5631_spormix_mixer_controls[0],
1019*4882a593Smuzhiyun 			ARRAY_SIZE(rt5631_spormix_mixer_controls)),
1020*4882a593Smuzhiyun 	/* AXO2 Mixer */
1021*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("AXO2MIX Mixer", RT5631_PWR_MANAG_ADD3,
1022*4882a593Smuzhiyun 			RT5631_PWR_AXO2MIXER_BIT, 0,
1023*4882a593Smuzhiyun 			&rt5631_AXO2MIX_mixer_controls[0],
1024*4882a593Smuzhiyun 			ARRAY_SIZE(rt5631_AXO2MIX_mixer_controls)),
1025*4882a593Smuzhiyun 
1026*4882a593Smuzhiyun 	/* Mux */
1027*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("SPOL Mux", SND_SOC_NOPM, 0, 0,
1028*4882a593Smuzhiyun 			&rt5631_spol_mux_control),
1029*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("SPOR Mux", SND_SOC_NOPM, 0, 0,
1030*4882a593Smuzhiyun 			&rt5631_spor_mux_control),
1031*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("MONO Mux", SND_SOC_NOPM, 0, 0,
1032*4882a593Smuzhiyun 			&rt5631_mono_mux_control),
1033*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0,
1034*4882a593Smuzhiyun 			&rt5631_hpl_mux_control),
1035*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0,
1036*4882a593Smuzhiyun 			&rt5631_hpr_mux_control),
1037*4882a593Smuzhiyun 
1038*4882a593Smuzhiyun 	/* AMP supply */
1039*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("MONO Depop", RT5631_PWR_MANAG_ADD3,
1040*4882a593Smuzhiyun 			RT5631_PWR_MONO_DEPOP_DIS_BIT, 0, NULL, 0),
1041*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Class D", RT5631_PWR_MANAG_ADD1,
1042*4882a593Smuzhiyun 			RT5631_PWR_CLASS_D_BIT, 0, NULL, 0),
1043*4882a593Smuzhiyun 
1044*4882a593Smuzhiyun 	/* Output Lines */
1045*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("AUXO1"),
1046*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("AUXO2"),
1047*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("SPOL"),
1048*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("SPOR"),
1049*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HPOL"),
1050*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HPOR"),
1051*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("MONO"),
1052*4882a593Smuzhiyun };
1053*4882a593Smuzhiyun 
1054*4882a593Smuzhiyun static const struct snd_soc_dapm_route rt5631_dapm_routes[] = {
1055*4882a593Smuzhiyun 	{"MIC1 Boost", NULL, "MIC1"},
1056*4882a593Smuzhiyun 	{"MIC2 Boost", NULL, "MIC2"},
1057*4882a593Smuzhiyun 	{"MONOIN_RXP Boost", NULL, "MONOIN_RXP"},
1058*4882a593Smuzhiyun 	{"MONOIN_RXN Boost", NULL, "MONOIN_RXN"},
1059*4882a593Smuzhiyun 	{"AXIL Boost", NULL, "AXIL"},
1060*4882a593Smuzhiyun 	{"AXIR Boost", NULL, "AXIR"},
1061*4882a593Smuzhiyun 
1062*4882a593Smuzhiyun 	{"MONO_IN", NULL, "MONOIN_RXP Boost"},
1063*4882a593Smuzhiyun 	{"MONO_IN", NULL, "MONOIN_RXN Boost"},
1064*4882a593Smuzhiyun 
1065*4882a593Smuzhiyun 	{"RECMIXL Mixer", "OUTMIXL Capture Switch", "OUTMIXL Mixer"},
1066*4882a593Smuzhiyun 	{"RECMIXL Mixer", "MIC1_BST1 Capture Switch", "MIC1 Boost"},
1067*4882a593Smuzhiyun 	{"RECMIXL Mixer", "AXILVOL Capture Switch", "AXIL Boost"},
1068*4882a593Smuzhiyun 	{"RECMIXL Mixer", "MONOIN_RX Capture Switch", "MONO_IN"},
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun 	{"RECMIXR Mixer", "OUTMIXR Capture Switch", "OUTMIXR Mixer"},
1071*4882a593Smuzhiyun 	{"RECMIXR Mixer", "MIC2_BST2 Capture Switch", "MIC2 Boost"},
1072*4882a593Smuzhiyun 	{"RECMIXR Mixer", "AXIRVOL Capture Switch", "AXIR Boost"},
1073*4882a593Smuzhiyun 	{"RECMIXR Mixer", "MONOIN_RX Capture Switch", "MONO_IN"},
1074*4882a593Smuzhiyun 
1075*4882a593Smuzhiyun 	{"ADC Mixer", NULL, "RECMIXL Mixer"},
1076*4882a593Smuzhiyun 	{"ADC Mixer", NULL, "RECMIXR Mixer"},
1077*4882a593Smuzhiyun 
1078*4882a593Smuzhiyun 	{"Left ADC", NULL, "ADC Mixer"},
1079*4882a593Smuzhiyun 	{"Left ADC", NULL, "Left ADC Select", check_adcl_select},
1080*4882a593Smuzhiyun 	{"Left ADC", NULL, "PLL1", check_sysclk1_source},
1081*4882a593Smuzhiyun 	{"Left ADC", NULL, "I2S"},
1082*4882a593Smuzhiyun 	{"Left ADC", NULL, "DAC REF"},
1083*4882a593Smuzhiyun 
1084*4882a593Smuzhiyun 	{"Right ADC", NULL, "ADC Mixer"},
1085*4882a593Smuzhiyun 	{"Right ADC", NULL, "Right ADC Select", check_adcr_select},
1086*4882a593Smuzhiyun 	{"Right ADC", NULL, "PLL1", check_sysclk1_source},
1087*4882a593Smuzhiyun 	{"Right ADC", NULL, "I2S"},
1088*4882a593Smuzhiyun 	{"Right ADC", NULL, "DAC REF"},
1089*4882a593Smuzhiyun 
1090*4882a593Smuzhiyun 	{"DMIC", NULL, "DMIC Supply", check_dmic_used},
1091*4882a593Smuzhiyun 	{"Left ADC", NULL, "DMIC"},
1092*4882a593Smuzhiyun 	{"Right ADC", NULL, "DMIC"},
1093*4882a593Smuzhiyun 
1094*4882a593Smuzhiyun 	{"Left DAC", NULL, "PLL1", check_sysclk1_source},
1095*4882a593Smuzhiyun 	{"Left DAC", NULL, "I2S"},
1096*4882a593Smuzhiyun 	{"Left DAC", NULL, "DAC REF"},
1097*4882a593Smuzhiyun 	{"Right DAC", NULL, "PLL1", check_sysclk1_source},
1098*4882a593Smuzhiyun 	{"Right DAC", NULL, "I2S"},
1099*4882a593Smuzhiyun 	{"Right DAC", NULL, "DAC REF"},
1100*4882a593Smuzhiyun 
1101*4882a593Smuzhiyun 	{"Voice DAC Boost", NULL, "Voice DAC"},
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun 	{"SPKMIXL Mixer", NULL, "Left DAC To Mixer", check_dacl_to_spkmixl},
1104*4882a593Smuzhiyun 	{"SPKMIXL Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
1105*4882a593Smuzhiyun 	{"SPKMIXL Mixer", "MIC1_P Playback Switch", "MIC1"},
1106*4882a593Smuzhiyun 	{"SPKMIXL Mixer", "DACL Playback Switch", "Left DAC"},
1107*4882a593Smuzhiyun 	{"SPKMIXL Mixer", "OUTMIXL Playback Switch", "OUTMIXL Mixer"},
1108*4882a593Smuzhiyun 
1109*4882a593Smuzhiyun 	{"SPKMIXR Mixer", NULL, "Right DAC To Mixer", check_dacr_to_spkmixr},
1110*4882a593Smuzhiyun 	{"SPKMIXR Mixer", "OUTMIXR Playback Switch", "OUTMIXR Mixer"},
1111*4882a593Smuzhiyun 	{"SPKMIXR Mixer", "DACR Playback Switch", "Right DAC"},
1112*4882a593Smuzhiyun 	{"SPKMIXR Mixer", "MIC2_P Playback Switch", "MIC2"},
1113*4882a593Smuzhiyun 	{"SPKMIXR Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun 	{"OUTMIXL Mixer", NULL, "Left DAC To Mixer", check_dacl_to_outmixl},
1116*4882a593Smuzhiyun 	{"OUTMIXL Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
1117*4882a593Smuzhiyun 	{"OUTMIXL Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
1118*4882a593Smuzhiyun 	{"OUTMIXL Mixer", "DACL Playback Switch", "Left DAC"},
1119*4882a593Smuzhiyun 	{"OUTMIXL Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1120*4882a593Smuzhiyun 	{"OUTMIXL Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1121*4882a593Smuzhiyun 	{"OUTMIXL Mixer", "MONOIN_RXP Playback Switch", "MONOIN_RXP Boost"},
1122*4882a593Smuzhiyun 	{"OUTMIXL Mixer", "AXILVOL Playback Switch", "AXIL Boost"},
1123*4882a593Smuzhiyun 	{"OUTMIXL Mixer", "AXIRVOL Playback Switch", "AXIR Boost"},
1124*4882a593Smuzhiyun 	{"OUTMIXL Mixer", "VDAC Playback Switch", "Voice DAC Boost"},
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun 	{"OUTMIXR Mixer", NULL, "Right DAC To Mixer", check_dacr_to_outmixr},
1127*4882a593Smuzhiyun 	{"OUTMIXR Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
1128*4882a593Smuzhiyun 	{"OUTMIXR Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
1129*4882a593Smuzhiyun 	{"OUTMIXR Mixer", "DACR Playback Switch", "Right DAC"},
1130*4882a593Smuzhiyun 	{"OUTMIXR Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1131*4882a593Smuzhiyun 	{"OUTMIXR Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1132*4882a593Smuzhiyun 	{"OUTMIXR Mixer", "MONOIN_RXN Playback Switch", "MONOIN_RXN Boost"},
1133*4882a593Smuzhiyun 	{"OUTMIXR Mixer", "AXILVOL Playback Switch", "AXIL Boost"},
1134*4882a593Smuzhiyun 	{"OUTMIXR Mixer", "AXIRVOL Playback Switch", "AXIR Boost"},
1135*4882a593Smuzhiyun 	{"OUTMIXR Mixer", "VDAC Playback Switch", "Voice DAC Boost"},
1136*4882a593Smuzhiyun 
1137*4882a593Smuzhiyun 	{"Left SPKVOL Mux",  "SPKMIXL", "SPKMIXL Mixer"},
1138*4882a593Smuzhiyun 	{"Left SPKVOL Mux",  "Vmid", "Vmid"},
1139*4882a593Smuzhiyun 	{"Left HPVOL Mux",  "OUTMIXL", "OUTMIXL Mixer"},
1140*4882a593Smuzhiyun 	{"Left HPVOL Mux",  "Vmid", "Vmid"},
1141*4882a593Smuzhiyun 	{"Left OUTVOL Mux",  "OUTMIXL", "OUTMIXL Mixer"},
1142*4882a593Smuzhiyun 	{"Left OUTVOL Mux",  "Vmid", "Vmid"},
1143*4882a593Smuzhiyun 	{"Right OUTVOL Mux",  "OUTMIXR", "OUTMIXR Mixer"},
1144*4882a593Smuzhiyun 	{"Right OUTVOL Mux",  "Vmid", "Vmid"},
1145*4882a593Smuzhiyun 	{"Right HPVOL Mux",  "OUTMIXR", "OUTMIXR Mixer"},
1146*4882a593Smuzhiyun 	{"Right HPVOL Mux",  "Vmid", "Vmid"},
1147*4882a593Smuzhiyun 	{"Right SPKVOL Mux",  "SPKMIXR", "SPKMIXR Mixer"},
1148*4882a593Smuzhiyun 	{"Right SPKVOL Mux",  "Vmid", "Vmid"},
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun 	{"AXO1MIX Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1151*4882a593Smuzhiyun 	{"AXO1MIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
1152*4882a593Smuzhiyun 	{"AXO1MIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
1153*4882a593Smuzhiyun 	{"AXO1MIX Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1154*4882a593Smuzhiyun 
1155*4882a593Smuzhiyun 	{"AXO2MIX Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1156*4882a593Smuzhiyun 	{"AXO2MIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
1157*4882a593Smuzhiyun 	{"AXO2MIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
1158*4882a593Smuzhiyun 	{"AXO2MIX Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1159*4882a593Smuzhiyun 
1160*4882a593Smuzhiyun 	{"SPOLMIX Mixer", "SPKVOLL Playback Switch", "Left SPKVOL Mux"},
1161*4882a593Smuzhiyun 	{"SPOLMIX Mixer", "SPKVOLR Playback Switch", "Right SPKVOL Mux"},
1162*4882a593Smuzhiyun 
1163*4882a593Smuzhiyun 	{"SPORMIX Mixer", "SPKVOLL Playback Switch", "Left SPKVOL Mux"},
1164*4882a593Smuzhiyun 	{"SPORMIX Mixer", "SPKVOLR Playback Switch", "Right SPKVOL Mux"},
1165*4882a593Smuzhiyun 
1166*4882a593Smuzhiyun 	{"MONOMIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
1167*4882a593Smuzhiyun 	{"MONOMIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
1168*4882a593Smuzhiyun 
1169*4882a593Smuzhiyun 	{"SPOL Mux", "SPOLMIX", "SPOLMIX Mixer"},
1170*4882a593Smuzhiyun 	{"SPOL Mux", "MONOIN_RX", "MONO_IN"},
1171*4882a593Smuzhiyun 	{"SPOL Mux", "VDAC", "Voice DAC Boost"},
1172*4882a593Smuzhiyun 	{"SPOL Mux", "DACL", "Left DAC"},
1173*4882a593Smuzhiyun 
1174*4882a593Smuzhiyun 	{"SPOR Mux", "SPORMIX", "SPORMIX Mixer"},
1175*4882a593Smuzhiyun 	{"SPOR Mux", "MONOIN_RX", "MONO_IN"},
1176*4882a593Smuzhiyun 	{"SPOR Mux", "VDAC", "Voice DAC Boost"},
1177*4882a593Smuzhiyun 	{"SPOR Mux", "DACR", "Right DAC"},
1178*4882a593Smuzhiyun 
1179*4882a593Smuzhiyun 	{"MONO Mux", "MONOMIX", "MONOMIX Mixer"},
1180*4882a593Smuzhiyun 	{"MONO Mux", "MONOIN_RX", "MONO_IN"},
1181*4882a593Smuzhiyun 	{"MONO Mux", "VDAC", "Voice DAC Boost"},
1182*4882a593Smuzhiyun 
1183*4882a593Smuzhiyun 	{"Right DAC_HP", NULL, "Right DAC"},
1184*4882a593Smuzhiyun 	{"Left DAC_HP", NULL, "Left DAC"},
1185*4882a593Smuzhiyun 
1186*4882a593Smuzhiyun 	{"HPL Mux", "Left HPVOL", "Left HPVOL Mux"},
1187*4882a593Smuzhiyun 	{"HPL Mux", "Left DAC", "Left DAC_HP"},
1188*4882a593Smuzhiyun 	{"HPR Mux", "Right HPVOL", "Right HPVOL Mux"},
1189*4882a593Smuzhiyun 	{"HPR Mux", "Right DAC", "Right DAC_HP"},
1190*4882a593Smuzhiyun 
1191*4882a593Smuzhiyun 	{"HP Depop", NULL, "HPL Mux"},
1192*4882a593Smuzhiyun 	{"HP Depop", NULL, "HPR Mux"},
1193*4882a593Smuzhiyun 
1194*4882a593Smuzhiyun 	{"AUXO1", NULL, "AXO1MIX Mixer"},
1195*4882a593Smuzhiyun 	{"AUXO2", NULL, "AXO2MIX Mixer"},
1196*4882a593Smuzhiyun 
1197*4882a593Smuzhiyun 	{"SPOL", NULL, "Class D"},
1198*4882a593Smuzhiyun 	{"SPOL", NULL, "SPOL Mux"},
1199*4882a593Smuzhiyun 	{"SPOR", NULL, "Class D"},
1200*4882a593Smuzhiyun 	{"SPOR", NULL, "SPOR Mux"},
1201*4882a593Smuzhiyun 
1202*4882a593Smuzhiyun 	{"HPOL", NULL, "HP Depop"},
1203*4882a593Smuzhiyun 	{"HPOR", NULL, "HP Depop"},
1204*4882a593Smuzhiyun 
1205*4882a593Smuzhiyun 	{"MONO", NULL, "MONO Depop"},
1206*4882a593Smuzhiyun 	{"MONO", NULL, "MONO Mux"},
1207*4882a593Smuzhiyun };
1208*4882a593Smuzhiyun 
1209*4882a593Smuzhiyun struct coeff_clk_div {
1210*4882a593Smuzhiyun 	u32 mclk;
1211*4882a593Smuzhiyun 	u32 bclk;
1212*4882a593Smuzhiyun 	u32 rate;
1213*4882a593Smuzhiyun 	u16 reg_val;
1214*4882a593Smuzhiyun };
1215*4882a593Smuzhiyun 
1216*4882a593Smuzhiyun /* PLL divisors */
1217*4882a593Smuzhiyun struct pll_div {
1218*4882a593Smuzhiyun 	u32 pll_in;
1219*4882a593Smuzhiyun 	u32 pll_out;
1220*4882a593Smuzhiyun 	u16 reg_val;
1221*4882a593Smuzhiyun };
1222*4882a593Smuzhiyun 
1223*4882a593Smuzhiyun static const struct pll_div codec_master_pll_div[] = {
1224*4882a593Smuzhiyun 	{2048000,  8192000,  0x0ea0},
1225*4882a593Smuzhiyun 	{3686400,  8192000,  0x4e27},
1226*4882a593Smuzhiyun 	{12000000,  8192000,  0x456b},
1227*4882a593Smuzhiyun 	{13000000,  8192000,  0x495f},
1228*4882a593Smuzhiyun 	{13100000,  8192000,  0x0320},
1229*4882a593Smuzhiyun 	{2048000,  11289600,  0xf637},
1230*4882a593Smuzhiyun 	{3686400,  11289600,  0x2f22},
1231*4882a593Smuzhiyun 	{12000000,  11289600,  0x3e2f},
1232*4882a593Smuzhiyun 	{13000000,  11289600,  0x4d5b},
1233*4882a593Smuzhiyun 	{13100000,  11289600,  0x363b},
1234*4882a593Smuzhiyun 	{2048000,  16384000,  0x1ea0},
1235*4882a593Smuzhiyun 	{3686400,  16384000,  0x9e27},
1236*4882a593Smuzhiyun 	{12000000,  16384000,  0x452b},
1237*4882a593Smuzhiyun 	{13000000,  16384000,  0x542f},
1238*4882a593Smuzhiyun 	{13100000,  16384000,  0x03a0},
1239*4882a593Smuzhiyun 	{2048000,  16934400,  0xe625},
1240*4882a593Smuzhiyun 	{3686400,  16934400,  0x9126},
1241*4882a593Smuzhiyun 	{12000000,  16934400,  0x4d2c},
1242*4882a593Smuzhiyun 	{13000000,  16934400,  0x742f},
1243*4882a593Smuzhiyun 	{13100000,  16934400,  0x3c27},
1244*4882a593Smuzhiyun 	{2048000,  22579200,  0x2aa0},
1245*4882a593Smuzhiyun 	{3686400,  22579200,  0x2f20},
1246*4882a593Smuzhiyun 	{12000000,  22579200,  0x7e2f},
1247*4882a593Smuzhiyun 	{13000000,  22579200,  0x742f},
1248*4882a593Smuzhiyun 	{13100000,  22579200,  0x3c27},
1249*4882a593Smuzhiyun 	{2048000,  24576000,  0x2ea0},
1250*4882a593Smuzhiyun 	{3686400,  24576000,  0xee27},
1251*4882a593Smuzhiyun 	{12000000,  24576000,  0x2915},
1252*4882a593Smuzhiyun 	{13000000,  24576000,  0x772e},
1253*4882a593Smuzhiyun 	{13100000,  24576000,  0x0d20},
1254*4882a593Smuzhiyun 	{26000000,  24576000,  0x2027},
1255*4882a593Smuzhiyun 	{26000000,  22579200,  0x392f},
1256*4882a593Smuzhiyun 	{24576000,  22579200,  0x0921},
1257*4882a593Smuzhiyun 	{24576000,  24576000,  0x02a0},
1258*4882a593Smuzhiyun };
1259*4882a593Smuzhiyun 
1260*4882a593Smuzhiyun static const struct pll_div codec_slave_pll_div[] = {
1261*4882a593Smuzhiyun 	{256000,  2048000,  0x46f0},
1262*4882a593Smuzhiyun 	{256000,  4096000,  0x3ea0},
1263*4882a593Smuzhiyun 	{352800,  5644800,  0x3ea0},
1264*4882a593Smuzhiyun 	{512000,  8192000,  0x3ea0},
1265*4882a593Smuzhiyun 	{1024000,  8192000,  0x46f0},
1266*4882a593Smuzhiyun 	{705600,  11289600,  0x3ea0},
1267*4882a593Smuzhiyun 	{1024000,  16384000,  0x3ea0},
1268*4882a593Smuzhiyun 	{1411200,  22579200,  0x3ea0},
1269*4882a593Smuzhiyun 	{1536000,  24576000,  0x3ea0},
1270*4882a593Smuzhiyun 	{2048000,  16384000,  0x1ea0},
1271*4882a593Smuzhiyun 	{2822400,  22579200,  0x1ea0},
1272*4882a593Smuzhiyun 	{2822400,  45158400,  0x5ec0},
1273*4882a593Smuzhiyun 	{5644800,  45158400,  0x46f0},
1274*4882a593Smuzhiyun 	{3072000,  24576000,  0x1ea0},
1275*4882a593Smuzhiyun 	{3072000,  49152000,  0x5ec0},
1276*4882a593Smuzhiyun 	{6144000,  49152000,  0x46f0},
1277*4882a593Smuzhiyun 	{705600,  11289600,  0x3ea0},
1278*4882a593Smuzhiyun 	{705600,  8467200,  0x3ab0},
1279*4882a593Smuzhiyun 	{24576000,  24576000,  0x02a0},
1280*4882a593Smuzhiyun 	{1411200,  11289600,  0x1690},
1281*4882a593Smuzhiyun 	{2822400,  11289600,  0x0a90},
1282*4882a593Smuzhiyun 	{1536000,  12288000,  0x1690},
1283*4882a593Smuzhiyun 	{3072000,  12288000,  0x0a90},
1284*4882a593Smuzhiyun };
1285*4882a593Smuzhiyun 
1286*4882a593Smuzhiyun static struct coeff_clk_div coeff_div[] = {
1287*4882a593Smuzhiyun 	/* sysclk is 256fs */
1288*4882a593Smuzhiyun 	{2048000,  8000 * 32,  8000, 0x1000},
1289*4882a593Smuzhiyun 	{2048000,  8000 * 64,  8000, 0x0000},
1290*4882a593Smuzhiyun 	{2822400,  11025 * 32,  11025,  0x1000},
1291*4882a593Smuzhiyun 	{2822400,  11025 * 64,  11025,  0x0000},
1292*4882a593Smuzhiyun 	{4096000,  16000 * 32,  16000,  0x1000},
1293*4882a593Smuzhiyun 	{4096000,  16000 * 64,  16000,  0x0000},
1294*4882a593Smuzhiyun 	{5644800,  22050 * 32,  22050,  0x1000},
1295*4882a593Smuzhiyun 	{5644800,  22050 * 64,  22050,  0x0000},
1296*4882a593Smuzhiyun 	{8192000,  32000 * 32,  32000,  0x1000},
1297*4882a593Smuzhiyun 	{8192000,  32000 * 64,  32000,  0x0000},
1298*4882a593Smuzhiyun 	{11289600,  44100 * 32,  44100,  0x1000},
1299*4882a593Smuzhiyun 	{11289600,  44100 * 64,  44100,  0x0000},
1300*4882a593Smuzhiyun 	{12288000,  48000 * 32,  48000,  0x1000},
1301*4882a593Smuzhiyun 	{12288000,  48000 * 64,  48000,  0x0000},
1302*4882a593Smuzhiyun 	{22579200,  88200 * 32,  88200,  0x1000},
1303*4882a593Smuzhiyun 	{22579200,  88200 * 64,  88200,  0x0000},
1304*4882a593Smuzhiyun 	{24576000,  96000 * 32,  96000,  0x1000},
1305*4882a593Smuzhiyun 	{24576000,  96000 * 64,  96000,  0x0000},
1306*4882a593Smuzhiyun 	/* sysclk is 512fs */
1307*4882a593Smuzhiyun 	{4096000,  8000 * 32,  8000, 0x3000},
1308*4882a593Smuzhiyun 	{4096000,  8000 * 64,  8000, 0x2000},
1309*4882a593Smuzhiyun 	{5644800,  11025 * 32,  11025, 0x3000},
1310*4882a593Smuzhiyun 	{5644800,  11025 * 64,  11025, 0x2000},
1311*4882a593Smuzhiyun 	{8192000,  16000 * 32,  16000, 0x3000},
1312*4882a593Smuzhiyun 	{8192000,  16000 * 64,  16000, 0x2000},
1313*4882a593Smuzhiyun 	{11289600,  22050 * 32,  22050, 0x3000},
1314*4882a593Smuzhiyun 	{11289600,  22050 * 64,  22050, 0x2000},
1315*4882a593Smuzhiyun 	{16384000,  32000 * 32,  32000, 0x3000},
1316*4882a593Smuzhiyun 	{16384000,  32000 * 64,  32000, 0x2000},
1317*4882a593Smuzhiyun 	{22579200,  44100 * 32,  44100, 0x3000},
1318*4882a593Smuzhiyun 	{22579200,  44100 * 64,  44100, 0x2000},
1319*4882a593Smuzhiyun 	{24576000,  48000 * 32,  48000, 0x3000},
1320*4882a593Smuzhiyun 	{24576000,  48000 * 64,  48000, 0x2000},
1321*4882a593Smuzhiyun 	{45158400,  88200 * 32,  88200, 0x3000},
1322*4882a593Smuzhiyun 	{45158400,  88200 * 64,  88200, 0x2000},
1323*4882a593Smuzhiyun 	{49152000,  96000 * 32,  96000, 0x3000},
1324*4882a593Smuzhiyun 	{49152000,  96000 * 64,  96000, 0x2000},
1325*4882a593Smuzhiyun 	/* sysclk is 24.576Mhz or 22.5792Mhz */
1326*4882a593Smuzhiyun 	{24576000,  8000 * 32,  8000,  0x7080},
1327*4882a593Smuzhiyun 	{24576000,  8000 * 64,  8000,  0x6080},
1328*4882a593Smuzhiyun 	{24576000,  16000 * 32,  16000,  0x5080},
1329*4882a593Smuzhiyun 	{24576000,  16000 * 64,  16000,  0x4080},
1330*4882a593Smuzhiyun 	{24576000,  24000 * 32,  24000,  0x5000},
1331*4882a593Smuzhiyun 	{24576000,  24000 * 64,  24000,  0x4000},
1332*4882a593Smuzhiyun 	{24576000,  32000 * 32,  32000,  0x3080},
1333*4882a593Smuzhiyun 	{24576000,  32000 * 64,  32000,  0x2080},
1334*4882a593Smuzhiyun 	{22579200,  11025 * 32,  11025,  0x7000},
1335*4882a593Smuzhiyun 	{22579200,  11025 * 64,  11025,  0x6000},
1336*4882a593Smuzhiyun 	{22579200,  22050 * 32,  22050,  0x5000},
1337*4882a593Smuzhiyun 	{22579200,  22050 * 64,  22050,  0x4000},
1338*4882a593Smuzhiyun };
1339*4882a593Smuzhiyun 
get_coeff(int mclk,int rate,int timesofbclk)1340*4882a593Smuzhiyun static int get_coeff(int mclk, int rate, int timesofbclk)
1341*4882a593Smuzhiyun {
1342*4882a593Smuzhiyun 	int i;
1343*4882a593Smuzhiyun 
1344*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
1345*4882a593Smuzhiyun 		if (coeff_div[i].mclk == mclk && coeff_div[i].rate == rate &&
1346*4882a593Smuzhiyun 			(coeff_div[i].bclk / coeff_div[i].rate) == timesofbclk)
1347*4882a593Smuzhiyun 			return i;
1348*4882a593Smuzhiyun 	}
1349*4882a593Smuzhiyun 	return -EINVAL;
1350*4882a593Smuzhiyun }
1351*4882a593Smuzhiyun 
rt5631_hifi_pcm_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1352*4882a593Smuzhiyun static int rt5631_hifi_pcm_params(struct snd_pcm_substream *substream,
1353*4882a593Smuzhiyun 		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1354*4882a593Smuzhiyun {
1355*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
1356*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
1357*4882a593Smuzhiyun 	int timesofbclk = 32, coeff;
1358*4882a593Smuzhiyun 	unsigned int iface = 0;
1359*4882a593Smuzhiyun 
1360*4882a593Smuzhiyun 	dev_dbg(component->dev, "enter %s\n", __func__);
1361*4882a593Smuzhiyun 
1362*4882a593Smuzhiyun 	rt5631->bclk_rate = snd_soc_params_to_bclk(params);
1363*4882a593Smuzhiyun 	if (rt5631->bclk_rate < 0) {
1364*4882a593Smuzhiyun 		dev_err(component->dev, "Fail to get BCLK rate\n");
1365*4882a593Smuzhiyun 		return rt5631->bclk_rate;
1366*4882a593Smuzhiyun 	}
1367*4882a593Smuzhiyun 	rt5631->rx_rate = params_rate(params);
1368*4882a593Smuzhiyun 
1369*4882a593Smuzhiyun 	if (rt5631->master)
1370*4882a593Smuzhiyun 		coeff = get_coeff(rt5631->sysclk, rt5631->rx_rate,
1371*4882a593Smuzhiyun 			rt5631->bclk_rate / rt5631->rx_rate);
1372*4882a593Smuzhiyun 	else
1373*4882a593Smuzhiyun 		coeff = get_coeff(rt5631->sysclk, rt5631->rx_rate,
1374*4882a593Smuzhiyun 					timesofbclk);
1375*4882a593Smuzhiyun 	if (coeff < 0) {
1376*4882a593Smuzhiyun 		dev_err(component->dev, "Fail to get coeff\n");
1377*4882a593Smuzhiyun 		return coeff;
1378*4882a593Smuzhiyun 	}
1379*4882a593Smuzhiyun 
1380*4882a593Smuzhiyun 	switch (params_width(params)) {
1381*4882a593Smuzhiyun 	case 16:
1382*4882a593Smuzhiyun 		break;
1383*4882a593Smuzhiyun 	case 20:
1384*4882a593Smuzhiyun 		iface |= RT5631_SDP_I2S_DL_20;
1385*4882a593Smuzhiyun 		break;
1386*4882a593Smuzhiyun 	case 24:
1387*4882a593Smuzhiyun 		iface |= RT5631_SDP_I2S_DL_24;
1388*4882a593Smuzhiyun 		break;
1389*4882a593Smuzhiyun 	case 8:
1390*4882a593Smuzhiyun 		iface |= RT5631_SDP_I2S_DL_8;
1391*4882a593Smuzhiyun 		break;
1392*4882a593Smuzhiyun 	default:
1393*4882a593Smuzhiyun 		return -EINVAL;
1394*4882a593Smuzhiyun 	}
1395*4882a593Smuzhiyun 
1396*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, RT5631_SDP_CTRL,
1397*4882a593Smuzhiyun 		RT5631_SDP_I2S_DL_MASK, iface);
1398*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_STEREO_AD_DA_CLK_CTRL,
1399*4882a593Smuzhiyun 					coeff_div[coeff].reg_val);
1400*4882a593Smuzhiyun 
1401*4882a593Smuzhiyun 	return 0;
1402*4882a593Smuzhiyun }
1403*4882a593Smuzhiyun 
rt5631_hifi_codec_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1404*4882a593Smuzhiyun static int rt5631_hifi_codec_set_dai_fmt(struct snd_soc_dai *codec_dai,
1405*4882a593Smuzhiyun 						unsigned int fmt)
1406*4882a593Smuzhiyun {
1407*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
1408*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
1409*4882a593Smuzhiyun 	unsigned int iface = 0;
1410*4882a593Smuzhiyun 
1411*4882a593Smuzhiyun 	dev_dbg(component->dev, "enter %s\n", __func__);
1412*4882a593Smuzhiyun 
1413*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1414*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
1415*4882a593Smuzhiyun 		rt5631->master = 1;
1416*4882a593Smuzhiyun 		break;
1417*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
1418*4882a593Smuzhiyun 		iface |= RT5631_SDP_MODE_SEL_SLAVE;
1419*4882a593Smuzhiyun 		rt5631->master = 0;
1420*4882a593Smuzhiyun 		break;
1421*4882a593Smuzhiyun 	default:
1422*4882a593Smuzhiyun 		return -EINVAL;
1423*4882a593Smuzhiyun 	}
1424*4882a593Smuzhiyun 
1425*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1426*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_I2S:
1427*4882a593Smuzhiyun 		break;
1428*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_LEFT_J:
1429*4882a593Smuzhiyun 		iface |= RT5631_SDP_I2S_DF_LEFT;
1430*4882a593Smuzhiyun 		break;
1431*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_DSP_A:
1432*4882a593Smuzhiyun 		iface |= RT5631_SDP_I2S_DF_PCM_A;
1433*4882a593Smuzhiyun 		break;
1434*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_DSP_B:
1435*4882a593Smuzhiyun 		iface  |= RT5631_SDP_I2S_DF_PCM_B;
1436*4882a593Smuzhiyun 		break;
1437*4882a593Smuzhiyun 	default:
1438*4882a593Smuzhiyun 		return -EINVAL;
1439*4882a593Smuzhiyun 	}
1440*4882a593Smuzhiyun 
1441*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1442*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_NB_NF:
1443*4882a593Smuzhiyun 		break;
1444*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_IB_NF:
1445*4882a593Smuzhiyun 		iface |= RT5631_SDP_I2S_BCLK_POL_CTRL;
1446*4882a593Smuzhiyun 		break;
1447*4882a593Smuzhiyun 	default:
1448*4882a593Smuzhiyun 		return -EINVAL;
1449*4882a593Smuzhiyun 	}
1450*4882a593Smuzhiyun 
1451*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_SDP_CTRL, iface);
1452*4882a593Smuzhiyun 
1453*4882a593Smuzhiyun 	return 0;
1454*4882a593Smuzhiyun }
1455*4882a593Smuzhiyun 
rt5631_hifi_codec_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)1456*4882a593Smuzhiyun static int rt5631_hifi_codec_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1457*4882a593Smuzhiyun 				int clk_id, unsigned int freq, int dir)
1458*4882a593Smuzhiyun {
1459*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
1460*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
1461*4882a593Smuzhiyun 
1462*4882a593Smuzhiyun 	dev_dbg(component->dev, "enter %s, syclk=%d\n", __func__, freq);
1463*4882a593Smuzhiyun 
1464*4882a593Smuzhiyun 	if ((freq >= (256 * 8000)) && (freq <= (512 * 96000))) {
1465*4882a593Smuzhiyun 		rt5631->sysclk = freq;
1466*4882a593Smuzhiyun 		return 0;
1467*4882a593Smuzhiyun 	}
1468*4882a593Smuzhiyun 
1469*4882a593Smuzhiyun 	return -EINVAL;
1470*4882a593Smuzhiyun }
1471*4882a593Smuzhiyun 
rt5631_codec_set_dai_pll(struct snd_soc_dai * codec_dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)1472*4882a593Smuzhiyun static int rt5631_codec_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1473*4882a593Smuzhiyun 		int source, unsigned int freq_in, unsigned int freq_out)
1474*4882a593Smuzhiyun {
1475*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
1476*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
1477*4882a593Smuzhiyun 	int i, ret = -EINVAL;
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	dev_dbg(component->dev, "enter %s\n", __func__);
1480*4882a593Smuzhiyun 
1481*4882a593Smuzhiyun 	if (!freq_in || !freq_out) {
1482*4882a593Smuzhiyun 		dev_dbg(component->dev, "PLL disabled\n");
1483*4882a593Smuzhiyun 
1484*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_GLOBAL_CLK_CTRL,
1485*4882a593Smuzhiyun 			RT5631_SYSCLK_SOUR_SEL_MASK,
1486*4882a593Smuzhiyun 			RT5631_SYSCLK_SOUR_SEL_MCLK);
1487*4882a593Smuzhiyun 
1488*4882a593Smuzhiyun 		return 0;
1489*4882a593Smuzhiyun 	}
1490*4882a593Smuzhiyun 
1491*4882a593Smuzhiyun 	if (rt5631->master) {
1492*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(codec_master_pll_div); i++)
1493*4882a593Smuzhiyun 			if (freq_in == codec_master_pll_div[i].pll_in &&
1494*4882a593Smuzhiyun 			freq_out == codec_master_pll_div[i].pll_out) {
1495*4882a593Smuzhiyun 				dev_info(component->dev,
1496*4882a593Smuzhiyun 					"change PLL in master mode\n");
1497*4882a593Smuzhiyun 				snd_soc_component_write(component, RT5631_PLL_CTRL,
1498*4882a593Smuzhiyun 					codec_master_pll_div[i].reg_val);
1499*4882a593Smuzhiyun 				schedule_timeout_uninterruptible(
1500*4882a593Smuzhiyun 					msecs_to_jiffies(20));
1501*4882a593Smuzhiyun 				snd_soc_component_update_bits(component,
1502*4882a593Smuzhiyun 					RT5631_GLOBAL_CLK_CTRL,
1503*4882a593Smuzhiyun 					RT5631_SYSCLK_SOUR_SEL_MASK |
1504*4882a593Smuzhiyun 					RT5631_PLLCLK_SOUR_SEL_MASK,
1505*4882a593Smuzhiyun 					RT5631_SYSCLK_SOUR_SEL_PLL |
1506*4882a593Smuzhiyun 					RT5631_PLLCLK_SOUR_SEL_MCLK);
1507*4882a593Smuzhiyun 				ret = 0;
1508*4882a593Smuzhiyun 				break;
1509*4882a593Smuzhiyun 			}
1510*4882a593Smuzhiyun 	} else {
1511*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++)
1512*4882a593Smuzhiyun 			if (freq_in == codec_slave_pll_div[i].pll_in &&
1513*4882a593Smuzhiyun 			freq_out == codec_slave_pll_div[i].pll_out) {
1514*4882a593Smuzhiyun 				dev_info(component->dev,
1515*4882a593Smuzhiyun 					"change PLL in slave mode\n");
1516*4882a593Smuzhiyun 				snd_soc_component_write(component, RT5631_PLL_CTRL,
1517*4882a593Smuzhiyun 					codec_slave_pll_div[i].reg_val);
1518*4882a593Smuzhiyun 				schedule_timeout_uninterruptible(
1519*4882a593Smuzhiyun 					msecs_to_jiffies(20));
1520*4882a593Smuzhiyun 				snd_soc_component_update_bits(component,
1521*4882a593Smuzhiyun 					RT5631_GLOBAL_CLK_CTRL,
1522*4882a593Smuzhiyun 					RT5631_SYSCLK_SOUR_SEL_MASK |
1523*4882a593Smuzhiyun 					RT5631_PLLCLK_SOUR_SEL_MASK,
1524*4882a593Smuzhiyun 					RT5631_SYSCLK_SOUR_SEL_PLL |
1525*4882a593Smuzhiyun 					RT5631_PLLCLK_SOUR_SEL_BCLK);
1526*4882a593Smuzhiyun 				ret = 0;
1527*4882a593Smuzhiyun 				break;
1528*4882a593Smuzhiyun 			}
1529*4882a593Smuzhiyun 	}
1530*4882a593Smuzhiyun 
1531*4882a593Smuzhiyun 	return ret;
1532*4882a593Smuzhiyun }
1533*4882a593Smuzhiyun 
rt5631_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1534*4882a593Smuzhiyun static int rt5631_set_bias_level(struct snd_soc_component *component,
1535*4882a593Smuzhiyun 			enum snd_soc_bias_level level)
1536*4882a593Smuzhiyun {
1537*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
1538*4882a593Smuzhiyun 
1539*4882a593Smuzhiyun 	switch (level) {
1540*4882a593Smuzhiyun 	case SND_SOC_BIAS_ON:
1541*4882a593Smuzhiyun 	case SND_SOC_BIAS_PREPARE:
1542*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD2,
1543*4882a593Smuzhiyun 			RT5631_PWR_MICBIAS1_VOL | RT5631_PWR_MICBIAS2_VOL,
1544*4882a593Smuzhiyun 			RT5631_PWR_MICBIAS1_VOL | RT5631_PWR_MICBIAS2_VOL);
1545*4882a593Smuzhiyun 		break;
1546*4882a593Smuzhiyun 
1547*4882a593Smuzhiyun 	case SND_SOC_BIAS_STANDBY:
1548*4882a593Smuzhiyun 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1549*4882a593Smuzhiyun 			snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
1550*4882a593Smuzhiyun 				RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS,
1551*4882a593Smuzhiyun 				RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS);
1552*4882a593Smuzhiyun 			msleep(80);
1553*4882a593Smuzhiyun 			snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
1554*4882a593Smuzhiyun 				RT5631_PWR_FAST_VREF_CTRL,
1555*4882a593Smuzhiyun 				RT5631_PWR_FAST_VREF_CTRL);
1556*4882a593Smuzhiyun 			regcache_cache_only(rt5631->regmap, false);
1557*4882a593Smuzhiyun 			regcache_sync(rt5631->regmap);
1558*4882a593Smuzhiyun 		}
1559*4882a593Smuzhiyun 		break;
1560*4882a593Smuzhiyun 
1561*4882a593Smuzhiyun 	case SND_SOC_BIAS_OFF:
1562*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_PWR_MANAG_ADD1, 0x0000);
1563*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_PWR_MANAG_ADD2, 0x0000);
1564*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_PWR_MANAG_ADD3, 0x0000);
1565*4882a593Smuzhiyun 		snd_soc_component_write(component, RT5631_PWR_MANAG_ADD4, 0x0000);
1566*4882a593Smuzhiyun 		break;
1567*4882a593Smuzhiyun 
1568*4882a593Smuzhiyun 	default:
1569*4882a593Smuzhiyun 		break;
1570*4882a593Smuzhiyun 	}
1571*4882a593Smuzhiyun 
1572*4882a593Smuzhiyun 	return 0;
1573*4882a593Smuzhiyun }
1574*4882a593Smuzhiyun 
rt5631_probe(struct snd_soc_component * component)1575*4882a593Smuzhiyun static int rt5631_probe(struct snd_soc_component *component)
1576*4882a593Smuzhiyun {
1577*4882a593Smuzhiyun 	struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
1578*4882a593Smuzhiyun 	unsigned int val;
1579*4882a593Smuzhiyun 
1580*4882a593Smuzhiyun 	val = rt5631_read_index(component, RT5631_ADDA_MIXER_INTL_REG3);
1581*4882a593Smuzhiyun 	if (val & 0x0002)
1582*4882a593Smuzhiyun 		rt5631->codec_version = 1;
1583*4882a593Smuzhiyun 	else
1584*4882a593Smuzhiyun 		rt5631->codec_version = 0;
1585*4882a593Smuzhiyun 
1586*4882a593Smuzhiyun 	rt5631_reset(component);
1587*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
1588*4882a593Smuzhiyun 		RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS,
1589*4882a593Smuzhiyun 		RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS);
1590*4882a593Smuzhiyun 	msleep(80);
1591*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
1592*4882a593Smuzhiyun 		RT5631_PWR_FAST_VREF_CTRL, RT5631_PWR_FAST_VREF_CTRL);
1593*4882a593Smuzhiyun 	/* enable HP zero cross */
1594*4882a593Smuzhiyun 	snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, 0x0f18);
1595*4882a593Smuzhiyun 	/* power off ClassD auto Recovery */
1596*4882a593Smuzhiyun 	if (rt5631->codec_version)
1597*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_INT_ST_IRQ_CTRL_2,
1598*4882a593Smuzhiyun 					0x2000, 0x2000);
1599*4882a593Smuzhiyun 	else
1600*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_INT_ST_IRQ_CTRL_2,
1601*4882a593Smuzhiyun 					0x2000, 0);
1602*4882a593Smuzhiyun 	/* DMIC */
1603*4882a593Smuzhiyun 	if (rt5631->dmic_used_flag) {
1604*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_GPIO_CTRL,
1605*4882a593Smuzhiyun 			RT5631_GPIO_PIN_FUN_SEL_MASK |
1606*4882a593Smuzhiyun 			RT5631_GPIO_DMIC_FUN_SEL_MASK,
1607*4882a593Smuzhiyun 			RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC |
1608*4882a593Smuzhiyun 			RT5631_GPIO_DMIC_FUN_SEL_DIMC);
1609*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, RT5631_DIG_MIC_CTRL,
1610*4882a593Smuzhiyun 			RT5631_DMIC_L_CH_LATCH_MASK |
1611*4882a593Smuzhiyun 			RT5631_DMIC_R_CH_LATCH_MASK,
1612*4882a593Smuzhiyun 			RT5631_DMIC_L_CH_LATCH_FALLING |
1613*4882a593Smuzhiyun 			RT5631_DMIC_R_CH_LATCH_RISING);
1614*4882a593Smuzhiyun 	}
1615*4882a593Smuzhiyun 
1616*4882a593Smuzhiyun 	snd_soc_component_init_bias_level(component, SND_SOC_BIAS_STANDBY);
1617*4882a593Smuzhiyun 
1618*4882a593Smuzhiyun 	return 0;
1619*4882a593Smuzhiyun }
1620*4882a593Smuzhiyun 
1621*4882a593Smuzhiyun #define RT5631_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1622*4882a593Smuzhiyun #define RT5631_FORMAT	(SNDRV_PCM_FMTBIT_S16_LE | \
1623*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S20_3LE | \
1624*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S24_LE | \
1625*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S8)
1626*4882a593Smuzhiyun 
1627*4882a593Smuzhiyun static const struct snd_soc_dai_ops rt5631_ops = {
1628*4882a593Smuzhiyun 	.hw_params = rt5631_hifi_pcm_params,
1629*4882a593Smuzhiyun 	.set_fmt = rt5631_hifi_codec_set_dai_fmt,
1630*4882a593Smuzhiyun 	.set_sysclk = rt5631_hifi_codec_set_dai_sysclk,
1631*4882a593Smuzhiyun 	.set_pll = rt5631_codec_set_dai_pll,
1632*4882a593Smuzhiyun };
1633*4882a593Smuzhiyun 
1634*4882a593Smuzhiyun static struct snd_soc_dai_driver rt5631_dai[] = {
1635*4882a593Smuzhiyun 	{
1636*4882a593Smuzhiyun 		.name = "rt5631-hifi",
1637*4882a593Smuzhiyun 		.id = 1,
1638*4882a593Smuzhiyun 		.playback = {
1639*4882a593Smuzhiyun 			.stream_name = "HIFI Playback",
1640*4882a593Smuzhiyun 			.channels_min = 1,
1641*4882a593Smuzhiyun 			.channels_max = 2,
1642*4882a593Smuzhiyun 			.rates = RT5631_STEREO_RATES,
1643*4882a593Smuzhiyun 			.formats = RT5631_FORMAT,
1644*4882a593Smuzhiyun 		},
1645*4882a593Smuzhiyun 		.capture = {
1646*4882a593Smuzhiyun 			.stream_name = "HIFI Capture",
1647*4882a593Smuzhiyun 			.channels_min = 1,
1648*4882a593Smuzhiyun 			.channels_max = 2,
1649*4882a593Smuzhiyun 			.rates = RT5631_STEREO_RATES,
1650*4882a593Smuzhiyun 			.formats = RT5631_FORMAT,
1651*4882a593Smuzhiyun 		},
1652*4882a593Smuzhiyun 		.ops = &rt5631_ops,
1653*4882a593Smuzhiyun 	},
1654*4882a593Smuzhiyun };
1655*4882a593Smuzhiyun 
1656*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_rt5631 = {
1657*4882a593Smuzhiyun 	.probe			= rt5631_probe,
1658*4882a593Smuzhiyun 	.set_bias_level		= rt5631_set_bias_level,
1659*4882a593Smuzhiyun 	.controls		= rt5631_snd_controls,
1660*4882a593Smuzhiyun 	.num_controls		= ARRAY_SIZE(rt5631_snd_controls),
1661*4882a593Smuzhiyun 	.dapm_widgets		= rt5631_dapm_widgets,
1662*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(rt5631_dapm_widgets),
1663*4882a593Smuzhiyun 	.dapm_routes		= rt5631_dapm_routes,
1664*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(rt5631_dapm_routes),
1665*4882a593Smuzhiyun 	.suspend_bias_off	= 1,
1666*4882a593Smuzhiyun 	.idle_bias_on		= 1,
1667*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
1668*4882a593Smuzhiyun 	.endianness		= 1,
1669*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
1670*4882a593Smuzhiyun };
1671*4882a593Smuzhiyun 
1672*4882a593Smuzhiyun static const struct i2c_device_id rt5631_i2c_id[] = {
1673*4882a593Smuzhiyun 	{ "rt5631", 0 },
1674*4882a593Smuzhiyun 	{ "alc5631", 0 },
1675*4882a593Smuzhiyun 	{ }
1676*4882a593Smuzhiyun };
1677*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, rt5631_i2c_id);
1678*4882a593Smuzhiyun 
1679*4882a593Smuzhiyun #ifdef CONFIG_OF
1680*4882a593Smuzhiyun static const struct of_device_id rt5631_i2c_dt_ids[] = {
1681*4882a593Smuzhiyun 	{ .compatible = "realtek,rt5631"},
1682*4882a593Smuzhiyun 	{ .compatible = "realtek,alc5631"},
1683*4882a593Smuzhiyun 	{ }
1684*4882a593Smuzhiyun };
1685*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rt5631_i2c_dt_ids);
1686*4882a593Smuzhiyun #endif
1687*4882a593Smuzhiyun 
1688*4882a593Smuzhiyun static const struct regmap_config rt5631_regmap_config = {
1689*4882a593Smuzhiyun 	.reg_bits = 8,
1690*4882a593Smuzhiyun 	.val_bits = 16,
1691*4882a593Smuzhiyun 
1692*4882a593Smuzhiyun 	.readable_reg = rt5631_readable_register,
1693*4882a593Smuzhiyun 	.volatile_reg = rt5631_volatile_register,
1694*4882a593Smuzhiyun 	.max_register = RT5631_VENDOR_ID2,
1695*4882a593Smuzhiyun 	.reg_defaults = rt5631_reg,
1696*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(rt5631_reg),
1697*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
1698*4882a593Smuzhiyun 	.use_single_read = true,
1699*4882a593Smuzhiyun 	.use_single_write = true,
1700*4882a593Smuzhiyun };
1701*4882a593Smuzhiyun 
rt5631_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1702*4882a593Smuzhiyun static int rt5631_i2c_probe(struct i2c_client *i2c,
1703*4882a593Smuzhiyun 		    const struct i2c_device_id *id)
1704*4882a593Smuzhiyun {
1705*4882a593Smuzhiyun 	struct rt5631_priv *rt5631;
1706*4882a593Smuzhiyun 	int ret;
1707*4882a593Smuzhiyun 
1708*4882a593Smuzhiyun 	rt5631 = devm_kzalloc(&i2c->dev, sizeof(struct rt5631_priv),
1709*4882a593Smuzhiyun 			      GFP_KERNEL);
1710*4882a593Smuzhiyun 	if (NULL == rt5631)
1711*4882a593Smuzhiyun 		return -ENOMEM;
1712*4882a593Smuzhiyun 
1713*4882a593Smuzhiyun 	i2c_set_clientdata(i2c, rt5631);
1714*4882a593Smuzhiyun 
1715*4882a593Smuzhiyun 	rt5631->regmap = devm_regmap_init_i2c(i2c, &rt5631_regmap_config);
1716*4882a593Smuzhiyun 	if (IS_ERR(rt5631->regmap))
1717*4882a593Smuzhiyun 		return PTR_ERR(rt5631->regmap);
1718*4882a593Smuzhiyun 
1719*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(&i2c->dev,
1720*4882a593Smuzhiyun 			&soc_component_dev_rt5631,
1721*4882a593Smuzhiyun 			rt5631_dai, ARRAY_SIZE(rt5631_dai));
1722*4882a593Smuzhiyun 	return ret;
1723*4882a593Smuzhiyun }
1724*4882a593Smuzhiyun 
rt5631_i2c_remove(struct i2c_client * client)1725*4882a593Smuzhiyun static int rt5631_i2c_remove(struct i2c_client *client)
1726*4882a593Smuzhiyun {
1727*4882a593Smuzhiyun 	return 0;
1728*4882a593Smuzhiyun }
1729*4882a593Smuzhiyun 
1730*4882a593Smuzhiyun static struct i2c_driver rt5631_i2c_driver = {
1731*4882a593Smuzhiyun 	.driver = {
1732*4882a593Smuzhiyun 		.name = "rt5631",
1733*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(rt5631_i2c_dt_ids),
1734*4882a593Smuzhiyun 	},
1735*4882a593Smuzhiyun 	.probe = rt5631_i2c_probe,
1736*4882a593Smuzhiyun 	.remove   = rt5631_i2c_remove,
1737*4882a593Smuzhiyun 	.id_table = rt5631_i2c_id,
1738*4882a593Smuzhiyun };
1739*4882a593Smuzhiyun 
1740*4882a593Smuzhiyun module_i2c_driver(rt5631_i2c_driver);
1741*4882a593Smuzhiyun 
1742*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC RT5631 driver");
1743*4882a593Smuzhiyun MODULE_AUTHOR("flove <flove@realtek.com>");
1744*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1745