1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * rt5514-spi.h -- RT5514 driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2015 Realtek Semiconductor Corp. 6*4882a593Smuzhiyun * Author: Oder Chiou <oder_chiou@realtek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __RT5514_SPI_H__ 10*4882a593Smuzhiyun #define __RT5514_SPI_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /** 13*4882a593Smuzhiyun * RT5514_SPI_BUF_LEN is the buffer size of SPI master controller. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define RT5514_SPI_BUF_LEN 240 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define RT5514_BUFFER_VOICE_BASE 0x18000200 18*4882a593Smuzhiyun #define RT5514_BUFFER_VOICE_LIMIT 0x18000204 19*4882a593Smuzhiyun #define RT5514_BUFFER_VOICE_WP 0x1800020c 20*4882a593Smuzhiyun #define RT5514_IRQ_CTRL 0x18002094 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define RT5514_IRQ_STATUS_BIT (0x1 << 5) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* SPI Command */ 25*4882a593Smuzhiyun enum { 26*4882a593Smuzhiyun RT5514_SPI_CMD_16_READ = 0, 27*4882a593Smuzhiyun RT5514_SPI_CMD_16_WRITE, 28*4882a593Smuzhiyun RT5514_SPI_CMD_32_READ, 29*4882a593Smuzhiyun RT5514_SPI_CMD_32_WRITE, 30*4882a593Smuzhiyun RT5514_SPI_CMD_BURST_READ, 31*4882a593Smuzhiyun RT5514_SPI_CMD_BURST_WRITE, 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun int rt5514_spi_burst_read(unsigned int addr, u8 *rxbuf, size_t len); 35*4882a593Smuzhiyun int rt5514_spi_burst_write(u32 addr, const u8 *txbuf, size_t len); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif /* __RT5514_SPI_H__ */ 38