xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/rt5514-spi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * rt5514-spi.c  --  RT5514 SPI driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2015 Realtek Semiconductor Corp.
6*4882a593Smuzhiyun  * Author: Oder Chiou <oder_chiou@realtek.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/input.h>
11*4882a593Smuzhiyun #include <linux/spi/spi.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/irq.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/gpio.h>
19*4882a593Smuzhiyun #include <linux/sched.h>
20*4882a593Smuzhiyun #include <linux/uaccess.h>
21*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
22*4882a593Smuzhiyun #include <linux/pm_qos.h>
23*4882a593Smuzhiyun #include <linux/sysfs.h>
24*4882a593Smuzhiyun #include <linux/clk.h>
25*4882a593Smuzhiyun #include <sound/core.h>
26*4882a593Smuzhiyun #include <sound/pcm.h>
27*4882a593Smuzhiyun #include <sound/pcm_params.h>
28*4882a593Smuzhiyun #include <sound/soc.h>
29*4882a593Smuzhiyun #include <sound/soc-dapm.h>
30*4882a593Smuzhiyun #include <sound/initval.h>
31*4882a593Smuzhiyun #include <sound/tlv.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include "rt5514-spi.h"
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define DRV_NAME "rt5514-spi"
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun static struct spi_device *rt5514_spi;
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun struct rt5514_dsp {
40*4882a593Smuzhiyun 	struct device *dev;
41*4882a593Smuzhiyun 	struct delayed_work copy_work;
42*4882a593Smuzhiyun 	struct mutex dma_lock;
43*4882a593Smuzhiyun 	struct snd_pcm_substream *substream;
44*4882a593Smuzhiyun 	unsigned int buf_base, buf_limit, buf_rp;
45*4882a593Smuzhiyun 	size_t buf_size, get_size, dma_offset;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun static const struct snd_pcm_hardware rt5514_spi_pcm_hardware = {
49*4882a593Smuzhiyun 	.info			= SNDRV_PCM_INFO_MMAP |
50*4882a593Smuzhiyun 				  SNDRV_PCM_INFO_MMAP_VALID |
51*4882a593Smuzhiyun 				  SNDRV_PCM_INFO_INTERLEAVED,
52*4882a593Smuzhiyun 	.formats		= SNDRV_PCM_FMTBIT_S16_LE,
53*4882a593Smuzhiyun 	.period_bytes_min	= PAGE_SIZE,
54*4882a593Smuzhiyun 	.period_bytes_max	= 0x20000 / 8,
55*4882a593Smuzhiyun 	.periods_min		= 8,
56*4882a593Smuzhiyun 	.periods_max		= 8,
57*4882a593Smuzhiyun 	.channels_min		= 1,
58*4882a593Smuzhiyun 	.channels_max		= 1,
59*4882a593Smuzhiyun 	.buffer_bytes_max	= 0x20000,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun static struct snd_soc_dai_driver rt5514_spi_dai = {
63*4882a593Smuzhiyun 	.name = "rt5514-dsp-cpu-dai",
64*4882a593Smuzhiyun 	.id = 0,
65*4882a593Smuzhiyun 	.capture = {
66*4882a593Smuzhiyun 		.stream_name = "DSP Capture",
67*4882a593Smuzhiyun 		.channels_min = 1,
68*4882a593Smuzhiyun 		.channels_max = 1,
69*4882a593Smuzhiyun 		.rates = SNDRV_PCM_RATE_16000,
70*4882a593Smuzhiyun 		.formats = SNDRV_PCM_FMTBIT_S16_LE,
71*4882a593Smuzhiyun 	},
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
rt5514_spi_copy_work(struct work_struct * work)74*4882a593Smuzhiyun static void rt5514_spi_copy_work(struct work_struct *work)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	struct rt5514_dsp *rt5514_dsp =
77*4882a593Smuzhiyun 		container_of(work, struct rt5514_dsp, copy_work.work);
78*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime;
79*4882a593Smuzhiyun 	size_t period_bytes, truncated_bytes = 0;
80*4882a593Smuzhiyun 	unsigned int cur_wp, remain_data;
81*4882a593Smuzhiyun 	u8 buf[8];
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	mutex_lock(&rt5514_dsp->dma_lock);
84*4882a593Smuzhiyun 	if (!rt5514_dsp->substream) {
85*4882a593Smuzhiyun 		dev_err(rt5514_dsp->dev, "No pcm substream\n");
86*4882a593Smuzhiyun 		goto done;
87*4882a593Smuzhiyun 	}
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	runtime = rt5514_dsp->substream->runtime;
90*4882a593Smuzhiyun 	period_bytes = snd_pcm_lib_period_bytes(rt5514_dsp->substream);
91*4882a593Smuzhiyun 	if (!period_bytes) {
92*4882a593Smuzhiyun 		schedule_delayed_work(&rt5514_dsp->copy_work, 5);
93*4882a593Smuzhiyun 		goto done;
94*4882a593Smuzhiyun 	}
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	if (rt5514_dsp->buf_size % period_bytes)
97*4882a593Smuzhiyun 		rt5514_dsp->buf_size = (rt5514_dsp->buf_size / period_bytes) *
98*4882a593Smuzhiyun 			period_bytes;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	if (rt5514_dsp->get_size >= rt5514_dsp->buf_size) {
101*4882a593Smuzhiyun 		rt5514_spi_burst_read(RT5514_BUFFER_VOICE_WP, (u8 *)&buf,
102*4882a593Smuzhiyun 			sizeof(buf));
103*4882a593Smuzhiyun 		cur_wp = buf[0] | buf[1] << 8 | buf[2] << 16 |
104*4882a593Smuzhiyun 					buf[3] << 24;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 		if (cur_wp >= rt5514_dsp->buf_rp)
107*4882a593Smuzhiyun 			remain_data = (cur_wp - rt5514_dsp->buf_rp);
108*4882a593Smuzhiyun 		else
109*4882a593Smuzhiyun 			remain_data =
110*4882a593Smuzhiyun 				(rt5514_dsp->buf_limit - rt5514_dsp->buf_rp) +
111*4882a593Smuzhiyun 				(cur_wp - rt5514_dsp->buf_base);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 		if (remain_data < period_bytes) {
114*4882a593Smuzhiyun 			schedule_delayed_work(&rt5514_dsp->copy_work, 5);
115*4882a593Smuzhiyun 			goto done;
116*4882a593Smuzhiyun 		}
117*4882a593Smuzhiyun 	}
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	if (rt5514_dsp->buf_rp + period_bytes <= rt5514_dsp->buf_limit) {
120*4882a593Smuzhiyun 		rt5514_spi_burst_read(rt5514_dsp->buf_rp,
121*4882a593Smuzhiyun 			runtime->dma_area + rt5514_dsp->dma_offset,
122*4882a593Smuzhiyun 			period_bytes);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 		if (rt5514_dsp->buf_rp + period_bytes == rt5514_dsp->buf_limit)
125*4882a593Smuzhiyun 			rt5514_dsp->buf_rp = rt5514_dsp->buf_base;
126*4882a593Smuzhiyun 		else
127*4882a593Smuzhiyun 			rt5514_dsp->buf_rp += period_bytes;
128*4882a593Smuzhiyun 	} else {
129*4882a593Smuzhiyun 		truncated_bytes = rt5514_dsp->buf_limit - rt5514_dsp->buf_rp;
130*4882a593Smuzhiyun 		rt5514_spi_burst_read(rt5514_dsp->buf_rp,
131*4882a593Smuzhiyun 			runtime->dma_area + rt5514_dsp->dma_offset,
132*4882a593Smuzhiyun 			truncated_bytes);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 		rt5514_spi_burst_read(rt5514_dsp->buf_base,
135*4882a593Smuzhiyun 			runtime->dma_area + rt5514_dsp->dma_offset +
136*4882a593Smuzhiyun 			truncated_bytes, period_bytes - truncated_bytes);
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 		rt5514_dsp->buf_rp = rt5514_dsp->buf_base + period_bytes -
139*4882a593Smuzhiyun 			truncated_bytes;
140*4882a593Smuzhiyun 	}
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	rt5514_dsp->get_size += period_bytes;
143*4882a593Smuzhiyun 	rt5514_dsp->dma_offset += period_bytes;
144*4882a593Smuzhiyun 	if (rt5514_dsp->dma_offset >= runtime->dma_bytes)
145*4882a593Smuzhiyun 		rt5514_dsp->dma_offset = 0;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	snd_pcm_period_elapsed(rt5514_dsp->substream);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	schedule_delayed_work(&rt5514_dsp->copy_work, 5);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun done:
152*4882a593Smuzhiyun 	mutex_unlock(&rt5514_dsp->dma_lock);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
rt5514_schedule_copy(struct rt5514_dsp * rt5514_dsp)155*4882a593Smuzhiyun static void rt5514_schedule_copy(struct rt5514_dsp *rt5514_dsp)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	u8 buf[8];
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	if (!rt5514_dsp->substream)
160*4882a593Smuzhiyun 		return;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	rt5514_dsp->get_size = 0;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/**
165*4882a593Smuzhiyun 	 * The address area x1800XXXX is the register address, and it cannot
166*4882a593Smuzhiyun 	 * support spi burst read perfectly. So we use the spi burst read
167*4882a593Smuzhiyun 	 * individually to make sure the data correctly.
168*4882a593Smuzhiyun 	 */
169*4882a593Smuzhiyun 	rt5514_spi_burst_read(RT5514_BUFFER_VOICE_BASE, (u8 *)&buf,
170*4882a593Smuzhiyun 		sizeof(buf));
171*4882a593Smuzhiyun 	rt5514_dsp->buf_base = buf[0] | buf[1] << 8 | buf[2] << 16 |
172*4882a593Smuzhiyun 				buf[3] << 24;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	rt5514_spi_burst_read(RT5514_BUFFER_VOICE_LIMIT, (u8 *)&buf,
175*4882a593Smuzhiyun 		sizeof(buf));
176*4882a593Smuzhiyun 	rt5514_dsp->buf_limit = buf[0] | buf[1] << 8 | buf[2] << 16 |
177*4882a593Smuzhiyun 				buf[3] << 24;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	rt5514_spi_burst_read(RT5514_BUFFER_VOICE_WP, (u8 *)&buf,
180*4882a593Smuzhiyun 		sizeof(buf));
181*4882a593Smuzhiyun 	rt5514_dsp->buf_rp = buf[0] | buf[1] << 8 | buf[2] << 16 |
182*4882a593Smuzhiyun 				buf[3] << 24;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	if (rt5514_dsp->buf_rp % 8)
185*4882a593Smuzhiyun 		rt5514_dsp->buf_rp = (rt5514_dsp->buf_rp / 8) * 8;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	rt5514_dsp->buf_size = rt5514_dsp->buf_limit - rt5514_dsp->buf_base;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	if (rt5514_dsp->buf_base && rt5514_dsp->buf_limit &&
190*4882a593Smuzhiyun 		rt5514_dsp->buf_rp && rt5514_dsp->buf_size)
191*4882a593Smuzhiyun 		schedule_delayed_work(&rt5514_dsp->copy_work, 0);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
rt5514_spi_irq(int irq,void * data)194*4882a593Smuzhiyun static irqreturn_t rt5514_spi_irq(int irq, void *data)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun 	struct rt5514_dsp *rt5514_dsp = data;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	rt5514_schedule_copy(rt5514_dsp);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	return IRQ_HANDLED;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun /* PCM for streaming audio from the DSP buffer */
rt5514_spi_pcm_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)204*4882a593Smuzhiyun static int rt5514_spi_pcm_open(struct snd_soc_component *component,
205*4882a593Smuzhiyun 			       struct snd_pcm_substream *substream)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	snd_soc_set_runtime_hwparams(substream, &rt5514_spi_pcm_hardware);
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	return 0;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun 
rt5514_spi_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)212*4882a593Smuzhiyun static int rt5514_spi_hw_params(struct snd_soc_component *component,
213*4882a593Smuzhiyun 				struct snd_pcm_substream *substream,
214*4882a593Smuzhiyun 				struct snd_pcm_hw_params *hw_params)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun 	struct rt5514_dsp *rt5514_dsp =
217*4882a593Smuzhiyun 		snd_soc_component_get_drvdata(component);
218*4882a593Smuzhiyun 	u8 buf[8];
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	mutex_lock(&rt5514_dsp->dma_lock);
221*4882a593Smuzhiyun 	rt5514_dsp->substream = substream;
222*4882a593Smuzhiyun 	rt5514_dsp->dma_offset = 0;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	/* Read IRQ status and schedule copy accordingly. */
225*4882a593Smuzhiyun 	rt5514_spi_burst_read(RT5514_IRQ_CTRL, (u8 *)&buf, sizeof(buf));
226*4882a593Smuzhiyun 	if (buf[0] & RT5514_IRQ_STATUS_BIT)
227*4882a593Smuzhiyun 		rt5514_schedule_copy(rt5514_dsp);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	mutex_unlock(&rt5514_dsp->dma_lock);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	return 0;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun 
rt5514_spi_hw_free(struct snd_soc_component * component,struct snd_pcm_substream * substream)234*4882a593Smuzhiyun static int rt5514_spi_hw_free(struct snd_soc_component *component,
235*4882a593Smuzhiyun 			      struct snd_pcm_substream *substream)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun 	struct rt5514_dsp *rt5514_dsp =
238*4882a593Smuzhiyun 		snd_soc_component_get_drvdata(component);
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	mutex_lock(&rt5514_dsp->dma_lock);
241*4882a593Smuzhiyun 	rt5514_dsp->substream = NULL;
242*4882a593Smuzhiyun 	mutex_unlock(&rt5514_dsp->dma_lock);
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	cancel_delayed_work_sync(&rt5514_dsp->copy_work);
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	return 0;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun 
rt5514_spi_pcm_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)249*4882a593Smuzhiyun static snd_pcm_uframes_t rt5514_spi_pcm_pointer(
250*4882a593Smuzhiyun 		struct snd_soc_component *component,
251*4882a593Smuzhiyun 		struct snd_pcm_substream *substream)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
254*4882a593Smuzhiyun 	struct rt5514_dsp *rt5514_dsp =
255*4882a593Smuzhiyun 		snd_soc_component_get_drvdata(component);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	return bytes_to_frames(runtime, rt5514_dsp->dma_offset);
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 
rt5514_spi_pcm_probe(struct snd_soc_component * component)261*4882a593Smuzhiyun static int rt5514_spi_pcm_probe(struct snd_soc_component *component)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun 	struct rt5514_dsp *rt5514_dsp;
264*4882a593Smuzhiyun 	int ret;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	rt5514_dsp = devm_kzalloc(component->dev, sizeof(*rt5514_dsp),
267*4882a593Smuzhiyun 			GFP_KERNEL);
268*4882a593Smuzhiyun 	if (!rt5514_dsp)
269*4882a593Smuzhiyun 		return -ENOMEM;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	rt5514_dsp->dev = &rt5514_spi->dev;
272*4882a593Smuzhiyun 	mutex_init(&rt5514_dsp->dma_lock);
273*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&rt5514_dsp->copy_work, rt5514_spi_copy_work);
274*4882a593Smuzhiyun 	snd_soc_component_set_drvdata(component, rt5514_dsp);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	if (rt5514_spi->irq) {
277*4882a593Smuzhiyun 		ret = devm_request_threaded_irq(&rt5514_spi->dev,
278*4882a593Smuzhiyun 			rt5514_spi->irq, NULL, rt5514_spi_irq,
279*4882a593Smuzhiyun 			IRQF_TRIGGER_RISING | IRQF_ONESHOT, "rt5514-spi",
280*4882a593Smuzhiyun 			rt5514_dsp);
281*4882a593Smuzhiyun 		if (ret)
282*4882a593Smuzhiyun 			dev_err(&rt5514_spi->dev,
283*4882a593Smuzhiyun 				"%s Failed to reguest IRQ: %d\n", __func__,
284*4882a593Smuzhiyun 				ret);
285*4882a593Smuzhiyun 		else
286*4882a593Smuzhiyun 			device_init_wakeup(rt5514_dsp->dev, true);
287*4882a593Smuzhiyun 	}
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	return 0;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun 
rt5514_spi_pcm_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)292*4882a593Smuzhiyun static int rt5514_spi_pcm_new(struct snd_soc_component *component,
293*4882a593Smuzhiyun 			      struct snd_soc_pcm_runtime *rtd)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun 	snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_VMALLOC,
296*4882a593Smuzhiyun 				       NULL, 0, 0);
297*4882a593Smuzhiyun 	return 0;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun static const struct snd_soc_component_driver rt5514_spi_component = {
301*4882a593Smuzhiyun 	.name		= DRV_NAME,
302*4882a593Smuzhiyun 	.probe		= rt5514_spi_pcm_probe,
303*4882a593Smuzhiyun 	.open		= rt5514_spi_pcm_open,
304*4882a593Smuzhiyun 	.hw_params	= rt5514_spi_hw_params,
305*4882a593Smuzhiyun 	.hw_free	= rt5514_spi_hw_free,
306*4882a593Smuzhiyun 	.pointer	= rt5514_spi_pcm_pointer,
307*4882a593Smuzhiyun 	.pcm_construct	= rt5514_spi_pcm_new,
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun /**
311*4882a593Smuzhiyun  * rt5514_spi_burst_read - Read data from SPI by rt5514 address.
312*4882a593Smuzhiyun  * @addr: Start address.
313*4882a593Smuzhiyun  * @rxbuf: Data Buffer for reading.
314*4882a593Smuzhiyun  * @len: Data length, it must be a multiple of 8.
315*4882a593Smuzhiyun  *
316*4882a593Smuzhiyun  *
317*4882a593Smuzhiyun  * Returns true for success.
318*4882a593Smuzhiyun  */
rt5514_spi_burst_read(unsigned int addr,u8 * rxbuf,size_t len)319*4882a593Smuzhiyun int rt5514_spi_burst_read(unsigned int addr, u8 *rxbuf, size_t len)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun 	u8 spi_cmd = RT5514_SPI_CMD_BURST_READ;
322*4882a593Smuzhiyun 	int status;
323*4882a593Smuzhiyun 	u8 write_buf[8];
324*4882a593Smuzhiyun 	unsigned int i, end, offset = 0;
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	struct spi_message message;
327*4882a593Smuzhiyun 	struct spi_transfer x[3];
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	while (offset < len) {
330*4882a593Smuzhiyun 		if (offset + RT5514_SPI_BUF_LEN <= len)
331*4882a593Smuzhiyun 			end = RT5514_SPI_BUF_LEN;
332*4882a593Smuzhiyun 		else
333*4882a593Smuzhiyun 			end = len % RT5514_SPI_BUF_LEN;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 		write_buf[0] = spi_cmd;
336*4882a593Smuzhiyun 		write_buf[1] = ((addr + offset) & 0xff000000) >> 24;
337*4882a593Smuzhiyun 		write_buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
338*4882a593Smuzhiyun 		write_buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
339*4882a593Smuzhiyun 		write_buf[4] = ((addr + offset) & 0x000000ff) >> 0;
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 		spi_message_init(&message);
342*4882a593Smuzhiyun 		memset(x, 0, sizeof(x));
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 		x[0].len = 5;
345*4882a593Smuzhiyun 		x[0].tx_buf = write_buf;
346*4882a593Smuzhiyun 		spi_message_add_tail(&x[0], &message);
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 		x[1].len = 4;
349*4882a593Smuzhiyun 		x[1].tx_buf = write_buf;
350*4882a593Smuzhiyun 		spi_message_add_tail(&x[1], &message);
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 		x[2].len = end;
353*4882a593Smuzhiyun 		x[2].rx_buf = rxbuf + offset;
354*4882a593Smuzhiyun 		spi_message_add_tail(&x[2], &message);
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 		status = spi_sync(rt5514_spi, &message);
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 		if (status)
359*4882a593Smuzhiyun 			return false;
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 		offset += RT5514_SPI_BUF_LEN;
362*4882a593Smuzhiyun 	}
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	for (i = 0; i < len; i += 8) {
365*4882a593Smuzhiyun 		write_buf[0] = rxbuf[i + 0];
366*4882a593Smuzhiyun 		write_buf[1] = rxbuf[i + 1];
367*4882a593Smuzhiyun 		write_buf[2] = rxbuf[i + 2];
368*4882a593Smuzhiyun 		write_buf[3] = rxbuf[i + 3];
369*4882a593Smuzhiyun 		write_buf[4] = rxbuf[i + 4];
370*4882a593Smuzhiyun 		write_buf[5] = rxbuf[i + 5];
371*4882a593Smuzhiyun 		write_buf[6] = rxbuf[i + 6];
372*4882a593Smuzhiyun 		write_buf[7] = rxbuf[i + 7];
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 		rxbuf[i + 0] = write_buf[7];
375*4882a593Smuzhiyun 		rxbuf[i + 1] = write_buf[6];
376*4882a593Smuzhiyun 		rxbuf[i + 2] = write_buf[5];
377*4882a593Smuzhiyun 		rxbuf[i + 3] = write_buf[4];
378*4882a593Smuzhiyun 		rxbuf[i + 4] = write_buf[3];
379*4882a593Smuzhiyun 		rxbuf[i + 5] = write_buf[2];
380*4882a593Smuzhiyun 		rxbuf[i + 6] = write_buf[1];
381*4882a593Smuzhiyun 		rxbuf[i + 7] = write_buf[0];
382*4882a593Smuzhiyun 	}
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	return true;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt5514_spi_burst_read);
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun /**
389*4882a593Smuzhiyun  * rt5514_spi_burst_write - Write data to SPI by rt5514 address.
390*4882a593Smuzhiyun  * @addr: Start address.
391*4882a593Smuzhiyun  * @txbuf: Data Buffer for writng.
392*4882a593Smuzhiyun  * @len: Data length, it must be a multiple of 8.
393*4882a593Smuzhiyun  *
394*4882a593Smuzhiyun  *
395*4882a593Smuzhiyun  * Returns true for success.
396*4882a593Smuzhiyun  */
rt5514_spi_burst_write(u32 addr,const u8 * txbuf,size_t len)397*4882a593Smuzhiyun int rt5514_spi_burst_write(u32 addr, const u8 *txbuf, size_t len)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun 	u8 spi_cmd = RT5514_SPI_CMD_BURST_WRITE;
400*4882a593Smuzhiyun 	u8 *write_buf;
401*4882a593Smuzhiyun 	unsigned int i, end, offset = 0;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	write_buf = kmalloc(RT5514_SPI_BUF_LEN + 6, GFP_KERNEL);
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	if (write_buf == NULL)
406*4882a593Smuzhiyun 		return -ENOMEM;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	while (offset < len) {
409*4882a593Smuzhiyun 		if (offset + RT5514_SPI_BUF_LEN <= len)
410*4882a593Smuzhiyun 			end = RT5514_SPI_BUF_LEN;
411*4882a593Smuzhiyun 		else
412*4882a593Smuzhiyun 			end = len % RT5514_SPI_BUF_LEN;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 		write_buf[0] = spi_cmd;
415*4882a593Smuzhiyun 		write_buf[1] = ((addr + offset) & 0xff000000) >> 24;
416*4882a593Smuzhiyun 		write_buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
417*4882a593Smuzhiyun 		write_buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
418*4882a593Smuzhiyun 		write_buf[4] = ((addr + offset) & 0x000000ff) >> 0;
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 		for (i = 0; i < end; i += 8) {
421*4882a593Smuzhiyun 			write_buf[i + 12] = txbuf[offset + i + 0];
422*4882a593Smuzhiyun 			write_buf[i + 11] = txbuf[offset + i + 1];
423*4882a593Smuzhiyun 			write_buf[i + 10] = txbuf[offset + i + 2];
424*4882a593Smuzhiyun 			write_buf[i +  9] = txbuf[offset + i + 3];
425*4882a593Smuzhiyun 			write_buf[i +  8] = txbuf[offset + i + 4];
426*4882a593Smuzhiyun 			write_buf[i +  7] = txbuf[offset + i + 5];
427*4882a593Smuzhiyun 			write_buf[i +  6] = txbuf[offset + i + 6];
428*4882a593Smuzhiyun 			write_buf[i +  5] = txbuf[offset + i + 7];
429*4882a593Smuzhiyun 		}
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 		write_buf[end + 5] = spi_cmd;
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 		spi_write(rt5514_spi, write_buf, end + 6);
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 		offset += RT5514_SPI_BUF_LEN;
436*4882a593Smuzhiyun 	}
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	kfree(write_buf);
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 	return 0;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt5514_spi_burst_write);
443*4882a593Smuzhiyun 
rt5514_spi_probe(struct spi_device * spi)444*4882a593Smuzhiyun static int rt5514_spi_probe(struct spi_device *spi)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun 	int ret;
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	rt5514_spi = spi;
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(&spi->dev,
451*4882a593Smuzhiyun 					      &rt5514_spi_component,
452*4882a593Smuzhiyun 					      &rt5514_spi_dai, 1);
453*4882a593Smuzhiyun 	if (ret < 0) {
454*4882a593Smuzhiyun 		dev_err(&spi->dev, "Failed to register component.\n");
455*4882a593Smuzhiyun 		return ret;
456*4882a593Smuzhiyun 	}
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	return 0;
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun 
rt5514_suspend(struct device * dev)461*4882a593Smuzhiyun static int __maybe_unused rt5514_suspend(struct device *dev)
462*4882a593Smuzhiyun {
463*4882a593Smuzhiyun 	int irq = to_spi_device(dev)->irq;
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	if (device_may_wakeup(dev))
466*4882a593Smuzhiyun 		enable_irq_wake(irq);
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	return 0;
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun 
rt5514_resume(struct device * dev)471*4882a593Smuzhiyun static int __maybe_unused rt5514_resume(struct device *dev)
472*4882a593Smuzhiyun {
473*4882a593Smuzhiyun 	struct rt5514_dsp *rt5514_dsp = dev_get_drvdata(dev);
474*4882a593Smuzhiyun 	int irq = to_spi_device(dev)->irq;
475*4882a593Smuzhiyun 	u8 buf[8];
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	if (device_may_wakeup(dev))
478*4882a593Smuzhiyun 		disable_irq_wake(irq);
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	if (rt5514_dsp) {
481*4882a593Smuzhiyun 		if (rt5514_dsp->substream) {
482*4882a593Smuzhiyun 			rt5514_spi_burst_read(RT5514_IRQ_CTRL, (u8 *)&buf,
483*4882a593Smuzhiyun 				sizeof(buf));
484*4882a593Smuzhiyun 			if (buf[0] & RT5514_IRQ_STATUS_BIT)
485*4882a593Smuzhiyun 				rt5514_schedule_copy(rt5514_dsp);
486*4882a593Smuzhiyun 		}
487*4882a593Smuzhiyun 	}
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	return 0;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun static const struct dev_pm_ops rt5514_pm_ops = {
493*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(rt5514_suspend, rt5514_resume)
494*4882a593Smuzhiyun };
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun static const struct of_device_id rt5514_of_match[] = {
497*4882a593Smuzhiyun 	{ .compatible = "realtek,rt5514", },
498*4882a593Smuzhiyun 	{},
499*4882a593Smuzhiyun };
500*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rt5514_of_match);
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun static struct spi_driver rt5514_spi_driver = {
503*4882a593Smuzhiyun 	.driver = {
504*4882a593Smuzhiyun 		.name = "rt5514",
505*4882a593Smuzhiyun 		.pm = &rt5514_pm_ops,
506*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(rt5514_of_match),
507*4882a593Smuzhiyun 	},
508*4882a593Smuzhiyun 	.probe = rt5514_spi_probe,
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun module_spi_driver(rt5514_spi_driver);
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun MODULE_DESCRIPTION("RT5514 SPI driver");
513*4882a593Smuzhiyun MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
514*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
515