1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * rt298.c -- RT298 ALSA SoC audio codec driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2015 Realtek Semiconductor Corp.
6*4882a593Smuzhiyun * Author: Bard Liao <bardliao@realtek.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/moduleparam.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/pm.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/spi/spi.h>
17*4882a593Smuzhiyun #include <linux/dmi.h>
18*4882a593Smuzhiyun #include <linux/acpi.h>
19*4882a593Smuzhiyun #include <sound/core.h>
20*4882a593Smuzhiyun #include <sound/pcm.h>
21*4882a593Smuzhiyun #include <sound/pcm_params.h>
22*4882a593Smuzhiyun #include <sound/soc.h>
23*4882a593Smuzhiyun #include <sound/soc-dapm.h>
24*4882a593Smuzhiyun #include <sound/initval.h>
25*4882a593Smuzhiyun #include <sound/tlv.h>
26*4882a593Smuzhiyun #include <sound/jack.h>
27*4882a593Smuzhiyun #include <linux/workqueue.h>
28*4882a593Smuzhiyun #include <sound/rt298.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "rl6347a.h"
31*4882a593Smuzhiyun #include "rt298.h"
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define RT298_VENDOR_ID 0x10ec0298
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct rt298_priv {
36*4882a593Smuzhiyun struct reg_default *index_cache;
37*4882a593Smuzhiyun int index_cache_size;
38*4882a593Smuzhiyun struct regmap *regmap;
39*4882a593Smuzhiyun struct snd_soc_component *component;
40*4882a593Smuzhiyun struct rt298_platform_data pdata;
41*4882a593Smuzhiyun struct i2c_client *i2c;
42*4882a593Smuzhiyun struct snd_soc_jack *jack;
43*4882a593Smuzhiyun struct delayed_work jack_detect_work;
44*4882a593Smuzhiyun int sys_clk;
45*4882a593Smuzhiyun int clk_id;
46*4882a593Smuzhiyun int is_hp_in;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static const struct reg_default rt298_index_def[] = {
50*4882a593Smuzhiyun { 0x01, 0xa5a8 },
51*4882a593Smuzhiyun { 0x02, 0x8e95 },
52*4882a593Smuzhiyun { 0x03, 0x0002 },
53*4882a593Smuzhiyun { 0x04, 0xaf67 },
54*4882a593Smuzhiyun { 0x08, 0x200f },
55*4882a593Smuzhiyun { 0x09, 0xd010 },
56*4882a593Smuzhiyun { 0x0a, 0x0100 },
57*4882a593Smuzhiyun { 0x0b, 0x0000 },
58*4882a593Smuzhiyun { 0x0d, 0x2800 },
59*4882a593Smuzhiyun { 0x0f, 0x0022 },
60*4882a593Smuzhiyun { 0x19, 0x0217 },
61*4882a593Smuzhiyun { 0x20, 0x0020 },
62*4882a593Smuzhiyun { 0x33, 0x0208 },
63*4882a593Smuzhiyun { 0x46, 0x0300 },
64*4882a593Smuzhiyun { 0x49, 0x4004 },
65*4882a593Smuzhiyun { 0x4f, 0x50c9 },
66*4882a593Smuzhiyun { 0x50, 0x3000 },
67*4882a593Smuzhiyun { 0x63, 0x1b02 },
68*4882a593Smuzhiyun { 0x67, 0x1111 },
69*4882a593Smuzhiyun { 0x68, 0x1016 },
70*4882a593Smuzhiyun { 0x69, 0x273f },
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun #define INDEX_CACHE_SIZE ARRAY_SIZE(rt298_index_def)
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static const struct reg_default rt298_reg[] = {
75*4882a593Smuzhiyun { 0x00170500, 0x00000400 },
76*4882a593Smuzhiyun { 0x00220000, 0x00000031 },
77*4882a593Smuzhiyun { 0x00239000, 0x0000007f },
78*4882a593Smuzhiyun { 0x0023a000, 0x0000007f },
79*4882a593Smuzhiyun { 0x00270500, 0x00000400 },
80*4882a593Smuzhiyun { 0x00370500, 0x00000400 },
81*4882a593Smuzhiyun { 0x00870500, 0x00000400 },
82*4882a593Smuzhiyun { 0x00920000, 0x00000031 },
83*4882a593Smuzhiyun { 0x00935000, 0x000000c3 },
84*4882a593Smuzhiyun { 0x00936000, 0x000000c3 },
85*4882a593Smuzhiyun { 0x00970500, 0x00000400 },
86*4882a593Smuzhiyun { 0x00b37000, 0x00000097 },
87*4882a593Smuzhiyun { 0x00b37200, 0x00000097 },
88*4882a593Smuzhiyun { 0x00b37300, 0x00000097 },
89*4882a593Smuzhiyun { 0x00c37000, 0x00000000 },
90*4882a593Smuzhiyun { 0x00c37100, 0x00000080 },
91*4882a593Smuzhiyun { 0x01270500, 0x00000400 },
92*4882a593Smuzhiyun { 0x01370500, 0x00000400 },
93*4882a593Smuzhiyun { 0x01371f00, 0x411111f0 },
94*4882a593Smuzhiyun { 0x01439000, 0x00000080 },
95*4882a593Smuzhiyun { 0x0143a000, 0x00000080 },
96*4882a593Smuzhiyun { 0x01470700, 0x00000000 },
97*4882a593Smuzhiyun { 0x01470500, 0x00000400 },
98*4882a593Smuzhiyun { 0x01470c00, 0x00000000 },
99*4882a593Smuzhiyun { 0x01470100, 0x00000000 },
100*4882a593Smuzhiyun { 0x01837000, 0x00000000 },
101*4882a593Smuzhiyun { 0x01870500, 0x00000400 },
102*4882a593Smuzhiyun { 0x02050000, 0x00000000 },
103*4882a593Smuzhiyun { 0x02139000, 0x00000080 },
104*4882a593Smuzhiyun { 0x0213a000, 0x00000080 },
105*4882a593Smuzhiyun { 0x02170100, 0x00000000 },
106*4882a593Smuzhiyun { 0x02170500, 0x00000400 },
107*4882a593Smuzhiyun { 0x02170700, 0x00000000 },
108*4882a593Smuzhiyun { 0x02270100, 0x00000000 },
109*4882a593Smuzhiyun { 0x02370100, 0x00000000 },
110*4882a593Smuzhiyun { 0x01870700, 0x00000020 },
111*4882a593Smuzhiyun { 0x00830000, 0x000000c3 },
112*4882a593Smuzhiyun { 0x00930000, 0x000000c3 },
113*4882a593Smuzhiyun { 0x01270700, 0x00000000 },
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
rt298_volatile_register(struct device * dev,unsigned int reg)116*4882a593Smuzhiyun static bool rt298_volatile_register(struct device *dev, unsigned int reg)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun switch (reg) {
119*4882a593Smuzhiyun case 0 ... 0xff:
120*4882a593Smuzhiyun case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
121*4882a593Smuzhiyun case RT298_GET_HP_SENSE:
122*4882a593Smuzhiyun case RT298_GET_MIC1_SENSE:
123*4882a593Smuzhiyun case RT298_PROC_COEF:
124*4882a593Smuzhiyun case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0):
125*4882a593Smuzhiyun case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0):
126*4882a593Smuzhiyun case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0):
127*4882a593Smuzhiyun return true;
128*4882a593Smuzhiyun default:
129*4882a593Smuzhiyun return false;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
rt298_readable_register(struct device * dev,unsigned int reg)135*4882a593Smuzhiyun static bool rt298_readable_register(struct device *dev, unsigned int reg)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun switch (reg) {
138*4882a593Smuzhiyun case 0 ... 0xff:
139*4882a593Smuzhiyun case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
140*4882a593Smuzhiyun case RT298_GET_HP_SENSE:
141*4882a593Smuzhiyun case RT298_GET_MIC1_SENSE:
142*4882a593Smuzhiyun case RT298_SET_AUDIO_POWER:
143*4882a593Smuzhiyun case RT298_SET_HPO_POWER:
144*4882a593Smuzhiyun case RT298_SET_SPK_POWER:
145*4882a593Smuzhiyun case RT298_SET_DMIC1_POWER:
146*4882a593Smuzhiyun case RT298_SPK_MUX:
147*4882a593Smuzhiyun case RT298_HPO_MUX:
148*4882a593Smuzhiyun case RT298_ADC0_MUX:
149*4882a593Smuzhiyun case RT298_ADC1_MUX:
150*4882a593Smuzhiyun case RT298_SET_MIC1:
151*4882a593Smuzhiyun case RT298_SET_PIN_HPO:
152*4882a593Smuzhiyun case RT298_SET_PIN_SPK:
153*4882a593Smuzhiyun case RT298_SET_PIN_DMIC1:
154*4882a593Smuzhiyun case RT298_SPK_EAPD:
155*4882a593Smuzhiyun case RT298_SET_AMP_GAIN_HPO:
156*4882a593Smuzhiyun case RT298_SET_DMIC2_DEFAULT:
157*4882a593Smuzhiyun case RT298_DACL_GAIN:
158*4882a593Smuzhiyun case RT298_DACR_GAIN:
159*4882a593Smuzhiyun case RT298_ADCL_GAIN:
160*4882a593Smuzhiyun case RT298_ADCR_GAIN:
161*4882a593Smuzhiyun case RT298_MIC_GAIN:
162*4882a593Smuzhiyun case RT298_SPOL_GAIN:
163*4882a593Smuzhiyun case RT298_SPOR_GAIN:
164*4882a593Smuzhiyun case RT298_HPOL_GAIN:
165*4882a593Smuzhiyun case RT298_HPOR_GAIN:
166*4882a593Smuzhiyun case RT298_F_DAC_SWITCH:
167*4882a593Smuzhiyun case RT298_F_RECMIX_SWITCH:
168*4882a593Smuzhiyun case RT298_REC_MIC_SWITCH:
169*4882a593Smuzhiyun case RT298_REC_I2S_SWITCH:
170*4882a593Smuzhiyun case RT298_REC_LINE_SWITCH:
171*4882a593Smuzhiyun case RT298_REC_BEEP_SWITCH:
172*4882a593Smuzhiyun case RT298_DAC_FORMAT:
173*4882a593Smuzhiyun case RT298_ADC_FORMAT:
174*4882a593Smuzhiyun case RT298_COEF_INDEX:
175*4882a593Smuzhiyun case RT298_PROC_COEF:
176*4882a593Smuzhiyun case RT298_SET_AMP_GAIN_ADC_IN1:
177*4882a593Smuzhiyun case RT298_SET_AMP_GAIN_ADC_IN2:
178*4882a593Smuzhiyun case RT298_SET_POWER(RT298_DAC_OUT1):
179*4882a593Smuzhiyun case RT298_SET_POWER(RT298_DAC_OUT2):
180*4882a593Smuzhiyun case RT298_SET_POWER(RT298_ADC_IN1):
181*4882a593Smuzhiyun case RT298_SET_POWER(RT298_ADC_IN2):
182*4882a593Smuzhiyun case RT298_SET_POWER(RT298_DMIC2):
183*4882a593Smuzhiyun case RT298_SET_POWER(RT298_MIC1):
184*4882a593Smuzhiyun case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0):
185*4882a593Smuzhiyun case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0):
186*4882a593Smuzhiyun case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0):
187*4882a593Smuzhiyun return true;
188*4882a593Smuzhiyun default:
189*4882a593Smuzhiyun return false;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun #ifdef CONFIG_PM
rt298_index_sync(struct snd_soc_component * component)194*4882a593Smuzhiyun static void rt298_index_sync(struct snd_soc_component *component)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
197*4882a593Smuzhiyun int i;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun for (i = 0; i < INDEX_CACHE_SIZE; i++) {
200*4882a593Smuzhiyun snd_soc_component_write(component, rt298->index_cache[i].reg,
201*4882a593Smuzhiyun rt298->index_cache[i].def);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun #endif
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun static int rt298_support_power_controls[] = {
207*4882a593Smuzhiyun RT298_DAC_OUT1,
208*4882a593Smuzhiyun RT298_DAC_OUT2,
209*4882a593Smuzhiyun RT298_ADC_IN1,
210*4882a593Smuzhiyun RT298_ADC_IN2,
211*4882a593Smuzhiyun RT298_MIC1,
212*4882a593Smuzhiyun RT298_DMIC1,
213*4882a593Smuzhiyun RT298_DMIC2,
214*4882a593Smuzhiyun RT298_SPK_OUT,
215*4882a593Smuzhiyun RT298_HP_OUT,
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun #define RT298_POWER_REG_LEN ARRAY_SIZE(rt298_support_power_controls)
218*4882a593Smuzhiyun
rt298_jack_detect(struct rt298_priv * rt298,bool * hp,bool * mic)219*4882a593Smuzhiyun static int rt298_jack_detect(struct rt298_priv *rt298, bool *hp, bool *mic)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm;
222*4882a593Smuzhiyun unsigned int val, buf;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun *hp = false;
225*4882a593Smuzhiyun *mic = false;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun if (!rt298->component)
228*4882a593Smuzhiyun return -EINVAL;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun dapm = snd_soc_component_get_dapm(rt298->component);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun if (rt298->pdata.cbj_en) {
233*4882a593Smuzhiyun regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf);
234*4882a593Smuzhiyun *hp = buf & 0x80000000;
235*4882a593Smuzhiyun if (*hp == rt298->is_hp_in)
236*4882a593Smuzhiyun return -1;
237*4882a593Smuzhiyun rt298->is_hp_in = *hp;
238*4882a593Smuzhiyun if (*hp) {
239*4882a593Smuzhiyun /* power on HV,VERF */
240*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
241*4882a593Smuzhiyun RT298_DC_GAIN, 0x200, 0x200);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun snd_soc_dapm_force_enable_pin(dapm, "HV");
244*4882a593Smuzhiyun snd_soc_dapm_force_enable_pin(dapm, "VREF");
245*4882a593Smuzhiyun /* power LDO1 */
246*4882a593Smuzhiyun snd_soc_dapm_force_enable_pin(dapm, "LDO1");
247*4882a593Smuzhiyun snd_soc_dapm_sync(dapm);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
250*4882a593Smuzhiyun RT298_POWER_CTRL1, 0x1001, 0);
251*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
252*4882a593Smuzhiyun RT298_POWER_CTRL2, 0x4, 0x4);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_SET_MIC1, 0x24);
255*4882a593Smuzhiyun msleep(50);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
258*4882a593Smuzhiyun RT298_CBJ_CTRL1, 0xfcc0, 0xd400);
259*4882a593Smuzhiyun msleep(300);
260*4882a593Smuzhiyun regmap_read(rt298->regmap, RT298_CBJ_CTRL2, &val);
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun if (0x0070 == (val & 0x0070)) {
263*4882a593Smuzhiyun *mic = true;
264*4882a593Smuzhiyun } else {
265*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
266*4882a593Smuzhiyun RT298_CBJ_CTRL1, 0xfcc0, 0xe400);
267*4882a593Smuzhiyun msleep(300);
268*4882a593Smuzhiyun regmap_read(rt298->regmap,
269*4882a593Smuzhiyun RT298_CBJ_CTRL2, &val);
270*4882a593Smuzhiyun if (0x0070 == (val & 0x0070))
271*4882a593Smuzhiyun *mic = true;
272*4882a593Smuzhiyun else
273*4882a593Smuzhiyun *mic = false;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
276*4882a593Smuzhiyun RT298_DC_GAIN, 0x200, 0x0);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun } else {
279*4882a593Smuzhiyun *mic = false;
280*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_SET_MIC1, 0x20);
281*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
282*4882a593Smuzhiyun RT298_CBJ_CTRL1, 0x0400, 0x0000);
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun } else {
285*4882a593Smuzhiyun regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf);
286*4882a593Smuzhiyun *hp = buf & 0x80000000;
287*4882a593Smuzhiyun regmap_read(rt298->regmap, RT298_GET_MIC1_SENSE, &buf);
288*4882a593Smuzhiyun *mic = buf & 0x80000000;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun if (!*mic) {
291*4882a593Smuzhiyun snd_soc_dapm_disable_pin(dapm, "HV");
292*4882a593Smuzhiyun snd_soc_dapm_disable_pin(dapm, "VREF");
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun if (!*hp)
295*4882a593Smuzhiyun snd_soc_dapm_disable_pin(dapm, "LDO1");
296*4882a593Smuzhiyun snd_soc_dapm_sync(dapm);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun pr_debug("*hp = %d *mic = %d\n", *hp, *mic);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun return 0;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
rt298_jack_detect_work(struct work_struct * work)303*4882a593Smuzhiyun static void rt298_jack_detect_work(struct work_struct *work)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun struct rt298_priv *rt298 =
306*4882a593Smuzhiyun container_of(work, struct rt298_priv, jack_detect_work.work);
307*4882a593Smuzhiyun int status = 0;
308*4882a593Smuzhiyun bool hp = false;
309*4882a593Smuzhiyun bool mic = false;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun if (rt298_jack_detect(rt298, &hp, &mic) < 0)
312*4882a593Smuzhiyun return;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun if (hp)
315*4882a593Smuzhiyun status |= SND_JACK_HEADPHONE;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun if (mic)
318*4882a593Smuzhiyun status |= SND_JACK_MICROPHONE;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun snd_soc_jack_report(rt298->jack, status,
321*4882a593Smuzhiyun SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
rt298_mic_detect(struct snd_soc_component * component,struct snd_soc_jack * jack)324*4882a593Smuzhiyun int rt298_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
327*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm;
328*4882a593Smuzhiyun bool hp = false;
329*4882a593Smuzhiyun bool mic = false;
330*4882a593Smuzhiyun int status = 0;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun /* If jack in NULL, disable HS jack */
333*4882a593Smuzhiyun if (!jack) {
334*4882a593Smuzhiyun regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x2, 0x0);
335*4882a593Smuzhiyun dapm = snd_soc_component_get_dapm(component);
336*4882a593Smuzhiyun snd_soc_dapm_disable_pin(dapm, "LDO1");
337*4882a593Smuzhiyun snd_soc_dapm_sync(dapm);
338*4882a593Smuzhiyun return 0;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun rt298->jack = jack;
342*4882a593Smuzhiyun regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x2, 0x2);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun rt298_jack_detect(rt298, &hp, &mic);
345*4882a593Smuzhiyun if (hp)
346*4882a593Smuzhiyun status |= SND_JACK_HEADPHONE;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun if (mic)
349*4882a593Smuzhiyun status |= SND_JACK_MICROPHONE;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun snd_soc_jack_report(rt298->jack, status,
352*4882a593Smuzhiyun SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun return 0;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt298_mic_detect);
357*4882a593Smuzhiyun
is_mclk_mode(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)358*4882a593Smuzhiyun static int is_mclk_mode(struct snd_soc_dapm_widget *source,
359*4882a593Smuzhiyun struct snd_soc_dapm_widget *sink)
360*4882a593Smuzhiyun {
361*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
362*4882a593Smuzhiyun struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun if (rt298->clk_id == RT298_SCLK_S_MCLK)
365*4882a593Smuzhiyun return 1;
366*4882a593Smuzhiyun else
367*4882a593Smuzhiyun return 0;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
371*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun static const struct snd_kcontrol_new rt298_snd_controls[] = {
374*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT298_DACL_GAIN,
375*4882a593Smuzhiyun RT298_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
376*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT298_ADCL_GAIN,
377*4882a593Smuzhiyun RT298_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
378*4882a593Smuzhiyun SOC_SINGLE_TLV("AMIC Volume", RT298_MIC_GAIN,
379*4882a593Smuzhiyun 0, 0x3, 0, mic_vol_tlv),
380*4882a593Smuzhiyun SOC_DOUBLE_R("Speaker Playback Switch", RT298_SPOL_GAIN,
381*4882a593Smuzhiyun RT298_SPOR_GAIN, RT298_MUTE_SFT, 1, 1),
382*4882a593Smuzhiyun };
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun /* Digital Mixer */
385*4882a593Smuzhiyun static const struct snd_kcontrol_new rt298_front_mix[] = {
386*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC Switch", RT298_F_DAC_SWITCH,
387*4882a593Smuzhiyun RT298_MUTE_SFT, 1, 1),
388*4882a593Smuzhiyun SOC_DAPM_SINGLE("RECMIX Switch", RT298_F_RECMIX_SWITCH,
389*4882a593Smuzhiyun RT298_MUTE_SFT, 1, 1),
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun /* Analog Input Mixer */
393*4882a593Smuzhiyun static const struct snd_kcontrol_new rt298_rec_mix[] = {
394*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mic1 Switch", RT298_REC_MIC_SWITCH,
395*4882a593Smuzhiyun RT298_MUTE_SFT, 1, 1),
396*4882a593Smuzhiyun SOC_DAPM_SINGLE("I2S Switch", RT298_REC_I2S_SWITCH,
397*4882a593Smuzhiyun RT298_MUTE_SFT, 1, 1),
398*4882a593Smuzhiyun SOC_DAPM_SINGLE("Line1 Switch", RT298_REC_LINE_SWITCH,
399*4882a593Smuzhiyun RT298_MUTE_SFT, 1, 1),
400*4882a593Smuzhiyun SOC_DAPM_SINGLE("Beep Switch", RT298_REC_BEEP_SWITCH,
401*4882a593Smuzhiyun RT298_MUTE_SFT, 1, 1),
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun static const struct snd_kcontrol_new spo_enable_control =
405*4882a593Smuzhiyun SOC_DAPM_SINGLE("Switch", RT298_SET_PIN_SPK,
406*4882a593Smuzhiyun RT298_SET_PIN_SFT, 1, 0);
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun static const struct snd_kcontrol_new hpol_enable_control =
409*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOL_GAIN,
410*4882a593Smuzhiyun RT298_MUTE_SFT, 1, 1);
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun static const struct snd_kcontrol_new hpor_enable_control =
413*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOR_GAIN,
414*4882a593Smuzhiyun RT298_MUTE_SFT, 1, 1);
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun /* ADC0 source */
417*4882a593Smuzhiyun static const char * const rt298_adc_src[] = {
418*4882a593Smuzhiyun "Mic", "RECMIX", "Dmic"
419*4882a593Smuzhiyun };
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun static const int rt298_adc_values[] = {
422*4882a593Smuzhiyun 0, 4, 5,
423*4882a593Smuzhiyun };
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun static SOC_VALUE_ENUM_SINGLE_DECL(
426*4882a593Smuzhiyun rt298_adc0_enum, RT298_ADC0_MUX, RT298_ADC_SEL_SFT,
427*4882a593Smuzhiyun RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun static const struct snd_kcontrol_new rt298_adc0_mux =
430*4882a593Smuzhiyun SOC_DAPM_ENUM("ADC 0 source", rt298_adc0_enum);
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun static SOC_VALUE_ENUM_SINGLE_DECL(
433*4882a593Smuzhiyun rt298_adc1_enum, RT298_ADC1_MUX, RT298_ADC_SEL_SFT,
434*4882a593Smuzhiyun RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values);
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun static const struct snd_kcontrol_new rt298_adc1_mux =
437*4882a593Smuzhiyun SOC_DAPM_ENUM("ADC 1 source", rt298_adc1_enum);
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun static const char * const rt298_dac_src[] = {
440*4882a593Smuzhiyun "Front", "Surround"
441*4882a593Smuzhiyun };
442*4882a593Smuzhiyun /* HP-OUT source */
443*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt298_hpo_enum, RT298_HPO_MUX,
444*4882a593Smuzhiyun 0, rt298_dac_src);
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun static const struct snd_kcontrol_new rt298_hpo_mux =
447*4882a593Smuzhiyun SOC_DAPM_ENUM("HPO source", rt298_hpo_enum);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun /* SPK-OUT source */
450*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt298_spo_enum, RT298_SPK_MUX,
451*4882a593Smuzhiyun 0, rt298_dac_src);
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun static const struct snd_kcontrol_new rt298_spo_mux =
454*4882a593Smuzhiyun SOC_DAPM_ENUM("SPO source", rt298_spo_enum);
455*4882a593Smuzhiyun
rt298_spk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)456*4882a593Smuzhiyun static int rt298_spk_event(struct snd_soc_dapm_widget *w,
457*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
458*4882a593Smuzhiyun {
459*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun switch (event) {
462*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
463*4882a593Smuzhiyun snd_soc_component_write(component,
464*4882a593Smuzhiyun RT298_SPK_EAPD, RT298_SET_EAPD_HIGH);
465*4882a593Smuzhiyun break;
466*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
467*4882a593Smuzhiyun snd_soc_component_write(component,
468*4882a593Smuzhiyun RT298_SPK_EAPD, RT298_SET_EAPD_LOW);
469*4882a593Smuzhiyun break;
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun default:
472*4882a593Smuzhiyun return 0;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun return 0;
476*4882a593Smuzhiyun }
477*4882a593Smuzhiyun
rt298_set_dmic1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)478*4882a593Smuzhiyun static int rt298_set_dmic1_event(struct snd_soc_dapm_widget *w,
479*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
480*4882a593Smuzhiyun {
481*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun switch (event) {
484*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
485*4882a593Smuzhiyun snd_soc_component_write(component, RT298_SET_PIN_DMIC1, 0x20);
486*4882a593Smuzhiyun break;
487*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
488*4882a593Smuzhiyun snd_soc_component_write(component, RT298_SET_PIN_DMIC1, 0);
489*4882a593Smuzhiyun break;
490*4882a593Smuzhiyun default:
491*4882a593Smuzhiyun return 0;
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun return 0;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
rt298_adc_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)497*4882a593Smuzhiyun static int rt298_adc_event(struct snd_soc_dapm_widget *w,
498*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
501*4882a593Smuzhiyun unsigned int nid;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun nid = (w->reg >> 20) & 0xff;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun switch (event) {
506*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
507*4882a593Smuzhiyun snd_soc_component_update_bits(component,
508*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
509*4882a593Smuzhiyun 0x7080, 0x7000);
510*4882a593Smuzhiyun /* If MCLK doesn't exist, reset AD filter */
511*4882a593Smuzhiyun if (!(snd_soc_component_read(component, RT298_VAD_CTRL) & 0x200)) {
512*4882a593Smuzhiyun pr_info("NO MCLK\n");
513*4882a593Smuzhiyun switch (nid) {
514*4882a593Smuzhiyun case RT298_ADC_IN1:
515*4882a593Smuzhiyun snd_soc_component_update_bits(component,
516*4882a593Smuzhiyun RT298_D_FILTER_CTRL, 0x2, 0x2);
517*4882a593Smuzhiyun mdelay(10);
518*4882a593Smuzhiyun snd_soc_component_update_bits(component,
519*4882a593Smuzhiyun RT298_D_FILTER_CTRL, 0x2, 0x0);
520*4882a593Smuzhiyun break;
521*4882a593Smuzhiyun case RT298_ADC_IN2:
522*4882a593Smuzhiyun snd_soc_component_update_bits(component,
523*4882a593Smuzhiyun RT298_D_FILTER_CTRL, 0x4, 0x4);
524*4882a593Smuzhiyun mdelay(10);
525*4882a593Smuzhiyun snd_soc_component_update_bits(component,
526*4882a593Smuzhiyun RT298_D_FILTER_CTRL, 0x4, 0x0);
527*4882a593Smuzhiyun break;
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun break;
531*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
532*4882a593Smuzhiyun snd_soc_component_update_bits(component,
533*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
534*4882a593Smuzhiyun 0x7080, 0x7080);
535*4882a593Smuzhiyun break;
536*4882a593Smuzhiyun default:
537*4882a593Smuzhiyun return 0;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun return 0;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun
rt298_mic1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)543*4882a593Smuzhiyun static int rt298_mic1_event(struct snd_soc_dapm_widget *w,
544*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun switch (event) {
549*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
550*4882a593Smuzhiyun snd_soc_component_update_bits(component,
551*4882a593Smuzhiyun RT298_A_BIAS_CTRL3, 0xc000, 0x8000);
552*4882a593Smuzhiyun snd_soc_component_update_bits(component,
553*4882a593Smuzhiyun RT298_A_BIAS_CTRL2, 0xc000, 0x8000);
554*4882a593Smuzhiyun break;
555*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
556*4882a593Smuzhiyun snd_soc_component_update_bits(component,
557*4882a593Smuzhiyun RT298_A_BIAS_CTRL3, 0xc000, 0x0000);
558*4882a593Smuzhiyun snd_soc_component_update_bits(component,
559*4882a593Smuzhiyun RT298_A_BIAS_CTRL2, 0xc000, 0x0000);
560*4882a593Smuzhiyun break;
561*4882a593Smuzhiyun default:
562*4882a593Smuzhiyun return 0;
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun return 0;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun static const struct snd_soc_dapm_widget rt298_dapm_widgets[] = {
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("HV", 1, RT298_POWER_CTRL1,
571*4882a593Smuzhiyun 12, 1, NULL, 0),
572*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("VREF", RT298_POWER_CTRL1,
573*4882a593Smuzhiyun 0, 1, NULL, 0),
574*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("BG_MBIAS", 1, RT298_POWER_CTRL2,
575*4882a593Smuzhiyun 1, 0, NULL, 0),
576*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT298_POWER_CTRL2,
577*4882a593Smuzhiyun 2, 0, NULL, 0),
578*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT298_POWER_CTRL2,
579*4882a593Smuzhiyun 3, 0, NULL, 0),
580*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("VREF1", 1, RT298_POWER_CTRL2,
581*4882a593Smuzhiyun 4, 1, NULL, 0),
582*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("LV", 2, RT298_POWER_CTRL1,
583*4882a593Smuzhiyun 13, 1, NULL, 0),
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MCLK MODE", RT298_PLL_CTRL1,
587*4882a593Smuzhiyun 5, 0, NULL, 0),
588*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
589*4882a593Smuzhiyun 0, 0, rt298_mic1_event, SND_SOC_DAPM_PRE_PMU |
590*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMD),
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun /* Input Lines */
593*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC1 Pin"),
594*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC2 Pin"),
595*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MIC1"),
596*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("LINE1"),
597*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("Beep"),
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun /* DMIC */
600*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("DMIC1", RT298_SET_POWER(RT298_DMIC1), 0, 1,
601*4882a593Smuzhiyun NULL, 0, rt298_set_dmic1_event,
602*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
603*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DMIC2", RT298_SET_POWER(RT298_DMIC2), 0, 1,
604*4882a593Smuzhiyun NULL, 0),
605*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
606*4882a593Smuzhiyun 0, 0, NULL, 0),
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun /* REC Mixer */
609*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
610*4882a593Smuzhiyun rt298_rec_mix, ARRAY_SIZE(rt298_rec_mix)),
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun /* ADCs */
613*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
614*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun /* ADC Mux */
617*4882a593Smuzhiyun SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT298_SET_POWER(RT298_ADC_IN1), 0, 1,
618*4882a593Smuzhiyun &rt298_adc0_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD |
619*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU),
620*4882a593Smuzhiyun SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT298_SET_POWER(RT298_ADC_IN2), 0, 1,
621*4882a593Smuzhiyun &rt298_adc1_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD |
622*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU),
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun /* Audio Interface */
625*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
626*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
627*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
628*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun /* Output Side */
631*4882a593Smuzhiyun /* DACs */
632*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
633*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun /* Output Mux */
636*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt298_spo_mux),
637*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt298_hpo_mux),
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("HP Power", RT298_SET_PIN_HPO,
640*4882a593Smuzhiyun RT298_SET_PIN_SFT, 0, NULL, 0),
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun /* Output Mixer */
643*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Front", RT298_SET_POWER(RT298_DAC_OUT1), 0, 1,
644*4882a593Smuzhiyun rt298_front_mix, ARRAY_SIZE(rt298_front_mix)),
645*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Surround", RT298_SET_POWER(RT298_DAC_OUT2), 0, 1,
646*4882a593Smuzhiyun NULL, 0),
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun /* Output Pga */
649*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
650*4882a593Smuzhiyun &spo_enable_control, rt298_spk_event,
651*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
652*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
653*4882a593Smuzhiyun &hpol_enable_control),
654*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
655*4882a593Smuzhiyun &hpor_enable_control),
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun /* Output Lines */
658*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPOL"),
659*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPOR"),
660*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPO Pin"),
661*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPDIF"),
662*4882a593Smuzhiyun };
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun static const struct snd_soc_dapm_route rt298_dapm_routes[] = {
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
667*4882a593Smuzhiyun {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
668*4882a593Smuzhiyun {"Front", NULL, "MCLK MODE", is_mclk_mode},
669*4882a593Smuzhiyun {"Surround", NULL, "MCLK MODE", is_mclk_mode},
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun {"HP Power", NULL, "LDO1"},
672*4882a593Smuzhiyun {"HP Power", NULL, "LDO2"},
673*4882a593Smuzhiyun {"HP Power", NULL, "LV"},
674*4882a593Smuzhiyun {"HP Power", NULL, "VREF1"},
675*4882a593Smuzhiyun {"HP Power", NULL, "BG_MBIAS"},
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun {"MIC1", NULL, "LDO1"},
678*4882a593Smuzhiyun {"MIC1", NULL, "LDO2"},
679*4882a593Smuzhiyun {"MIC1", NULL, "HV"},
680*4882a593Smuzhiyun {"MIC1", NULL, "LV"},
681*4882a593Smuzhiyun {"MIC1", NULL, "VREF"},
682*4882a593Smuzhiyun {"MIC1", NULL, "VREF1"},
683*4882a593Smuzhiyun {"MIC1", NULL, "BG_MBIAS"},
684*4882a593Smuzhiyun {"MIC1", NULL, "MIC1 Input Buffer"},
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun {"SPO", NULL, "LDO1"},
687*4882a593Smuzhiyun {"SPO", NULL, "LDO2"},
688*4882a593Smuzhiyun {"SPO", NULL, "HV"},
689*4882a593Smuzhiyun {"SPO", NULL, "LV"},
690*4882a593Smuzhiyun {"SPO", NULL, "VREF"},
691*4882a593Smuzhiyun {"SPO", NULL, "VREF1"},
692*4882a593Smuzhiyun {"SPO", NULL, "BG_MBIAS"},
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun {"DMIC1", NULL, "DMIC1 Pin"},
695*4882a593Smuzhiyun {"DMIC2", NULL, "DMIC2 Pin"},
696*4882a593Smuzhiyun {"DMIC1", NULL, "DMIC Receiver"},
697*4882a593Smuzhiyun {"DMIC2", NULL, "DMIC Receiver"},
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun {"RECMIX", "Beep Switch", "Beep"},
700*4882a593Smuzhiyun {"RECMIX", "Line1 Switch", "LINE1"},
701*4882a593Smuzhiyun {"RECMIX", "Mic1 Switch", "MIC1"},
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun {"ADC 0 Mux", "Dmic", "DMIC1"},
704*4882a593Smuzhiyun {"ADC 0 Mux", "RECMIX", "RECMIX"},
705*4882a593Smuzhiyun {"ADC 0 Mux", "Mic", "MIC1"},
706*4882a593Smuzhiyun {"ADC 1 Mux", "Dmic", "DMIC2"},
707*4882a593Smuzhiyun {"ADC 1 Mux", "RECMIX", "RECMIX"},
708*4882a593Smuzhiyun {"ADC 1 Mux", "Mic", "MIC1"},
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun {"ADC 0", NULL, "ADC 0 Mux"},
711*4882a593Smuzhiyun {"ADC 1", NULL, "ADC 1 Mux"},
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun {"AIF1TX", NULL, "ADC 0"},
714*4882a593Smuzhiyun {"AIF2TX", NULL, "ADC 1"},
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun {"DAC 0", NULL, "AIF1RX"},
717*4882a593Smuzhiyun {"DAC 1", NULL, "AIF2RX"},
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun {"Front", "DAC Switch", "DAC 0"},
720*4882a593Smuzhiyun {"Front", "RECMIX Switch", "RECMIX"},
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun {"Surround", NULL, "DAC 1"},
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun {"SPK Mux", "Front", "Front"},
725*4882a593Smuzhiyun {"SPK Mux", "Surround", "Surround"},
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun {"HPO Mux", "Front", "Front"},
728*4882a593Smuzhiyun {"HPO Mux", "Surround", "Surround"},
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun {"SPO", "Switch", "SPK Mux"},
731*4882a593Smuzhiyun {"HPO L", "Switch", "HPO Mux"},
732*4882a593Smuzhiyun {"HPO R", "Switch", "HPO Mux"},
733*4882a593Smuzhiyun {"HPO L", NULL, "HP Power"},
734*4882a593Smuzhiyun {"HPO R", NULL, "HP Power"},
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun {"SPOL", NULL, "SPO"},
737*4882a593Smuzhiyun {"SPOR", NULL, "SPO"},
738*4882a593Smuzhiyun {"HPO Pin", NULL, "HPO L"},
739*4882a593Smuzhiyun {"HPO Pin", NULL, "HPO R"},
740*4882a593Smuzhiyun };
741*4882a593Smuzhiyun
rt298_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)742*4882a593Smuzhiyun static int rt298_hw_params(struct snd_pcm_substream *substream,
743*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
744*4882a593Smuzhiyun struct snd_soc_dai *dai)
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
747*4882a593Smuzhiyun struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
748*4882a593Smuzhiyun unsigned int val = 0;
749*4882a593Smuzhiyun int d_len_code;
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun switch (params_rate(params)) {
752*4882a593Smuzhiyun /* bit 14 0:48K 1:44.1K */
753*4882a593Smuzhiyun case 44100:
754*4882a593Smuzhiyun case 48000:
755*4882a593Smuzhiyun break;
756*4882a593Smuzhiyun default:
757*4882a593Smuzhiyun dev_err(component->dev, "Unsupported sample rate %d\n",
758*4882a593Smuzhiyun params_rate(params));
759*4882a593Smuzhiyun return -EINVAL;
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun switch (rt298->sys_clk) {
762*4882a593Smuzhiyun case 12288000:
763*4882a593Smuzhiyun case 24576000:
764*4882a593Smuzhiyun if (params_rate(params) != 48000) {
765*4882a593Smuzhiyun dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
766*4882a593Smuzhiyun params_rate(params), rt298->sys_clk);
767*4882a593Smuzhiyun return -EINVAL;
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun break;
770*4882a593Smuzhiyun case 11289600:
771*4882a593Smuzhiyun case 22579200:
772*4882a593Smuzhiyun if (params_rate(params) != 44100) {
773*4882a593Smuzhiyun dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
774*4882a593Smuzhiyun params_rate(params), rt298->sys_clk);
775*4882a593Smuzhiyun return -EINVAL;
776*4882a593Smuzhiyun }
777*4882a593Smuzhiyun break;
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun if (params_channels(params) <= 16) {
781*4882a593Smuzhiyun /* bit 3:0 Number of Channel */
782*4882a593Smuzhiyun val |= (params_channels(params) - 1);
783*4882a593Smuzhiyun } else {
784*4882a593Smuzhiyun dev_err(component->dev, "Unsupported channels %d\n",
785*4882a593Smuzhiyun params_channels(params));
786*4882a593Smuzhiyun return -EINVAL;
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun d_len_code = 0;
790*4882a593Smuzhiyun switch (params_width(params)) {
791*4882a593Smuzhiyun /* bit 6:4 Bits per Sample */
792*4882a593Smuzhiyun case 16:
793*4882a593Smuzhiyun d_len_code = 0;
794*4882a593Smuzhiyun val |= (0x1 << 4);
795*4882a593Smuzhiyun break;
796*4882a593Smuzhiyun case 32:
797*4882a593Smuzhiyun d_len_code = 2;
798*4882a593Smuzhiyun val |= (0x4 << 4);
799*4882a593Smuzhiyun break;
800*4882a593Smuzhiyun case 20:
801*4882a593Smuzhiyun d_len_code = 1;
802*4882a593Smuzhiyun val |= (0x2 << 4);
803*4882a593Smuzhiyun break;
804*4882a593Smuzhiyun case 24:
805*4882a593Smuzhiyun d_len_code = 2;
806*4882a593Smuzhiyun val |= (0x3 << 4);
807*4882a593Smuzhiyun break;
808*4882a593Smuzhiyun case 8:
809*4882a593Smuzhiyun d_len_code = 3;
810*4882a593Smuzhiyun break;
811*4882a593Smuzhiyun default:
812*4882a593Smuzhiyun return -EINVAL;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun snd_soc_component_update_bits(component,
816*4882a593Smuzhiyun RT298_I2S_CTRL1, 0x0018, d_len_code << 3);
817*4882a593Smuzhiyun dev_dbg(component->dev, "format val = 0x%x\n", val);
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x407f, val);
820*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x407f, val);
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun return 0;
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun
rt298_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)825*4882a593Smuzhiyun static int rt298_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
830*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
831*4882a593Smuzhiyun snd_soc_component_update_bits(component,
832*4882a593Smuzhiyun RT298_I2S_CTRL1, 0x800, 0x800);
833*4882a593Smuzhiyun break;
834*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
835*4882a593Smuzhiyun snd_soc_component_update_bits(component,
836*4882a593Smuzhiyun RT298_I2S_CTRL1, 0x800, 0x0);
837*4882a593Smuzhiyun break;
838*4882a593Smuzhiyun default:
839*4882a593Smuzhiyun return -EINVAL;
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
843*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
844*4882a593Smuzhiyun snd_soc_component_update_bits(component,
845*4882a593Smuzhiyun RT298_I2S_CTRL1, 0x300, 0x0);
846*4882a593Smuzhiyun break;
847*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
848*4882a593Smuzhiyun snd_soc_component_update_bits(component,
849*4882a593Smuzhiyun RT298_I2S_CTRL1, 0x300, 0x1 << 8);
850*4882a593Smuzhiyun break;
851*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
852*4882a593Smuzhiyun snd_soc_component_update_bits(component,
853*4882a593Smuzhiyun RT298_I2S_CTRL1, 0x300, 0x2 << 8);
854*4882a593Smuzhiyun break;
855*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
856*4882a593Smuzhiyun snd_soc_component_update_bits(component,
857*4882a593Smuzhiyun RT298_I2S_CTRL1, 0x300, 0x3 << 8);
858*4882a593Smuzhiyun break;
859*4882a593Smuzhiyun default:
860*4882a593Smuzhiyun return -EINVAL;
861*4882a593Smuzhiyun }
862*4882a593Smuzhiyun /* bit 15 Stream Type 0:PCM 1:Non-PCM */
863*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x8000, 0);
864*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x8000, 0);
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun return 0;
867*4882a593Smuzhiyun }
868*4882a593Smuzhiyun
rt298_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)869*4882a593Smuzhiyun static int rt298_set_dai_sysclk(struct snd_soc_dai *dai,
870*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
871*4882a593Smuzhiyun {
872*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
873*4882a593Smuzhiyun struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun if (RT298_SCLK_S_MCLK == clk_id) {
878*4882a593Smuzhiyun snd_soc_component_update_bits(component,
879*4882a593Smuzhiyun RT298_I2S_CTRL2, 0x0100, 0x0);
880*4882a593Smuzhiyun snd_soc_component_update_bits(component,
881*4882a593Smuzhiyun RT298_PLL_CTRL1, 0x20, 0x20);
882*4882a593Smuzhiyun } else {
883*4882a593Smuzhiyun snd_soc_component_update_bits(component,
884*4882a593Smuzhiyun RT298_I2S_CTRL2, 0x0100, 0x0100);
885*4882a593Smuzhiyun snd_soc_component_update_bits(component,
886*4882a593Smuzhiyun RT298_PLL_CTRL1, 0x20, 0x0);
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun switch (freq) {
890*4882a593Smuzhiyun case 19200000:
891*4882a593Smuzhiyun if (RT298_SCLK_S_MCLK == clk_id) {
892*4882a593Smuzhiyun dev_err(component->dev, "Should not use MCLK\n");
893*4882a593Smuzhiyun return -EINVAL;
894*4882a593Smuzhiyun }
895*4882a593Smuzhiyun snd_soc_component_update_bits(component,
896*4882a593Smuzhiyun RT298_I2S_CTRL2, 0x40, 0x40);
897*4882a593Smuzhiyun break;
898*4882a593Smuzhiyun case 24000000:
899*4882a593Smuzhiyun if (RT298_SCLK_S_MCLK == clk_id) {
900*4882a593Smuzhiyun dev_err(component->dev, "Should not use MCLK\n");
901*4882a593Smuzhiyun return -EINVAL;
902*4882a593Smuzhiyun }
903*4882a593Smuzhiyun snd_soc_component_update_bits(component,
904*4882a593Smuzhiyun RT298_I2S_CTRL2, 0x40, 0x0);
905*4882a593Smuzhiyun break;
906*4882a593Smuzhiyun case 12288000:
907*4882a593Smuzhiyun case 11289600:
908*4882a593Smuzhiyun snd_soc_component_update_bits(component,
909*4882a593Smuzhiyun RT298_I2S_CTRL2, 0x8, 0x0);
910*4882a593Smuzhiyun snd_soc_component_update_bits(component,
911*4882a593Smuzhiyun RT298_CLK_DIV, 0xfc1e, 0x0004);
912*4882a593Smuzhiyun break;
913*4882a593Smuzhiyun case 24576000:
914*4882a593Smuzhiyun case 22579200:
915*4882a593Smuzhiyun snd_soc_component_update_bits(component,
916*4882a593Smuzhiyun RT298_I2S_CTRL2, 0x8, 0x8);
917*4882a593Smuzhiyun snd_soc_component_update_bits(component,
918*4882a593Smuzhiyun RT298_CLK_DIV, 0xfc1e, 0x5406);
919*4882a593Smuzhiyun break;
920*4882a593Smuzhiyun default:
921*4882a593Smuzhiyun dev_err(component->dev, "Unsupported system clock\n");
922*4882a593Smuzhiyun return -EINVAL;
923*4882a593Smuzhiyun }
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun rt298->sys_clk = freq;
926*4882a593Smuzhiyun rt298->clk_id = clk_id;
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun return 0;
929*4882a593Smuzhiyun }
930*4882a593Smuzhiyun
rt298_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)931*4882a593Smuzhiyun static int rt298_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
932*4882a593Smuzhiyun {
933*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
936*4882a593Smuzhiyun if (50 == ratio)
937*4882a593Smuzhiyun snd_soc_component_update_bits(component,
938*4882a593Smuzhiyun RT298_I2S_CTRL1, 0x1000, 0x1000);
939*4882a593Smuzhiyun else
940*4882a593Smuzhiyun snd_soc_component_update_bits(component,
941*4882a593Smuzhiyun RT298_I2S_CTRL1, 0x1000, 0x0);
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun return 0;
945*4882a593Smuzhiyun }
946*4882a593Smuzhiyun
rt298_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)947*4882a593Smuzhiyun static int rt298_set_bias_level(struct snd_soc_component *component,
948*4882a593Smuzhiyun enum snd_soc_bias_level level)
949*4882a593Smuzhiyun {
950*4882a593Smuzhiyun switch (level) {
951*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
952*4882a593Smuzhiyun if (SND_SOC_BIAS_STANDBY ==
953*4882a593Smuzhiyun snd_soc_component_get_bias_level(component)) {
954*4882a593Smuzhiyun snd_soc_component_write(component,
955*4882a593Smuzhiyun RT298_SET_AUDIO_POWER, AC_PWRST_D0);
956*4882a593Smuzhiyun snd_soc_component_update_bits(component, 0x0d, 0x200, 0x200);
957*4882a593Smuzhiyun snd_soc_component_update_bits(component, 0x52, 0x80, 0x0);
958*4882a593Smuzhiyun mdelay(20);
959*4882a593Smuzhiyun snd_soc_component_update_bits(component, 0x0d, 0x200, 0x0);
960*4882a593Smuzhiyun snd_soc_component_update_bits(component, 0x52, 0x80, 0x80);
961*4882a593Smuzhiyun }
962*4882a593Smuzhiyun break;
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
965*4882a593Smuzhiyun snd_soc_component_write(component,
966*4882a593Smuzhiyun RT298_SET_AUDIO_POWER, AC_PWRST_D3);
967*4882a593Smuzhiyun break;
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun default:
970*4882a593Smuzhiyun break;
971*4882a593Smuzhiyun }
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun return 0;
974*4882a593Smuzhiyun }
975*4882a593Smuzhiyun
rt298_irq(int irq,void * data)976*4882a593Smuzhiyun static irqreturn_t rt298_irq(int irq, void *data)
977*4882a593Smuzhiyun {
978*4882a593Smuzhiyun struct rt298_priv *rt298 = data;
979*4882a593Smuzhiyun bool hp = false;
980*4882a593Smuzhiyun bool mic = false;
981*4882a593Smuzhiyun int ret, status = 0;
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun ret = rt298_jack_detect(rt298, &hp, &mic);
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun /* Clear IRQ */
986*4882a593Smuzhiyun regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x1, 0x1);
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun if (ret == 0) {
989*4882a593Smuzhiyun if (hp)
990*4882a593Smuzhiyun status |= SND_JACK_HEADPHONE;
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun if (mic)
993*4882a593Smuzhiyun status |= SND_JACK_MICROPHONE;
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun snd_soc_jack_report(rt298->jack, status,
996*4882a593Smuzhiyun SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun pm_wakeup_event(&rt298->i2c->dev, 300);
999*4882a593Smuzhiyun }
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun return IRQ_HANDLED;
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun
rt298_probe(struct snd_soc_component * component)1004*4882a593Smuzhiyun static int rt298_probe(struct snd_soc_component *component)
1005*4882a593Smuzhiyun {
1006*4882a593Smuzhiyun struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun rt298->component = component;
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun if (rt298->i2c->irq) {
1011*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
1012*4882a593Smuzhiyun RT298_IRQ_CTRL, 0x2, 0x2);
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun INIT_DELAYED_WORK(&rt298->jack_detect_work,
1015*4882a593Smuzhiyun rt298_jack_detect_work);
1016*4882a593Smuzhiyun schedule_delayed_work(&rt298->jack_detect_work,
1017*4882a593Smuzhiyun msecs_to_jiffies(1250));
1018*4882a593Smuzhiyun }
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun return 0;
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun
rt298_remove(struct snd_soc_component * component)1023*4882a593Smuzhiyun static void rt298_remove(struct snd_soc_component *component)
1024*4882a593Smuzhiyun {
1025*4882a593Smuzhiyun struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun cancel_delayed_work_sync(&rt298->jack_detect_work);
1028*4882a593Smuzhiyun }
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun #ifdef CONFIG_PM
rt298_suspend(struct snd_soc_component * component)1031*4882a593Smuzhiyun static int rt298_suspend(struct snd_soc_component *component)
1032*4882a593Smuzhiyun {
1033*4882a593Smuzhiyun struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun rt298->is_hp_in = -1;
1036*4882a593Smuzhiyun regcache_cache_only(rt298->regmap, true);
1037*4882a593Smuzhiyun regcache_mark_dirty(rt298->regmap);
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun return 0;
1040*4882a593Smuzhiyun }
1041*4882a593Smuzhiyun
rt298_resume(struct snd_soc_component * component)1042*4882a593Smuzhiyun static int rt298_resume(struct snd_soc_component *component)
1043*4882a593Smuzhiyun {
1044*4882a593Smuzhiyun struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun regcache_cache_only(rt298->regmap, false);
1047*4882a593Smuzhiyun rt298_index_sync(component);
1048*4882a593Smuzhiyun regcache_sync(rt298->regmap);
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun return 0;
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun #else
1053*4882a593Smuzhiyun #define rt298_suspend NULL
1054*4882a593Smuzhiyun #define rt298_resume NULL
1055*4882a593Smuzhiyun #endif
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun #define RT298_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1058*4882a593Smuzhiyun #define RT298_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1059*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun static const struct snd_soc_dai_ops rt298_aif_dai_ops = {
1062*4882a593Smuzhiyun .hw_params = rt298_hw_params,
1063*4882a593Smuzhiyun .set_fmt = rt298_set_dai_fmt,
1064*4882a593Smuzhiyun .set_sysclk = rt298_set_dai_sysclk,
1065*4882a593Smuzhiyun .set_bclk_ratio = rt298_set_bclk_ratio,
1066*4882a593Smuzhiyun };
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun static struct snd_soc_dai_driver rt298_dai[] = {
1069*4882a593Smuzhiyun {
1070*4882a593Smuzhiyun .name = "rt298-aif1",
1071*4882a593Smuzhiyun .id = RT298_AIF1,
1072*4882a593Smuzhiyun .playback = {
1073*4882a593Smuzhiyun .stream_name = "AIF1 Playback",
1074*4882a593Smuzhiyun .channels_min = 1,
1075*4882a593Smuzhiyun .channels_max = 2,
1076*4882a593Smuzhiyun .rates = RT298_STEREO_RATES,
1077*4882a593Smuzhiyun .formats = RT298_FORMATS,
1078*4882a593Smuzhiyun },
1079*4882a593Smuzhiyun .capture = {
1080*4882a593Smuzhiyun .stream_name = "AIF1 Capture",
1081*4882a593Smuzhiyun .channels_min = 1,
1082*4882a593Smuzhiyun .channels_max = 2,
1083*4882a593Smuzhiyun .rates = RT298_STEREO_RATES,
1084*4882a593Smuzhiyun .formats = RT298_FORMATS,
1085*4882a593Smuzhiyun },
1086*4882a593Smuzhiyun .ops = &rt298_aif_dai_ops,
1087*4882a593Smuzhiyun .symmetric_rates = 1,
1088*4882a593Smuzhiyun },
1089*4882a593Smuzhiyun {
1090*4882a593Smuzhiyun .name = "rt298-aif2",
1091*4882a593Smuzhiyun .id = RT298_AIF2,
1092*4882a593Smuzhiyun .playback = {
1093*4882a593Smuzhiyun .stream_name = "AIF2 Playback",
1094*4882a593Smuzhiyun .channels_min = 1,
1095*4882a593Smuzhiyun .channels_max = 2,
1096*4882a593Smuzhiyun .rates = RT298_STEREO_RATES,
1097*4882a593Smuzhiyun .formats = RT298_FORMATS,
1098*4882a593Smuzhiyun },
1099*4882a593Smuzhiyun .capture = {
1100*4882a593Smuzhiyun .stream_name = "AIF2 Capture",
1101*4882a593Smuzhiyun .channels_min = 1,
1102*4882a593Smuzhiyun .channels_max = 2,
1103*4882a593Smuzhiyun .rates = RT298_STEREO_RATES,
1104*4882a593Smuzhiyun .formats = RT298_FORMATS,
1105*4882a593Smuzhiyun },
1106*4882a593Smuzhiyun .ops = &rt298_aif_dai_ops,
1107*4882a593Smuzhiyun .symmetric_rates = 1,
1108*4882a593Smuzhiyun },
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun };
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_rt298 = {
1113*4882a593Smuzhiyun .probe = rt298_probe,
1114*4882a593Smuzhiyun .remove = rt298_remove,
1115*4882a593Smuzhiyun .suspend = rt298_suspend,
1116*4882a593Smuzhiyun .resume = rt298_resume,
1117*4882a593Smuzhiyun .set_bias_level = rt298_set_bias_level,
1118*4882a593Smuzhiyun .controls = rt298_snd_controls,
1119*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(rt298_snd_controls),
1120*4882a593Smuzhiyun .dapm_widgets = rt298_dapm_widgets,
1121*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(rt298_dapm_widgets),
1122*4882a593Smuzhiyun .dapm_routes = rt298_dapm_routes,
1123*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(rt298_dapm_routes),
1124*4882a593Smuzhiyun .use_pmdown_time = 1,
1125*4882a593Smuzhiyun .endianness = 1,
1126*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
1127*4882a593Smuzhiyun };
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun static const struct regmap_config rt298_regmap = {
1130*4882a593Smuzhiyun .reg_bits = 32,
1131*4882a593Smuzhiyun .val_bits = 32,
1132*4882a593Smuzhiyun .max_register = 0x02370100,
1133*4882a593Smuzhiyun .volatile_reg = rt298_volatile_register,
1134*4882a593Smuzhiyun .readable_reg = rt298_readable_register,
1135*4882a593Smuzhiyun .reg_write = rl6347a_hw_write,
1136*4882a593Smuzhiyun .reg_read = rl6347a_hw_read,
1137*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
1138*4882a593Smuzhiyun .reg_defaults = rt298_reg,
1139*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(rt298_reg),
1140*4882a593Smuzhiyun };
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun static const struct i2c_device_id rt298_i2c_id[] = {
1143*4882a593Smuzhiyun {"rt298", 0},
1144*4882a593Smuzhiyun {}
1145*4882a593Smuzhiyun };
1146*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, rt298_i2c_id);
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun #ifdef CONFIG_ACPI
1149*4882a593Smuzhiyun static const struct acpi_device_id rt298_acpi_match[] = {
1150*4882a593Smuzhiyun { "INT343A", 0 },
1151*4882a593Smuzhiyun {},
1152*4882a593Smuzhiyun };
1153*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, rt298_acpi_match);
1154*4882a593Smuzhiyun #endif
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun static const struct dmi_system_id force_combo_jack_table[] = {
1157*4882a593Smuzhiyun {
1158*4882a593Smuzhiyun .ident = "Intel Broxton P",
1159*4882a593Smuzhiyun .matches = {
1160*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"),
1161*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "Broxton P")
1162*4882a593Smuzhiyun }
1163*4882a593Smuzhiyun },
1164*4882a593Smuzhiyun {
1165*4882a593Smuzhiyun .ident = "Intel Gemini Lake",
1166*4882a593Smuzhiyun .matches = {
1167*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"),
1168*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "Geminilake")
1169*4882a593Smuzhiyun }
1170*4882a593Smuzhiyun },
1171*4882a593Smuzhiyun { }
1172*4882a593Smuzhiyun };
1173*4882a593Smuzhiyun
rt298_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1174*4882a593Smuzhiyun static int rt298_i2c_probe(struct i2c_client *i2c,
1175*4882a593Smuzhiyun const struct i2c_device_id *id)
1176*4882a593Smuzhiyun {
1177*4882a593Smuzhiyun struct rt298_platform_data *pdata = dev_get_platdata(&i2c->dev);
1178*4882a593Smuzhiyun struct rt298_priv *rt298;
1179*4882a593Smuzhiyun struct device *dev = &i2c->dev;
1180*4882a593Smuzhiyun const struct acpi_device_id *acpiid;
1181*4882a593Smuzhiyun int i, ret;
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun rt298 = devm_kzalloc(&i2c->dev, sizeof(*rt298),
1184*4882a593Smuzhiyun GFP_KERNEL);
1185*4882a593Smuzhiyun if (NULL == rt298)
1186*4882a593Smuzhiyun return -ENOMEM;
1187*4882a593Smuzhiyun
1188*4882a593Smuzhiyun rt298->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt298_regmap);
1189*4882a593Smuzhiyun if (IS_ERR(rt298->regmap)) {
1190*4882a593Smuzhiyun ret = PTR_ERR(rt298->regmap);
1191*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1192*4882a593Smuzhiyun ret);
1193*4882a593Smuzhiyun return ret;
1194*4882a593Smuzhiyun }
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun regmap_read(rt298->regmap,
1197*4882a593Smuzhiyun RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
1198*4882a593Smuzhiyun if (ret != RT298_VENDOR_ID) {
1199*4882a593Smuzhiyun dev_err(&i2c->dev,
1200*4882a593Smuzhiyun "Device with ID register %#x is not rt298\n", ret);
1201*4882a593Smuzhiyun return -ENODEV;
1202*4882a593Smuzhiyun }
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun rt298->index_cache = devm_kmemdup(&i2c->dev, rt298_index_def,
1205*4882a593Smuzhiyun sizeof(rt298_index_def), GFP_KERNEL);
1206*4882a593Smuzhiyun if (!rt298->index_cache)
1207*4882a593Smuzhiyun return -ENOMEM;
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun rt298->index_cache_size = INDEX_CACHE_SIZE;
1210*4882a593Smuzhiyun rt298->i2c = i2c;
1211*4882a593Smuzhiyun i2c_set_clientdata(i2c, rt298);
1212*4882a593Smuzhiyun
1213*4882a593Smuzhiyun /* restore codec default */
1214*4882a593Smuzhiyun for (i = 0; i < INDEX_CACHE_SIZE; i++)
1215*4882a593Smuzhiyun regmap_write(rt298->regmap, rt298->index_cache[i].reg,
1216*4882a593Smuzhiyun rt298->index_cache[i].def);
1217*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(rt298_reg); i++)
1218*4882a593Smuzhiyun regmap_write(rt298->regmap, rt298_reg[i].reg,
1219*4882a593Smuzhiyun rt298_reg[i].def);
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun if (pdata)
1222*4882a593Smuzhiyun rt298->pdata = *pdata;
1223*4882a593Smuzhiyun
1224*4882a593Smuzhiyun /* enable jack combo mode on supported devices */
1225*4882a593Smuzhiyun acpiid = acpi_match_device(dev->driver->acpi_match_table, dev);
1226*4882a593Smuzhiyun if (acpiid && acpiid->driver_data) {
1227*4882a593Smuzhiyun rt298->pdata = *(struct rt298_platform_data *)
1228*4882a593Smuzhiyun acpiid->driver_data;
1229*4882a593Smuzhiyun }
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun if (dmi_check_system(force_combo_jack_table)) {
1232*4882a593Smuzhiyun rt298->pdata.cbj_en = true;
1233*4882a593Smuzhiyun rt298->pdata.gpio2_en = false;
1234*4882a593Smuzhiyun }
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun /* VREF Charging */
1237*4882a593Smuzhiyun regmap_update_bits(rt298->regmap, 0x04, 0x80, 0x80);
1238*4882a593Smuzhiyun regmap_update_bits(rt298->regmap, 0x1b, 0x860, 0x860);
1239*4882a593Smuzhiyun /* Vref2 */
1240*4882a593Smuzhiyun regmap_update_bits(rt298->regmap, 0x08, 0x20, 0x20);
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_SET_AUDIO_POWER, AC_PWRST_D3);
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun for (i = 0; i < RT298_POWER_REG_LEN; i++)
1245*4882a593Smuzhiyun regmap_write(rt298->regmap,
1246*4882a593Smuzhiyun RT298_SET_POWER(rt298_support_power_controls[i]),
1247*4882a593Smuzhiyun AC_PWRST_D1);
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun if (!rt298->pdata.cbj_en) {
1250*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_CBJ_CTRL2, 0x0000);
1251*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_MIC1_DET_CTRL, 0x0816);
1252*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
1253*4882a593Smuzhiyun RT298_CBJ_CTRL1, 0xf000, 0xb000);
1254*4882a593Smuzhiyun } else {
1255*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
1256*4882a593Smuzhiyun RT298_CBJ_CTRL1, 0xf000, 0x5000);
1257*4882a593Smuzhiyun }
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun mdelay(10);
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun if (!rt298->pdata.gpio2_en)
1262*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0x40);
1263*4882a593Smuzhiyun else
1264*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0);
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun mdelay(10);
1267*4882a593Smuzhiyun
1268*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_MISC_CTRL1, 0x0000);
1269*4882a593Smuzhiyun regmap_update_bits(rt298->regmap,
1270*4882a593Smuzhiyun RT298_WIND_FILTER_CTRL, 0x0082, 0x0082);
1271*4882a593Smuzhiyun
1272*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_UNSOLICITED_INLINE_CMD, 0x81);
1273*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_UNSOLICITED_HP_OUT, 0x82);
1274*4882a593Smuzhiyun regmap_write(rt298->regmap, RT298_UNSOLICITED_MIC1, 0x84);
1275*4882a593Smuzhiyun regmap_update_bits(rt298->regmap, RT298_IRQ_FLAG_CTRL, 0x2, 0x2);
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun rt298->is_hp_in = -1;
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun if (rt298->i2c->irq) {
1280*4882a593Smuzhiyun ret = request_threaded_irq(rt298->i2c->irq, NULL, rt298_irq,
1281*4882a593Smuzhiyun IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt298", rt298);
1282*4882a593Smuzhiyun if (ret != 0) {
1283*4882a593Smuzhiyun dev_err(&i2c->dev,
1284*4882a593Smuzhiyun "Failed to reguest IRQ: %d\n", ret);
1285*4882a593Smuzhiyun return ret;
1286*4882a593Smuzhiyun }
1287*4882a593Smuzhiyun }
1288*4882a593Smuzhiyun
1289*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev,
1290*4882a593Smuzhiyun &soc_component_dev_rt298,
1291*4882a593Smuzhiyun rt298_dai, ARRAY_SIZE(rt298_dai));
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun return ret;
1294*4882a593Smuzhiyun }
1295*4882a593Smuzhiyun
rt298_i2c_remove(struct i2c_client * i2c)1296*4882a593Smuzhiyun static int rt298_i2c_remove(struct i2c_client *i2c)
1297*4882a593Smuzhiyun {
1298*4882a593Smuzhiyun struct rt298_priv *rt298 = i2c_get_clientdata(i2c);
1299*4882a593Smuzhiyun
1300*4882a593Smuzhiyun if (i2c->irq)
1301*4882a593Smuzhiyun free_irq(i2c->irq, rt298);
1302*4882a593Smuzhiyun
1303*4882a593Smuzhiyun return 0;
1304*4882a593Smuzhiyun }
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun static struct i2c_driver rt298_i2c_driver = {
1308*4882a593Smuzhiyun .driver = {
1309*4882a593Smuzhiyun .name = "rt298",
1310*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(rt298_acpi_match),
1311*4882a593Smuzhiyun },
1312*4882a593Smuzhiyun .probe = rt298_i2c_probe,
1313*4882a593Smuzhiyun .remove = rt298_i2c_remove,
1314*4882a593Smuzhiyun .id_table = rt298_i2c_id,
1315*4882a593Smuzhiyun };
1316*4882a593Smuzhiyun
1317*4882a593Smuzhiyun module_i2c_driver(rt298_i2c_driver);
1318*4882a593Smuzhiyun
1319*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC RT298 driver");
1320*4882a593Smuzhiyun MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1321*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1322