1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * rt286.c -- RT286 ALSA SoC audio codec driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2013 Realtek Semiconductor Corp.
6*4882a593Smuzhiyun * Author: Bard Liao <bardliao@realtek.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/moduleparam.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/pm.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/spi/spi.h>
17*4882a593Smuzhiyun #include <linux/dmi.h>
18*4882a593Smuzhiyun #include <linux/acpi.h>
19*4882a593Smuzhiyun #include <sound/core.h>
20*4882a593Smuzhiyun #include <sound/pcm.h>
21*4882a593Smuzhiyun #include <sound/pcm_params.h>
22*4882a593Smuzhiyun #include <sound/soc.h>
23*4882a593Smuzhiyun #include <sound/soc-dapm.h>
24*4882a593Smuzhiyun #include <sound/initval.h>
25*4882a593Smuzhiyun #include <sound/tlv.h>
26*4882a593Smuzhiyun #include <sound/jack.h>
27*4882a593Smuzhiyun #include <linux/workqueue.h>
28*4882a593Smuzhiyun #include <sound/rt286.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "rl6347a.h"
31*4882a593Smuzhiyun #include "rt286.h"
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define RT286_VENDOR_ID 0x10ec0286
34*4882a593Smuzhiyun #define RT288_VENDOR_ID 0x10ec0288
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct rt286_priv {
37*4882a593Smuzhiyun struct reg_default *index_cache;
38*4882a593Smuzhiyun int index_cache_size;
39*4882a593Smuzhiyun struct regmap *regmap;
40*4882a593Smuzhiyun struct snd_soc_component *component;
41*4882a593Smuzhiyun struct rt286_platform_data pdata;
42*4882a593Smuzhiyun struct i2c_client *i2c;
43*4882a593Smuzhiyun struct snd_soc_jack *jack;
44*4882a593Smuzhiyun struct delayed_work jack_detect_work;
45*4882a593Smuzhiyun int sys_clk;
46*4882a593Smuzhiyun int clk_id;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static const struct reg_default rt286_index_def[] = {
50*4882a593Smuzhiyun { 0x01, 0xaaaa },
51*4882a593Smuzhiyun { 0x02, 0x8aaa },
52*4882a593Smuzhiyun { 0x03, 0x0002 },
53*4882a593Smuzhiyun { 0x04, 0xaf01 },
54*4882a593Smuzhiyun { 0x08, 0x000d },
55*4882a593Smuzhiyun { 0x09, 0xd810 },
56*4882a593Smuzhiyun { 0x0a, 0x0120 },
57*4882a593Smuzhiyun { 0x0b, 0x0000 },
58*4882a593Smuzhiyun { 0x0d, 0x2800 },
59*4882a593Smuzhiyun { 0x0f, 0x0000 },
60*4882a593Smuzhiyun { 0x19, 0x0a17 },
61*4882a593Smuzhiyun { 0x20, 0x0020 },
62*4882a593Smuzhiyun { 0x33, 0x0208 },
63*4882a593Smuzhiyun { 0x49, 0x0004 },
64*4882a593Smuzhiyun { 0x4f, 0x50e9 },
65*4882a593Smuzhiyun { 0x50, 0x2000 },
66*4882a593Smuzhiyun { 0x63, 0x2902 },
67*4882a593Smuzhiyun { 0x67, 0x1111 },
68*4882a593Smuzhiyun { 0x68, 0x1016 },
69*4882a593Smuzhiyun { 0x69, 0x273f },
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static const struct reg_default rt286_reg[] = {
74*4882a593Smuzhiyun { 0x00170500, 0x00000400 },
75*4882a593Smuzhiyun { 0x00220000, 0x00000031 },
76*4882a593Smuzhiyun { 0x00239000, 0x0000007f },
77*4882a593Smuzhiyun { 0x0023a000, 0x0000007f },
78*4882a593Smuzhiyun { 0x00270500, 0x00000400 },
79*4882a593Smuzhiyun { 0x00370500, 0x00000400 },
80*4882a593Smuzhiyun { 0x00870500, 0x00000400 },
81*4882a593Smuzhiyun { 0x00920000, 0x00000031 },
82*4882a593Smuzhiyun { 0x00935000, 0x000000c3 },
83*4882a593Smuzhiyun { 0x00936000, 0x000000c3 },
84*4882a593Smuzhiyun { 0x00970500, 0x00000400 },
85*4882a593Smuzhiyun { 0x00b37000, 0x00000097 },
86*4882a593Smuzhiyun { 0x00b37200, 0x00000097 },
87*4882a593Smuzhiyun { 0x00b37300, 0x00000097 },
88*4882a593Smuzhiyun { 0x00c37000, 0x00000000 },
89*4882a593Smuzhiyun { 0x00c37100, 0x00000080 },
90*4882a593Smuzhiyun { 0x01270500, 0x00000400 },
91*4882a593Smuzhiyun { 0x01370500, 0x00000400 },
92*4882a593Smuzhiyun { 0x01371f00, 0x411111f0 },
93*4882a593Smuzhiyun { 0x01439000, 0x00000080 },
94*4882a593Smuzhiyun { 0x0143a000, 0x00000080 },
95*4882a593Smuzhiyun { 0x01470700, 0x00000000 },
96*4882a593Smuzhiyun { 0x01470500, 0x00000400 },
97*4882a593Smuzhiyun { 0x01470c00, 0x00000000 },
98*4882a593Smuzhiyun { 0x01470100, 0x00000000 },
99*4882a593Smuzhiyun { 0x01837000, 0x00000000 },
100*4882a593Smuzhiyun { 0x01870500, 0x00000400 },
101*4882a593Smuzhiyun { 0x02050000, 0x00000000 },
102*4882a593Smuzhiyun { 0x02139000, 0x00000080 },
103*4882a593Smuzhiyun { 0x0213a000, 0x00000080 },
104*4882a593Smuzhiyun { 0x02170100, 0x00000000 },
105*4882a593Smuzhiyun { 0x02170500, 0x00000400 },
106*4882a593Smuzhiyun { 0x02170700, 0x00000000 },
107*4882a593Smuzhiyun { 0x02270100, 0x00000000 },
108*4882a593Smuzhiyun { 0x02370100, 0x00000000 },
109*4882a593Smuzhiyun { 0x01870700, 0x00000020 },
110*4882a593Smuzhiyun { 0x00830000, 0x000000c3 },
111*4882a593Smuzhiyun { 0x00930000, 0x000000c3 },
112*4882a593Smuzhiyun { 0x01270700, 0x00000000 },
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
rt286_volatile_register(struct device * dev,unsigned int reg)115*4882a593Smuzhiyun static bool rt286_volatile_register(struct device *dev, unsigned int reg)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun switch (reg) {
118*4882a593Smuzhiyun case 0 ... 0xff:
119*4882a593Smuzhiyun case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
120*4882a593Smuzhiyun case RT286_GET_HP_SENSE:
121*4882a593Smuzhiyun case RT286_GET_MIC1_SENSE:
122*4882a593Smuzhiyun case RT286_PROC_COEF:
123*4882a593Smuzhiyun return true;
124*4882a593Smuzhiyun default:
125*4882a593Smuzhiyun return false;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
rt286_readable_register(struct device * dev,unsigned int reg)131*4882a593Smuzhiyun static bool rt286_readable_register(struct device *dev, unsigned int reg)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun switch (reg) {
134*4882a593Smuzhiyun case 0 ... 0xff:
135*4882a593Smuzhiyun case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
136*4882a593Smuzhiyun case RT286_GET_HP_SENSE:
137*4882a593Smuzhiyun case RT286_GET_MIC1_SENSE:
138*4882a593Smuzhiyun case RT286_SET_AUDIO_POWER:
139*4882a593Smuzhiyun case RT286_SET_HPO_POWER:
140*4882a593Smuzhiyun case RT286_SET_SPK_POWER:
141*4882a593Smuzhiyun case RT286_SET_DMIC1_POWER:
142*4882a593Smuzhiyun case RT286_SPK_MUX:
143*4882a593Smuzhiyun case RT286_HPO_MUX:
144*4882a593Smuzhiyun case RT286_ADC0_MUX:
145*4882a593Smuzhiyun case RT286_ADC1_MUX:
146*4882a593Smuzhiyun case RT286_SET_MIC1:
147*4882a593Smuzhiyun case RT286_SET_PIN_HPO:
148*4882a593Smuzhiyun case RT286_SET_PIN_SPK:
149*4882a593Smuzhiyun case RT286_SET_PIN_DMIC1:
150*4882a593Smuzhiyun case RT286_SPK_EAPD:
151*4882a593Smuzhiyun case RT286_SET_AMP_GAIN_HPO:
152*4882a593Smuzhiyun case RT286_SET_DMIC2_DEFAULT:
153*4882a593Smuzhiyun case RT286_DACL_GAIN:
154*4882a593Smuzhiyun case RT286_DACR_GAIN:
155*4882a593Smuzhiyun case RT286_ADCL_GAIN:
156*4882a593Smuzhiyun case RT286_ADCR_GAIN:
157*4882a593Smuzhiyun case RT286_MIC_GAIN:
158*4882a593Smuzhiyun case RT286_SPOL_GAIN:
159*4882a593Smuzhiyun case RT286_SPOR_GAIN:
160*4882a593Smuzhiyun case RT286_HPOL_GAIN:
161*4882a593Smuzhiyun case RT286_HPOR_GAIN:
162*4882a593Smuzhiyun case RT286_F_DAC_SWITCH:
163*4882a593Smuzhiyun case RT286_F_RECMIX_SWITCH:
164*4882a593Smuzhiyun case RT286_REC_MIC_SWITCH:
165*4882a593Smuzhiyun case RT286_REC_I2S_SWITCH:
166*4882a593Smuzhiyun case RT286_REC_LINE_SWITCH:
167*4882a593Smuzhiyun case RT286_REC_BEEP_SWITCH:
168*4882a593Smuzhiyun case RT286_DAC_FORMAT:
169*4882a593Smuzhiyun case RT286_ADC_FORMAT:
170*4882a593Smuzhiyun case RT286_COEF_INDEX:
171*4882a593Smuzhiyun case RT286_PROC_COEF:
172*4882a593Smuzhiyun case RT286_SET_AMP_GAIN_ADC_IN1:
173*4882a593Smuzhiyun case RT286_SET_AMP_GAIN_ADC_IN2:
174*4882a593Smuzhiyun case RT286_SET_GPIO_MASK:
175*4882a593Smuzhiyun case RT286_SET_GPIO_DIRECTION:
176*4882a593Smuzhiyun case RT286_SET_GPIO_DATA:
177*4882a593Smuzhiyun case RT286_SET_POWER(RT286_DAC_OUT1):
178*4882a593Smuzhiyun case RT286_SET_POWER(RT286_DAC_OUT2):
179*4882a593Smuzhiyun case RT286_SET_POWER(RT286_ADC_IN1):
180*4882a593Smuzhiyun case RT286_SET_POWER(RT286_ADC_IN2):
181*4882a593Smuzhiyun case RT286_SET_POWER(RT286_DMIC2):
182*4882a593Smuzhiyun case RT286_SET_POWER(RT286_MIC1):
183*4882a593Smuzhiyun return true;
184*4882a593Smuzhiyun default:
185*4882a593Smuzhiyun return false;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun #ifdef CONFIG_PM
rt286_index_sync(struct snd_soc_component * component)190*4882a593Smuzhiyun static void rt286_index_sync(struct snd_soc_component *component)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
193*4882a593Smuzhiyun int i;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun for (i = 0; i < INDEX_CACHE_SIZE; i++) {
196*4882a593Smuzhiyun snd_soc_component_write(component, rt286->index_cache[i].reg,
197*4882a593Smuzhiyun rt286->index_cache[i].def);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun #endif
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun static int rt286_support_power_controls[] = {
203*4882a593Smuzhiyun RT286_DAC_OUT1,
204*4882a593Smuzhiyun RT286_DAC_OUT2,
205*4882a593Smuzhiyun RT286_ADC_IN1,
206*4882a593Smuzhiyun RT286_ADC_IN2,
207*4882a593Smuzhiyun RT286_MIC1,
208*4882a593Smuzhiyun RT286_DMIC1,
209*4882a593Smuzhiyun RT286_DMIC2,
210*4882a593Smuzhiyun RT286_SPK_OUT,
211*4882a593Smuzhiyun RT286_HP_OUT,
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
214*4882a593Smuzhiyun
rt286_jack_detect(struct rt286_priv * rt286,bool * hp,bool * mic)215*4882a593Smuzhiyun static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm;
218*4882a593Smuzhiyun unsigned int val, buf;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun *hp = false;
221*4882a593Smuzhiyun *mic = false;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun if (!rt286->component)
224*4882a593Smuzhiyun return -EINVAL;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun dapm = snd_soc_component_get_dapm(rt286->component);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun if (rt286->pdata.cbj_en) {
229*4882a593Smuzhiyun regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
230*4882a593Smuzhiyun *hp = buf & 0x80000000;
231*4882a593Smuzhiyun if (*hp) {
232*4882a593Smuzhiyun /* power on HV,VERF */
233*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
234*4882a593Smuzhiyun RT286_DC_GAIN, 0x200, 0x200);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun snd_soc_dapm_force_enable_pin(dapm, "HV");
237*4882a593Smuzhiyun snd_soc_dapm_force_enable_pin(dapm, "VREF");
238*4882a593Smuzhiyun /* power LDO1 */
239*4882a593Smuzhiyun snd_soc_dapm_force_enable_pin(dapm, "LDO1");
240*4882a593Smuzhiyun snd_soc_dapm_sync(dapm);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
243*4882a593Smuzhiyun msleep(50);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
246*4882a593Smuzhiyun RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
247*4882a593Smuzhiyun msleep(300);
248*4882a593Smuzhiyun regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun if (0x0070 == (val & 0x0070)) {
251*4882a593Smuzhiyun *mic = true;
252*4882a593Smuzhiyun } else {
253*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
254*4882a593Smuzhiyun RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
255*4882a593Smuzhiyun msleep(300);
256*4882a593Smuzhiyun regmap_read(rt286->regmap,
257*4882a593Smuzhiyun RT286_CBJ_CTRL2, &val);
258*4882a593Smuzhiyun if (0x0070 == (val & 0x0070))
259*4882a593Smuzhiyun *mic = true;
260*4882a593Smuzhiyun else
261*4882a593Smuzhiyun *mic = false;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
264*4882a593Smuzhiyun RT286_DC_GAIN, 0x200, 0x0);
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun } else {
267*4882a593Smuzhiyun *mic = false;
268*4882a593Smuzhiyun regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
269*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
270*4882a593Smuzhiyun RT286_CBJ_CTRL1, 0x0400, 0x0000);
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun } else {
273*4882a593Smuzhiyun regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
274*4882a593Smuzhiyun *hp = buf & 0x80000000;
275*4882a593Smuzhiyun regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
276*4882a593Smuzhiyun *mic = buf & 0x80000000;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun if (!*hp) {
280*4882a593Smuzhiyun snd_soc_dapm_disable_pin(dapm, "HV");
281*4882a593Smuzhiyun snd_soc_dapm_disable_pin(dapm, "VREF");
282*4882a593Smuzhiyun snd_soc_dapm_disable_pin(dapm, "LDO1");
283*4882a593Smuzhiyun snd_soc_dapm_sync(dapm);
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun return 0;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
rt286_jack_detect_work(struct work_struct * work)289*4882a593Smuzhiyun static void rt286_jack_detect_work(struct work_struct *work)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun struct rt286_priv *rt286 =
292*4882a593Smuzhiyun container_of(work, struct rt286_priv, jack_detect_work.work);
293*4882a593Smuzhiyun int status = 0;
294*4882a593Smuzhiyun bool hp = false;
295*4882a593Smuzhiyun bool mic = false;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun rt286_jack_detect(rt286, &hp, &mic);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun if (hp)
300*4882a593Smuzhiyun status |= SND_JACK_HEADPHONE;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun if (mic)
303*4882a593Smuzhiyun status |= SND_JACK_MICROPHONE;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun snd_soc_jack_report(rt286->jack, status,
306*4882a593Smuzhiyun SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
rt286_mic_detect(struct snd_soc_component * component,struct snd_soc_jack * jack)309*4882a593Smuzhiyun int rt286_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
312*4882a593Smuzhiyun struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun rt286->jack = jack;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun if (jack) {
317*4882a593Smuzhiyun /* enable IRQ */
318*4882a593Smuzhiyun if (rt286->jack->status & SND_JACK_HEADPHONE)
319*4882a593Smuzhiyun snd_soc_dapm_force_enable_pin(dapm, "LDO1");
320*4882a593Smuzhiyun regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
321*4882a593Smuzhiyun /* Send an initial empty report */
322*4882a593Smuzhiyun snd_soc_jack_report(rt286->jack, rt286->jack->status,
323*4882a593Smuzhiyun SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
324*4882a593Smuzhiyun } else {
325*4882a593Smuzhiyun /* disable IRQ */
326*4882a593Smuzhiyun regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
327*4882a593Smuzhiyun snd_soc_dapm_disable_pin(dapm, "LDO1");
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun snd_soc_dapm_sync(dapm);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun return 0;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt286_mic_detect);
334*4882a593Smuzhiyun
is_mclk_mode(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)335*4882a593Smuzhiyun static int is_mclk_mode(struct snd_soc_dapm_widget *source,
336*4882a593Smuzhiyun struct snd_soc_dapm_widget *sink)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
339*4882a593Smuzhiyun struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun if (rt286->clk_id == RT286_SCLK_S_MCLK)
342*4882a593Smuzhiyun return 1;
343*4882a593Smuzhiyun else
344*4882a593Smuzhiyun return 0;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
348*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun static const struct snd_kcontrol_new rt286_snd_controls[] = {
351*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
352*4882a593Smuzhiyun RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
353*4882a593Smuzhiyun SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
354*4882a593Smuzhiyun RT286_ADCR_GAIN, 7, 1, 1),
355*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
356*4882a593Smuzhiyun RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
357*4882a593Smuzhiyun SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
358*4882a593Smuzhiyun 0, 0x3, 0, mic_vol_tlv),
359*4882a593Smuzhiyun SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
360*4882a593Smuzhiyun RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun /* Digital Mixer */
364*4882a593Smuzhiyun static const struct snd_kcontrol_new rt286_front_mix[] = {
365*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
366*4882a593Smuzhiyun RT286_MUTE_SFT, 1, 1),
367*4882a593Smuzhiyun SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
368*4882a593Smuzhiyun RT286_MUTE_SFT, 1, 1),
369*4882a593Smuzhiyun };
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun /* Analog Input Mixer */
372*4882a593Smuzhiyun static const struct snd_kcontrol_new rt286_rec_mix[] = {
373*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
374*4882a593Smuzhiyun RT286_MUTE_SFT, 1, 1),
375*4882a593Smuzhiyun SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
376*4882a593Smuzhiyun RT286_MUTE_SFT, 1, 1),
377*4882a593Smuzhiyun SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
378*4882a593Smuzhiyun RT286_MUTE_SFT, 1, 1),
379*4882a593Smuzhiyun SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
380*4882a593Smuzhiyun RT286_MUTE_SFT, 1, 1),
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun static const struct snd_kcontrol_new spo_enable_control =
384*4882a593Smuzhiyun SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
385*4882a593Smuzhiyun RT286_SET_PIN_SFT, 1, 0);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun static const struct snd_kcontrol_new hpol_enable_control =
388*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
389*4882a593Smuzhiyun RT286_MUTE_SFT, 1, 1);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun static const struct snd_kcontrol_new hpor_enable_control =
392*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
393*4882a593Smuzhiyun RT286_MUTE_SFT, 1, 1);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun /* ADC0 source */
396*4882a593Smuzhiyun static const char * const rt286_adc_src[] = {
397*4882a593Smuzhiyun "Mic", "RECMIX", "Dmic"
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun static const int rt286_adc_values[] = {
401*4882a593Smuzhiyun 0, 4, 5,
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun static SOC_VALUE_ENUM_SINGLE_DECL(
405*4882a593Smuzhiyun rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
406*4882a593Smuzhiyun RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun static const struct snd_kcontrol_new rt286_adc0_mux =
409*4882a593Smuzhiyun SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun static SOC_VALUE_ENUM_SINGLE_DECL(
412*4882a593Smuzhiyun rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
413*4882a593Smuzhiyun RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun static const struct snd_kcontrol_new rt286_adc1_mux =
416*4882a593Smuzhiyun SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun static const char * const rt286_dac_src[] = {
419*4882a593Smuzhiyun "Front", "Surround"
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun /* HP-OUT source */
422*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
423*4882a593Smuzhiyun 0, rt286_dac_src);
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun static const struct snd_kcontrol_new rt286_hpo_mux =
426*4882a593Smuzhiyun SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun /* SPK-OUT source */
429*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
430*4882a593Smuzhiyun 0, rt286_dac_src);
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun static const struct snd_kcontrol_new rt286_spo_mux =
433*4882a593Smuzhiyun SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
434*4882a593Smuzhiyun
rt286_spk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)435*4882a593Smuzhiyun static int rt286_spk_event(struct snd_soc_dapm_widget *w,
436*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
437*4882a593Smuzhiyun {
438*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun switch (event) {
441*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
442*4882a593Smuzhiyun snd_soc_component_write(component,
443*4882a593Smuzhiyun RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
444*4882a593Smuzhiyun break;
445*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
446*4882a593Smuzhiyun snd_soc_component_write(component,
447*4882a593Smuzhiyun RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
448*4882a593Smuzhiyun break;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun default:
451*4882a593Smuzhiyun return 0;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun return 0;
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
rt286_set_dmic1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)457*4882a593Smuzhiyun static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
458*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun switch (event) {
463*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
464*4882a593Smuzhiyun snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0x20);
465*4882a593Smuzhiyun break;
466*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
467*4882a593Smuzhiyun snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0);
468*4882a593Smuzhiyun break;
469*4882a593Smuzhiyun default:
470*4882a593Smuzhiyun return 0;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun return 0;
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun
rt286_ldo2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)476*4882a593Smuzhiyun static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
477*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun switch (event) {
482*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
483*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x08);
484*4882a593Smuzhiyun break;
485*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
486*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x30);
487*4882a593Smuzhiyun break;
488*4882a593Smuzhiyun default:
489*4882a593Smuzhiyun return 0;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun return 0;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun
rt286_mic1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)495*4882a593Smuzhiyun static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
496*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun switch (event) {
501*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
502*4882a593Smuzhiyun snd_soc_component_update_bits(component,
503*4882a593Smuzhiyun RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
504*4882a593Smuzhiyun snd_soc_component_update_bits(component,
505*4882a593Smuzhiyun RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
506*4882a593Smuzhiyun break;
507*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
508*4882a593Smuzhiyun snd_soc_component_update_bits(component,
509*4882a593Smuzhiyun RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
510*4882a593Smuzhiyun snd_soc_component_update_bits(component,
511*4882a593Smuzhiyun RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
512*4882a593Smuzhiyun break;
513*4882a593Smuzhiyun default:
514*4882a593Smuzhiyun return 0;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun return 0;
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
521*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
522*4882a593Smuzhiyun 12, 1, NULL, 0),
523*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
524*4882a593Smuzhiyun 0, 1, NULL, 0),
525*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
526*4882a593Smuzhiyun 2, 0, NULL, 0),
527*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
528*4882a593Smuzhiyun 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
529*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU),
530*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
531*4882a593Smuzhiyun 5, 0, NULL, 0),
532*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
533*4882a593Smuzhiyun 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
534*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMD),
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun /* Input Lines */
537*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC1 Pin"),
538*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC2 Pin"),
539*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MIC1"),
540*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("LINE1"),
541*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("Beep"),
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun /* DMIC */
544*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
545*4882a593Smuzhiyun NULL, 0, rt286_set_dmic1_event,
546*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
547*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
548*4882a593Smuzhiyun NULL, 0),
549*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
550*4882a593Smuzhiyun 0, 0, NULL, 0),
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun /* REC Mixer */
553*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
554*4882a593Smuzhiyun rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun /* ADCs */
557*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
558*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun /* ADC Mux */
561*4882a593Smuzhiyun SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
562*4882a593Smuzhiyun &rt286_adc0_mux),
563*4882a593Smuzhiyun SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
564*4882a593Smuzhiyun &rt286_adc1_mux),
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun /* Audio Interface */
567*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
568*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
569*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
570*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun /* Output Side */
573*4882a593Smuzhiyun /* DACs */
574*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
575*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun /* Output Mux */
578*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
579*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
582*4882a593Smuzhiyun RT286_SET_PIN_SFT, 0, NULL, 0),
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun /* Output Mixer */
585*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
586*4882a593Smuzhiyun rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
587*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
588*4882a593Smuzhiyun NULL, 0),
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun /* Output Pga */
591*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
592*4882a593Smuzhiyun &spo_enable_control, rt286_spk_event,
593*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
594*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
595*4882a593Smuzhiyun &hpol_enable_control),
596*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
597*4882a593Smuzhiyun &hpor_enable_control),
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun /* Output Lines */
600*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPOL"),
601*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPOR"),
602*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPO Pin"),
603*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPDIF"),
604*4882a593Smuzhiyun };
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
607*4882a593Smuzhiyun {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
608*4882a593Smuzhiyun {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
609*4882a593Smuzhiyun {"Front", NULL, "MCLK MODE", is_mclk_mode},
610*4882a593Smuzhiyun {"Surround", NULL, "MCLK MODE", is_mclk_mode},
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun {"HP Power", NULL, "LDO1"},
613*4882a593Smuzhiyun {"HP Power", NULL, "LDO2"},
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun {"MIC1", NULL, "LDO1"},
616*4882a593Smuzhiyun {"MIC1", NULL, "LDO2"},
617*4882a593Smuzhiyun {"MIC1", NULL, "HV"},
618*4882a593Smuzhiyun {"MIC1", NULL, "VREF"},
619*4882a593Smuzhiyun {"MIC1", NULL, "MIC1 Input Buffer"},
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun {"SPO", NULL, "LDO1"},
622*4882a593Smuzhiyun {"SPO", NULL, "LDO2"},
623*4882a593Smuzhiyun {"SPO", NULL, "HV"},
624*4882a593Smuzhiyun {"SPO", NULL, "VREF"},
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun {"DMIC1", NULL, "DMIC1 Pin"},
627*4882a593Smuzhiyun {"DMIC2", NULL, "DMIC2 Pin"},
628*4882a593Smuzhiyun {"DMIC1", NULL, "DMIC Receiver"},
629*4882a593Smuzhiyun {"DMIC2", NULL, "DMIC Receiver"},
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun {"RECMIX", "Beep Switch", "Beep"},
632*4882a593Smuzhiyun {"RECMIX", "Line1 Switch", "LINE1"},
633*4882a593Smuzhiyun {"RECMIX", "Mic1 Switch", "MIC1"},
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun {"ADC 0 Mux", "Dmic", "DMIC1"},
636*4882a593Smuzhiyun {"ADC 0 Mux", "RECMIX", "RECMIX"},
637*4882a593Smuzhiyun {"ADC 0 Mux", "Mic", "MIC1"},
638*4882a593Smuzhiyun {"ADC 1 Mux", "Dmic", "DMIC2"},
639*4882a593Smuzhiyun {"ADC 1 Mux", "RECMIX", "RECMIX"},
640*4882a593Smuzhiyun {"ADC 1 Mux", "Mic", "MIC1"},
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun {"ADC 0", NULL, "ADC 0 Mux"},
643*4882a593Smuzhiyun {"ADC 1", NULL, "ADC 1 Mux"},
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun {"AIF1TX", NULL, "ADC 0"},
646*4882a593Smuzhiyun {"AIF2TX", NULL, "ADC 1"},
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun {"DAC 0", NULL, "AIF1RX"},
649*4882a593Smuzhiyun {"DAC 1", NULL, "AIF2RX"},
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun {"Front", "DAC Switch", "DAC 0"},
652*4882a593Smuzhiyun {"Front", "RECMIX Switch", "RECMIX"},
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun {"Surround", NULL, "DAC 1"},
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun {"SPK Mux", "Front", "Front"},
657*4882a593Smuzhiyun {"SPK Mux", "Surround", "Surround"},
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun {"HPO Mux", "Front", "Front"},
660*4882a593Smuzhiyun {"HPO Mux", "Surround", "Surround"},
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun {"SPO", "Switch", "SPK Mux"},
663*4882a593Smuzhiyun {"HPO L", "Switch", "HPO Mux"},
664*4882a593Smuzhiyun {"HPO R", "Switch", "HPO Mux"},
665*4882a593Smuzhiyun {"HPO L", NULL, "HP Power"},
666*4882a593Smuzhiyun {"HPO R", NULL, "HP Power"},
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun {"SPOL", NULL, "SPO"},
669*4882a593Smuzhiyun {"SPOR", NULL, "SPO"},
670*4882a593Smuzhiyun {"HPO Pin", NULL, "HPO L"},
671*4882a593Smuzhiyun {"HPO Pin", NULL, "HPO R"},
672*4882a593Smuzhiyun };
673*4882a593Smuzhiyun
rt286_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)674*4882a593Smuzhiyun static int rt286_hw_params(struct snd_pcm_substream *substream,
675*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
676*4882a593Smuzhiyun struct snd_soc_dai *dai)
677*4882a593Smuzhiyun {
678*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
679*4882a593Smuzhiyun struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
680*4882a593Smuzhiyun unsigned int val = 0;
681*4882a593Smuzhiyun int d_len_code;
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun switch (params_rate(params)) {
684*4882a593Smuzhiyun /* bit 14 0:48K 1:44.1K */
685*4882a593Smuzhiyun case 44100:
686*4882a593Smuzhiyun val |= 0x4000;
687*4882a593Smuzhiyun break;
688*4882a593Smuzhiyun case 48000:
689*4882a593Smuzhiyun break;
690*4882a593Smuzhiyun default:
691*4882a593Smuzhiyun dev_err(component->dev, "Unsupported sample rate %d\n",
692*4882a593Smuzhiyun params_rate(params));
693*4882a593Smuzhiyun return -EINVAL;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun switch (rt286->sys_clk) {
696*4882a593Smuzhiyun case 12288000:
697*4882a593Smuzhiyun case 24576000:
698*4882a593Smuzhiyun if (params_rate(params) != 48000) {
699*4882a593Smuzhiyun dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
700*4882a593Smuzhiyun params_rate(params), rt286->sys_clk);
701*4882a593Smuzhiyun return -EINVAL;
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun break;
704*4882a593Smuzhiyun case 11289600:
705*4882a593Smuzhiyun case 22579200:
706*4882a593Smuzhiyun if (params_rate(params) != 44100) {
707*4882a593Smuzhiyun dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
708*4882a593Smuzhiyun params_rate(params), rt286->sys_clk);
709*4882a593Smuzhiyun return -EINVAL;
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun break;
712*4882a593Smuzhiyun }
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun if (params_channels(params) <= 16) {
715*4882a593Smuzhiyun /* bit 3:0 Number of Channel */
716*4882a593Smuzhiyun val |= (params_channels(params) - 1);
717*4882a593Smuzhiyun } else {
718*4882a593Smuzhiyun dev_err(component->dev, "Unsupported channels %d\n",
719*4882a593Smuzhiyun params_channels(params));
720*4882a593Smuzhiyun return -EINVAL;
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun d_len_code = 0;
724*4882a593Smuzhiyun switch (params_width(params)) {
725*4882a593Smuzhiyun /* bit 6:4 Bits per Sample */
726*4882a593Smuzhiyun case 16:
727*4882a593Smuzhiyun d_len_code = 0;
728*4882a593Smuzhiyun val |= (0x1 << 4);
729*4882a593Smuzhiyun break;
730*4882a593Smuzhiyun case 32:
731*4882a593Smuzhiyun d_len_code = 2;
732*4882a593Smuzhiyun val |= (0x4 << 4);
733*4882a593Smuzhiyun break;
734*4882a593Smuzhiyun case 20:
735*4882a593Smuzhiyun d_len_code = 1;
736*4882a593Smuzhiyun val |= (0x2 << 4);
737*4882a593Smuzhiyun break;
738*4882a593Smuzhiyun case 24:
739*4882a593Smuzhiyun d_len_code = 2;
740*4882a593Smuzhiyun val |= (0x3 << 4);
741*4882a593Smuzhiyun break;
742*4882a593Smuzhiyun case 8:
743*4882a593Smuzhiyun d_len_code = 3;
744*4882a593Smuzhiyun break;
745*4882a593Smuzhiyun default:
746*4882a593Smuzhiyun return -EINVAL;
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun snd_soc_component_update_bits(component,
750*4882a593Smuzhiyun RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
751*4882a593Smuzhiyun dev_dbg(component->dev, "format val = 0x%x\n", val);
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x407f, val);
754*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x407f, val);
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun return 0;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
rt286_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)759*4882a593Smuzhiyun static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
760*4882a593Smuzhiyun {
761*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
764*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
765*4882a593Smuzhiyun snd_soc_component_update_bits(component,
766*4882a593Smuzhiyun RT286_I2S_CTRL1, 0x800, 0x800);
767*4882a593Smuzhiyun break;
768*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
769*4882a593Smuzhiyun snd_soc_component_update_bits(component,
770*4882a593Smuzhiyun RT286_I2S_CTRL1, 0x800, 0x0);
771*4882a593Smuzhiyun break;
772*4882a593Smuzhiyun default:
773*4882a593Smuzhiyun return -EINVAL;
774*4882a593Smuzhiyun }
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
777*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
778*4882a593Smuzhiyun snd_soc_component_update_bits(component,
779*4882a593Smuzhiyun RT286_I2S_CTRL1, 0x300, 0x0);
780*4882a593Smuzhiyun break;
781*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
782*4882a593Smuzhiyun snd_soc_component_update_bits(component,
783*4882a593Smuzhiyun RT286_I2S_CTRL1, 0x300, 0x1 << 8);
784*4882a593Smuzhiyun break;
785*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
786*4882a593Smuzhiyun snd_soc_component_update_bits(component,
787*4882a593Smuzhiyun RT286_I2S_CTRL1, 0x300, 0x2 << 8);
788*4882a593Smuzhiyun break;
789*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
790*4882a593Smuzhiyun snd_soc_component_update_bits(component,
791*4882a593Smuzhiyun RT286_I2S_CTRL1, 0x300, 0x3 << 8);
792*4882a593Smuzhiyun break;
793*4882a593Smuzhiyun default:
794*4882a593Smuzhiyun return -EINVAL;
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun /* bit 15 Stream Type 0:PCM 1:Non-PCM */
797*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x8000, 0);
798*4882a593Smuzhiyun snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x8000, 0);
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun return 0;
801*4882a593Smuzhiyun }
802*4882a593Smuzhiyun
rt286_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)803*4882a593Smuzhiyun static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
804*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
805*4882a593Smuzhiyun {
806*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
807*4882a593Smuzhiyun struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun if (RT286_SCLK_S_MCLK == clk_id) {
812*4882a593Smuzhiyun snd_soc_component_update_bits(component,
813*4882a593Smuzhiyun RT286_I2S_CTRL2, 0x0100, 0x0);
814*4882a593Smuzhiyun snd_soc_component_update_bits(component,
815*4882a593Smuzhiyun RT286_PLL_CTRL1, 0x20, 0x20);
816*4882a593Smuzhiyun } else {
817*4882a593Smuzhiyun snd_soc_component_update_bits(component,
818*4882a593Smuzhiyun RT286_I2S_CTRL2, 0x0100, 0x0100);
819*4882a593Smuzhiyun snd_soc_component_update_bits(component,
820*4882a593Smuzhiyun RT286_PLL_CTRL, 0x4, 0x4);
821*4882a593Smuzhiyun snd_soc_component_update_bits(component,
822*4882a593Smuzhiyun RT286_PLL_CTRL1, 0x20, 0x0);
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun switch (freq) {
826*4882a593Smuzhiyun case 19200000:
827*4882a593Smuzhiyun if (RT286_SCLK_S_MCLK == clk_id) {
828*4882a593Smuzhiyun dev_err(component->dev, "Should not use MCLK\n");
829*4882a593Smuzhiyun return -EINVAL;
830*4882a593Smuzhiyun }
831*4882a593Smuzhiyun snd_soc_component_update_bits(component,
832*4882a593Smuzhiyun RT286_I2S_CTRL2, 0x40, 0x40);
833*4882a593Smuzhiyun break;
834*4882a593Smuzhiyun case 24000000:
835*4882a593Smuzhiyun if (RT286_SCLK_S_MCLK == clk_id) {
836*4882a593Smuzhiyun dev_err(component->dev, "Should not use MCLK\n");
837*4882a593Smuzhiyun return -EINVAL;
838*4882a593Smuzhiyun }
839*4882a593Smuzhiyun snd_soc_component_update_bits(component,
840*4882a593Smuzhiyun RT286_I2S_CTRL2, 0x40, 0x0);
841*4882a593Smuzhiyun break;
842*4882a593Smuzhiyun case 12288000:
843*4882a593Smuzhiyun case 11289600:
844*4882a593Smuzhiyun snd_soc_component_update_bits(component,
845*4882a593Smuzhiyun RT286_I2S_CTRL2, 0x8, 0x0);
846*4882a593Smuzhiyun snd_soc_component_update_bits(component,
847*4882a593Smuzhiyun RT286_CLK_DIV, 0xfc1e, 0x0004);
848*4882a593Smuzhiyun break;
849*4882a593Smuzhiyun case 24576000:
850*4882a593Smuzhiyun case 22579200:
851*4882a593Smuzhiyun snd_soc_component_update_bits(component,
852*4882a593Smuzhiyun RT286_I2S_CTRL2, 0x8, 0x8);
853*4882a593Smuzhiyun snd_soc_component_update_bits(component,
854*4882a593Smuzhiyun RT286_CLK_DIV, 0xfc1e, 0x5406);
855*4882a593Smuzhiyun break;
856*4882a593Smuzhiyun default:
857*4882a593Smuzhiyun dev_err(component->dev, "Unsupported system clock\n");
858*4882a593Smuzhiyun return -EINVAL;
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun rt286->sys_clk = freq;
862*4882a593Smuzhiyun rt286->clk_id = clk_id;
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun return 0;
865*4882a593Smuzhiyun }
866*4882a593Smuzhiyun
rt286_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)867*4882a593Smuzhiyun static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
868*4882a593Smuzhiyun {
869*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
872*4882a593Smuzhiyun if (50 == ratio)
873*4882a593Smuzhiyun snd_soc_component_update_bits(component,
874*4882a593Smuzhiyun RT286_I2S_CTRL1, 0x1000, 0x1000);
875*4882a593Smuzhiyun else
876*4882a593Smuzhiyun snd_soc_component_update_bits(component,
877*4882a593Smuzhiyun RT286_I2S_CTRL1, 0x1000, 0x0);
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun return 0;
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun
rt286_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)883*4882a593Smuzhiyun static int rt286_set_bias_level(struct snd_soc_component *component,
884*4882a593Smuzhiyun enum snd_soc_bias_level level)
885*4882a593Smuzhiyun {
886*4882a593Smuzhiyun switch (level) {
887*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
888*4882a593Smuzhiyun if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
889*4882a593Smuzhiyun snd_soc_component_write(component,
890*4882a593Smuzhiyun RT286_SET_AUDIO_POWER, AC_PWRST_D0);
891*4882a593Smuzhiyun snd_soc_component_update_bits(component,
892*4882a593Smuzhiyun RT286_DC_GAIN, 0x200, 0x200);
893*4882a593Smuzhiyun }
894*4882a593Smuzhiyun break;
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
897*4882a593Smuzhiyun mdelay(10);
898*4882a593Smuzhiyun snd_soc_component_update_bits(component,
899*4882a593Smuzhiyun RT286_DC_GAIN, 0x200, 0x0);
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun break;
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
904*4882a593Smuzhiyun snd_soc_component_write(component,
905*4882a593Smuzhiyun RT286_SET_AUDIO_POWER, AC_PWRST_D3);
906*4882a593Smuzhiyun break;
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun default:
909*4882a593Smuzhiyun break;
910*4882a593Smuzhiyun }
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun return 0;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun
rt286_irq(int irq,void * data)915*4882a593Smuzhiyun static irqreturn_t rt286_irq(int irq, void *data)
916*4882a593Smuzhiyun {
917*4882a593Smuzhiyun struct rt286_priv *rt286 = data;
918*4882a593Smuzhiyun bool hp = false;
919*4882a593Smuzhiyun bool mic = false;
920*4882a593Smuzhiyun int status = 0;
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun rt286_jack_detect(rt286, &hp, &mic);
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun /* Clear IRQ */
925*4882a593Smuzhiyun regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun if (hp)
928*4882a593Smuzhiyun status |= SND_JACK_HEADPHONE;
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun if (mic)
931*4882a593Smuzhiyun status |= SND_JACK_MICROPHONE;
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun snd_soc_jack_report(rt286->jack, status,
934*4882a593Smuzhiyun SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun pm_wakeup_event(&rt286->i2c->dev, 300);
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun return IRQ_HANDLED;
939*4882a593Smuzhiyun }
940*4882a593Smuzhiyun
rt286_probe(struct snd_soc_component * component)941*4882a593Smuzhiyun static int rt286_probe(struct snd_soc_component *component)
942*4882a593Smuzhiyun {
943*4882a593Smuzhiyun struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun rt286->component = component;
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun if (rt286->i2c->irq) {
948*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
949*4882a593Smuzhiyun RT286_IRQ_CTRL, 0x2, 0x2);
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun INIT_DELAYED_WORK(&rt286->jack_detect_work,
952*4882a593Smuzhiyun rt286_jack_detect_work);
953*4882a593Smuzhiyun schedule_delayed_work(&rt286->jack_detect_work,
954*4882a593Smuzhiyun msecs_to_jiffies(1250));
955*4882a593Smuzhiyun }
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun return 0;
958*4882a593Smuzhiyun }
959*4882a593Smuzhiyun
rt286_remove(struct snd_soc_component * component)960*4882a593Smuzhiyun static void rt286_remove(struct snd_soc_component *component)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun cancel_delayed_work_sync(&rt286->jack_detect_work);
965*4882a593Smuzhiyun }
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun #ifdef CONFIG_PM
rt286_suspend(struct snd_soc_component * component)968*4882a593Smuzhiyun static int rt286_suspend(struct snd_soc_component *component)
969*4882a593Smuzhiyun {
970*4882a593Smuzhiyun struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun regcache_cache_only(rt286->regmap, true);
973*4882a593Smuzhiyun regcache_mark_dirty(rt286->regmap);
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun return 0;
976*4882a593Smuzhiyun }
977*4882a593Smuzhiyun
rt286_resume(struct snd_soc_component * component)978*4882a593Smuzhiyun static int rt286_resume(struct snd_soc_component *component)
979*4882a593Smuzhiyun {
980*4882a593Smuzhiyun struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun regcache_cache_only(rt286->regmap, false);
983*4882a593Smuzhiyun rt286_index_sync(component);
984*4882a593Smuzhiyun regcache_sync(rt286->regmap);
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun return 0;
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun #else
989*4882a593Smuzhiyun #define rt286_suspend NULL
990*4882a593Smuzhiyun #define rt286_resume NULL
991*4882a593Smuzhiyun #endif
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
994*4882a593Smuzhiyun #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
995*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
998*4882a593Smuzhiyun .hw_params = rt286_hw_params,
999*4882a593Smuzhiyun .set_fmt = rt286_set_dai_fmt,
1000*4882a593Smuzhiyun .set_sysclk = rt286_set_dai_sysclk,
1001*4882a593Smuzhiyun .set_bclk_ratio = rt286_set_bclk_ratio,
1002*4882a593Smuzhiyun };
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun static struct snd_soc_dai_driver rt286_dai[] = {
1005*4882a593Smuzhiyun {
1006*4882a593Smuzhiyun .name = "rt286-aif1",
1007*4882a593Smuzhiyun .id = RT286_AIF1,
1008*4882a593Smuzhiyun .playback = {
1009*4882a593Smuzhiyun .stream_name = "AIF1 Playback",
1010*4882a593Smuzhiyun .channels_min = 1,
1011*4882a593Smuzhiyun .channels_max = 2,
1012*4882a593Smuzhiyun .rates = RT286_STEREO_RATES,
1013*4882a593Smuzhiyun .formats = RT286_FORMATS,
1014*4882a593Smuzhiyun },
1015*4882a593Smuzhiyun .capture = {
1016*4882a593Smuzhiyun .stream_name = "AIF1 Capture",
1017*4882a593Smuzhiyun .channels_min = 1,
1018*4882a593Smuzhiyun .channels_max = 2,
1019*4882a593Smuzhiyun .rates = RT286_STEREO_RATES,
1020*4882a593Smuzhiyun .formats = RT286_FORMATS,
1021*4882a593Smuzhiyun },
1022*4882a593Smuzhiyun .ops = &rt286_aif_dai_ops,
1023*4882a593Smuzhiyun .symmetric_rates = 1,
1024*4882a593Smuzhiyun },
1025*4882a593Smuzhiyun {
1026*4882a593Smuzhiyun .name = "rt286-aif2",
1027*4882a593Smuzhiyun .id = RT286_AIF2,
1028*4882a593Smuzhiyun .playback = {
1029*4882a593Smuzhiyun .stream_name = "AIF2 Playback",
1030*4882a593Smuzhiyun .channels_min = 1,
1031*4882a593Smuzhiyun .channels_max = 2,
1032*4882a593Smuzhiyun .rates = RT286_STEREO_RATES,
1033*4882a593Smuzhiyun .formats = RT286_FORMATS,
1034*4882a593Smuzhiyun },
1035*4882a593Smuzhiyun .capture = {
1036*4882a593Smuzhiyun .stream_name = "AIF2 Capture",
1037*4882a593Smuzhiyun .channels_min = 1,
1038*4882a593Smuzhiyun .channels_max = 2,
1039*4882a593Smuzhiyun .rates = RT286_STEREO_RATES,
1040*4882a593Smuzhiyun .formats = RT286_FORMATS,
1041*4882a593Smuzhiyun },
1042*4882a593Smuzhiyun .ops = &rt286_aif_dai_ops,
1043*4882a593Smuzhiyun .symmetric_rates = 1,
1044*4882a593Smuzhiyun },
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun };
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_rt286 = {
1049*4882a593Smuzhiyun .probe = rt286_probe,
1050*4882a593Smuzhiyun .remove = rt286_remove,
1051*4882a593Smuzhiyun .suspend = rt286_suspend,
1052*4882a593Smuzhiyun .resume = rt286_resume,
1053*4882a593Smuzhiyun .set_bias_level = rt286_set_bias_level,
1054*4882a593Smuzhiyun .controls = rt286_snd_controls,
1055*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(rt286_snd_controls),
1056*4882a593Smuzhiyun .dapm_widgets = rt286_dapm_widgets,
1057*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1058*4882a593Smuzhiyun .dapm_routes = rt286_dapm_routes,
1059*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1060*4882a593Smuzhiyun .use_pmdown_time = 1,
1061*4882a593Smuzhiyun .endianness = 1,
1062*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
1063*4882a593Smuzhiyun };
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun static const struct regmap_config rt286_regmap = {
1066*4882a593Smuzhiyun .reg_bits = 32,
1067*4882a593Smuzhiyun .val_bits = 32,
1068*4882a593Smuzhiyun .max_register = 0x02370100,
1069*4882a593Smuzhiyun .volatile_reg = rt286_volatile_register,
1070*4882a593Smuzhiyun .readable_reg = rt286_readable_register,
1071*4882a593Smuzhiyun .reg_write = rl6347a_hw_write,
1072*4882a593Smuzhiyun .reg_read = rl6347a_hw_read,
1073*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
1074*4882a593Smuzhiyun .reg_defaults = rt286_reg,
1075*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1076*4882a593Smuzhiyun };
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun static const struct i2c_device_id rt286_i2c_id[] = {
1079*4882a593Smuzhiyun {"rt286", 0},
1080*4882a593Smuzhiyun {"rt288", 0},
1081*4882a593Smuzhiyun {}
1082*4882a593Smuzhiyun };
1083*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun #ifdef CONFIG_ACPI
1086*4882a593Smuzhiyun static const struct acpi_device_id rt286_acpi_match[] = {
1087*4882a593Smuzhiyun { "INT343A", 0 },
1088*4882a593Smuzhiyun {},
1089*4882a593Smuzhiyun };
1090*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1091*4882a593Smuzhiyun #endif
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun static const struct dmi_system_id force_combo_jack_table[] = {
1094*4882a593Smuzhiyun {
1095*4882a593Smuzhiyun .ident = "Intel Wilson Beach",
1096*4882a593Smuzhiyun .matches = {
1097*4882a593Smuzhiyun DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1098*4882a593Smuzhiyun }
1099*4882a593Smuzhiyun },
1100*4882a593Smuzhiyun {
1101*4882a593Smuzhiyun .ident = "Intel Skylake RVP",
1102*4882a593Smuzhiyun .matches = {
1103*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun },
1106*4882a593Smuzhiyun {
1107*4882a593Smuzhiyun .ident = "Intel Kabylake RVP",
1108*4882a593Smuzhiyun .matches = {
1109*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
1110*4882a593Smuzhiyun }
1111*4882a593Smuzhiyun },
1112*4882a593Smuzhiyun {
1113*4882a593Smuzhiyun .ident = "Thinkpad Helix 2nd",
1114*4882a593Smuzhiyun .matches = {
1115*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1116*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Helix 2nd")
1117*4882a593Smuzhiyun }
1118*4882a593Smuzhiyun },
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun { }
1121*4882a593Smuzhiyun };
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun static const struct dmi_system_id dmi_dell[] = {
1124*4882a593Smuzhiyun {
1125*4882a593Smuzhiyun .ident = "Dell",
1126*4882a593Smuzhiyun .matches = {
1127*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1128*4882a593Smuzhiyun }
1129*4882a593Smuzhiyun },
1130*4882a593Smuzhiyun { }
1131*4882a593Smuzhiyun };
1132*4882a593Smuzhiyun
rt286_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1133*4882a593Smuzhiyun static int rt286_i2c_probe(struct i2c_client *i2c,
1134*4882a593Smuzhiyun const struct i2c_device_id *id)
1135*4882a593Smuzhiyun {
1136*4882a593Smuzhiyun struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1137*4882a593Smuzhiyun struct rt286_priv *rt286;
1138*4882a593Smuzhiyun int i, ret, vendor_id;
1139*4882a593Smuzhiyun
1140*4882a593Smuzhiyun rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1141*4882a593Smuzhiyun GFP_KERNEL);
1142*4882a593Smuzhiyun if (NULL == rt286)
1143*4882a593Smuzhiyun return -ENOMEM;
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1146*4882a593Smuzhiyun if (IS_ERR(rt286->regmap)) {
1147*4882a593Smuzhiyun ret = PTR_ERR(rt286->regmap);
1148*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1149*4882a593Smuzhiyun ret);
1150*4882a593Smuzhiyun return ret;
1151*4882a593Smuzhiyun }
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun ret = regmap_read(rt286->regmap,
1154*4882a593Smuzhiyun RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &vendor_id);
1155*4882a593Smuzhiyun if (ret != 0) {
1156*4882a593Smuzhiyun dev_err(&i2c->dev, "I2C error %d\n", ret);
1157*4882a593Smuzhiyun return ret;
1158*4882a593Smuzhiyun }
1159*4882a593Smuzhiyun if (vendor_id != RT286_VENDOR_ID && vendor_id != RT288_VENDOR_ID) {
1160*4882a593Smuzhiyun dev_err(&i2c->dev,
1161*4882a593Smuzhiyun "Device with ID register %#x is not rt286\n",
1162*4882a593Smuzhiyun vendor_id);
1163*4882a593Smuzhiyun return -ENODEV;
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def,
1167*4882a593Smuzhiyun sizeof(rt286_index_def), GFP_KERNEL);
1168*4882a593Smuzhiyun if (!rt286->index_cache)
1169*4882a593Smuzhiyun return -ENOMEM;
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun rt286->index_cache_size = INDEX_CACHE_SIZE;
1172*4882a593Smuzhiyun rt286->i2c = i2c;
1173*4882a593Smuzhiyun i2c_set_clientdata(i2c, rt286);
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun /* restore codec default */
1176*4882a593Smuzhiyun for (i = 0; i < INDEX_CACHE_SIZE; i++)
1177*4882a593Smuzhiyun regmap_write(rt286->regmap, rt286->index_cache[i].reg,
1178*4882a593Smuzhiyun rt286->index_cache[i].def);
1179*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
1180*4882a593Smuzhiyun regmap_write(rt286->regmap, rt286_reg[i].reg,
1181*4882a593Smuzhiyun rt286_reg[i].def);
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun if (pdata)
1184*4882a593Smuzhiyun rt286->pdata = *pdata;
1185*4882a593Smuzhiyun
1186*4882a593Smuzhiyun if ((vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) ||
1187*4882a593Smuzhiyun dmi_check_system(force_combo_jack_table))
1188*4882a593Smuzhiyun rt286->pdata.cbj_en = true;
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1191*4882a593Smuzhiyun
1192*4882a593Smuzhiyun for (i = 0; i < RT286_POWER_REG_LEN; i++)
1193*4882a593Smuzhiyun regmap_write(rt286->regmap,
1194*4882a593Smuzhiyun RT286_SET_POWER(rt286_support_power_controls[i]),
1195*4882a593Smuzhiyun AC_PWRST_D1);
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun if (!rt286->pdata.cbj_en) {
1198*4882a593Smuzhiyun regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1199*4882a593Smuzhiyun regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
1200*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
1201*4882a593Smuzhiyun RT286_CBJ_CTRL1, 0xf000, 0xb000);
1202*4882a593Smuzhiyun } else {
1203*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
1204*4882a593Smuzhiyun RT286_CBJ_CTRL1, 0xf000, 0x5000);
1205*4882a593Smuzhiyun }
1206*4882a593Smuzhiyun
1207*4882a593Smuzhiyun mdelay(10);
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun if (!rt286->pdata.gpio2_en)
1210*4882a593Smuzhiyun regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1211*4882a593Smuzhiyun else
1212*4882a593Smuzhiyun regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun mdelay(10);
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
1217*4882a593Smuzhiyun /* Power down LDO, VREF */
1218*4882a593Smuzhiyun regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1219*4882a593Smuzhiyun regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun /* Set depop parameter */
1222*4882a593Smuzhiyun regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1223*4882a593Smuzhiyun regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1224*4882a593Smuzhiyun regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun if (vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) {
1227*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
1228*4882a593Smuzhiyun RT286_SET_GPIO_MASK, 0x40, 0x40);
1229*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
1230*4882a593Smuzhiyun RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1231*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
1232*4882a593Smuzhiyun RT286_SET_GPIO_DATA, 0x40, 0x40);
1233*4882a593Smuzhiyun regmap_update_bits(rt286->regmap,
1234*4882a593Smuzhiyun RT286_GPIO_CTRL, 0xc, 0x8);
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun if (rt286->i2c->irq) {
1238*4882a593Smuzhiyun ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1239*4882a593Smuzhiyun IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1240*4882a593Smuzhiyun if (ret != 0) {
1241*4882a593Smuzhiyun dev_err(&i2c->dev,
1242*4882a593Smuzhiyun "Failed to reguest IRQ: %d\n", ret);
1243*4882a593Smuzhiyun return ret;
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun }
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev,
1248*4882a593Smuzhiyun &soc_component_dev_rt286,
1249*4882a593Smuzhiyun rt286_dai, ARRAY_SIZE(rt286_dai));
1250*4882a593Smuzhiyun
1251*4882a593Smuzhiyun return ret;
1252*4882a593Smuzhiyun }
1253*4882a593Smuzhiyun
rt286_i2c_remove(struct i2c_client * i2c)1254*4882a593Smuzhiyun static int rt286_i2c_remove(struct i2c_client *i2c)
1255*4882a593Smuzhiyun {
1256*4882a593Smuzhiyun struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1257*4882a593Smuzhiyun
1258*4882a593Smuzhiyun if (i2c->irq)
1259*4882a593Smuzhiyun free_irq(i2c->irq, rt286);
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun return 0;
1262*4882a593Smuzhiyun }
1263*4882a593Smuzhiyun
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun static struct i2c_driver rt286_i2c_driver = {
1266*4882a593Smuzhiyun .driver = {
1267*4882a593Smuzhiyun .name = "rt286",
1268*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1269*4882a593Smuzhiyun },
1270*4882a593Smuzhiyun .probe = rt286_i2c_probe,
1271*4882a593Smuzhiyun .remove = rt286_i2c_remove,
1272*4882a593Smuzhiyun .id_table = rt286_i2c_id,
1273*4882a593Smuzhiyun };
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun module_i2c_driver(rt286_i2c_driver);
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC RT286 driver");
1278*4882a593Smuzhiyun MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1279*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1280