1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * rt274.h -- RT274 ALSA SoC audio driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2016 Realtek Microelectronics 6*4882a593Smuzhiyun * Author: Bard Liao <bardliao@realtek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __RT274_H__ 10*4882a593Smuzhiyun #define __RT274_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define VERB_CMD(V, N, D) ((N << 20) | (V << 8) | D) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define RT274_AUDIO_FUNCTION_GROUP 0x01 15*4882a593Smuzhiyun #define RT274_DAC_OUT0 0x02 16*4882a593Smuzhiyun #define RT274_DAC_OUT1 0x03 17*4882a593Smuzhiyun #define RT274_ADC_IN2 0x08 18*4882a593Smuzhiyun #define RT274_ADC_IN1 0x09 19*4882a593Smuzhiyun #define RT274_DIG_CVT 0x0a 20*4882a593Smuzhiyun #define RT274_DMIC1 0x12 21*4882a593Smuzhiyun #define RT274_DMIC2 0x13 22*4882a593Smuzhiyun #define RT274_MIC 0x19 23*4882a593Smuzhiyun #define RT274_LINE1 0x1a 24*4882a593Smuzhiyun #define RT274_LINE2 0x1b 25*4882a593Smuzhiyun #define RT274_LINE3 0x16 26*4882a593Smuzhiyun #define RT274_SPDIF 0x1e 27*4882a593Smuzhiyun #define RT274_VENDOR_REGISTERS 0x20 28*4882a593Smuzhiyun #define RT274_HP_OUT 0x21 29*4882a593Smuzhiyun #define RT274_MIXER_IN1 0x22 30*4882a593Smuzhiyun #define RT274_MIXER_IN2 0x23 31*4882a593Smuzhiyun #define RT274_INLINE_CMD 0x55 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define RT274_SET_PIN_SFT 6 34*4882a593Smuzhiyun #define RT274_SET_PIN_ENABLE 0x40 35*4882a593Smuzhiyun #define RT274_SET_PIN_DISABLE 0 36*4882a593Smuzhiyun #define RT274_SET_EAPD_HIGH 0x2 37*4882a593Smuzhiyun #define RT274_SET_EAPD_LOW 0 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define RT274_MUTE_SFT 7 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Verb commands */ 42*4882a593Smuzhiyun #define RT274_RESET\ 43*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CODEC_RESET, RT274_AUDIO_FUNCTION_GROUP, 0) 44*4882a593Smuzhiyun #define RT274_GET_PARAM(NID, PARAM) VERB_CMD(AC_VERB_PARAMETERS, NID, PARAM) 45*4882a593Smuzhiyun #define RT274_SET_POWER(NID) VERB_CMD(AC_VERB_SET_POWER_STATE, NID, 0) 46*4882a593Smuzhiyun #define RT274_SET_AUDIO_POWER RT274_SET_POWER(RT274_AUDIO_FUNCTION_GROUP) 47*4882a593Smuzhiyun #define RT274_SET_HPO_POWER RT274_SET_POWER(RT274_HP_OUT) 48*4882a593Smuzhiyun #define RT274_SET_DMIC1_POWER RT274_SET_POWER(RT274_DMIC1) 49*4882a593Smuzhiyun #define RT274_LOUT_MUX\ 50*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT274_LINE3, 0) 51*4882a593Smuzhiyun #define RT274_HPO_MUX\ 52*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT274_HP_OUT, 0) 53*4882a593Smuzhiyun #define RT274_ADC0_MUX\ 54*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT274_MIXER_IN1, 0) 55*4882a593Smuzhiyun #define RT274_ADC1_MUX\ 56*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT274_MIXER_IN2, 0) 57*4882a593Smuzhiyun #define RT274_SET_MIC\ 58*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT274_MIC, 0) 59*4882a593Smuzhiyun #define RT274_SET_PIN_LOUT3\ 60*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT274_LINE3, 0) 61*4882a593Smuzhiyun #define RT274_SET_PIN_HPO\ 62*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0) 63*4882a593Smuzhiyun #define RT274_SET_PIN_DMIC1\ 64*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0) 65*4882a593Smuzhiyun #define RT274_SET_PIN_SPDIF\ 66*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT274_SPDIF, 0) 67*4882a593Smuzhiyun #define RT274_SET_PIN_DIG_CVT\ 68*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_DIGI_CONVERT_1, RT274_DIG_CVT, 0) 69*4882a593Smuzhiyun #define RT274_SET_AMP_GAIN_HPO\ 70*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_HP_OUT, 0) 71*4882a593Smuzhiyun #define RT274_SET_AMP_GAIN_ADC_IN1\ 72*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0) 73*4882a593Smuzhiyun #define RT274_SET_AMP_GAIN_ADC_IN2\ 74*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0) 75*4882a593Smuzhiyun #define RT274_GET_HP_SENSE\ 76*4882a593Smuzhiyun VERB_CMD(AC_VERB_GET_PIN_SENSE, RT274_HP_OUT, 0) 77*4882a593Smuzhiyun #define RT274_GET_MIC_SENSE\ 78*4882a593Smuzhiyun VERB_CMD(AC_VERB_GET_PIN_SENSE, RT274_MIC, 0) 79*4882a593Smuzhiyun #define RT274_SET_DMIC2_DEFAULT\ 80*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CONFIG_DEFAULT_BYTES_3, RT274_DMIC2, 0) 81*4882a593Smuzhiyun #define RT274_SET_SPDIF_DEFAULT\ 82*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CONFIG_DEFAULT_BYTES_3, RT274_SPDIF, 0) 83*4882a593Smuzhiyun #define RT274_DAC0L_GAIN\ 84*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0xa000) 85*4882a593Smuzhiyun #define RT274_DAC0R_GAIN\ 86*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0x9000) 87*4882a593Smuzhiyun #define RT274_DAC1L_GAIN\ 88*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0xa000) 89*4882a593Smuzhiyun #define RT274_DAC1R_GAIN\ 90*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0x9000) 91*4882a593Smuzhiyun #define RT274_ADCL_GAIN\ 92*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0x6000) 93*4882a593Smuzhiyun #define RT274_ADCR_GAIN\ 94*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0x5000) 95*4882a593Smuzhiyun #define RT274_MIC_GAIN\ 96*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_MIC, 0x7000) 97*4882a593Smuzhiyun #define RT274_LOUTL_GAIN\ 98*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_LINE3, 0xa000) 99*4882a593Smuzhiyun #define RT274_LOUTR_GAIN\ 100*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_LINE3, 0x9000) 101*4882a593Smuzhiyun #define RT274_HPOL_GAIN\ 102*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_HP_OUT, 0xa000) 103*4882a593Smuzhiyun #define RT274_HPOR_GAIN\ 104*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_HP_OUT, 0x9000) 105*4882a593Smuzhiyun #define RT274_DAC_FORMAT\ 106*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_STREAM_FORMAT, RT274_DAC_OUT0, 0) 107*4882a593Smuzhiyun #define RT274_ADC_FORMAT\ 108*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_STREAM_FORMAT, RT274_ADC_IN1, 0) 109*4882a593Smuzhiyun #define RT274_COEF_INDEX\ 110*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_COEF_INDEX, RT274_VENDOR_REGISTERS, 0) 111*4882a593Smuzhiyun #define RT274_PROC_COEF\ 112*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_PROC_COEF, RT274_VENDOR_REGISTERS, 0) 113*4882a593Smuzhiyun #define RT274_UNSOLICITED_INLINE_CMD\ 114*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_UNSOLICITED_ENABLE, RT274_INLINE_CMD, 0) 115*4882a593Smuzhiyun #define RT274_UNSOLICITED_HP_OUT\ 116*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_UNSOLICITED_ENABLE, RT274_HP_OUT, 0) 117*4882a593Smuzhiyun #define RT274_UNSOLICITED_MIC\ 118*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_UNSOLICITED_ENABLE, RT274_MIC, 0) 119*4882a593Smuzhiyun #define RT274_COEF58_INDEX\ 120*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_COEF_INDEX, 0x58, 0) 121*4882a593Smuzhiyun #define RT274_COEF58_COEF\ 122*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_PROC_COEF, 0x58, 0) 123*4882a593Smuzhiyun #define RT274_COEF5b_INDEX\ 124*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_COEF_INDEX, 0x5b, 0) 125*4882a593Smuzhiyun #define RT274_COEF5b_COEF\ 126*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_PROC_COEF, 0x5b, 0) 127*4882a593Smuzhiyun #define RT274_SET_STREAMID_DAC0\ 128*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CHANNEL_STREAMID, RT274_DAC_OUT0, 0) 129*4882a593Smuzhiyun #define RT274_SET_STREAMID_DAC1\ 130*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CHANNEL_STREAMID, RT274_DAC_OUT1, 0) 131*4882a593Smuzhiyun #define RT274_SET_STREAMID_ADC1\ 132*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CHANNEL_STREAMID, RT274_ADC_IN1, 0) 133*4882a593Smuzhiyun #define RT274_SET_STREAMID_ADC2\ 134*4882a593Smuzhiyun VERB_CMD(AC_VERB_SET_CHANNEL_STREAMID, RT274_ADC_IN2, 0) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Index registers */ 137*4882a593Smuzhiyun #define RT274_EAPD_GPIO_IRQ_CTRL 0x10 138*4882a593Smuzhiyun #define RT274_PAD_CTRL12 0x35 139*4882a593Smuzhiyun #define RT274_I2S_CTRL1 0x63 140*4882a593Smuzhiyun #define RT274_I2S_CTRL2 0x64 141*4882a593Smuzhiyun #define RT274_MCLK_CTRL 0x71 142*4882a593Smuzhiyun #define RT274_CLK_CTRL 0x72 143*4882a593Smuzhiyun #define RT274_PLL2_CTRL 0x7b 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* EAPD GPIO IRQ control (Index 0x10) */ 147*4882a593Smuzhiyun #define RT274_IRQ_DIS (0x0 << 13) 148*4882a593Smuzhiyun #define RT274_IRQ_EN (0x1 << 13) 149*4882a593Smuzhiyun #define RT274_IRQ_CLR (0x1 << 12) 150*4882a593Smuzhiyun #define RT274_GPI2_SEL_MASK (0x3 << 7) 151*4882a593Smuzhiyun #define RT274_GPI2_SEL_GPIO2 (0x0 << 7) 152*4882a593Smuzhiyun #define RT274_GPI2_SEL_I2S (0x1 << 7) 153*4882a593Smuzhiyun #define RT274_GPI2_SEL_DMIC_CLK (0x2 << 7) 154*4882a593Smuzhiyun #define RT274_GPI2_SEL_CBJ (0x3 << 7) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* Front I2S_Interface control 1 (Index 0x63) */ 157*4882a593Smuzhiyun #define RT274_I2S_MODE_MASK (0x1 << 11) 158*4882a593Smuzhiyun #define RT274_I2S_MODE_S (0x0 << 11) 159*4882a593Smuzhiyun #define RT274_I2S_MODE_M (0x1 << 11) 160*4882a593Smuzhiyun #define RT274_TDM_DIS (0x0 << 10) 161*4882a593Smuzhiyun #define RT274_TDM_EN (0x1 << 10) 162*4882a593Smuzhiyun #define RT274_TDM_CH_NUM (0x1 << 7) 163*4882a593Smuzhiyun #define RT274_TDM_2CH (0x0 << 7) 164*4882a593Smuzhiyun #define RT274_TDM_4CH (0x1 << 7) 165*4882a593Smuzhiyun #define RT274_I2S_FMT_MASK (0x3 << 8) 166*4882a593Smuzhiyun #define RT274_I2S_FMT_I2S (0x0 << 8) 167*4882a593Smuzhiyun #define RT274_I2S_FMT_LJ (0x1 << 8) 168*4882a593Smuzhiyun #define RT274_I2S_FMT_PCMA (0x2 << 8) 169*4882a593Smuzhiyun #define RT274_I2S_FMT_PCMB (0x3 << 8) 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* MCLK clock domain control (Index 0x71) */ 172*4882a593Smuzhiyun #define RT274_MCLK_MODE_MASK (0x1 << 14) 173*4882a593Smuzhiyun #define RT274_MCLK_MODE_DIS (0x0 << 14) 174*4882a593Smuzhiyun #define RT274_MCLK_MODE_EN (0x1 << 14) 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* Clock control (Index 0x72) */ 177*4882a593Smuzhiyun #define RT274_CLK_SRC_MASK (0x7 << 3) 178*4882a593Smuzhiyun #define RT274_CLK_SRC_MCLK (0x0 << 3) 179*4882a593Smuzhiyun #define RT274_CLK_SRC_PLL2 (0x3 << 3) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* PLL2 control (Index 0x7b) */ 182*4882a593Smuzhiyun #define RT274_PLL2_SRC_MASK (0x1 << 13) 183*4882a593Smuzhiyun #define RT274_PLL2_SRC_MCLK (0x0 << 13) 184*4882a593Smuzhiyun #define RT274_PLL2_SRC_BCLK (0x1 << 13) 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* HP-OUT (0x21) */ 187*4882a593Smuzhiyun #define RT274_M_HP_MUX_SFT 14 188*4882a593Smuzhiyun #define RT274_HP_SEL_MASK 0x1 189*4882a593Smuzhiyun #define RT274_HP_SEL_SFT 0 190*4882a593Smuzhiyun #define RT274_HP_SEL_F 0 191*4882a593Smuzhiyun #define RT274_HP_SEL_S 1 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* ADC (0x22) (0x23) */ 194*4882a593Smuzhiyun #define RT274_ADC_SEL_MASK 0x7 195*4882a593Smuzhiyun #define RT274_ADC_SEL_SFT 0 196*4882a593Smuzhiyun #define RT274_ADC_SEL_MIC 0 197*4882a593Smuzhiyun #define RT274_ADC_SEL_LINE1 1 198*4882a593Smuzhiyun #define RT274_ADC_SEL_LINE2 2 199*4882a593Smuzhiyun #define RT274_ADC_SEL_DMIC 3 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun #define RT274_SCLK_S_MCLK 0 202*4882a593Smuzhiyun #define RT274_SCLK_S_PLL1 1 203*4882a593Smuzhiyun #define RT274_SCLK_S_PLL2 2 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun #define RT274_PLL2_S_MCLK 0 206*4882a593Smuzhiyun #define RT274_PLL2_S_BCLK 1 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun enum { 209*4882a593Smuzhiyun RT274_AIF1, 210*4882a593Smuzhiyun RT274_AIFS, 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #endif /* __RT274_H__ */ 214*4882a593Smuzhiyun 215