1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * rl6231.h - RL6231 class device shared support 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2014 Realtek Semiconductor Corp. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Oder Chiou <oder_chiou@realtek.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __RL6231_H__ 11*4882a593Smuzhiyun #define __RL6231_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define RL6231_PLL_INP_MAX 50000000 14*4882a593Smuzhiyun #define RL6231_PLL_INP_MIN 256000 15*4882a593Smuzhiyun #define RL6231_PLL_N_MAX 0x1ff 16*4882a593Smuzhiyun #define RL6231_PLL_K_MAX 0x1f 17*4882a593Smuzhiyun #define RL6231_PLL_M_MAX 0xf 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct rl6231_pll_code { 20*4882a593Smuzhiyun bool m_bp; /* Indicates bypass m code or not. */ 21*4882a593Smuzhiyun bool k_bp; /* Indicates bypass k code or not. */ 22*4882a593Smuzhiyun int m_code; 23*4882a593Smuzhiyun int n_code; 24*4882a593Smuzhiyun int k_code; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun int rl6231_calc_dmic_clk(int rate); 28*4882a593Smuzhiyun int rl6231_pll_calc(const unsigned int freq_in, 29*4882a593Smuzhiyun const unsigned int freq_out, struct rl6231_pll_code *pll_code); 30*4882a593Smuzhiyun int rl6231_get_clk_info(int sclk, int rate); 31*4882a593Smuzhiyun int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* __RL6231_H__ */ 34