1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip Audio Delta-sigma Digital Converter Interface
4 *
5 * Copyright (C) 2023 Rockchip Electronics Co.,Ltd
6 *
7 */
8
9 #include <linux/module.h>
10 #include <linux/device.h>
11 #include <linux/delay.h>
12 #include <linux/of.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_platform.h>
15 #include <linux/clk.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/reset.h>
21 #include <sound/pcm_params.h>
22 #include <sound/dmaengine_pcm.h>
23 #include <sound/tlv.h>
24 #include "rk_dsm.h"
25
26 #define RK3562_GRF_PERI_AUDIO_CON (0x0070)
27
28 struct rk_dsm_soc_data {
29 int (*init)(struct device *dev);
30 void (*deinit)(struct device *dev);
31 };
32
33 struct rk_dsm_priv {
34 struct regmap *grf;
35 struct regmap *regmap;
36 struct clk *clk_dac;
37 struct clk *pclk;
38 unsigned int pa_ctl_delay_ms;
39 struct gpio_desc *pa_ctl;
40 struct reset_control *rc;
41 const struct rk_dsm_soc_data *data;
42 };
43
44 /* DAC digital gain */
45 static const DECLARE_TLV_DB_SCALE(dac_tlv, -95625, 375, 0);
46
47 /* DAC Cutoff for High Pass Filter */
48 static const char * const dac_hpf_cutoff_text[] = {
49 "80Hz", "100Hz", "120Hz", "140Hz",
50 };
51
52 static SOC_ENUM_SINGLE_DECL(dac_hpf_cutoff_enum, DACHPF, 4,
53 dac_hpf_cutoff_text);
54
55 static const char * const pa_ctl[] = {"Off", "On"};
56
57 static const struct soc_enum pa_enum =
58 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(pa_ctl), pa_ctl);
59
rk_dsm_dac_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)60 static int rk_dsm_dac_vol_get(struct snd_kcontrol *kcontrol,
61 struct snd_ctl_elem_value *ucontrol)
62 {
63 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
64 struct soc_mixer_control *mc =
65 (struct soc_mixer_control *)kcontrol->private_value;
66 unsigned int val = snd_soc_component_read(component, mc->reg);
67 unsigned int sign = snd_soc_component_read(component, DACVOGP);
68 unsigned int mask = (1 << fls(mc->max)) - 1;
69 unsigned int shift = mc->shift;
70 int mid = mc->max / 2;
71 int uv;
72
73 uv = (val >> shift) & mask;
74 if (sign)
75 uv = mid + uv;
76 else
77 uv = mid - uv;
78
79 ucontrol->value.integer.value[0] = uv;
80 ucontrol->value.integer.value[1] = uv;
81
82 return 0;
83 }
84
rk_dsm_dac_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)85 static int rk_dsm_dac_vol_put(struct snd_kcontrol *kcontrol,
86 struct snd_ctl_elem_value *ucontrol)
87 {
88 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
89 struct soc_mixer_control *mc =
90 (struct soc_mixer_control *)kcontrol->private_value;
91 unsigned int reg = mc->reg;
92 unsigned int rreg = mc->rreg;
93 unsigned int shift = mc->shift;
94 unsigned int mask = (1 << fls(mc->max)) - 1;
95 unsigned int val, val_mask, sign;
96 int uv = ucontrol->value.integer.value[0];
97 int min = mc->min;
98 int mid = mc->max / 2;
99
100 if (uv > mid) {
101 sign = DSM_DACVOGP_VOLGPL0_POS | DSM_DACVOGP_VOLGPR0_POS;
102 uv = uv - mid;
103 } else {
104 sign = DSM_DACVOGP_VOLGPL0_NEG | DSM_DACVOGP_VOLGPR0_NEG;
105 uv = mid - uv;
106 }
107
108 val = ((uv + min) & mask);
109 val_mask = mask << shift;
110 val = val << shift;
111
112 snd_soc_component_update_bits(component, reg, val_mask, val);
113 snd_soc_component_update_bits(component, rreg, val_mask, val);
114 snd_soc_component_write(component, DACVOGP, sign);
115
116 return 0;
117 }
118
rk_dsm_dac_pa_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)119 static int rk_dsm_dac_pa_get(struct snd_kcontrol *kcontrol,
120 struct snd_ctl_elem_value *ucontrol)
121 {
122 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
123 struct rk_dsm_priv *rd = snd_soc_component_get_drvdata(component);
124
125 if (!rd->pa_ctl)
126 return -EINVAL;
127
128 ucontrol->value.enumerated.item[0] = gpiod_get_value(rd->pa_ctl);
129
130 return 0;
131 }
132
rk_dsm_dac_pa_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)133 static int rk_dsm_dac_pa_put(struct snd_kcontrol *kcontrol,
134 struct snd_ctl_elem_value *ucontrol)
135 {
136 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
137 struct rk_dsm_priv *rd = snd_soc_component_get_drvdata(component);
138
139 if (!rd->pa_ctl)
140 return -EINVAL;
141
142 gpiod_set_value(rd->pa_ctl, ucontrol->value.enumerated.item[0]);
143
144 return 0;
145 }
146
147 static const struct snd_kcontrol_new rk_dsm_snd_controls[] = {
148 SOC_DOUBLE_R_EXT_TLV("DAC Digital Volume",
149 DACVOLL0, DACVOLR0, 0, 0x1fe, 0,
150 rk_dsm_dac_vol_get,
151 rk_dsm_dac_vol_put,
152 dac_tlv),
153
154 SOC_ENUM("DAC HPF Cutoff", dac_hpf_cutoff_enum),
155 SOC_SINGLE("DAC HPF Switch", DACHPF, 0, 1, 0),
156 SOC_ENUM_EXT("Power Amplifier", pa_enum,
157 rk_dsm_dac_pa_get,
158 rk_dsm_dac_pa_put),
159 };
160
161 /*
162 * ACDC_CLK D2A_CLK D2A_SYNC Sample rates supported
163 * 49.152MHz 49.152MHz 6.144MHz 12/24/48/96/192kHz
164 * 45.154MHz 45.154MHz 5.644MHz 11.025/22.05/44.1/88.2/176.4kHz
165 * 32.768MHz 32.768MHz 4.096MHz 8/16/32/64/128kHz
166 */
rk_dsm_get_clk(unsigned int samplerate,unsigned int * mclk,unsigned int * sclk)167 static void rk_dsm_get_clk(unsigned int samplerate,
168 unsigned int *mclk,
169 unsigned int *sclk)
170 {
171 switch (samplerate) {
172 case 12000:
173 case 24000:
174 case 48000:
175 case 96000:
176 case 192000:
177 *mclk = 49152000;
178 *sclk = 6144000;
179 break;
180 case 11025:
181 case 22050:
182 case 44100:
183 case 88200:
184 case 176400:
185 *mclk = 45158400;
186 *sclk = 5644800;
187 break;
188 case 8000:
189 case 16000:
190 case 32000:
191 case 64000:
192 case 128000:
193 *mclk = 32768000;
194 *sclk = 4096000;
195 break;
196 default:
197 *mclk = 0;
198 *sclk = 0;
199 break;
200 }
201 }
202
rk_dsm_enable_clk_dac(struct rk_dsm_priv * rd)203 static void rk_dsm_enable_clk_dac(struct rk_dsm_priv *rd)
204 {
205 regmap_update_bits(rd->regmap, DACCLKCTRL,
206 DSM_DACCLKCTRL_DAC_CKE_MASK |
207 DSM_DACCLKCTRL_I2SRX_CKE_MASK |
208 DSM_DACCLKCTRL_CKE_BCLKRX_MASK |
209 DSM_DACCLKCTRL_DAC_SYNC_ENA_MASK |
210 DSM_DACCLKCTRL_DAC_MODE_ATTENU_MASK,
211 DSM_DACCLKCTRL_DAC_CKE_EN |
212 DSM_DACCLKCTRL_I2SRX_CKE_EN |
213 DSM_DACCLKCTRL_CKE_BCLKRX_EN |
214 DSM_DACCLKCTRL_DAC_SYNC_ENA_EN |
215 DSM_DACCLKCTRL_DAC_MODE_ATTENU_EN);
216 }
217
rk_dsm_set_clk(struct rk_dsm_priv * rd,struct snd_pcm_substream * substream,unsigned int samplerate)218 static int rk_dsm_set_clk(struct rk_dsm_priv *rd,
219 struct snd_pcm_substream *substream,
220 unsigned int samplerate)
221 {
222 unsigned int mclk, sclk, bclk;
223 unsigned int div_bclk;
224
225 rk_dsm_get_clk(samplerate, &mclk, &sclk);
226 if (!mclk || !sclk)
227 return -EINVAL;
228
229 bclk = 64 * samplerate;
230 div_bclk = DIV_ROUND_CLOSEST(mclk, bclk);
231
232 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
233 clk_set_rate(rd->clk_dac, mclk);
234
235 rk_dsm_enable_clk_dac(rd);
236
237 regmap_update_bits(rd->regmap, DACSCLKRXINT_DIV,
238 DSM_DACSCLKRXINT_DIV_SCKRXDIV_MASK,
239 DSM_DACSCLKRXINT_DIV_SCKRXDIV(div_bclk));
240 regmap_update_bits(rd->regmap, I2S_CKR0,
241 DSM_I2S_CKR0_RSD_MASK,
242 DSM_I2S_CKR0_RSD_64);
243 }
244
245 return 0;
246 }
247
rk_dsm_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)248 static int rk_dsm_set_dai_fmt(struct snd_soc_dai *dai,
249 unsigned int fmt)
250 {
251 struct rk_dsm_priv *rd =
252 snd_soc_component_get_drvdata(dai->component);
253 unsigned int mask = 0, val = 0;
254
255 /* master mode only */
256 regmap_update_bits(rd->regmap, I2S_CKR1,
257 DSM_I2S_CKR1_MSS_MASK,
258 DSM_I2S_CKR1_MSS_MASTER);
259
260 mask = DSM_I2S_CKR1_CKP_MASK |
261 DSM_I2S_CKR1_RLP_MASK;
262
263 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
264 case SND_SOC_DAIFMT_NB_NF:
265 val = DSM_I2S_CKR1_CKP_NORMAL |
266 DSM_I2S_CKR1_RLP_NORMAL;
267 break;
268 case SND_SOC_DAIFMT_IB_IF:
269 val = DSM_I2S_CKR1_CKP_INVERTED |
270 DSM_I2S_CKR1_RLP_INVERTED;
271 break;
272 case SND_SOC_DAIFMT_IB_NF:
273 val = DSM_I2S_CKR1_CKP_INVERTED |
274 DSM_I2S_CKR1_RLP_NORMAL;
275 break;
276 case SND_SOC_DAIFMT_NB_IF:
277 val = DSM_I2S_CKR1_CKP_NORMAL |
278 DSM_I2S_CKR1_RLP_INVERTED;
279 break;
280 default:
281 return -EINVAL;
282 }
283
284 regmap_update_bits(rd->regmap, I2S_CKR1, mask, val);
285
286 return 0;
287 }
288
rk_dsm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)289 static int rk_dsm_hw_params(struct snd_pcm_substream *substream,
290 struct snd_pcm_hw_params *params,
291 struct snd_soc_dai *dai)
292 {
293 struct rk_dsm_priv *rd =
294 snd_soc_component_get_drvdata(dai->component);
295 unsigned int srt = 0, val = 0;
296
297 rk_dsm_set_clk(rd, substream, params_rate(params));
298
299 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
300 switch (params_rate(params)) {
301 case 8000:
302 case 11025:
303 case 12000:
304 srt = 0;
305 break;
306 case 16000:
307 case 22050:
308 case 24000:
309 srt = 1;
310 break;
311 case 32000:
312 case 44100:
313 case 48000:
314 srt = 2;
315 break;
316 case 64000:
317 case 88200:
318 case 96000:
319 srt = 3;
320 break;
321 case 128000:
322 case 176400:
323 case 192000:
324 srt = 4;
325 break;
326 default:
327 return -EINVAL;
328 }
329
330 regmap_update_bits(rd->regmap, DACCFG1,
331 DSM_DACCFG1_DACSRT_MASK,
332 DSM_DACCFG1_DACSRT(srt));
333
334 switch (params_format(params)) {
335 case SNDRV_PCM_FORMAT_S16_LE:
336 val = 16;
337 break;
338 case SNDRV_PCM_FORMAT_S24_LE:
339 case SNDRV_PCM_FORMAT_S32_LE:
340 val = 24;
341 break;
342 default:
343 return -EINVAL;
344 }
345
346 regmap_update_bits(rd->regmap, I2S_RXCR0,
347 DSM_I2S_RXCR0_VDW_MASK,
348 DSM_I2S_RXCR0_VDW(val));
349 regmap_update_bits(rd->regmap, DACPWM_CTRL,
350 DSM_DACPWM_CTRL_PWM_MODE_CKE_MASK |
351 DSM_DACPWM_CTRL_PWM_EN_MASK,
352 DSM_DACPWM_CTRL_PWM_MODE_CKE_EN |
353 DSM_DACPWM_CTRL_PWM_EN);
354 }
355
356 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
357 regmap_update_bits(rd->regmap, I2S_XFER,
358 DSM_I2S_XFER_RXS_MASK,
359 DSM_I2S_XFER_RXS_START);
360 regmap_update_bits(rd->regmap, DACDIGEN,
361 DSM_DACDIGEN_DAC_GLBEN_MASK |
362 DSM_DACDIGEN_DACEN_L0R1_MASK,
363 DSM_DACDIGEN_DAC_GLBEN_EN |
364 DSM_DACDIGEN_DACEN_L0R1_EN);
365 }
366
367 return 0;
368 }
369
rk_dsm_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)370 static int rk_dsm_pcm_startup(struct snd_pcm_substream *substream,
371 struct snd_soc_dai *dai)
372 {
373 struct rk_dsm_priv *rd =
374 snd_soc_component_get_drvdata(dai->component);
375
376 gpiod_set_value(rd->pa_ctl, 1);
377 if (rd->pa_ctl_delay_ms)
378 msleep(rd->pa_ctl_delay_ms);
379
380 return 0;
381 }
382
rk_dsm_reset(struct rk_dsm_priv * rd)383 static void rk_dsm_reset(struct rk_dsm_priv *rd)
384 {
385 if (IS_ERR(rd->rc))
386 return;
387
388 reset_control_assert(rd->rc);
389 udelay(5);
390 reset_control_deassert(rd->rc);
391 udelay(5);
392 }
393
rk_dsm_pcm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)394 static void rk_dsm_pcm_shutdown(struct snd_pcm_substream *substream,
395 struct snd_soc_dai *dai)
396 {
397 struct rk_dsm_priv *rd =
398 snd_soc_component_get_drvdata(dai->component);
399
400 gpiod_set_value(rd->pa_ctl, 0);
401
402 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
403 regmap_update_bits(rd->regmap, DACPWM_CTRL,
404 DSM_DACPWM_CTRL_PWM_MODE_CKE_MASK |
405 DSM_DACPWM_CTRL_PWM_EN_MASK,
406 DSM_DACPWM_CTRL_PWM_MODE_CKE_DIS |
407 DSM_DACPWM_CTRL_PWM_DIS);
408 regmap_update_bits(rd->regmap, I2S_XFER,
409 DSM_I2S_XFER_RXS_MASK,
410 DSM_I2S_XFER_RXS_STOP);
411 regmap_update_bits(rd->regmap, I2S_CLR,
412 DSM_I2S_CLR_RXC_MASK,
413 DSM_I2S_CLR_RXC_CLR);
414 regmap_update_bits(rd->regmap, DACDIGEN,
415 DSM_DACDIGEN_DAC_GLBEN_MASK |
416 DSM_DACDIGEN_DACEN_L0R1_MASK,
417 DSM_DACDIGEN_DAC_GLBEN_DIS |
418 DSM_DACDIGEN_DACEN_L0R1_DIS);
419 }
420
421 rk_dsm_reset(rd);
422 }
423
424 static const struct snd_soc_dai_ops rd_dai_ops = {
425 .hw_params = rk_dsm_hw_params,
426 .set_fmt = rk_dsm_set_dai_fmt,
427 .startup = rk_dsm_pcm_startup,
428 .shutdown = rk_dsm_pcm_shutdown,
429 };
430
431 static struct snd_soc_dai_driver rd_dai[] = {
432 {
433 .name = "rk_dsm",
434 .id = 0,
435 .playback = {
436 .stream_name = "Playback",
437 .channels_min = 2,
438 .channels_max = 2,
439 .rates = SNDRV_PCM_RATE_8000_192000,
440 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
441 SNDRV_PCM_FMTBIT_S24_LE |
442 SNDRV_PCM_FMTBIT_S32_LE),
443 },
444 .ops = &rd_dai_ops,
445 },
446 };
447
448 static const struct snd_soc_component_driver soc_codec_dev_rd = {
449 .controls = rk_dsm_snd_controls,
450 .num_controls = ARRAY_SIZE(rk_dsm_snd_controls),
451 };
452
453 static const struct regmap_config rd_regmap_config = {
454 .reg_bits = 32,
455 .reg_stride = 4,
456 .val_bits = 32,
457 .max_register = VERSION,
458 .cache_type = REGCACHE_FLAT,
459 };
460
rk3562_soc_init(struct device * dev)461 static int rk3562_soc_init(struct device *dev)
462 {
463 struct rk_dsm_priv *rd = dev_get_drvdata(dev);
464
465 if (IS_ERR(rd->grf))
466 return PTR_ERR(rd->grf);
467
468 /* enable internal codec to i2s1 */
469 return regmap_write(rd->grf, RK3562_GRF_PERI_AUDIO_CON,
470 (BIT(14) << 16 | BIT(14) | 0x0a100a10));
471 }
472
rk3562_soc_deinit(struct device * dev)473 static void rk3562_soc_deinit(struct device *dev)
474 {
475 struct rk_dsm_priv *rd = dev_get_drvdata(dev);
476
477 if (IS_ERR(rd->grf))
478 return;
479
480 regmap_write(rd->grf, RK3562_GRF_PERI_AUDIO_CON, (BIT(14) << 16) | 0x0a100a10);
481 }
482
483 static const struct rk_dsm_soc_data rk3562_data = {
484 .init = rk3562_soc_init,
485 .deinit = rk3562_soc_deinit,
486 };
487
488 #ifdef CONFIG_OF
489 static const struct of_device_id rd_of_match[] = {
490 { .compatible = "rockchip,rk3562-dsm", .data = &rk3562_data },
491 {},
492 };
493 MODULE_DEVICE_TABLE(of, rd_of_match);
494 #endif
495
496 #ifdef CONFIG_PM
rk_dsm_runtime_resume(struct device * dev)497 static int rk_dsm_runtime_resume(struct device *dev)
498 {
499 struct rk_dsm_priv *rd = dev_get_drvdata(dev);
500 int ret = 0;
501
502 ret = clk_prepare_enable(rd->pclk);
503 if (ret)
504 return ret;
505
506 regcache_cache_only(rd->regmap, false);
507 regcache_mark_dirty(rd->regmap);
508
509 ret = clk_prepare_enable(rd->clk_dac);
510 if (ret)
511 goto err;
512
513 return 0;
514 err:
515 clk_disable_unprepare(rd->pclk);
516
517 return ret;
518 }
519
rk_dsm_runtime_suspend(struct device * dev)520 static int rk_dsm_runtime_suspend(struct device *dev)
521 {
522 struct rk_dsm_priv *rd = dev_get_drvdata(dev);
523
524 regcache_cache_only(rd->regmap, true);
525 clk_disable_unprepare(rd->clk_dac);
526 clk_disable_unprepare(rd->pclk);
527
528 return 0;
529 }
530 #endif
531
rk_dsm_platform_probe(struct platform_device * pdev)532 static int rk_dsm_platform_probe(struct platform_device *pdev)
533 {
534 struct device_node *np = pdev->dev.of_node;
535 struct rk_dsm_priv *rd;
536 void __iomem *base;
537 int ret = 0;
538
539 rd = devm_kzalloc(&pdev->dev, sizeof(*rd), GFP_KERNEL);
540 if (!rd)
541 return -ENOMEM;
542
543 rd->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
544 if (IS_ERR(rd->grf))
545 return PTR_ERR(rd->grf);
546
547 if (device_property_read_u32(&pdev->dev, "rockchip,pa-ctl-delay-ms",
548 &rd->pa_ctl_delay_ms))
549 rd->pa_ctl_delay_ms = 0;
550
551 rd->rc = devm_reset_control_get(&pdev->dev, "reset");
552
553 rd->clk_dac = devm_clk_get(&pdev->dev, "dac");
554 if (IS_ERR(rd->clk_dac))
555 return PTR_ERR(rd->clk_dac);
556
557 rd->pclk = devm_clk_get(&pdev->dev, "pclk");
558 if (IS_ERR(rd->pclk))
559 return PTR_ERR(rd->pclk);
560
561 base = devm_platform_ioremap_resource(pdev, 0);
562 if (IS_ERR(base))
563 return PTR_ERR(base);
564
565 rd->regmap =
566 devm_regmap_init_mmio(&pdev->dev, base, &rd_regmap_config);
567 if (IS_ERR(rd->regmap))
568 return PTR_ERR(rd->regmap);
569
570 platform_set_drvdata(pdev, rd);
571
572 rd->data = device_get_match_data(&pdev->dev);
573 if (rd->data && rd->data->init) {
574 ret = rd->data->init(&pdev->dev);
575 if (ret)
576 return ret;
577 }
578
579 pm_runtime_enable(&pdev->dev);
580 if (!pm_runtime_enabled(&pdev->dev)) {
581 ret = rk_dsm_runtime_resume(&pdev->dev);
582 if (ret)
583 goto err_pm_disable;
584 }
585
586 regmap_update_bits(rd->regmap, DACPWM_CTRL,
587 DSM_DACPWM_CTRL_PWM_MODE_MASK,
588 DSM_DACPWM_CTRL_PWM_MODE_0);
589
590 rd->pa_ctl = devm_gpiod_get_optional(&pdev->dev, "pa-ctl",
591 GPIOD_OUT_LOW);
592
593 if (!rd->pa_ctl) {
594 dev_info(&pdev->dev, "no need pa-ctl gpio\n");
595 } else if (IS_ERR(rd->pa_ctl)) {
596 ret = PTR_ERR(rd->pa_ctl);
597 dev_err(&pdev->dev, "fail to request gpio pa-ctl\n");
598 goto err_suspend;
599 }
600
601 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rd,
602 rd_dai, ARRAY_SIZE(rd_dai));
603
604 if (ret)
605 goto err_suspend;
606
607 return 0;
608
609 err_suspend:
610 if (!pm_runtime_status_suspended(&pdev->dev))
611 rk_dsm_runtime_suspend(&pdev->dev);
612 err_pm_disable:
613 pm_runtime_disable(&pdev->dev);
614
615 if (rd->data && rd->data->deinit)
616 rd->data->deinit(&pdev->dev);
617
618 return ret;
619 }
620
rk_dsm_platform_remove(struct platform_device * pdev)621 static int rk_dsm_platform_remove(struct platform_device *pdev)
622 {
623 struct rk_dsm_priv *rd = dev_get_drvdata(&pdev->dev);
624
625 pm_runtime_disable(&pdev->dev);
626 if (!pm_runtime_status_suspended(&pdev->dev))
627 rk_dsm_runtime_suspend(&pdev->dev);
628
629 if (rd->data && rd->data->deinit)
630 rd->data->deinit(&pdev->dev);
631
632 return 0;
633 }
634
635 static const struct dev_pm_ops rd_pm = {
636 SET_RUNTIME_PM_OPS(rk_dsm_runtime_suspend,
637 rk_dsm_runtime_resume, NULL)
638 };
639
640 static struct platform_driver rk_dsm_driver = {
641 .driver = {
642 .name = "rk_dsm",
643 .of_match_table = of_match_ptr(rd_of_match),
644 .pm = &rd_pm,
645 },
646 .probe = rk_dsm_platform_probe,
647 .remove = rk_dsm_platform_remove,
648 };
649 module_platform_driver(rk_dsm_driver);
650
651 MODULE_AUTHOR("Jason Zhu <jason.zhu@rock-chips.com>");
652 MODULE_DESCRIPTION("ASoC Rockchip Delta-sigma Digital Converter Driver");
653 MODULE_LICENSE("GPL");
654