xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/rk3528_codec.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * rk3528_codec.h - Rockchip RK3528 SoC Codec Driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __RK3528_CODEC_H__
9*4882a593Smuzhiyun #define __RK3528_CODEC_H__
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define ACODEC_DIG00			0x00 /* REG 0x00 */
12*4882a593Smuzhiyun #define ACODEC_DIG01			0x04 /* REG 0x01 */
13*4882a593Smuzhiyun #define ACODEC_DIG02			0x08 /* REG 0x02 */
14*4882a593Smuzhiyun #define ACODEC_DIG03			0x0c /* REG 0x03 */
15*4882a593Smuzhiyun #define ACODEC_DIG04			0x10 /* REG 0x04 */
16*4882a593Smuzhiyun #define ACODEC_DIG05			0x14 /* REG 0x05 */
17*4882a593Smuzhiyun #define ACODEC_DIG06			0x18 /* REG 0x06 */
18*4882a593Smuzhiyun #define ACODEC_DIG07			0x1c /* REG 0x07 */
19*4882a593Smuzhiyun #define ACODEC_DIG08			0x20 /* REG 0x08 */
20*4882a593Smuzhiyun #define ACODEC_DIG09			0x24 /* REG 0x09 */
21*4882a593Smuzhiyun #define ACODEC_DIG0A			0x28 /* REG 0x0a */
22*4882a593Smuzhiyun #define ACODEC_DIG0B			0x2c /* REG 0x0b */
23*4882a593Smuzhiyun #define ACODEC_DIG0D			0x34 /* REG 0x0d */
24*4882a593Smuzhiyun #define ACODEC_DIG0E			0x38 /* REG 0x0e */
25*4882a593Smuzhiyun #define ACODEC_DIG10			0x40 /* REG 0x10 */
26*4882a593Smuzhiyun #define ACODEC_DIG11			0x44 /* REG 0x11 */
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define ACODEC_ANA00			0x80 /* REG 0x20 */
29*4882a593Smuzhiyun #define ACODEC_ANA01			0x84 /* REG 0x21 */
30*4882a593Smuzhiyun #define ACODEC_ANA02			0x88 /* REG 0x22 */
31*4882a593Smuzhiyun #define ACODEC_ANA08			0xa0 /* REG 0x28 */
32*4882a593Smuzhiyun #define ACODEC_ANA09			0xa4 /* REG 0x29 */
33*4882a593Smuzhiyun #define ACODEC_ANA0A			0xa8 /* REG 0x2a */
34*4882a593Smuzhiyun #define ACODEC_ANA0B			0xac /* REG 0x2b */
35*4882a593Smuzhiyun #define ACODEC_ANA0C			0xb0 /* REG 0x2c */
36*4882a593Smuzhiyun #define ACODEC_ANA0D			0xb4 /* REG 0x2d */
37*4882a593Smuzhiyun #define ACODEC_ANA0E			0xb8 /* REG 0x2e */
38*4882a593Smuzhiyun #define ACODEC_ANA0F			0xbc /* REG 0x2f */
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define ACODEC_REG_MAX			ACODEC_ANA0F
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* ACODEC_DIG00 */
43*4882a593Smuzhiyun #define ACODEC_DAC_RST_MASK		(0x1 << 4)
44*4882a593Smuzhiyun #define ACODEC_DAC_RST_P		(0x1 << 4)
45*4882a593Smuzhiyun #define ACODEC_DAC_RST_N		(0x0 << 4)
46*4882a593Smuzhiyun #define ACODEC_REG_BIST_EN		(0x1 << 1)
47*4882a593Smuzhiyun #define ACODEC_SYS_RST_MASK		(0x1 << 0)
48*4882a593Smuzhiyun #define ACODEC_SYS_RST_P		(0x1 << 0)
49*4882a593Smuzhiyun #define ACODEC_SYS_RST_N		(0x0 << 0)
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* ACODEC_DIG01 */
52*4882a593Smuzhiyun #define ACODEC_DAC_I2S_WL_SHIFT		4
53*4882a593Smuzhiyun #define ACODEC_DAC_I2S_WL_MASK		(0x3 << ACODEC_DAC_I2S_WL_SHIFT)
54*4882a593Smuzhiyun #define ACODEC_DAC_I2S_32B		(0x3 << ACODEC_DAC_I2S_WL_SHIFT)
55*4882a593Smuzhiyun #define ACODEC_DAC_I2S_24B		(0x2 << ACODEC_DAC_I2S_WL_SHIFT)
56*4882a593Smuzhiyun #define ACODEC_DAC_I2S_20B		(0x1 << ACODEC_DAC_I2S_WL_SHIFT)
57*4882a593Smuzhiyun #define ACODEC_DAC_I2S_16B		(0x0 << ACODEC_DAC_I2S_WL_SHIFT)
58*4882a593Smuzhiyun #define ACODEC_DAC_I2S_FMT_SHIFT	2
59*4882a593Smuzhiyun #define ACODEC_DAC_I2S_FMT_MASK		(0x3 << ACODEC_DAC_I2S_FMT_SHIFT)
60*4882a593Smuzhiyun #define ACODEC_DAC_I2S_I2S		(0x2 << ACODEC_DAC_I2S_FMT_SHIFT)
61*4882a593Smuzhiyun #define ACODEC_DAC_I2S_LJM		(0x1 << ACODEC_DAC_I2S_FMT_SHIFT)
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /* ACODEC_DIG02 */
64*4882a593Smuzhiyun #define ACODEC_DAC_I2S_LRP_MASK		(0x1 << 7)
65*4882a593Smuzhiyun #define ACODEC_DAC_I2S_LRP_REVSL	(0x1 << 7)
66*4882a593Smuzhiyun #define ACODEC_DAC_I2S_LRP_NORMAL	(0x0 << 7)
67*4882a593Smuzhiyun #define ACODEC_DAC_I2S_LR_SWAP		(0x1 << 6)
68*4882a593Smuzhiyun #define ACODEC_DAC_I2S_MST_FUNC_MASK	(0x1 << 5)
69*4882a593Smuzhiyun #define ACODEC_DAC_I2S_MST_FUNC_MASTER	(0x1 << 5)
70*4882a593Smuzhiyun #define ACODEC_DAC_I2S_MST_FUNC_SLAVE	(0x0 << 5)
71*4882a593Smuzhiyun #define ACODEC_DAC_I2S_MST_IO_MASK	(0x1 << 4)
72*4882a593Smuzhiyun #define ACODEC_DAC_I2S_MST_IO_MASTER	(0x1 << 4)
73*4882a593Smuzhiyun #define ACODEC_DAC_I2S_MST_IO_SLAVE	(0x0 << 4)
74*4882a593Smuzhiyun #define ACODEC_DAC_I2S_RST_MASK		(0x1 << 0)
75*4882a593Smuzhiyun #define ACODEC_DAC_I2S_RST_P		(0x1 << 0)
76*4882a593Smuzhiyun #define ACODEC_DAC_I2S_RST_N		(0x0 << 0)
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /* ACODEC_DIG03 */
79*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_EN		(0x1 << 7)
80*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_SR_SHIFT	4
81*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_SR_MASK		(0x7 << ACODEC_DAC_MUTE_SR_SHIFT)
82*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_SR_96K		(0x7 << ACODEC_DAC_MUTE_SR_SHIFT)
83*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_SR_88K2		(0x6 << ACODEC_DAC_MUTE_SR_SHIFT)
84*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_SR_48K		(0x5 << ACODEC_DAC_MUTE_SR_SHIFT)
85*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_SR_44K1		(0x4 << ACODEC_DAC_MUTE_SR_SHIFT)
86*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_SR_32K		(0x3 << ACODEC_DAC_MUTE_SR_SHIFT)
87*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_SR_24K		(0x2 << ACODEC_DAC_MUTE_SR_SHIFT)
88*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_SR_16K		(0x1 << ACODEC_DAC_MUTE_SR_SHIFT)
89*4882a593Smuzhiyun #define ACODEC_DAC_MUTE_SR_8K		(0x0 << ACODEC_DAC_MUTE_SR_SHIFT)
90*4882a593Smuzhiyun #define ACODEC_DA_EN			(0x1 << 3)
91*4882a593Smuzhiyun #define ACODEC_DITHER_EN		(0x1 << 2)
92*4882a593Smuzhiyun #define ACODEC_DITHER_LEVEL		(0x1 << 1)
93*4882a593Smuzhiyun #define ACODEC_DITHER_SIGN		(0x1 << 0)
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun /* ACODEC_DIG04 */
96*4882a593Smuzhiyun #define ACODEC_DAC_DEEMP_SEL_MASK	0x3
97*4882a593Smuzhiyun #define ACODEC_DAC_DEEMP_48K		0x3
98*4882a593Smuzhiyun #define ACODEC_DAC_DEEMP_44K1		0x2
99*4882a593Smuzhiyun #define ACODEC_DAC_DEEMP_32K		0x1
100*4882a593Smuzhiyun #define ACODEC_DAC_DEEMP_DIS		0x0
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun /* ACODEC_DIG05 */
103*4882a593Smuzhiyun #define ACODEC_DAC_R_BIST_SEL_SHIFT	6
104*4882a593Smuzhiyun #define ACODEC_DAC_R_BIST_SEL_MASK	(0x3 << ACODEC_DAC_R_BIST_SEL_SHIFT)
105*4882a593Smuzhiyun #define ACODEC_DAC_R_BIST_SEL_L		(0x2 << ACODEC_DAC_R_BIST_SEL_SHIFT)
106*4882a593Smuzhiyun #define ACODEC_DAC_R_BIST_SEL_SINE	(0x1 << ACODEC_DAC_R_BIST_SEL_SHIFT)
107*4882a593Smuzhiyun #define ACODEC_DAC_R_BIST_SEL_R		(0x0 << ACODEC_DAC_R_BIST_SEL_SHIFT)
108*4882a593Smuzhiyun #define ACODEC_DAC_R_MUTE		(0x1 << 4)
109*4882a593Smuzhiyun #define ACODEC_DAC_L_BIST_SEL_SHIFT	2
110*4882a593Smuzhiyun #define ACODEC_DAC_L_BIST_SEL_MASK	(0x3 << ACODEC_DAC_L_BIST_SEL_SHIFT)
111*4882a593Smuzhiyun #define ACODEC_DAC_L_BIST_SEL_R		(0x2 << ACODEC_DAC_L_BIST_SEL_SHIFT)
112*4882a593Smuzhiyun #define ACODEC_DAC_L_BIST_SEL_SINE	(0x1 << ACODEC_DAC_L_BIST_SEL_SHIFT)
113*4882a593Smuzhiyun #define ACODEC_DAC_L_BIST_SEL_L		(0x0 << ACODEC_DAC_L_BIST_SEL_SHIFT)
114*4882a593Smuzhiyun #define ACODEC_DAC_J_MUTE		(0x1 << 0)
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun /* ACODEC_DIG06 */
117*4882a593Smuzhiyun #define ACODEC_DAC_DIG_GAIN_SHIT	0
118*4882a593Smuzhiyun #define ACODEC_DAC_DIG_GAIN_MASK	(0xff << ACODEC_DAC_DIG_GAIN_SHIT)
119*4882a593Smuzhiyun /*  0.5dB every step , 1: -121dB, 255: 6dB */
120*4882a593Smuzhiyun #define ACODEC_DAC_DIG_GAIN(x)		((x) & ACODEC_DAC_DIG_GAIN_MASK)
121*4882a593Smuzhiyun #define ACODEC_DAC_DIG_0DB		0xe1
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun /* ACODEC_ANA00 */
124*4882a593Smuzhiyun #define ACODEC_IBIAS_DAC_MASK		(0x1 << 1)
125*4882a593Smuzhiyun #define ACODEC_IBIAS_DAC_EN		(0x1 << 1)
126*4882a593Smuzhiyun #define ACODEC_IBIAS_DAC_DIS		(0x0 << 1)
127*4882a593Smuzhiyun #define ACODEC_VREF_MASK		(0x1 << 0)
128*4882a593Smuzhiyun #define ACODEC_VREF_EN			(0x1 << 0)
129*4882a593Smuzhiyun #define ACODEC_VREF_DIS			(0x0 << 0)
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /* ACODEC_ANA01 */
132*4882a593Smuzhiyun #define ACODEC_VREF_SEL_SHIFT		0
133*4882a593Smuzhiyun /* Bit 0 is I0, bit 1 is 2 * I0 ... bit 7 is 128 * I0 */
134*4882a593Smuzhiyun #define ACODEC_VREF_SEL_MASK		(0xff << ACODEC_VREF_SEL_SHIFT)
135*4882a593Smuzhiyun #define ACODEC_VREF_SEL(x)		((x) & ACODEC_VREF_SEL_MASK)
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun /* ACODEC_ANA02 */
138*4882a593Smuzhiyun #define ACODEC_IBIAS_DAC_SEL_SHIFT	0
139*4882a593Smuzhiyun /* Ibias_DAC = I0 * (BIT[3]*8+BIT[2]*4+BIT[1]*2+BIT[0]+1) */
140*4882a593Smuzhiyun #define ACODEC_IBIAS_DAC_SEL		(0xf << ACODEC_IBIAS_DAC_SEL_SHIFT)
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /* ACODEC_ANA08 */
143*4882a593Smuzhiyun #define ACODEC_DAC_L_POP_CTRL_SHIFT	5
144*4882a593Smuzhiyun #define ACODEC_DAC_L_POP_CTRL_MASK	(0x3 << ACODEC_DAC_L_POP_CTRL_SHIFT)
145*4882a593Smuzhiyun #define ACODEC_DAC_L_POP_CTRL_ON	(0x1 << ACODEC_DAC_L_POP_CTRL_SHIFT)
146*4882a593Smuzhiyun #define ACODEC_DAC_L_POP_CTRL_OFF	(0x0 << ACODEC_DAC_L_POP_CTRL_SHIFT)
147*4882a593Smuzhiyun #define ACODEC_DAC_L_INIT_MASK		(0x1 << 4)
148*4882a593Smuzhiyun #define ACODEC_DAC_L_WORK		(0x1 << 4)
149*4882a593Smuzhiyun #define ACODEC_DAC_L_INIT		(0x0 << 4)
150*4882a593Smuzhiyun #define ACODEC_DAC_L_VREF_MASK		(0x1 << 3)
151*4882a593Smuzhiyun #define ACODEC_DAC_L_VREF_EN		(0x1 << 3)
152*4882a593Smuzhiyun #define ACODEC_DAC_L_VREF_DIS		(0x0 << 3)
153*4882a593Smuzhiyun #define ACODEC_DAC_L_BUF_MASK		(0x1 << 2)
154*4882a593Smuzhiyun #define ACODEC_DAC_L_BUF_EN		(0x1 << 2)
155*4882a593Smuzhiyun #define ACODEC_DAC_L_BUF_DIS		(0x0 << 2)
156*4882a593Smuzhiyun #define ACODEC_DAC_L_CLK_MASK		(0x1 << 1)
157*4882a593Smuzhiyun #define ACODEC_DAC_L_CLK_EN		(0x1 << 1)
158*4882a593Smuzhiyun #define ACODEC_DAC_L_CLK_DIS		(0x0 << 1)
159*4882a593Smuzhiyun #define ACODEC_DAC_L_MASK		(0x1 << 0)
160*4882a593Smuzhiyun #define ACODEC_DAC_L_EN			(0x1 << 0)
161*4882a593Smuzhiyun #define ACODEC_DAC_L_DIS		(0x0 << 0)
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun /* ACODEC_ANA09 */
164*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_MUTE_MASK	(0x1 << 5)
165*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_WORK		(0x1 << 5)
166*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_MUTE		(0x0 << 5)
167*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_INIT_MASK	(0x1 << 4)
168*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_INIT_WORK	(0x1 << 4)
169*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_INIT		(0x0 << 4)
170*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_MASK		(0x1 << 0)
171*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_EN		(0x1 << 0)
172*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_DIS		(0x0 << 0)
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun /* ACODEC_ANA0A */
175*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_SEL_SHIFT	0
176*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_SEL_MASK	(0xf << ACODEC_LINEOUT_L_SEL_SHIFT)
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun /* ACODEC_ANA0B */
179*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_GAIN_SHIFT	0
180*4882a593Smuzhiyun /* 1.5dB every step. 0: -39dB, 0x1f: 0dB */
181*4882a593Smuzhiyun #define ACODEC_LINEOUT_L_GAIN_MASK	(0x1f << ACODEC_LINEOUT_L_GAIN_SHIFT)
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun /* ACODEC_ANA0C */
184*4882a593Smuzhiyun #define ACODEC_DAC_R_POP_CTRL_SHIFT	5
185*4882a593Smuzhiyun #define ACODEC_DAC_R_POP_CTRL_MASK	(0x3 << ACODEC_DAC_R_POP_CTRL_SHIFT)
186*4882a593Smuzhiyun #define ACODEC_DAC_R_POP_CTRL_ON	(0x1 << ACODEC_DAC_R_POP_CTRL_SHIFT)
187*4882a593Smuzhiyun #define ACODEC_DAC_R_POP_CTRL_OFF	(0x0 << ACODEC_DAC_R_POP_CTRL_SHIFT)
188*4882a593Smuzhiyun #define ACODEC_DAC_R_INIT_MASK		(0x1 << 4)
189*4882a593Smuzhiyun #define ACODEC_DAC_R_WORK		(0x1 << 4)
190*4882a593Smuzhiyun #define ACODEC_DAC_R_INIT		(0x0 << 4)
191*4882a593Smuzhiyun #define ACODEC_DAC_R_VREF_MASK		(0x1 << 3)
192*4882a593Smuzhiyun #define ACODEC_DAC_R_VREF_EN		(0x1 << 3)
193*4882a593Smuzhiyun #define ACODEC_DAC_R_VREF_DIS		(0x0 << 3)
194*4882a593Smuzhiyun #define ACODEC_DAC_R_BUF_MASK		(0x1 << 2)
195*4882a593Smuzhiyun #define ACODEC_DAC_R_BUF_EN		(0x1 << 2)
196*4882a593Smuzhiyun #define ACODEC_DAC_R_BUF_DIS		(0x0 << 2)
197*4882a593Smuzhiyun #define ACODEC_DAC_R_CLK_MASK		(0x1 << 1)
198*4882a593Smuzhiyun #define ACODEC_DAC_R_CLK_EN		(0x1 << 1)
199*4882a593Smuzhiyun #define ACODEC_DAC_R_CLK_DIS		(0x0 << 1)
200*4882a593Smuzhiyun #define ACODEC_DAC_R_MASK		(0x1 << 0)
201*4882a593Smuzhiyun #define ACODEC_DAC_R_EN			(0x1 << 0)
202*4882a593Smuzhiyun #define ACODEC_DAC_R_DIS		(0x0 << 0)
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun /* ACODEC_ANA0D */
205*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_MUTE_MASK	(0x1 << 5)
206*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_WORK		(0x1 << 5)
207*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_MUTE		(0x0 << 5)
208*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_INIT_MASK	(0x1 << 4)
209*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_INIT_WORK	(0x1 << 4)
210*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_INIT		(0x0 << 4)
211*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_MASK		(0x1 << 0)
212*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_EN		(0x1 << 0)
213*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_DIS		(0x0 << 0)
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun /* ACODEC_ANA0E */
216*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_SEL_SHIFT	0
217*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_SEL_MASK	(0xf << ACODEC_LINEOUT_L_SEL_SHIFT)
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun /* ACODEC_ANA0F */
220*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_GAIN_SHIFT	0
221*4882a593Smuzhiyun /* 1.5dB every step. 0: -39dB, 0x1f: 0dB */
222*4882a593Smuzhiyun #define ACODEC_LINEOUT_R_GAIN_MASK	(0x1f << ACODEC_LINEOUT_L_GAIN_SHIFT)
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun #define ACODEC_DAC_LINEOUT_GAIN_MAX		0x1e
225*4882a593Smuzhiyun #define ACODEC_DAC_LINEOUT_GAIN_MIN		0
226*4882a593Smuzhiyun #define ACODEC_HIFI				0x0
227*4882a593Smuzhiyun #define ACODEC_DAC_LINEOUT_GAIN_0DB		0x1a
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun #endif /* __RK3528_CODEC_H__ */
230