1 /*
2 * rk3308_codec.c -- RK3308 ALSA Soc Audio Driver
3 *
4 * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 */
19
20 #include <linux/clk.h>
21 #include <linux/device.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_gpio.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/regmap.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/reset.h>
34 #include <linux/rockchip/grf.h>
35 #include <linux/version.h>
36 #include <sound/core.h>
37 #include <sound/dmaengine_pcm.h>
38 #include <sound/initval.h>
39 #include <sound/jack.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/simple_card.h>
43 #include <sound/soc.h>
44 #include <sound/tlv.h>
45
46 #include "rk3308_codec.h"
47
48 #if defined(CONFIG_DEBUG_FS)
49 #include <linux/fs.h>
50 #include <linux/debugfs.h>
51 #include <linux/seq_file.h>
52 #endif
53
54 #define CODEC_DRV_NAME "rk3308-acodec"
55
56 #define ADC_GRP_SKIP_MAGIC 0x1001
57 #define ADC_LR_GROUP_MAX 4
58 #define ADC_STABLE_MS 200
59 #define DEBUG_POP_ALWAYS 0
60 #define HPDET_POLL_MS 2000
61 #define NOT_USED 255
62 #define LOOPBACK_HANDLE_MS 100
63 #define PA_DRV_MS 5
64
65 #define GRF_SOC_CON1 0x304
66 #define GRF_CHIP_ID 0x800
67 #define GRF_I2S2_8CH_SDI_SFT 0
68 #define GRF_I2S3_4CH_SDI_SFT 8
69 #define GRF_I2S1_2CH_SDI_SFT 12
70
71 #define GRF_I2S2_8CH_SDI_R_MSK(i, v) ((v >> (i * 2 + GRF_I2S2_8CH_SDI_SFT)) & 0x3)
72 #define GRF_I2S2_8CH_SDI_W_MSK(i) (0x3 << (i * 2 + GRF_I2S2_8CH_SDI_SFT + 16))
73 #define GRF_I2S2_8CH_SDI(i, v) (((v & 0x3) << (i * 2 + GRF_I2S2_8CH_SDI_SFT)) |\
74 GRF_I2S2_8CH_SDI_W_MSK(i))
75
76 #define GRF_I2S3_4CH_SDI_W_MSK(i) (0x3 << (i * 2 + GRF_I2S3_4CH_SDI_SFT + 16))
77 #define GRF_I2S3_4CH_SDI(i, v) (((v & 0x3) << (i * 2 + GRF_I2S3_4CH_SDI_SFT)) |\
78 GRF_I2S3_4CH_SDI_W_MSK(i))
79
80 #define GRF_I2S1_2CH_SDI_W_MSK (0x3 << (GRF_I2S1_2CH_SDI_SFT + 16))
81 #define GRF_I2S1_2CH_SDI(v) (((v & 0x3) << GRF_I2S1_2CH_SDI_SFT) |\
82 GRF_I2S1_2CH_SDI_W_MSK)
83
84 #define DETECT_GRF_ACODEC_HPDET_COUNTER 0x0030
85 #define DETECT_GRF_ACODEC_HPDET_CON 0x0034
86 #define DETECT_GRF_ACODEC_HPDET_STATUS 0x0038
87 #define DETECT_GRF_ACODEC_HPDET_STATUS_CLR 0x003c
88
89 /* 200ms based on pclk is 100MHz */
90 #define DEFAULT_HPDET_COUNT 20000000
91 #define HPDET_NEG_IRQ_SFT 1
92 #define HPDET_POS_IRQ_SFT 0
93 #define HPDET_BOTH_NEG_POS ((1 << HPDET_NEG_IRQ_SFT) |\
94 (1 << HPDET_POS_IRQ_SFT))
95
96 #define ACODEC_VERSION_A 0xa
97 #define ACODEC_VERSION_B 0xb
98 #define ACODEC_VERSION_C 0xc
99
100 enum {
101 ACODEC_TO_I2S2_8CH = 0,
102 ACODEC_TO_I2S3_4CH,
103 ACODEC_TO_I2S1_2CH,
104 };
105
106 enum {
107 ADC_GRP0_MICIN = 0,
108 ADC_GRP0_LINEIN
109 };
110
111 enum {
112 ADC_TYPE_NORMAL = 0,
113 ADC_TYPE_LOOPBACK,
114 ADC_TYPE_DBG,
115 ADC_TYPE_ALL,
116 };
117
118 enum {
119 DAC_LINEOUT = 0,
120 DAC_HPOUT = 1,
121 DAC_LINEOUT_HPOUT = 11,
122 };
123
124 enum {
125 EXT_MICBIAS_NONE = 0,
126 EXT_MICBIAS_FUNC1, /* enable external micbias via GPIO */
127 EXT_MICBIAS_FUNC2, /* enable external micbias via regulator */
128 };
129
130 enum {
131 PATH_IDLE = 0,
132 PATH_BUSY,
133 };
134
135 enum {
136 PM_NORMAL = 0,
137 PM_LLP_DOWN, /* light low power down */
138 PM_LLP_UP,
139 PM_DLP_DOWN, /* deep low power down */
140 PM_DLP_UP,
141 PM_DLP_DOWN2,
142 PM_DLP_UP2,
143 };
144
145 struct rk3308_codec_priv {
146 const struct device *plat_dev;
147 struct device dev;
148 struct reset_control *reset;
149 struct regmap *regmap;
150 struct regmap *grf;
151 struct regmap *detect_grf;
152 struct clk *pclk;
153 struct clk *mclk_rx;
154 struct clk *mclk_tx;
155 struct gpio_desc *micbias_en_gpio;
156 struct gpio_desc *hp_ctl_gpio;
157 struct gpio_desc *spk_ctl_gpio;
158 struct gpio_desc *pa_drv_gpio;
159 struct snd_soc_component *component;
160 struct snd_soc_jack *hpdet_jack;
161 struct regulator *vcc_micbias;
162 u32 codec_ver;
163
164 /*
165 * To select ADCs for groups:
166 *
167 * grp 0 -- select ADC1 / ADC2
168 * grp 1 -- select ADC3 / ADC4
169 * grp 2 -- select ADC5 / ADC6
170 * grp 3 -- select ADC7 / ADC8
171 */
172 u32 used_adc_grps;
173 /* The ADC group which is used for loop back */
174 u32 loopback_grp;
175 u32 cur_dbg_grp;
176 u32 en_always_grps[ADC_LR_GROUP_MAX];
177 u32 en_always_grps_num;
178 u32 skip_grps[ADC_LR_GROUP_MAX];
179 u32 i2s_sdis[ADC_LR_GROUP_MAX];
180 u32 to_i2s_grps;
181 u32 delay_loopback_handle_ms;
182 u32 delay_start_play_ms;
183 u32 delay_pa_drv_ms;
184 u32 micbias_num;
185 u32 micbias_volt;
186 int which_i2s;
187 int irq;
188 int adc_grp0_using_linein;
189 int adc_zerocross;
190 /* 0: line out, 1: hp out, 11: lineout and hpout */
191 int dac_output;
192 int dac_path_state;
193
194 int ext_micbias;
195 int pm_state;
196
197 /* ADC MIC Mute/Work */
198 unsigned int mic_mute_l[ADC_LR_GROUP_MAX];
199 unsigned int mic_mute_r[ADC_LR_GROUP_MAX];
200
201 /* For the high pass filter */
202 unsigned int hpf_cutoff[ADC_LR_GROUP_MAX];
203
204 /* Only hpout do fade-in and fade-out */
205 unsigned int hpout_l_dgain;
206 unsigned int hpout_r_dgain;
207
208 bool adc_grps_endisable[ADC_LR_GROUP_MAX];
209 bool dac_endisable;
210 bool enable_all_adcs;
211 bool enable_micbias;
212 bool micbias1;
213 bool micbias2;
214 bool hp_jack_reversed;
215 bool hp_plugged;
216 bool loopback_dacs_enabled;
217 bool no_deep_low_power;
218 bool no_hp_det;
219 struct delayed_work hpdet_work;
220 struct delayed_work loopback_work;
221
222 #if defined(CONFIG_DEBUG_FS)
223 struct dentry *dbg_codec;
224 #endif
225 };
226
227 static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_alc_gain_tlv,
228 -1800, 150, 2850);
229 static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_lineout_gain_tlv,
230 -600, 150, 0);
231 static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpout_gain_tlv,
232 -3900, 150, 600);
233 static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpmix_gain_tlv,
234 -600, 600, 0);
235
236 static const DECLARE_TLV_DB_RANGE(rk3308_codec_adc_mic_gain_tlv_a,
237 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
238 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0),
239 );
240
241 static const DECLARE_TLV_DB_RANGE(rk3308_codec_adc_mic_gain_tlv_b,
242 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
243 1, 1, TLV_DB_SCALE_ITEM(660, 0, 0),
244 2, 2, TLV_DB_SCALE_ITEM(1300, 0, 0),
245 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0),
246 );
247
248 static bool handle_loopback(struct rk3308_codec_priv *rk3308);
249
250 static int check_micbias(int micbias);
251
252 static void rk3308_codec_dac_mclk_enable(struct rk3308_codec_priv *rk3308);
253
254 static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308,
255 int micbias);
256 static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308);
257
258 static int rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol *kcontrol,
259 struct snd_ctl_elem_value *ucontrol);
260 static int rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol *kcontrol,
261 struct snd_ctl_elem_value *ucontrol);
262 static int rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol *kcontrol,
263 struct snd_ctl_elem_value *ucontrol);
264 static int rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol);
266 static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol,
267 struct snd_ctl_elem_value *ucontrol);
268 static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol,
269 struct snd_ctl_elem_value *ucontrol);
270 static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol,
271 struct snd_ctl_elem_value *ucontrol);
272 static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol,
273 struct snd_ctl_elem_value *ucontrol);
274 static int rk3308_codec_mic_gain_get(struct snd_kcontrol *kcontrol,
275 struct snd_ctl_elem_value *ucontrol);
276 static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol,
277 struct snd_ctl_elem_value *ucontrol);
278 static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol,
279 struct snd_ctl_elem_value *ucontrol);
280 static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol,
281 struct snd_ctl_elem_value *ucontrol);
282 static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol,
283 struct snd_ctl_elem_value *ucontrol);
284 static int rk3308_codec_main_micbias_put(struct snd_kcontrol *kcontrol,
285 struct snd_ctl_elem_value *ucontrol);
286
287 static const char *offon_text[2] = {
288 [0] = "Off",
289 [1] = "On",
290 };
291
292 static const char *mute_text[2] = {
293 [0] = "Work",
294 [1] = "Mute",
295 };
296
297 /* ADC MICBIAS Volt */
298 #define MICBIAS_VOLT_NUM 8
299
300 #define MICBIAS_VREFx0_5 0
301 #define MICBIAS_VREFx0_55 1
302 #define MICBIAS_VREFx0_6 2
303 #define MICBIAS_VREFx0_65 3
304 #define MICBIAS_VREFx0_7 4
305 #define MICBIAS_VREFx0_75 5
306 #define MICBIAS_VREFx0_8 6
307 #define MICBIAS_VREFx0_85 7
308
309 static const char *micbias_volts_enum_array[MICBIAS_VOLT_NUM] = {
310 [MICBIAS_VREFx0_5] = "VREFx0_5",
311 [MICBIAS_VREFx0_55] = "VREFx0_55",
312 [MICBIAS_VREFx0_6] = "VREFx0_6",
313 [MICBIAS_VREFx0_65] = "VREFx0_65",
314 [MICBIAS_VREFx0_7] = "VREFx0_7",
315 [MICBIAS_VREFx0_75] = "VREFx0_75",
316 [MICBIAS_VREFx0_8] = "VREFx0_8",
317 [MICBIAS_VREFx0_85] = "VREFx0_85",
318 };
319
320 static const struct soc_enum rk3308_micbias_volts_enum_array[] = {
321 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(micbias_volts_enum_array), micbias_volts_enum_array),
322 };
323
324 /* ADC MICBIAS1 and MICBIAS2 Main Switch */
325 static const struct soc_enum rk3308_main_micbias_enum_array[] = {
326 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text),
327 };
328
329 static const struct soc_enum rk3308_hpf_enum_array[] = {
330 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text),
331 SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(offon_text), offon_text),
332 SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(offon_text), offon_text),
333 SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(offon_text), offon_text),
334 };
335
336 /* ADC MIC Mute/Work Switch */
337 static const struct soc_enum rk3308_mic_mute_enum_array[] = {
338 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(mute_text), mute_text),
339 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(mute_text), mute_text),
340 SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(mute_text), mute_text),
341 SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(mute_text), mute_text),
342 SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(mute_text), mute_text),
343 SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(mute_text), mute_text),
344 SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(mute_text), mute_text),
345 SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(mute_text), mute_text),
346 };
347
348 static const struct snd_kcontrol_new mic_gains_a[] = {
349 /* ADC MIC */
350 SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Left Gain",
351 RK3308_ADC_ANA_CON01(0),
352 RK3308_ADC_CH1_MIC_GAIN_SFT,
353 RK3308_ADC_CH1_MIC_GAIN_MAX,
354 0,
355 rk3308_codec_mic_gain_get,
356 rk3308_codec_mic_gain_put,
357 rk3308_codec_adc_mic_gain_tlv_a),
358 SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Right Gain",
359 RK3308_ADC_ANA_CON01(0),
360 RK3308_ADC_CH2_MIC_GAIN_SFT,
361 RK3308_ADC_CH2_MIC_GAIN_MAX,
362 0,
363 rk3308_codec_mic_gain_get,
364 rk3308_codec_mic_gain_put,
365 rk3308_codec_adc_mic_gain_tlv_a),
366 SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Left Gain",
367 RK3308_ADC_ANA_CON01(1),
368 RK3308_ADC_CH1_MIC_GAIN_SFT,
369 RK3308_ADC_CH1_MIC_GAIN_MAX,
370 0,
371 rk3308_codec_mic_gain_get,
372 rk3308_codec_mic_gain_put,
373 rk3308_codec_adc_mic_gain_tlv_a),
374 SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Right Gain",
375 RK3308_ADC_ANA_CON01(1),
376 RK3308_ADC_CH2_MIC_GAIN_SFT,
377 RK3308_ADC_CH2_MIC_GAIN_MAX,
378 0,
379 rk3308_codec_mic_gain_get,
380 rk3308_codec_mic_gain_put,
381 rk3308_codec_adc_mic_gain_tlv_a),
382 SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Left Gain",
383 RK3308_ADC_ANA_CON01(2),
384 RK3308_ADC_CH1_MIC_GAIN_SFT,
385 RK3308_ADC_CH1_MIC_GAIN_MAX,
386 0,
387 rk3308_codec_mic_gain_get,
388 rk3308_codec_mic_gain_put,
389 rk3308_codec_adc_mic_gain_tlv_a),
390 SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Right Gain",
391 RK3308_ADC_ANA_CON01(2),
392 RK3308_ADC_CH2_MIC_GAIN_SFT,
393 RK3308_ADC_CH2_MIC_GAIN_MAX,
394 0,
395 rk3308_codec_mic_gain_get,
396 rk3308_codec_mic_gain_put,
397 rk3308_codec_adc_mic_gain_tlv_a),
398 SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Left Gain",
399 RK3308_ADC_ANA_CON01(3),
400 RK3308_ADC_CH1_MIC_GAIN_SFT,
401 RK3308_ADC_CH1_MIC_GAIN_MAX,
402 0,
403 rk3308_codec_mic_gain_get,
404 rk3308_codec_mic_gain_put,
405 rk3308_codec_adc_mic_gain_tlv_a),
406 SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Right Gain",
407 RK3308_ADC_ANA_CON01(3),
408 RK3308_ADC_CH2_MIC_GAIN_SFT,
409 RK3308_ADC_CH2_MIC_GAIN_MAX,
410 0,
411 rk3308_codec_mic_gain_get,
412 rk3308_codec_mic_gain_put,
413 rk3308_codec_adc_mic_gain_tlv_a),
414 };
415
416 static const struct snd_kcontrol_new mic_gains_b[] = {
417 /* ADC MIC */
418 SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Left Gain",
419 RK3308_ADC_ANA_CON01(0),
420 RK3308_ADC_CH1_MIC_GAIN_SFT,
421 RK3308_ADC_CH1_MIC_GAIN_MAX,
422 0,
423 rk3308_codec_mic_gain_get,
424 rk3308_codec_mic_gain_put,
425 rk3308_codec_adc_mic_gain_tlv_b),
426 SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Right Gain",
427 RK3308_ADC_ANA_CON01(0),
428 RK3308_ADC_CH2_MIC_GAIN_SFT,
429 RK3308_ADC_CH2_MIC_GAIN_MAX,
430 0,
431 rk3308_codec_mic_gain_get,
432 rk3308_codec_mic_gain_put,
433 rk3308_codec_adc_mic_gain_tlv_b),
434 SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Left Gain",
435 RK3308_ADC_ANA_CON01(1),
436 RK3308_ADC_CH1_MIC_GAIN_SFT,
437 RK3308_ADC_CH1_MIC_GAIN_MAX,
438 0,
439 rk3308_codec_mic_gain_get,
440 rk3308_codec_mic_gain_put,
441 rk3308_codec_adc_mic_gain_tlv_b),
442 SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Right Gain",
443 RK3308_ADC_ANA_CON01(1),
444 RK3308_ADC_CH2_MIC_GAIN_SFT,
445 RK3308_ADC_CH2_MIC_GAIN_MAX,
446 0,
447 rk3308_codec_mic_gain_get,
448 rk3308_codec_mic_gain_put,
449 rk3308_codec_adc_mic_gain_tlv_b),
450 SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Left Gain",
451 RK3308_ADC_ANA_CON01(2),
452 RK3308_ADC_CH1_MIC_GAIN_SFT,
453 RK3308_ADC_CH1_MIC_GAIN_MAX,
454 0,
455 rk3308_codec_mic_gain_get,
456 rk3308_codec_mic_gain_put,
457 rk3308_codec_adc_mic_gain_tlv_b),
458 SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Right Gain",
459 RK3308_ADC_ANA_CON01(2),
460 RK3308_ADC_CH2_MIC_GAIN_SFT,
461 RK3308_ADC_CH2_MIC_GAIN_MAX,
462 0,
463 rk3308_codec_mic_gain_get,
464 rk3308_codec_mic_gain_put,
465 rk3308_codec_adc_mic_gain_tlv_b),
466 SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Left Gain",
467 RK3308_ADC_ANA_CON01(3),
468 RK3308_ADC_CH1_MIC_GAIN_SFT,
469 RK3308_ADC_CH1_MIC_GAIN_MAX,
470 0,
471 rk3308_codec_mic_gain_get,
472 rk3308_codec_mic_gain_put,
473 rk3308_codec_adc_mic_gain_tlv_b),
474 SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Right Gain",
475 RK3308_ADC_ANA_CON01(3),
476 RK3308_ADC_CH2_MIC_GAIN_SFT,
477 RK3308_ADC_CH2_MIC_GAIN_MAX,
478 0,
479 rk3308_codec_mic_gain_get,
480 rk3308_codec_mic_gain_put,
481 rk3308_codec_adc_mic_gain_tlv_b),
482 };
483
484 static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = {
485 /* ADC MICBIAS Voltage */
486 SOC_ENUM_EXT("ADC MICBIAS Voltage", rk3308_micbias_volts_enum_array[0],
487 rk3308_codec_micbias_volts_get, rk3308_codec_micbias_volts_put),
488
489 /* ADC Main MICBIAS Switch */
490 SOC_ENUM_EXT("ADC Main MICBIAS", rk3308_main_micbias_enum_array[0],
491 rk3308_codec_main_micbias_get, rk3308_codec_main_micbias_put),
492
493 /* ADC MICBIAS1 and MICBIAS2 Switch */
494 SOC_SINGLE("ADC MICBIAS1", RK3308_ADC_ANA_CON07(1),
495 RK3308_ADC_MIC_BIAS_BUF_SFT, 1, 0),
496 SOC_SINGLE("ADC MICBIAS2", RK3308_ADC_ANA_CON07(2),
497 RK3308_ADC_MIC_BIAS_BUF_SFT, 1, 0),
498
499 /* ADC MIC Mute/Work Switch */
500 SOC_ENUM_EXT("ADC MIC Group 0 Left Switch", rk3308_mic_mute_enum_array[0],
501 rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
502 SOC_ENUM_EXT("ADC MIC Group 0 Right Switch", rk3308_mic_mute_enum_array[1],
503 rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
504 SOC_ENUM_EXT("ADC MIC Group 1 Left Switch", rk3308_mic_mute_enum_array[2],
505 rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
506 SOC_ENUM_EXT("ADC MIC Group 1 Right Switch", rk3308_mic_mute_enum_array[3],
507 rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
508 SOC_ENUM_EXT("ADC MIC Group 2 Left Switch", rk3308_mic_mute_enum_array[4],
509 rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
510 SOC_ENUM_EXT("ADC MIC Group 2 Right Switch", rk3308_mic_mute_enum_array[5],
511 rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
512 SOC_ENUM_EXT("ADC MIC Group 3 Left Switch", rk3308_mic_mute_enum_array[6],
513 rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
514 SOC_ENUM_EXT("ADC MIC Group 3 Right Switch", rk3308_mic_mute_enum_array[7],
515 rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put),
516
517 /* ADC ALC */
518 SOC_SINGLE_RANGE_TLV("ADC ALC Group 0 Left Volume",
519 RK3308_ADC_ANA_CON03(0),
520 RK3308_ADC_CH1_ALC_GAIN_SFT,
521 RK3308_ADC_CH1_ALC_GAIN_MIN,
522 RK3308_ADC_CH1_ALC_GAIN_MAX,
523 0, rk3308_codec_adc_alc_gain_tlv),
524 SOC_SINGLE_RANGE_TLV("ADC ALC Group 0 Right Volume",
525 RK3308_ADC_ANA_CON04(0),
526 RK3308_ADC_CH2_ALC_GAIN_SFT,
527 RK3308_ADC_CH2_ALC_GAIN_MIN,
528 RK3308_ADC_CH2_ALC_GAIN_MAX,
529 0, rk3308_codec_adc_alc_gain_tlv),
530 SOC_SINGLE_RANGE_TLV("ADC ALC Group 1 Left Volume",
531 RK3308_ADC_ANA_CON03(1),
532 RK3308_ADC_CH1_ALC_GAIN_SFT,
533 RK3308_ADC_CH1_ALC_GAIN_MIN,
534 RK3308_ADC_CH1_ALC_GAIN_MAX,
535 0, rk3308_codec_adc_alc_gain_tlv),
536 SOC_SINGLE_RANGE_TLV("ADC ALC Group 1 Right Volume",
537 RK3308_ADC_ANA_CON04(1),
538 RK3308_ADC_CH2_ALC_GAIN_SFT,
539 RK3308_ADC_CH2_ALC_GAIN_MIN,
540 RK3308_ADC_CH2_ALC_GAIN_MAX,
541 0, rk3308_codec_adc_alc_gain_tlv),
542 SOC_SINGLE_RANGE_TLV("ADC ALC Group 2 Left Volume",
543 RK3308_ADC_ANA_CON03(2),
544 RK3308_ADC_CH1_ALC_GAIN_SFT,
545 RK3308_ADC_CH1_ALC_GAIN_MIN,
546 RK3308_ADC_CH1_ALC_GAIN_MAX,
547 0, rk3308_codec_adc_alc_gain_tlv),
548 SOC_SINGLE_RANGE_TLV("ADC ALC Group 2 Right Volume",
549 RK3308_ADC_ANA_CON04(2),
550 RK3308_ADC_CH2_ALC_GAIN_SFT,
551 RK3308_ADC_CH2_ALC_GAIN_MIN,
552 RK3308_ADC_CH2_ALC_GAIN_MAX,
553 0, rk3308_codec_adc_alc_gain_tlv),
554 SOC_SINGLE_RANGE_TLV("ADC ALC Group 3 Left Volume",
555 RK3308_ADC_ANA_CON03(3),
556 RK3308_ADC_CH1_ALC_GAIN_SFT,
557 RK3308_ADC_CH1_ALC_GAIN_MIN,
558 RK3308_ADC_CH1_ALC_GAIN_MAX,
559 0, rk3308_codec_adc_alc_gain_tlv),
560 SOC_SINGLE_RANGE_TLV("ADC ALC Group 3 Right Volume",
561 RK3308_ADC_ANA_CON04(3),
562 RK3308_ADC_CH2_ALC_GAIN_SFT,
563 RK3308_ADC_CH2_ALC_GAIN_MIN,
564 RK3308_ADC_CH2_ALC_GAIN_MAX,
565 0, rk3308_codec_adc_alc_gain_tlv),
566
567 /* ADC High Pass Filter */
568 SOC_ENUM_EXT("ADC Group 0 HPF Cut-off", rk3308_hpf_enum_array[0],
569 rk3308_codec_hpf_get, rk3308_codec_hpf_put),
570 SOC_ENUM_EXT("ADC Group 1 HPF Cut-off", rk3308_hpf_enum_array[1],
571 rk3308_codec_hpf_get, rk3308_codec_hpf_put),
572 SOC_ENUM_EXT("ADC Group 2 HPF Cut-off", rk3308_hpf_enum_array[2],
573 rk3308_codec_hpf_get, rk3308_codec_hpf_put),
574 SOC_ENUM_EXT("ADC Group 3 HPF Cut-off", rk3308_hpf_enum_array[3],
575 rk3308_codec_hpf_get, rk3308_codec_hpf_put),
576
577 /* DAC LINEOUT */
578 SOC_SINGLE_TLV("DAC LINEOUT Left Volume",
579 RK3308_DAC_ANA_CON04,
580 RK3308_DAC_L_LINEOUT_GAIN_SFT,
581 RK3308_DAC_L_LINEOUT_GAIN_MAX,
582 0, rk3308_codec_dac_lineout_gain_tlv),
583 SOC_SINGLE_TLV("DAC LINEOUT Right Volume",
584 RK3308_DAC_ANA_CON04,
585 RK3308_DAC_R_LINEOUT_GAIN_SFT,
586 RK3308_DAC_R_LINEOUT_GAIN_MAX,
587 0, rk3308_codec_dac_lineout_gain_tlv),
588
589 /* DAC HPOUT */
590 SOC_SINGLE_EXT_TLV("DAC HPOUT Left Volume",
591 RK3308_DAC_ANA_CON05,
592 RK3308_DAC_L_HPOUT_GAIN_SFT,
593 RK3308_DAC_L_HPOUT_GAIN_MAX,
594 0,
595 rk3308_codec_hpout_l_get_tlv,
596 rk3308_codec_hpout_l_put_tlv,
597 rk3308_codec_dac_hpout_gain_tlv),
598 SOC_SINGLE_EXT_TLV("DAC HPOUT Right Volume",
599 RK3308_DAC_ANA_CON06,
600 RK3308_DAC_R_HPOUT_GAIN_SFT,
601 RK3308_DAC_R_HPOUT_GAIN_MAX,
602 0,
603 rk3308_codec_hpout_r_get_tlv,
604 rk3308_codec_hpout_r_put_tlv,
605 rk3308_codec_dac_hpout_gain_tlv),
606
607 /* DAC HPMIX */
608 SOC_SINGLE_RANGE_TLV("DAC HPMIX Left Volume",
609 RK3308_DAC_ANA_CON12,
610 RK3308_DAC_L_HPMIX_GAIN_SFT,
611 RK3308_DAC_L_HPMIX_GAIN_MIN,
612 RK3308_DAC_L_HPMIX_GAIN_MAX,
613 0, rk3308_codec_dac_hpmix_gain_tlv),
614 SOC_SINGLE_RANGE_TLV("DAC HPMIX Right Volume",
615 RK3308_DAC_ANA_CON12,
616 RK3308_DAC_R_HPMIX_GAIN_SFT,
617 RK3308_DAC_R_HPMIX_GAIN_MIN,
618 RK3308_DAC_R_HPMIX_GAIN_MAX,
619 0, rk3308_codec_dac_hpmix_gain_tlv),
620 };
621
rk3308_codec_mic_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)622 static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol,
623 struct snd_ctl_elem_value *ucontrol)
624 {
625 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
626 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
627 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
628 unsigned int value;
629 int grp = e->reg;
630
631 if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
632 dev_err(rk3308->plat_dev,
633 "%s: Invalid ADC grp: %d\n", __func__, e->reg);
634 return -EINVAL;
635 }
636
637 if (e->shift_l) {
638 /* ADC MIC Right Mute/Work Infos */
639 regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), &value);
640 rk3308->mic_mute_r[e->reg] = (value & RK3308_ADC_R_CH_BIST_SINE) >>
641 RK3308_ADC_R_CH_BIST_SFT;
642 ucontrol->value.integer.value[0] = rk3308->mic_mute_r[e->reg];
643 } else {
644 /* ADC MIC Left Mute/Work Infos */
645 regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), &value);
646 rk3308->mic_mute_l[e->reg] = (value & RK3308_ADC_L_CH_BIST_SINE) >>
647 RK3308_ADC_L_CH_BIST_SFT;
648 ucontrol->value.integer.value[0] = rk3308->mic_mute_l[e->reg];
649 }
650
651 return 0;
652 }
653
rk3308_codec_mic_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)654 static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol,
655 struct snd_ctl_elem_value *ucontrol)
656 {
657 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
658 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
659 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
660 unsigned int value;
661 int grp = e->reg;
662
663 if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
664 dev_err(rk3308->plat_dev,
665 "%s: Invalid ADC grp: %d\n", __func__, e->reg);
666 return -EINVAL;
667 }
668
669 if (e->shift_l) {
670 /* ADC MIC Right Mute/Work Configuration */
671 value = ucontrol->value.integer.value[0] << RK3308_ADC_R_CH_BIST_SFT;
672 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(grp),
673 RK3308_ADC_R_CH_BIST_SINE,
674 value);
675 rk3308->mic_mute_r[e->reg] = ucontrol->value.integer.value[0];
676 } else {
677 /* ADC MIC Left Mute/Work Configuration */
678 value = ucontrol->value.integer.value[0] << RK3308_ADC_L_CH_BIST_SFT;
679 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(grp),
680 RK3308_ADC_L_CH_BIST_SINE,
681 value);
682 rk3308->mic_mute_l[e->reg] = ucontrol->value.integer.value[0];
683 }
684
685 return 0;
686 }
687
rk3308_codec_micbias_volts_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)688 static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol,
689 struct snd_ctl_elem_value *ucontrol)
690 {
691 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
692 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
693
694 ucontrol->value.integer.value[0] = rk3308->micbias_volt;
695
696 return 0;
697 }
698
rk3308_codec_micbias_volts_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)699 static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol,
700 struct snd_ctl_elem_value *ucontrol)
701 {
702 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
703 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
704 unsigned int volt = ucontrol->value.integer.value[0];
705 int ret;
706
707 ret = check_micbias(volt);
708 if (ret < 0) {
709 dev_err(rk3308->plat_dev, "The invalid micbias volt: %d\n",
710 volt);
711 return ret;
712 }
713
714 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0),
715 RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK,
716 volt);
717
718 rk3308->micbias_volt = volt;
719
720 return 0;
721 }
722
rk3308_codec_main_micbias_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)723 static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol,
724 struct snd_ctl_elem_value *ucontrol)
725 {
726 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
727 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
728
729 ucontrol->value.integer.value[0] = rk3308->enable_micbias;
730
731 return 0;
732 }
733
rk3308_codec_main_micbias_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)734 static int rk3308_codec_main_micbias_put(struct snd_kcontrol *kcontrol,
735 struct snd_ctl_elem_value *ucontrol)
736 {
737 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
738 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
739 unsigned int on = ucontrol->value.integer.value[0];
740
741 if (on) {
742 if (!rk3308->enable_micbias)
743 rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt);
744 } else {
745 if (rk3308->enable_micbias)
746 rk3308_codec_micbias_disable(rk3308);
747 }
748
749 return 0;
750 }
751
rk3308_codec_mic_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)752 static int rk3308_codec_mic_gain_get(struct snd_kcontrol *kcontrol,
753 struct snd_ctl_elem_value *ucontrol)
754 {
755 return snd_soc_get_volsw_range(kcontrol, ucontrol);
756 }
757
rk3308_codec_mic_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)758 static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol,
759 struct snd_ctl_elem_value *ucontrol)
760 {
761 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
762 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
763 unsigned int gain = ucontrol->value.integer.value[0];
764
765 if (gain > RK3308_ADC_CH1_MIC_GAIN_MAX) {
766 dev_err(rk3308->plat_dev, "%s: invalid mic gain: %d\n",
767 __func__, gain);
768 return -EINVAL;
769 }
770
771 if (rk3308->codec_ver == ACODEC_VERSION_A) {
772 /*
773 * From the TRM, there are only suupport 0dB(gain==0) and
774 * 20dB(gain==3) on the codec version A.
775 */
776 if (!(gain == 0 || gain == RK3308_ADC_CH1_MIC_GAIN_MAX)) {
777 dev_err(rk3308->plat_dev,
778 "version A doesn't supported: %d, expect: 0,%d\n",
779 gain, RK3308_ADC_CH1_MIC_GAIN_MAX);
780 return 0;
781 }
782 }
783
784 return snd_soc_put_volsw_range(kcontrol, ucontrol);
785 }
786
rk3308_codec_hpf_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)787 static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol,
788 struct snd_ctl_elem_value *ucontrol)
789 {
790 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
791 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
792 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
793 unsigned int value;
794
795 if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
796 dev_err(rk3308->plat_dev,
797 "%s: Invalid ADC grp: %d\n", __func__, e->reg);
798 return -EINVAL;
799 }
800
801 regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg), &value);
802 if (value & RK3308_ADC_HPF_PATH_MSK)
803 rk3308->hpf_cutoff[e->reg] = 0;
804 else
805 rk3308->hpf_cutoff[e->reg] = 1;
806
807 ucontrol->value.integer.value[0] = rk3308->hpf_cutoff[e->reg];
808
809 return 0;
810 }
811
rk3308_codec_hpf_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)812 static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol,
813 struct snd_ctl_elem_value *ucontrol)
814 {
815 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
816 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
817 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
818 unsigned int value = ucontrol->value.integer.value[0];
819
820 if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
821 dev_err(rk3308->plat_dev,
822 "%s: Invalid ADC grp: %d\n", __func__, e->reg);
823 return -EINVAL;
824 }
825
826 if (value) {
827 /* Enable high pass filter for ADCs */
828 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg),
829 RK3308_ADC_HPF_PATH_MSK,
830 RK3308_ADC_HPF_PATH_EN);
831 } else {
832 /* Disable high pass filter for ADCs. */
833 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg),
834 RK3308_ADC_HPF_PATH_MSK,
835 RK3308_ADC_HPF_PATH_DIS);
836 }
837
838 rk3308->hpf_cutoff[e->reg] = value;
839
840 return 0;
841 }
842
rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)843 static int rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol *kcontrol,
844 struct snd_ctl_elem_value *ucontrol)
845 {
846 return snd_soc_get_volsw_range(kcontrol, ucontrol);
847 }
848
rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)849 static int rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol *kcontrol,
850 struct snd_ctl_elem_value *ucontrol)
851 {
852 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
853 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
854 unsigned int dgain = ucontrol->value.integer.value[0];
855
856 if (dgain > RK3308_DAC_L_HPOUT_GAIN_MAX) {
857 dev_err(rk3308->plat_dev, "%s: invalid l_dgain: %d\n",
858 __func__, dgain);
859 return -EINVAL;
860 }
861
862 rk3308->hpout_l_dgain = dgain;
863
864 return snd_soc_put_volsw_range(kcontrol, ucontrol);
865 }
866
rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)867 static int rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol *kcontrol,
868 struct snd_ctl_elem_value *ucontrol)
869 {
870 return snd_soc_get_volsw_range(kcontrol, ucontrol);
871 }
872
rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)873 static int rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol *kcontrol,
874 struct snd_ctl_elem_value *ucontrol)
875 {
876 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
877 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
878 unsigned int dgain = ucontrol->value.integer.value[0];
879
880 if (dgain > RK3308_DAC_R_HPOUT_GAIN_MAX) {
881 dev_err(rk3308->plat_dev, "%s: invalid r_dgain: %d\n",
882 __func__, dgain);
883 return -EINVAL;
884 }
885
886 rk3308->hpout_r_dgain = dgain;
887
888 return snd_soc_put_volsw_range(kcontrol, ucontrol);
889 }
890
to_mapped_grp(struct rk3308_codec_priv * rk3308,int idx)891 static u32 to_mapped_grp(struct rk3308_codec_priv *rk3308, int idx)
892 {
893 return rk3308->i2s_sdis[idx];
894 }
895
adc_for_each_grp(struct rk3308_codec_priv * rk3308,int type,int idx,u32 * grp)896 static bool adc_for_each_grp(struct rk3308_codec_priv *rk3308,
897 int type, int idx, u32 *grp)
898 {
899 if (type == ADC_TYPE_NORMAL) {
900 u32 mapped_grp = to_mapped_grp(rk3308, idx);
901 int max_grps;
902
903 if (rk3308->enable_all_adcs)
904 max_grps = ADC_LR_GROUP_MAX;
905 else
906 max_grps = rk3308->used_adc_grps;
907
908 if (idx >= max_grps)
909 return false;
910
911 if ((!rk3308->loopback_dacs_enabled) &&
912 handle_loopback(rk3308) &&
913 rk3308->loopback_grp == mapped_grp) {
914 /*
915 * Ths loopback DACs are closed, and specify the
916 * loopback ADCs.
917 */
918 *grp = ADC_GRP_SKIP_MAGIC;
919 } else if (rk3308->en_always_grps_num &&
920 rk3308->skip_grps[mapped_grp]) {
921 /* To set the skip flag if the ADC GRP is enabled. */
922 *grp = ADC_GRP_SKIP_MAGIC;
923 } else {
924 *grp = mapped_grp;
925 }
926
927 dev_dbg(rk3308->plat_dev,
928 "ADC_TYPE_NORMAL, idx: %d, mapped_grp: %d, get grp: %d,\n",
929 idx, mapped_grp, *grp);
930 } else if (type == ADC_TYPE_ALL) {
931 if (idx >= ADC_LR_GROUP_MAX)
932 return false;
933
934 *grp = idx;
935 dev_dbg(rk3308->plat_dev,
936 "ADC_TYPE_ALL, idx: %d, get grp: %d\n",
937 idx, *grp);
938 } else if (type == ADC_TYPE_DBG) {
939 if (idx >= ADC_LR_GROUP_MAX)
940 return false;
941
942 if (idx == (int)rk3308->cur_dbg_grp)
943 *grp = idx;
944 else
945 *grp = ADC_GRP_SKIP_MAGIC;
946
947 dev_dbg(rk3308->plat_dev,
948 "ADC_TYPE_DBG, idx: %d, get grp: %d\n",
949 idx, *grp);
950 } else {
951 if (idx >= 1)
952 return false;
953
954 *grp = rk3308->loopback_grp;
955 dev_dbg(rk3308->plat_dev,
956 "ADC_TYPE_LOOPBACK, idx: %d, get grp: %d\n",
957 idx, *grp);
958 }
959
960 return true;
961 }
962
rk3308_codec_get_dac_path_state(struct rk3308_codec_priv * rk3308)963 static int rk3308_codec_get_dac_path_state(struct rk3308_codec_priv *rk3308)
964 {
965 return rk3308->dac_path_state;
966 }
967
rk3308_codec_set_dac_path_state(struct rk3308_codec_priv * rk3308,int state)968 static void rk3308_codec_set_dac_path_state(struct rk3308_codec_priv *rk3308,
969 int state)
970 {
971 rk3308->dac_path_state = state;
972 }
973
rk3308_headphone_ctl(struct rk3308_codec_priv * rk3308,int on)974 static void rk3308_headphone_ctl(struct rk3308_codec_priv *rk3308, int on)
975 {
976 if (rk3308->hp_ctl_gpio)
977 gpiod_direction_output(rk3308->hp_ctl_gpio, on);
978 }
979
rk3308_speaker_ctl(struct rk3308_codec_priv * rk3308,int on)980 static void rk3308_speaker_ctl(struct rk3308_codec_priv *rk3308, int on)
981 {
982 if (on) {
983 if (rk3308->pa_drv_gpio) {
984 gpiod_direction_output(rk3308->pa_drv_gpio, on);
985 msleep(rk3308->delay_pa_drv_ms);
986 }
987
988 if (rk3308->spk_ctl_gpio)
989 gpiod_direction_output(rk3308->spk_ctl_gpio, on);
990 } else {
991 if (rk3308->spk_ctl_gpio)
992 gpiod_direction_output(rk3308->spk_ctl_gpio, on);
993
994 if (rk3308->pa_drv_gpio) {
995 msleep(rk3308->delay_pa_drv_ms);
996 gpiod_direction_output(rk3308->pa_drv_gpio, on);
997 }
998 }
999 }
1000
rk3308_codec_reset(struct snd_soc_component * component)1001 static int rk3308_codec_reset(struct snd_soc_component *component)
1002 {
1003 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
1004
1005 reset_control_assert(rk3308->reset);
1006 usleep_range(10000, 11000); /* estimated value */
1007 reset_control_deassert(rk3308->reset);
1008
1009 regmap_write(rk3308->regmap, RK3308_GLB_CON, 0x00);
1010 usleep_range(10000, 11000); /* estimated value */
1011 regmap_write(rk3308->regmap, RK3308_GLB_CON,
1012 RK3308_SYS_WORK |
1013 RK3308_DAC_DIG_WORK |
1014 RK3308_ADC_DIG_WORK);
1015
1016 return 0;
1017 }
1018
rk3308_codec_adc_dig_reset(struct rk3308_codec_priv * rk3308)1019 static int rk3308_codec_adc_dig_reset(struct rk3308_codec_priv *rk3308)
1020 {
1021 regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
1022 RK3308_ADC_DIG_WORK,
1023 RK3308_ADC_DIG_RESET);
1024 udelay(50);
1025 regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
1026 RK3308_ADC_DIG_WORK,
1027 RK3308_ADC_DIG_WORK);
1028
1029 return 0;
1030 }
1031
rk3308_codec_dac_dig_reset(struct rk3308_codec_priv * rk3308)1032 static int rk3308_codec_dac_dig_reset(struct rk3308_codec_priv *rk3308)
1033 {
1034 regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
1035 RK3308_DAC_DIG_WORK,
1036 RK3308_DAC_DIG_RESET);
1037 usleep_range(10000, 11000);
1038 regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
1039 RK3308_DAC_DIG_WORK,
1040 RK3308_DAC_DIG_WORK);
1041
1042 return 0;
1043 }
1044
rk3308_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1045 static int rk3308_set_bias_level(struct snd_soc_component *component,
1046 enum snd_soc_bias_level level)
1047 {
1048 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
1049
1050 switch (level) {
1051 case SND_SOC_BIAS_ON:
1052 break;
1053 case SND_SOC_BIAS_PREPARE:
1054 break;
1055 case SND_SOC_BIAS_STANDBY:
1056 regcache_cache_only(rk3308->regmap, false);
1057 regcache_sync(rk3308->regmap);
1058 break;
1059 case SND_SOC_BIAS_OFF:
1060 break;
1061 }
1062
1063 return 0;
1064 }
1065
rk3308_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1066 static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai,
1067 unsigned int fmt)
1068 {
1069 struct snd_soc_component *component = codec_dai->component;
1070 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
1071 unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0;
1072 int idx, grp, is_master;
1073 int type = ADC_TYPE_ALL;
1074
1075 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1076 case SND_SOC_DAIFMT_CBS_CFS:
1077 adc_aif2 |= RK3308_ADC_IO_MODE_SLAVE;
1078 adc_aif2 |= RK3308_ADC_MODE_SLAVE;
1079 if (rk3308->codec_ver == ACODEC_VERSION_C) {
1080 dac_aif2 |= RK3308BS_DAC_IO_MODE_SLAVE;
1081 dac_aif2 |= RK3308BS_DAC_MODE_SLAVE;
1082 } else {
1083 dac_aif2 |= RK3308_DAC_IO_MODE_SLAVE;
1084 dac_aif2 |= RK3308_DAC_MODE_SLAVE;
1085 }
1086 is_master = 0;
1087 break;
1088 case SND_SOC_DAIFMT_CBM_CFM:
1089 adc_aif2 |= RK3308_ADC_IO_MODE_MASTER;
1090 adc_aif2 |= RK3308_ADC_MODE_MASTER;
1091 if (rk3308->codec_ver == ACODEC_VERSION_C) {
1092 dac_aif2 |= RK3308BS_DAC_IO_MODE_MASTER;
1093 dac_aif2 |= RK3308BS_DAC_MODE_MASTER;
1094 } else {
1095 dac_aif2 |= RK3308_DAC_IO_MODE_MASTER;
1096 dac_aif2 |= RK3308_DAC_MODE_MASTER;
1097 }
1098 is_master = 1;
1099 break;
1100 default:
1101 return -EINVAL;
1102 }
1103
1104 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1105 case SND_SOC_DAIFMT_DSP_A:
1106 adc_aif1 |= RK3308_ADC_I2S_MODE_PCM;
1107 dac_aif1 |= RK3308_DAC_I2S_MODE_PCM;
1108 break;
1109 case SND_SOC_DAIFMT_I2S:
1110 adc_aif1 |= RK3308_ADC_I2S_MODE_I2S;
1111 dac_aif1 |= RK3308_DAC_I2S_MODE_I2S;
1112 break;
1113 case SND_SOC_DAIFMT_RIGHT_J:
1114 adc_aif1 |= RK3308_ADC_I2S_MODE_RJ;
1115 dac_aif1 |= RK3308_DAC_I2S_MODE_RJ;
1116 break;
1117 case SND_SOC_DAIFMT_LEFT_J:
1118 adc_aif1 |= RK3308_ADC_I2S_MODE_LJ;
1119 dac_aif1 |= RK3308_DAC_I2S_MODE_LJ;
1120 break;
1121 default:
1122 return -EINVAL;
1123 }
1124
1125 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1126 case SND_SOC_DAIFMT_NB_NF:
1127 adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL;
1128 adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL;
1129 dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL;
1130 dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL;
1131 break;
1132 case SND_SOC_DAIFMT_IB_IF:
1133 adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL;
1134 adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL;
1135 dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL;
1136 dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL;
1137 break;
1138 case SND_SOC_DAIFMT_IB_NF:
1139 adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL;
1140 adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL;
1141 dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL;
1142 dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL;
1143 break;
1144 case SND_SOC_DAIFMT_NB_IF:
1145 adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL;
1146 adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL;
1147 dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL;
1148 dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL;
1149 break;
1150 default:
1151 return -EINVAL;
1152 }
1153
1154 /*
1155 * Hold ADC Digital registers start at master mode
1156 *
1157 * There are 8 ADCs and use the same SCLK and LRCK internal for master
1158 * mode, We need to make sure that they are in effect at the same time,
1159 * otherwise they will cause the abnormal clocks.
1160 */
1161 if (is_master)
1162 regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
1163 RK3308_ADC_DIG_WORK,
1164 RK3308_ADC_DIG_RESET);
1165
1166 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
1167 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
1168 continue;
1169
1170 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp),
1171 RK3308_ADC_I2S_LRC_POL_MSK |
1172 RK3308_ADC_I2S_MODE_MSK,
1173 adc_aif1);
1174 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp),
1175 RK3308_ADC_IO_MODE_MSK |
1176 RK3308_ADC_MODE_MSK |
1177 RK3308_ADC_I2S_BIT_CLK_POL_MSK,
1178 adc_aif2);
1179 }
1180
1181 /* Hold ADC Digital registers end at master mode */
1182 if (is_master)
1183 regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
1184 RK3308_ADC_DIG_WORK,
1185 RK3308_ADC_DIG_WORK);
1186
1187 regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01,
1188 RK3308_DAC_I2S_LRC_POL_MSK |
1189 RK3308_DAC_I2S_MODE_MSK,
1190 dac_aif1);
1191 if (rk3308->codec_ver == ACODEC_VERSION_C) {
1192 regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02,
1193 RK3308BS_DAC_IO_MODE_MSK |
1194 RK3308BS_DAC_MODE_MSK |
1195 RK3308_DAC_I2S_BIT_CLK_POL_MSK,
1196 dac_aif2);
1197 } else {
1198 regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02,
1199 RK3308_DAC_IO_MODE_MSK |
1200 RK3308_DAC_MODE_MSK |
1201 RK3308_DAC_I2S_BIT_CLK_POL_MSK,
1202 dac_aif2);
1203 }
1204
1205 return 0;
1206 }
1207
rk3308_codec_dac_dig_config(struct rk3308_codec_priv * rk3308,struct snd_pcm_hw_params * params)1208 static int rk3308_codec_dac_dig_config(struct rk3308_codec_priv *rk3308,
1209 struct snd_pcm_hw_params *params)
1210 {
1211 unsigned int dac_aif1 = 0, dac_aif2 = 0;
1212
1213 /* Clear the status of DAC DIG Digital reigisters */
1214 rk3308_codec_dac_dig_reset(rk3308);
1215
1216 switch (params_format(params)) {
1217 case SNDRV_PCM_FORMAT_S16_LE:
1218 dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_16BITS;
1219 break;
1220 case SNDRV_PCM_FORMAT_S20_3LE:
1221 dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_20BITS;
1222 break;
1223 case SNDRV_PCM_FORMAT_S24_LE:
1224 dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_24BITS;
1225 break;
1226 case SNDRV_PCM_FORMAT_S32_LE:
1227 dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_32BITS;
1228 break;
1229 default:
1230 return -EINVAL;
1231 }
1232
1233 dac_aif1 |= RK3308_DAC_I2S_LR_NORMAL;
1234 dac_aif2 |= RK3308_DAC_I2S_WORK;
1235
1236 regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01,
1237 RK3308_DAC_I2S_VALID_LEN_MSK |
1238 RK3308_DAC_I2S_LR_MSK,
1239 dac_aif1);
1240 regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02,
1241 RK3308_DAC_I2S_MSK,
1242 dac_aif2);
1243
1244 return 0;
1245 }
1246
rk3308_codec_adc_dig_config(struct rk3308_codec_priv * rk3308,struct snd_pcm_hw_params * params)1247 static int rk3308_codec_adc_dig_config(struct rk3308_codec_priv *rk3308,
1248 struct snd_pcm_hw_params *params)
1249 {
1250 unsigned int adc_aif1 = 0, adc_aif2 = 0;
1251 int type = ADC_TYPE_NORMAL;
1252 int idx, grp;
1253
1254 /* Clear the status of ADC DIG Digital reigisters */
1255 rk3308_codec_adc_dig_reset(rk3308);
1256
1257 switch (params_format(params)) {
1258 case SNDRV_PCM_FORMAT_S16_LE:
1259 adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_16BITS;
1260 break;
1261 case SNDRV_PCM_FORMAT_S20_3LE:
1262 adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_20BITS;
1263 break;
1264 case SNDRV_PCM_FORMAT_S24_LE:
1265 adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_24BITS;
1266 break;
1267 case SNDRV_PCM_FORMAT_S32_LE:
1268 adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_32BITS;
1269 break;
1270 default:
1271 return -EINVAL;
1272 }
1273
1274 switch (params_channels(params)) {
1275 case 1:
1276 adc_aif1 |= RK3308_ADC_I2S_MONO;
1277 break;
1278 case 2:
1279 case 4:
1280 case 6:
1281 case 8:
1282 adc_aif1 |= RK3308_ADC_I2S_STEREO;
1283 break;
1284 default:
1285 return -EINVAL;
1286 }
1287
1288 adc_aif1 |= RK3308_ADC_I2S_LR_NORMAL;
1289 adc_aif2 |= RK3308_ADC_I2S_WORK;
1290
1291 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
1292 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
1293 continue;
1294
1295 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp),
1296 RK3308_ADC_I2S_VALID_LEN_MSK |
1297 RK3308_ADC_I2S_LR_MSK |
1298 RK3308_ADC_I2S_TYPE_MSK,
1299 adc_aif1);
1300 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp),
1301 RK3308_ADC_I2S_MSK,
1302 adc_aif2);
1303 }
1304
1305 return 0;
1306 }
1307
rk3308_codec_update_adc_grps(struct rk3308_codec_priv * rk3308,struct snd_pcm_hw_params * params)1308 static int rk3308_codec_update_adc_grps(struct rk3308_codec_priv *rk3308,
1309 struct snd_pcm_hw_params *params)
1310 {
1311 switch (params_channels(params)) {
1312 case 1:
1313 rk3308->used_adc_grps = 1;
1314 break;
1315 case 2:
1316 case 4:
1317 case 6:
1318 case 8:
1319 rk3308->used_adc_grps = params_channels(params) / 2;
1320 break;
1321 default:
1322 dev_err(rk3308->plat_dev, "Invalid channels: %d\n",
1323 params_channels(params));
1324 return -EINVAL;
1325 }
1326
1327 return 0;
1328 }
1329
rk3308_mute_stream(struct snd_soc_dai * dai,int mute,int stream)1330 static int rk3308_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
1331 {
1332 struct snd_soc_component *component = dai->component;
1333 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
1334
1335 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1336 int dgain;
1337
1338 if (mute) {
1339 if (rk3308->codec_ver <= ACODEC_VERSION_B) {
1340 for (dgain = 0x2; dgain <= 0x7; dgain++) {
1341 /*
1342 * Keep the max -> min digital CIC interpolation
1343 * filter gain step by step.
1344 *
1345 * loud: 0x2; whisper: 0x7
1346 */
1347 regmap_update_bits(rk3308->regmap,
1348 RK3308_DAC_DIG_CON04,
1349 RK3308_DAC_CIC_IF_GAIN_MSK,
1350 dgain);
1351 usleep_range(200, 300); /* estimated value */
1352 }
1353 }
1354
1355 #if !DEBUG_POP_ALWAYS
1356 rk3308_headphone_ctl(rk3308, 0);
1357 rk3308_speaker_ctl(rk3308, 0);
1358 #endif
1359 } else {
1360 #if !DEBUG_POP_ALWAYS
1361 if (rk3308->dac_output == DAC_LINEOUT)
1362 rk3308_speaker_ctl(rk3308, 1);
1363 else if (rk3308->dac_output == DAC_HPOUT)
1364 rk3308_headphone_ctl(rk3308, 1);
1365
1366 if (rk3308->delay_start_play_ms)
1367 msleep(rk3308->delay_start_play_ms);
1368 #endif
1369 if (rk3308->codec_ver <= ACODEC_VERSION_B) {
1370 for (dgain = 0x7; dgain >= 0x2; dgain--) {
1371 /*
1372 * Keep the min -> max digital CIC interpolation
1373 * filter gain step by step
1374 *
1375 * loud: 0x2; whisper: 0x7
1376 */
1377 regmap_update_bits(rk3308->regmap,
1378 RK3308_DAC_DIG_CON04,
1379 RK3308_DAC_CIC_IF_GAIN_MSK,
1380 dgain);
1381 usleep_range(200, 300); /* estimated value */
1382 }
1383 }
1384 }
1385 }
1386
1387 return 0;
1388 }
1389
rk3308_codec_digital_fadein(struct rk3308_codec_priv * rk3308)1390 static int rk3308_codec_digital_fadein(struct rk3308_codec_priv *rk3308)
1391 {
1392 unsigned int dgain, dgain_ref;
1393
1394 if (rk3308->hpout_l_dgain != rk3308->hpout_r_dgain) {
1395 pr_warn("HPOUT l_dgain: 0x%x != r_dgain: 0x%x\n",
1396 rk3308->hpout_l_dgain, rk3308->hpout_r_dgain);
1397 dgain_ref = min(rk3308->hpout_l_dgain, rk3308->hpout_r_dgain);
1398 } else {
1399 dgain_ref = rk3308->hpout_l_dgain;
1400 }
1401
1402 /*
1403 * We'd better change the gain of the left and right channels
1404 * at the same time to avoid different listening
1405 */
1406 for (dgain = RK3308_DAC_L_HPOUT_GAIN_NDB_39;
1407 dgain <= dgain_ref; dgain++) {
1408 /* Step 02 decrease dgains for de-pop */
1409 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05,
1410 RK3308_DAC_L_HPOUT_GAIN_MSK,
1411 dgain);
1412
1413 /* Step 02 decrease dgains for de-pop */
1414 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06,
1415 RK3308_DAC_R_HPOUT_GAIN_MSK,
1416 dgain);
1417 }
1418
1419 return 0;
1420 }
1421
rk3308_codec_digital_fadeout(struct rk3308_codec_priv * rk3308)1422 static int rk3308_codec_digital_fadeout(struct rk3308_codec_priv *rk3308)
1423 {
1424 unsigned int l_dgain, r_dgain;
1425
1426 /*
1427 * Note. In the step2, adjusting the register step by step to
1428 * the appropriate value and taking 20ms as time step
1429 */
1430 regmap_read(rk3308->regmap, RK3308_DAC_ANA_CON05, &l_dgain);
1431 l_dgain &= RK3308_DAC_L_HPOUT_GAIN_MSK;
1432
1433 regmap_read(rk3308->regmap, RK3308_DAC_ANA_CON06, &r_dgain);
1434 r_dgain &= RK3308_DAC_R_HPOUT_GAIN_MSK;
1435
1436 if (l_dgain != r_dgain) {
1437 pr_warn("HPOUT l_dgain: 0x%x != r_dgain: 0x%x\n",
1438 l_dgain, r_dgain);
1439 l_dgain = min(l_dgain, r_dgain);
1440 }
1441
1442 /*
1443 * We'd better change the gain of the left and right channels
1444 * at the same time to avoid different listening
1445 */
1446 while (l_dgain >= RK3308_DAC_L_HPOUT_GAIN_NDB_39) {
1447 /* Step 02 decrease dgains for de-pop */
1448 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05,
1449 RK3308_DAC_L_HPOUT_GAIN_MSK,
1450 l_dgain);
1451
1452 /* Step 02 decrease dgains for de-pop */
1453 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06,
1454 RK3308_DAC_R_HPOUT_GAIN_MSK,
1455 l_dgain);
1456
1457 usleep_range(200, 300); /* estimated value */
1458
1459 if (l_dgain == RK3308_DAC_L_HPOUT_GAIN_NDB_39)
1460 break;
1461
1462 l_dgain--;
1463 }
1464
1465 return 0;
1466 }
1467
rk3308_codec_dac_lineout_enable(struct rk3308_codec_priv * rk3308)1468 static int rk3308_codec_dac_lineout_enable(struct rk3308_codec_priv *rk3308)
1469 {
1470 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
1471 RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
1472 RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
1473 RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL |
1474 RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL);
1475
1476 udelay(20);
1477
1478 /* Step 07 */
1479 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
1480 RK3308_DAC_L_LINEOUT_EN |
1481 RK3308_DAC_R_LINEOUT_EN,
1482 RK3308_DAC_L_LINEOUT_EN |
1483 RK3308_DAC_R_LINEOUT_EN);
1484
1485 udelay(20);
1486
1487 /* Step 19 */
1488 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
1489 RK3308_DAC_L_LINEOUT_UNMUTE |
1490 RK3308_DAC_R_LINEOUT_UNMUTE,
1491 RK3308_DAC_L_LINEOUT_UNMUTE |
1492 RK3308_DAC_R_LINEOUT_UNMUTE);
1493 udelay(20);
1494
1495 return 0;
1496 }
1497
rk3308_codec_dac_lineout_disable(struct rk3308_codec_priv * rk3308)1498 static int rk3308_codec_dac_lineout_disable(struct rk3308_codec_priv *rk3308)
1499 {
1500 /* Step 08 */
1501 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
1502 RK3308_DAC_L_LINEOUT_UNMUTE |
1503 RK3308_DAC_R_LINEOUT_UNMUTE,
1504 RK3308_DAC_L_LINEOUT_MUTE |
1505 RK3308_DAC_R_LINEOUT_MUTE);
1506
1507 /* Step 09 */
1508 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
1509 RK3308_DAC_L_LINEOUT_EN |
1510 RK3308_DAC_R_LINEOUT_EN,
1511 RK3308_DAC_L_LINEOUT_DIS |
1512 RK3308_DAC_R_LINEOUT_DIS);
1513
1514 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
1515 RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
1516 RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
1517 RK3308_DAC_L_SEL_DC_FROM_INTERNAL |
1518 RK3308_DAC_R_SEL_DC_FROM_INTERNAL);
1519
1520 return 0;
1521 }
1522
rk3308_codec_dac_hpout_enable(struct rk3308_codec_priv * rk3308)1523 static int rk3308_codec_dac_hpout_enable(struct rk3308_codec_priv *rk3308)
1524 {
1525 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
1526 RK3308_DAC_HPOUT_POP_SOUND_L_MSK |
1527 RK3308_DAC_HPOUT_POP_SOUND_R_MSK,
1528 RK3308_DAC_HPOUT_POP_SOUND_L_WORK |
1529 RK3308_DAC_HPOUT_POP_SOUND_R_WORK);
1530 udelay(20);
1531
1532 /* Step 07 */
1533 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1534 RK3308_DAC_L_HPOUT_EN |
1535 RK3308_DAC_R_HPOUT_EN,
1536 RK3308_DAC_L_HPOUT_EN |
1537 RK3308_DAC_R_HPOUT_EN);
1538
1539 udelay(20);
1540
1541 /* Step 08 */
1542 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1543 RK3308_DAC_L_HPOUT_WORK |
1544 RK3308_DAC_R_HPOUT_WORK,
1545 RK3308_DAC_L_HPOUT_WORK |
1546 RK3308_DAC_R_HPOUT_WORK);
1547
1548 udelay(20);
1549
1550 /* Step 16 */
1551 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1552 RK3308_DAC_L_HPOUT_UNMUTE |
1553 RK3308_DAC_R_HPOUT_UNMUTE,
1554 RK3308_DAC_L_HPOUT_UNMUTE |
1555 RK3308_DAC_R_HPOUT_UNMUTE);
1556
1557 udelay(20);
1558
1559 return 0;
1560 }
1561
rk3308_codec_dac_hpout_disable(struct rk3308_codec_priv * rk3308)1562 static int rk3308_codec_dac_hpout_disable(struct rk3308_codec_priv *rk3308)
1563 {
1564 /* Step 07 */
1565 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1566 RK3308_DAC_L_HPOUT_EN |
1567 RK3308_DAC_R_HPOUT_EN,
1568 RK3308_DAC_L_HPOUT_DIS |
1569 RK3308_DAC_R_HPOUT_DIS);
1570
1571 /* Step 08 */
1572 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1573 RK3308_DAC_L_HPOUT_WORK |
1574 RK3308_DAC_R_HPOUT_WORK,
1575 RK3308_DAC_L_HPOUT_INIT |
1576 RK3308_DAC_R_HPOUT_INIT);
1577
1578 /* Step 16 */
1579 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1580 RK3308_DAC_L_HPOUT_UNMUTE |
1581 RK3308_DAC_R_HPOUT_UNMUTE,
1582 RK3308_DAC_L_HPOUT_MUTE |
1583 RK3308_DAC_R_HPOUT_MUTE);
1584
1585 udelay(20);
1586 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
1587 RK3308_DAC_HPOUT_POP_SOUND_L_MSK |
1588 RK3308_DAC_HPOUT_POP_SOUND_R_MSK,
1589 RK3308_DAC_HPOUT_POP_SOUND_L_DIS |
1590 RK3308_DAC_HPOUT_POP_SOUND_R_DIS);
1591 return 0;
1592 }
1593
rk3308_codec_dac_switch(struct rk3308_codec_priv * rk3308,int dac_output)1594 static int rk3308_codec_dac_switch(struct rk3308_codec_priv *rk3308,
1595 int dac_output)
1596 { int ret = 0;
1597
1598 if (rk3308->dac_output == dac_output) {
1599 dev_info(rk3308->plat_dev,
1600 "Don't need to change dac_output: %d\n", dac_output);
1601 goto out;
1602 }
1603
1604 switch (dac_output) {
1605 case DAC_LINEOUT:
1606 case DAC_HPOUT:
1607 case DAC_LINEOUT_HPOUT:
1608 break;
1609 default:
1610 dev_err(rk3308->plat_dev, "Unknown value: %d\n", dac_output);
1611 ret = -EINVAL;
1612 goto out;
1613 }
1614
1615 if (rk3308_codec_get_dac_path_state(rk3308) == PATH_BUSY) {
1616 /*
1617 * We can only switch the audio path to LINEOUT or HPOUT on
1618 * codec during playbacking, otherwise, just update the
1619 * dac_output flag.
1620 */
1621 switch (dac_output) {
1622 case DAC_LINEOUT:
1623 rk3308_headphone_ctl(rk3308, 0);
1624 rk3308_speaker_ctl(rk3308, 1);
1625 rk3308_codec_dac_hpout_disable(rk3308);
1626 rk3308_codec_dac_lineout_enable(rk3308);
1627 break;
1628 case DAC_HPOUT:
1629 rk3308_speaker_ctl(rk3308, 0);
1630 rk3308_headphone_ctl(rk3308, 1);
1631 rk3308_codec_dac_lineout_disable(rk3308);
1632 rk3308_codec_dac_hpout_enable(rk3308);
1633 break;
1634 case DAC_LINEOUT_HPOUT:
1635 rk3308_speaker_ctl(rk3308, 1);
1636 rk3308_headphone_ctl(rk3308, 1);
1637 rk3308_codec_dac_lineout_enable(rk3308);
1638 rk3308_codec_dac_hpout_enable(rk3308);
1639 break;
1640 default:
1641 break;
1642 }
1643 }
1644
1645 rk3308->dac_output = dac_output;
1646 out:
1647 dev_dbg(rk3308->plat_dev, "switch dac_output to: %d\n",
1648 rk3308->dac_output);
1649
1650 return ret;
1651 }
1652
rk3308_codec_dac_enable(struct rk3308_codec_priv * rk3308)1653 static int rk3308_codec_dac_enable(struct rk3308_codec_priv *rk3308)
1654 {
1655 /*
1656 * Note1. If the ACODEC_DAC_ANA_CON12[6] or ACODEC_DAC_ANA_CON12[2]
1657 * is set to 0x1, ignoring the step9~12.
1658 */
1659
1660 /*
1661 * Note2. If the ACODEC_ DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3]
1662 * is set to 0x1, the ADC0 or ADC1 should be enabled firstly, and
1663 * please refer to Enable ADC Configuration Standard Usage Flow(expect
1664 * step7~step9,step14).
1665 */
1666
1667 /*
1668 * Note3. If no opening the line out, ignoring the step6, step17 and
1669 * step19.
1670 */
1671
1672 /*
1673 * Note4. If no opening the headphone out, ignoring the step3,step7~8,
1674 * step16 and step18.
1675 */
1676
1677 /*
1678 * Note5. In the step18, adjust the register step by step to the
1679 * appropriate value and taking 10ms as one time step
1680 */
1681
1682 /*
1683 * 1. Set the ACODEC_DAC_ANA_CON0[0] to 0x1, to enable the current
1684 * source of DAC
1685 */
1686 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
1687 RK3308_DAC_CURRENT_MSK,
1688 RK3308_DAC_CURRENT_EN);
1689
1690 udelay(20);
1691
1692 /*
1693 * 2. Set the ACODEC_DAC_ANA_CON1[6] and ACODEC_DAC_ANA_CON1[2] to 0x1,
1694 * to enable the reference voltage buffer
1695 */
1696 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
1697 RK3308_DAC_BUF_REF_L_MSK |
1698 RK3308_DAC_BUF_REF_R_MSK,
1699 RK3308_DAC_BUF_REF_L_EN |
1700 RK3308_DAC_BUF_REF_R_EN);
1701
1702 /* Waiting the stable reference voltage */
1703 mdelay(1);
1704
1705 /* Step 03 */
1706 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
1707 RK3308_DAC_HPOUT_POP_SOUND_L_MSK |
1708 RK3308_DAC_HPOUT_POP_SOUND_R_MSK,
1709 RK3308_DAC_HPOUT_POP_SOUND_L_WORK |
1710 RK3308_DAC_HPOUT_POP_SOUND_R_WORK);
1711
1712 udelay(20);
1713
1714 if (rk3308->codec_ver >= ACODEC_VERSION_B &&
1715 (rk3308->dac_output == DAC_LINEOUT ||
1716 rk3308->dac_output == DAC_LINEOUT_HPOUT)) {
1717 /* Step 04 */
1718 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
1719 RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
1720 RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
1721 RK3308_DAC_L_SEL_DC_FROM_INTERNAL |
1722 RK3308_DAC_R_SEL_DC_FROM_INTERNAL);
1723
1724 udelay(20);
1725 }
1726
1727 /* Step 05 */
1728 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
1729 RK3308_DAC_L_HPMIX_EN |
1730 RK3308_DAC_R_HPMIX_EN,
1731 RK3308_DAC_L_HPMIX_EN |
1732 RK3308_DAC_R_HPMIX_EN);
1733
1734 /* Waiting the stable HPMIX */
1735 mdelay(1);
1736
1737 /* Step 06. Reset HPMIX and recover HPMIX gains */
1738 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
1739 RK3308_DAC_L_HPMIX_WORK |
1740 RK3308_DAC_R_HPMIX_WORK,
1741 RK3308_DAC_L_HPMIX_INIT |
1742 RK3308_DAC_R_HPMIX_INIT);
1743 udelay(50);
1744 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
1745 RK3308_DAC_L_HPMIX_WORK |
1746 RK3308_DAC_R_HPMIX_WORK,
1747 RK3308_DAC_L_HPMIX_WORK |
1748 RK3308_DAC_R_HPMIX_WORK);
1749
1750 udelay(20);
1751
1752 if (rk3308->dac_output == DAC_LINEOUT ||
1753 rk3308->dac_output == DAC_LINEOUT_HPOUT) {
1754 /* Step 07 */
1755 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
1756 RK3308_DAC_L_LINEOUT_EN |
1757 RK3308_DAC_R_LINEOUT_EN,
1758 RK3308_DAC_L_LINEOUT_EN |
1759 RK3308_DAC_R_LINEOUT_EN);
1760
1761 udelay(20);
1762 }
1763
1764 if (rk3308->dac_output == DAC_HPOUT ||
1765 rk3308->dac_output == DAC_LINEOUT_HPOUT) {
1766 /* Step 08 */
1767 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1768 RK3308_DAC_L_HPOUT_EN |
1769 RK3308_DAC_R_HPOUT_EN,
1770 RK3308_DAC_L_HPOUT_EN |
1771 RK3308_DAC_R_HPOUT_EN);
1772
1773 udelay(20);
1774
1775 /* Step 09 */
1776 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1777 RK3308_DAC_L_HPOUT_WORK |
1778 RK3308_DAC_R_HPOUT_WORK,
1779 RK3308_DAC_L_HPOUT_WORK |
1780 RK3308_DAC_R_HPOUT_WORK);
1781
1782 udelay(20);
1783 }
1784
1785 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
1786 /* Step 10 */
1787 if (rk3308->dac_output == DAC_HPOUT) {
1788 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
1789 RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
1790 RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
1791 RK3308_DAC_L_SEL_DC_FROM_INTERNAL |
1792 RK3308_DAC_R_SEL_DC_FROM_INTERNAL);
1793 } else {
1794 /* LINEOUT and LINEOUT + HPOUT */
1795 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
1796 RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
1797 RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
1798 RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL |
1799 RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL);
1800 }
1801
1802 udelay(20);
1803 }
1804
1805 /* Step 11 */
1806 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
1807 RK3308_DAC_L_REF_EN |
1808 RK3308_DAC_R_REF_EN,
1809 RK3308_DAC_L_REF_EN |
1810 RK3308_DAC_R_REF_EN);
1811
1812 udelay(20);
1813
1814 /* Step 12 */
1815 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
1816 RK3308_DAC_L_CLK_EN |
1817 RK3308_DAC_R_CLK_EN,
1818 RK3308_DAC_L_CLK_EN |
1819 RK3308_DAC_R_CLK_EN);
1820
1821 udelay(20);
1822
1823 /* Step 13 */
1824 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
1825 RK3308_DAC_L_DAC_EN |
1826 RK3308_DAC_R_DAC_EN,
1827 RK3308_DAC_L_DAC_EN |
1828 RK3308_DAC_R_DAC_EN);
1829
1830 udelay(20);
1831
1832 /* Step 14 */
1833 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
1834 RK3308_DAC_L_DAC_WORK |
1835 RK3308_DAC_R_DAC_WORK,
1836 RK3308_DAC_L_DAC_WORK |
1837 RK3308_DAC_R_DAC_WORK);
1838
1839 udelay(20);
1840
1841 /* Step 15 */
1842 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
1843 RK3308_DAC_L_HPMIX_SEL_MSK |
1844 RK3308_DAC_R_HPMIX_SEL_MSK,
1845 RK3308_DAC_L_HPMIX_I2S |
1846 RK3308_DAC_R_HPMIX_I2S);
1847
1848 udelay(20);
1849
1850 /* Step 16 */
1851 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
1852 RK3308_DAC_L_HPMIX_UNMUTE |
1853 RK3308_DAC_R_HPMIX_UNMUTE,
1854 RK3308_DAC_L_HPMIX_UNMUTE |
1855 RK3308_DAC_R_HPMIX_UNMUTE);
1856
1857 udelay(20);
1858
1859 /* Step 17: Put configuration HPMIX Gain to DAPM */
1860
1861 if (rk3308->dac_output == DAC_HPOUT ||
1862 rk3308->dac_output == DAC_LINEOUT_HPOUT) {
1863 /* Step 18 */
1864 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1865 RK3308_DAC_L_HPOUT_UNMUTE |
1866 RK3308_DAC_R_HPOUT_UNMUTE,
1867 RK3308_DAC_L_HPOUT_UNMUTE |
1868 RK3308_DAC_R_HPOUT_UNMUTE);
1869
1870 udelay(20);
1871 }
1872
1873 if (rk3308->dac_output == DAC_LINEOUT ||
1874 rk3308->dac_output == DAC_LINEOUT_HPOUT) {
1875 /* Step 19 */
1876 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
1877 RK3308_DAC_L_LINEOUT_UNMUTE |
1878 RK3308_DAC_R_LINEOUT_UNMUTE,
1879 RK3308_DAC_L_LINEOUT_UNMUTE |
1880 RK3308_DAC_R_LINEOUT_UNMUTE);
1881 udelay(20);
1882 }
1883
1884 /* Step 20, put configuration HPOUT gain to DAPM control */
1885 /* Step 21, put configuration LINEOUT gain to DAPM control */
1886
1887 if (rk3308->dac_output == DAC_HPOUT ||
1888 rk3308->dac_output == DAC_LINEOUT_HPOUT) {
1889 /* Just for HPOUT */
1890 rk3308_codec_digital_fadein(rk3308);
1891 }
1892
1893 rk3308->dac_endisable = true;
1894
1895 /* TODO: TRY TO TEST DRIVE STRENGTH */
1896
1897 return 0;
1898 }
1899
rk3308_codec_dac_disable(struct rk3308_codec_priv * rk3308)1900 static int rk3308_codec_dac_disable(struct rk3308_codec_priv *rk3308)
1901 {
1902 /*
1903 * Step 00 skipped. Keep the DAC channel work and input the mute signal.
1904 */
1905
1906 /* Step 01 skipped. May set the min gain for LINEOUT. */
1907
1908 /* Step 02 skipped. May set the min gain for HPOUT. */
1909
1910 if (rk3308->dac_output == DAC_HPOUT ||
1911 rk3308->dac_output == DAC_LINEOUT_HPOUT) {
1912 /* Just for HPOUT */
1913 rk3308_codec_digital_fadeout(rk3308);
1914 }
1915
1916 /* Step 03 */
1917 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
1918 RK3308_DAC_L_HPMIX_UNMUTE |
1919 RK3308_DAC_R_HPMIX_UNMUTE,
1920 RK3308_DAC_L_HPMIX_UNMUTE |
1921 RK3308_DAC_R_HPMIX_UNMUTE);
1922
1923 /* Step 04 */
1924 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
1925 RK3308_DAC_L_HPMIX_SEL_MSK |
1926 RK3308_DAC_R_HPMIX_SEL_MSK,
1927 RK3308_DAC_L_HPMIX_NONE |
1928 RK3308_DAC_R_HPMIX_NONE);
1929 /* Step 05 */
1930 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1931 RK3308_DAC_L_HPOUT_UNMUTE |
1932 RK3308_DAC_R_HPOUT_UNMUTE,
1933 RK3308_DAC_L_HPOUT_MUTE |
1934 RK3308_DAC_R_HPOUT_MUTE);
1935
1936 /* Step 06 */
1937 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
1938 RK3308_DAC_L_DAC_WORK |
1939 RK3308_DAC_R_DAC_WORK,
1940 RK3308_DAC_L_DAC_INIT |
1941 RK3308_DAC_R_DAC_INIT);
1942
1943 /* Step 07 */
1944 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
1945 RK3308_DAC_L_HPOUT_EN |
1946 RK3308_DAC_R_HPOUT_EN,
1947 RK3308_DAC_L_HPOUT_DIS |
1948 RK3308_DAC_R_HPOUT_DIS);
1949
1950 /* Step 08 */
1951 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
1952 RK3308_DAC_L_LINEOUT_UNMUTE |
1953 RK3308_DAC_R_LINEOUT_UNMUTE,
1954 RK3308_DAC_L_LINEOUT_MUTE |
1955 RK3308_DAC_R_LINEOUT_MUTE);
1956
1957 /* Step 09 */
1958 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
1959 RK3308_DAC_L_LINEOUT_EN |
1960 RK3308_DAC_R_LINEOUT_EN,
1961 RK3308_DAC_L_LINEOUT_DIS |
1962 RK3308_DAC_R_LINEOUT_DIS);
1963
1964 /* Step 10 */
1965 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
1966 RK3308_DAC_L_HPMIX_EN |
1967 RK3308_DAC_R_HPMIX_EN,
1968 RK3308_DAC_L_HPMIX_DIS |
1969 RK3308_DAC_R_HPMIX_DIS);
1970
1971 /* Step 11 */
1972 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
1973 RK3308_DAC_L_DAC_EN |
1974 RK3308_DAC_R_DAC_EN,
1975 RK3308_DAC_L_DAC_DIS |
1976 RK3308_DAC_R_DAC_DIS);
1977
1978 /* Step 12 */
1979 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
1980 RK3308_DAC_L_CLK_EN |
1981 RK3308_DAC_R_CLK_EN,
1982 RK3308_DAC_L_CLK_DIS |
1983 RK3308_DAC_R_CLK_DIS);
1984
1985 /* Step 13 */
1986 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02,
1987 RK3308_DAC_L_REF_EN |
1988 RK3308_DAC_R_REF_EN,
1989 RK3308_DAC_L_REF_DIS |
1990 RK3308_DAC_R_REF_DIS);
1991
1992 /* Step 14 */
1993 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
1994 RK3308_DAC_HPOUT_POP_SOUND_L_MSK |
1995 RK3308_DAC_HPOUT_POP_SOUND_R_MSK,
1996 RK3308_DAC_HPOUT_POP_SOUND_L_INIT |
1997 RK3308_DAC_HPOUT_POP_SOUND_R_INIT);
1998
1999 /* Step 15 */
2000 if (rk3308->codec_ver >= ACODEC_VERSION_B &&
2001 (rk3308->dac_output == DAC_LINEOUT ||
2002 rk3308->dac_output == DAC_LINEOUT_HPOUT)) {
2003 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
2004 RK3308_DAC_LINEOUT_POP_SOUND_L_MSK |
2005 RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
2006 RK3308_DAC_L_SEL_DC_FROM_VCM |
2007 RK3308_DAC_R_SEL_DC_FROM_VCM);
2008 }
2009
2010 /* Step 16 */
2011 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
2012 RK3308_DAC_BUF_REF_L_EN |
2013 RK3308_DAC_BUF_REF_R_EN,
2014 RK3308_DAC_BUF_REF_L_DIS |
2015 RK3308_DAC_BUF_REF_R_DIS);
2016
2017 /* Step 17 */
2018 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
2019 RK3308_DAC_CURRENT_EN,
2020 RK3308_DAC_CURRENT_DIS);
2021
2022 /* Step 18 */
2023 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03,
2024 RK3308_DAC_L_HPOUT_WORK |
2025 RK3308_DAC_R_HPOUT_WORK,
2026 RK3308_DAC_L_HPOUT_INIT |
2027 RK3308_DAC_R_HPOUT_INIT);
2028
2029 /* Step 19 */
2030 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13,
2031 RK3308_DAC_L_HPMIX_WORK |
2032 RK3308_DAC_R_HPMIX_WORK,
2033 RK3308_DAC_L_HPMIX_WORK |
2034 RK3308_DAC_R_HPMIX_WORK);
2035
2036 /* Step 20 skipped, may set the min gain for HPOUT. */
2037
2038 /*
2039 * Note2. If the ACODEC_DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3]
2040 * is set to 0x1, add the steps from the section Disable ADC
2041 * Configuration Standard Usage Flow after complete the step 19
2042 *
2043 * IF USING LINE-IN
2044 * rk3308_codec_adc_ana_disable(rk3308, type);
2045 */
2046
2047 rk3308->dac_endisable = false;
2048
2049 return 0;
2050 }
2051
rk3308_codec_power_on(struct rk3308_codec_priv * rk3308)2052 static int rk3308_codec_power_on(struct rk3308_codec_priv *rk3308)
2053 {
2054 unsigned int v;
2055
2056 /* 0. Supply the power of digital part and reset the Audio Codec */
2057 /* Do nothing */
2058
2059 /*
2060 * 1. Configure ACODEC_DAC_ANA_CON1[1:0] and ACODEC_DAC_ANA_CON1[5:4]
2061 * to 0x1, to setup dc voltage of the DAC channel output.
2062 */
2063 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
2064 RK3308_DAC_HPOUT_POP_SOUND_L_MSK,
2065 RK3308_DAC_HPOUT_POP_SOUND_L_INIT);
2066 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01,
2067 RK3308_DAC_HPOUT_POP_SOUND_R_MSK,
2068 RK3308_DAC_HPOUT_POP_SOUND_R_INIT);
2069
2070 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
2071 /*
2072 * 2. Configure ACODEC_DAC_ANA_CON15[1:0] and
2073 * ACODEC_DAC_ANA_CON15[5:4] to 0x1, to setup dc voltage of
2074 * the DAC channel output.
2075 */
2076 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
2077 RK3308_DAC_LINEOUT_POP_SOUND_L_MSK,
2078 RK3308_DAC_L_SEL_DC_FROM_VCM);
2079 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15,
2080 RK3308_DAC_LINEOUT_POP_SOUND_R_MSK,
2081 RK3308_DAC_R_SEL_DC_FROM_VCM);
2082 }
2083
2084 /*
2085 * 3. Configure the register ACODEC_ADC_ANA_CON10[3:0] to 7’b000_0001.
2086 */
2087 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
2088 RK3308_ADC_CURRENT_CHARGE_MSK,
2089 RK3308_ADC_SEL_I(0x1));
2090
2091 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
2092 /*
2093 * 4. Configure the register ACODEC_ADC_ANA_CON14[3:0] to
2094 * 4’b0001.
2095 */
2096 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
2097 RK3308_DAC_CURRENT_CHARGE_MSK,
2098 RK3308_DAC_SEL_I(0x1));
2099 }
2100
2101 /* 5. Supply the power of the analog part(AVDD,AVDDRV) */
2102
2103 /*
2104 * 6. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x1 to setup
2105 * reference voltage
2106 */
2107 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
2108 RK3308_ADC_REF_EN, RK3308_ADC_REF_EN);
2109
2110 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
2111 /*
2112 * 7. Configure the register ACODEC_ADC_ANA_CON14[4] to 0x1 to
2113 * setup reference voltage
2114 */
2115 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
2116 RK3308_DAC_VCM_LINEOUT_EN,
2117 RK3308_DAC_VCM_LINEOUT_EN);
2118 }
2119
2120 /*
2121 * 8. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to
2122 * 0x7f step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to
2123 * 0x7f directly. Here the slot time of the step is 200us.
2124 */
2125 for (v = 0x1; v <= 0x7f; v++) {
2126 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
2127 RK3308_ADC_CURRENT_CHARGE_MSK,
2128 v);
2129 udelay(200);
2130 }
2131
2132 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
2133 /*
2134 * 9. Change the register ACODEC_ADC_ANA_CON14[3:0] from the 0x1
2135 * to 0xf step by step or configure the
2136 * ACODEC_ADC_ANA_CON14[3:0] to 0xf directly. Here the slot
2137 * time of the step is 200us.
2138 */
2139 for (v = 0x1; v <= 0xf; v++) {
2140 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
2141 RK3308_DAC_CURRENT_CHARGE_MSK,
2142 v);
2143 udelay(200);
2144 }
2145 }
2146
2147 /* 10. Wait until the voltage of VCM keeps stable at the AVDD/2 */
2148 msleep(20); /* estimated value */
2149
2150 /*
2151 * 11. Configure the register ACODEC_ADC_ANA_CON10[6:0] to the
2152 * appropriate value(expect 0x0) for reducing power.
2153 */
2154 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
2155 RK3308_ADC_CURRENT_CHARGE_MSK, 0x7c);
2156
2157 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
2158 /*
2159 * 12. Configure the register ACODEC_DAC_ANA_CON14[6:0] to the
2160 * appropriate value(expect 0x0) for reducing power.
2161 */
2162 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
2163 RK3308_DAC_CURRENT_CHARGE_MSK, 0xf);
2164 }
2165
2166 if (rk3308->codec_ver == ACODEC_VERSION_C) {
2167 /* Using large driver strength for HPOUT and LINEOUT */
2168 regmap_write(rk3308->regmap, RK3308_DAC_ANA_CON07, 0x11);
2169 regmap_write(rk3308->regmap, RK3308_DAC_ANA_CON08, 0x11);
2170 }
2171
2172 return 0;
2173 }
2174
rk3308_codec_power_off(struct rk3308_codec_priv * rk3308)2175 static int rk3308_codec_power_off(struct rk3308_codec_priv *rk3308)
2176 {
2177 unsigned int v;
2178
2179 /*
2180 * 0. Keep the power on and disable the DAC and ADC path according to
2181 * the section power on configuration standard usage flow.
2182 */
2183
2184 /*
2185 * 1. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 7’b000_0001.
2186 */
2187 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
2188 RK3308_ADC_CURRENT_CHARGE_MSK,
2189 RK3308_ADC_SEL_I(0x1));
2190
2191 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
2192 /*
2193 * 2. Configure the register ACODEC_DAC_ANA_CON14[3:0] to
2194 * 4’b0001.
2195 */
2196 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
2197 RK3308_DAC_CURRENT_CHARGE_MSK,
2198 RK3308_DAC_SEL_I(0x1));
2199 }
2200
2201 /* 3. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x0 */
2202 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
2203 RK3308_ADC_REF_EN,
2204 RK3308_ADC_REF_DIS);
2205
2206 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
2207 /* 4. Configure the register ACODEC_DAC_ANA_CON14[7] to 0x0 */
2208 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14,
2209 RK3308_DAC_VCM_LINEOUT_EN,
2210 RK3308_DAC_VCM_LINEOUT_DIS);
2211 }
2212
2213 /*
2214 * 5. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to 0x7f
2215 * step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to 0x7f
2216 * directly. Here the slot time of the step is 200us.
2217 */
2218 for (v = 0x1; v <= 0x7f; v++) {
2219 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0),
2220 RK3308_ADC_CURRENT_CHARGE_MSK,
2221 v);
2222 udelay(200);
2223 }
2224
2225 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
2226 /*
2227 * 6. Change the register ACODEC_DAC_ANA_CON14[3:0] from the 0x1
2228 * to 0xf step by step or configure the
2229 * ACODEC_DAC_ANA_CON14[3:0] to 0xf directly. Here the slot
2230 * time of the step is 200us.
2231 */
2232 for (v = 0x1; v <= 0x7f; v++) {
2233 regmap_update_bits(rk3308->regmap,
2234 RK3308_ADC_ANA_CON10(0),
2235 RK3308_ADC_CURRENT_CHARGE_MSK,
2236 v);
2237 udelay(200);
2238 }
2239 }
2240
2241 /* 7. Wait until the voltage of VCM keeps stable at the AGND */
2242 msleep(20); /* estimated value */
2243
2244 /* 8. Power off the analog power supply */
2245 /* 9. Power off the digital power supply */
2246
2247 /* Do something via hardware */
2248
2249 return 0;
2250 }
2251
rk3308_codec_headset_detect_enable(struct rk3308_codec_priv * rk3308)2252 static int rk3308_codec_headset_detect_enable(struct rk3308_codec_priv *rk3308)
2253 {
2254 if (rk3308->codec_ver == ACODEC_VERSION_C)
2255 rk3308_codec_dac_mclk_enable(rk3308);
2256
2257 /*
2258 * Set ACODEC_DAC_ANA_CON0[1] to 0x1, to enable the headset insert
2259 * detection
2260 *
2261 * Note. When the voltage of PAD HPDET> 8*AVDD/9, the output value of
2262 * the pin_hpdet will be set to 0x1 and assert a interrupt
2263 */
2264 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
2265 RK3308_DAC_HEADPHONE_DET_MSK,
2266 RK3308_DAC_HEADPHONE_DET_EN);
2267
2268 return 0;
2269 }
2270
rk3308_codec_headset_detect_disable(struct rk3308_codec_priv * rk3308)2271 static int rk3308_codec_headset_detect_disable(struct rk3308_codec_priv *rk3308)
2272 {
2273 /*
2274 * Set ACODEC_DAC_ANA_CON0[1] to 0x0, to disable the headset insert
2275 * detection
2276 */
2277 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00,
2278 RK3308_DAC_HEADPHONE_DET_MSK,
2279 RK3308_DAC_HEADPHONE_DET_DIS);
2280
2281 return 0;
2282 }
2283
rk3308_codec_check_i2s_sdis(struct rk3308_codec_priv * rk3308,int num)2284 static int rk3308_codec_check_i2s_sdis(struct rk3308_codec_priv *rk3308,
2285 int num)
2286 {
2287 int i, j, ret = 0;
2288
2289 switch (num) {
2290 case 1:
2291 rk3308->which_i2s = ACODEC_TO_I2S1_2CH;
2292 break;
2293 case 2:
2294 rk3308->which_i2s = ACODEC_TO_I2S3_4CH;
2295 break;
2296 case 4:
2297 rk3308->which_i2s = ACODEC_TO_I2S2_8CH;
2298 break;
2299 default:
2300 dev_err(rk3308->plat_dev, "Invalid i2s sdis num: %d\n", num);
2301 ret = -EINVAL;
2302 goto err;
2303 }
2304
2305 for (i = 0; i < num; i++) {
2306 if (rk3308->i2s_sdis[i] > ADC_LR_GROUP_MAX - 1) {
2307 dev_err(rk3308->plat_dev,
2308 "i2s_sdis[%d]: %d is overflow\n",
2309 i, rk3308->i2s_sdis[i]);
2310 ret = -EINVAL;
2311 goto err;
2312 }
2313
2314 for (j = 0; j < num; j++) {
2315 if (i == j)
2316 continue;
2317
2318 if (rk3308->i2s_sdis[i] == rk3308->i2s_sdis[j]) {
2319 dev_err(rk3308->plat_dev,
2320 "Invalid i2s_sdis: [%d]%d == [%d]%d\n",
2321 i, rk3308->i2s_sdis[i],
2322 j, rk3308->i2s_sdis[j]);
2323 ret = -EINVAL;
2324 goto err;
2325 }
2326 }
2327 }
2328
2329 err:
2330 return ret;
2331 }
2332
rk3308_codec_adc_grps_route_config(struct rk3308_codec_priv * rk3308)2333 static int rk3308_codec_adc_grps_route_config(struct rk3308_codec_priv *rk3308)
2334 {
2335 int idx = 0;
2336
2337 if (rk3308->which_i2s == ACODEC_TO_I2S2_8CH) {
2338 for (idx = 0; idx < rk3308->to_i2s_grps; idx++) {
2339 regmap_write(rk3308->grf, GRF_SOC_CON1,
2340 GRF_I2S2_8CH_SDI(idx, rk3308->i2s_sdis[idx]));
2341 }
2342 } else if (rk3308->which_i2s == ACODEC_TO_I2S3_4CH) {
2343 for (idx = 0; idx < rk3308->to_i2s_grps; idx++) {
2344 regmap_write(rk3308->grf, GRF_SOC_CON1,
2345 GRF_I2S3_4CH_SDI(idx, rk3308->i2s_sdis[idx]));
2346 }
2347 } else if (rk3308->which_i2s == ACODEC_TO_I2S1_2CH) {
2348 regmap_write(rk3308->grf, GRF_SOC_CON1,
2349 GRF_I2S1_2CH_SDI(rk3308->i2s_sdis[idx]));
2350 }
2351
2352 return 0;
2353 }
2354
2355 /* Put default one-to-one mapping */
rk3308_codec_adc_grps_route_default(struct rk3308_codec_priv * rk3308)2356 static int rk3308_codec_adc_grps_route_default(struct rk3308_codec_priv *rk3308)
2357 {
2358 unsigned int idx;
2359
2360 /*
2361 * The GRF values may be kept the previous status after hot reboot,
2362 * if the property 'rockchip,adc-grps-route' is not set, we need to
2363 * recover default the order of sdi/sdo for i2s2_8ch/i2s3_8ch/i2s1_2ch.
2364 */
2365 regmap_write(rk3308->grf, GRF_SOC_CON1,
2366 GRF_I2S1_2CH_SDI(0));
2367
2368 for (idx = 0; idx < 2; idx++) {
2369 regmap_write(rk3308->grf, GRF_SOC_CON1,
2370 GRF_I2S3_4CH_SDI(idx, idx));
2371 }
2372
2373 /* Using i2s2_8ch by default. */
2374 rk3308->which_i2s = ACODEC_TO_I2S2_8CH;
2375 rk3308->to_i2s_grps = ADC_LR_GROUP_MAX;
2376
2377 for (idx = 0; idx < ADC_LR_GROUP_MAX; idx++) {
2378 rk3308->i2s_sdis[idx] = idx;
2379 regmap_write(rk3308->grf, GRF_SOC_CON1,
2380 GRF_I2S2_8CH_SDI(idx, idx));
2381 }
2382
2383 return 0;
2384 }
2385
rk3308_codec_adc_grps_route(struct rk3308_codec_priv * rk3308,struct device_node * np)2386 static int rk3308_codec_adc_grps_route(struct rk3308_codec_priv *rk3308,
2387 struct device_node *np)
2388 {
2389 int num, ret;
2390
2391 num = of_count_phandle_with_args(np, "rockchip,adc-grps-route", NULL);
2392 if (num < 0) {
2393 if (num == -ENOENT) {
2394 /* Not use 'rockchip,adc-grps-route' property here */
2395 rk3308_codec_adc_grps_route_default(rk3308);
2396 ret = 0;
2397 } else {
2398 dev_err(rk3308->plat_dev,
2399 "Failed to read 'rockchip,adc-grps-route' num: %d\n",
2400 num);
2401 ret = num;
2402 }
2403 return ret;
2404 }
2405
2406 ret = of_property_read_u32_array(np, "rockchip,adc-grps-route",
2407 rk3308->i2s_sdis, num);
2408 if (ret < 0) {
2409 dev_err(rk3308->plat_dev,
2410 "Failed to read 'rockchip,adc-grps-route': %d\n",
2411 ret);
2412 return ret;
2413 }
2414
2415 ret = rk3308_codec_check_i2s_sdis(rk3308, num);
2416 if (ret < 0) {
2417 dev_err(rk3308->plat_dev,
2418 "Failed to check i2s_sdis: %d\n", ret);
2419 return ret;
2420 }
2421
2422 rk3308->to_i2s_grps = num;
2423
2424 rk3308_codec_adc_grps_route_config(rk3308);
2425
2426 return 0;
2427 }
2428
check_micbias(int micbias)2429 static int check_micbias(int micbias)
2430 {
2431 switch (micbias) {
2432 case RK3308_ADC_MICBIAS_VOLT_0_85:
2433 case RK3308_ADC_MICBIAS_VOLT_0_8:
2434 case RK3308_ADC_MICBIAS_VOLT_0_75:
2435 case RK3308_ADC_MICBIAS_VOLT_0_7:
2436 case RK3308_ADC_MICBIAS_VOLT_0_65:
2437 case RK3308_ADC_MICBIAS_VOLT_0_6:
2438 case RK3308_ADC_MICBIAS_VOLT_0_55:
2439 case RK3308_ADC_MICBIAS_VOLT_0_5:
2440 return 0;
2441 }
2442
2443 return -EINVAL;
2444 }
2445
handle_loopback(struct rk3308_codec_priv * rk3308)2446 static bool handle_loopback(struct rk3308_codec_priv *rk3308)
2447 {
2448 /* The version B doesn't need to handle loopback. */
2449 if (rk3308->codec_ver >= ACODEC_VERSION_B)
2450 return false;
2451
2452 switch (rk3308->loopback_grp) {
2453 case 0:
2454 case 1:
2455 case 2:
2456 case 3:
2457 return true;
2458 }
2459
2460 return false;
2461 }
2462
has_en_always_grps(struct rk3308_codec_priv * rk3308)2463 static bool has_en_always_grps(struct rk3308_codec_priv *rk3308)
2464 {
2465 int idx;
2466
2467 if (rk3308->en_always_grps_num) {
2468 for (idx = 0; idx < ADC_LR_GROUP_MAX; idx++) {
2469 if (rk3308->en_always_grps[idx] >= 0 &&
2470 rk3308->en_always_grps[idx] <= ADC_LR_GROUP_MAX - 1)
2471 return true;
2472 }
2473 }
2474
2475 return false;
2476 }
2477
rk3308_codec_micbias_enable(struct rk3308_codec_priv * rk3308,int micbias)2478 static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308,
2479 int micbias)
2480 {
2481 int ret;
2482
2483 if (rk3308->ext_micbias != EXT_MICBIAS_NONE)
2484 return 0;
2485
2486 /* 0. Power up the ACODEC and keep the AVDDH stable */
2487
2488 /* Step 1. Configure ACODEC_ADC_ANA_CON7[2:0] to the certain value */
2489 ret = check_micbias(micbias);
2490 if (ret < 0) {
2491 dev_err(rk3308->plat_dev, "This is an invalid micbias: %d\n",
2492 micbias);
2493 return ret;
2494 }
2495
2496 /*
2497 * Note: Only the reg (ADC_ANA_CON7+0x0)[2:0] represent the level range
2498 * control signal of MICBIAS voltage
2499 */
2500 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0),
2501 RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK,
2502 micbias);
2503
2504 /* Step 2. Wait until the VCMH keep stable */
2505 msleep(20); /* estimated value */
2506
2507 /*
2508 * Step 3. Configure ACODEC_ADC_ANA_CON8[4] to 0x1
2509 *
2510 * Note: Only the reg (ADC_ANA_CON8+0x0)[4] represent the enable
2511 * signal of current source for MICBIAS
2512 */
2513 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(0),
2514 RK3308_ADC_MICBIAS_CURRENT_MSK,
2515 RK3308_ADC_MICBIAS_CURRENT_EN);
2516
2517 /*
2518 * Step 4. Configure the (ADC_ANA_CON7+0x40)[3] or
2519 * (ADC_ANA_CON7+0x80)[3] to 0x1.
2520 *
2521 * (ADC_ANA_CON7+0x40)[3] used to control the MICBIAS1, and
2522 * (ADC_ANA_CON7+0x80)[3] used to control the MICBIAS2
2523 */
2524 if (rk3308->micbias1)
2525 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(1),
2526 RK3308_ADC_MIC_BIAS_BUF_EN,
2527 RK3308_ADC_MIC_BIAS_BUF_EN);
2528
2529 if (rk3308->micbias2)
2530 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(2),
2531 RK3308_ADC_MIC_BIAS_BUF_EN,
2532 RK3308_ADC_MIC_BIAS_BUF_EN);
2533
2534 /* waiting micbias stabled*/
2535 mdelay(50);
2536
2537 rk3308->enable_micbias = true;
2538
2539 return 0;
2540 }
2541
rk3308_codec_micbias_disable(struct rk3308_codec_priv * rk3308)2542 static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308)
2543 {
2544 if (rk3308->ext_micbias != EXT_MICBIAS_NONE)
2545 return 0;
2546
2547 /* Step 0. Enable the MICBIAS and keep the Audio Codec stable */
2548 /* Do nothing */
2549
2550 /*
2551 * Step 1. Configure the (ADC_ANA_CON7+0x40)[3] or
2552 * (ADC_ANA_CON7+0x80)[3] to 0x0
2553 */
2554 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(1),
2555 RK3308_ADC_MIC_BIAS_BUF_EN,
2556 RK3308_ADC_MIC_BIAS_BUF_DIS);
2557 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(2),
2558 RK3308_ADC_MIC_BIAS_BUF_EN,
2559 RK3308_ADC_MIC_BIAS_BUF_DIS);
2560
2561 /*
2562 * Step 2. Configure ACODEC_ADC_ANA_CON8[4] to 0x0
2563 *
2564 * Note: Only the reg (ADC_ANA_CON8+0x0)[4] represent the enable
2565 * signal of current source for MICBIAS
2566 */
2567 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(0),
2568 RK3308_ADC_MICBIAS_CURRENT_MSK,
2569 RK3308_ADC_MICBIAS_CURRENT_DIS);
2570
2571 rk3308->enable_micbias = false;
2572
2573 return 0;
2574 }
2575
rk3308_codec_adc_reinit_mics(struct rk3308_codec_priv * rk3308,int type)2576 static int rk3308_codec_adc_reinit_mics(struct rk3308_codec_priv *rk3308,
2577 int type)
2578 {
2579 int idx, grp;
2580
2581 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2582 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2583 continue;
2584
2585 /* vendor step 1 */
2586 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
2587 RK3308_ADC_CH1_ADC_WORK |
2588 RK3308_ADC_CH2_ADC_WORK,
2589 RK3308_ADC_CH1_ADC_INIT |
2590 RK3308_ADC_CH2_ADC_INIT);
2591 }
2592
2593 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2594 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2595 continue;
2596
2597 /* vendor step 2 */
2598 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
2599 RK3308_ADC_CH1_ALC_WORK |
2600 RK3308_ADC_CH2_ALC_WORK,
2601 RK3308_ADC_CH1_ALC_INIT |
2602 RK3308_ADC_CH2_ALC_INIT);
2603 }
2604
2605 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2606 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2607 continue;
2608
2609 /* vendor step 3 */
2610 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
2611 RK3308_ADC_CH1_MIC_WORK |
2612 RK3308_ADC_CH2_MIC_WORK,
2613 RK3308_ADC_CH1_MIC_INIT |
2614 RK3308_ADC_CH2_MIC_INIT);
2615 }
2616
2617 usleep_range(200, 250); /* estimated value */
2618
2619 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2620 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2621 continue;
2622
2623 /* vendor step 1 */
2624 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
2625 RK3308_ADC_CH1_ADC_WORK |
2626 RK3308_ADC_CH2_ADC_WORK,
2627 RK3308_ADC_CH1_ADC_WORK |
2628 RK3308_ADC_CH2_ADC_WORK);
2629 }
2630
2631 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2632 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2633 continue;
2634
2635 /* vendor step 2 */
2636 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
2637 RK3308_ADC_CH1_ALC_WORK |
2638 RK3308_ADC_CH2_ALC_WORK,
2639 RK3308_ADC_CH1_ALC_WORK |
2640 RK3308_ADC_CH2_ALC_WORK);
2641 }
2642
2643 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2644 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2645 continue;
2646
2647 /* vendor step 3 */
2648 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
2649 RK3308_ADC_CH1_MIC_WORK |
2650 RK3308_ADC_CH2_MIC_WORK,
2651 RK3308_ADC_CH1_MIC_WORK |
2652 RK3308_ADC_CH2_MIC_WORK);
2653 }
2654
2655 return 0;
2656 }
2657
rk3308_codec_adc_ana_enable(struct rk3308_codec_priv * rk3308,int type)2658 static int rk3308_codec_adc_ana_enable(struct rk3308_codec_priv *rk3308,
2659 int type)
2660 {
2661 unsigned int agc_func_en;
2662 int idx, grp;
2663
2664 /*
2665 * 1. Set the ACODEC_ADC_ANA_CON7[7:6] and ACODEC_ADC_ANA_CON7[5:4],
2666 * to select the line-in or microphone as input of ADC
2667 *
2668 * Note1. Please ignore the step1 for enabling ADC3, ADC4, ADC5,
2669 * ADC6, ADC7, and ADC8
2670 */
2671 if (rk3308->adc_grp0_using_linein) {
2672 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0),
2673 RK3308_ADC_CH1_IN_SEL_MSK |
2674 RK3308_ADC_CH2_IN_SEL_MSK,
2675 RK3308_ADC_CH1_IN_LINEIN |
2676 RK3308_ADC_CH2_IN_LINEIN);
2677
2678 /* Keep other ADCs as MIC-IN */
2679 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2680 /* The groups without line-in are >= 1 */
2681 if (grp < 1 || grp > ADC_LR_GROUP_MAX - 1)
2682 continue;
2683
2684 regmap_update_bits(rk3308->regmap,
2685 RK3308_ADC_ANA_CON07(grp),
2686 RK3308_ADC_CH1_IN_SEL_MSK |
2687 RK3308_ADC_CH2_IN_SEL_MSK,
2688 RK3308_ADC_CH1_IN_MIC |
2689 RK3308_ADC_CH2_IN_MIC);
2690 }
2691 } else {
2692 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2693 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2694 continue;
2695
2696 regmap_update_bits(rk3308->regmap,
2697 RK3308_ADC_ANA_CON07(grp),
2698 RK3308_ADC_CH1_IN_SEL_MSK |
2699 RK3308_ADC_CH2_IN_SEL_MSK,
2700 RK3308_ADC_CH1_IN_MIC |
2701 RK3308_ADC_CH2_IN_MIC);
2702 }
2703 }
2704
2705 /*
2706 * 2. Set ACODEC_ADC_ANA_CON0[7] and [3] to 0x1, to end the mute station
2707 * of ADC, to enable the MIC module, to enable the reference voltage
2708 * buffer, and to end the initialization of MIC
2709 */
2710 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2711 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2712 continue;
2713
2714 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
2715 RK3308_ADC_CH1_MIC_UNMUTE |
2716 RK3308_ADC_CH2_MIC_UNMUTE,
2717 RK3308_ADC_CH1_MIC_UNMUTE |
2718 RK3308_ADC_CH2_MIC_UNMUTE);
2719 }
2720
2721 /*
2722 * 3. Set ACODEC_ADC_ANA_CON6[0] to 0x1, to enable the current source
2723 * of audio
2724 */
2725 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2726 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2727 continue;
2728
2729 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(grp),
2730 RK3308_ADC_CURRENT_MSK,
2731 RK3308_ADC_CURRENT_EN);
2732 }
2733
2734 /*
2735 * This is mainly used for BIST mode that wait ADCs are stable.
2736 *
2737 * By tested results, the type delay is >40us, but we need to leave
2738 * enough delay margin.
2739 */
2740 usleep_range(400, 500);
2741
2742 /* vendor step 4*/
2743 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2744 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2745 continue;
2746
2747 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
2748 RK3308_ADC_CH1_BUF_REF_EN |
2749 RK3308_ADC_CH2_BUF_REF_EN,
2750 RK3308_ADC_CH1_BUF_REF_EN |
2751 RK3308_ADC_CH2_BUF_REF_EN);
2752 }
2753
2754 /* vendor step 5 */
2755 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2756 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2757 continue;
2758
2759 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
2760 RK3308_ADC_CH1_MIC_EN |
2761 RK3308_ADC_CH2_MIC_EN,
2762 RK3308_ADC_CH1_MIC_EN |
2763 RK3308_ADC_CH2_MIC_EN);
2764 }
2765
2766 /* vendor step 6 */
2767 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2768 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2769 continue;
2770
2771 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
2772 RK3308_ADC_CH1_ALC_EN |
2773 RK3308_ADC_CH2_ALC_EN,
2774 RK3308_ADC_CH1_ALC_EN |
2775 RK3308_ADC_CH2_ALC_EN);
2776 }
2777
2778 /* vendor step 7 */
2779 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2780 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2781 continue;
2782
2783 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
2784 RK3308_ADC_CH1_CLK_EN |
2785 RK3308_ADC_CH2_CLK_EN,
2786 RK3308_ADC_CH1_CLK_EN |
2787 RK3308_ADC_CH2_CLK_EN);
2788 }
2789
2790 /* vendor step 8 */
2791 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2792 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2793 continue;
2794
2795 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
2796 RK3308_ADC_CH1_ADC_EN |
2797 RK3308_ADC_CH2_ADC_EN,
2798 RK3308_ADC_CH1_ADC_EN |
2799 RK3308_ADC_CH2_ADC_EN);
2800 }
2801
2802 /* vendor step 9 */
2803 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2804 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2805 continue;
2806
2807 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
2808 RK3308_ADC_CH1_ADC_WORK |
2809 RK3308_ADC_CH2_ADC_WORK,
2810 RK3308_ADC_CH1_ADC_WORK |
2811 RK3308_ADC_CH2_ADC_WORK);
2812 }
2813
2814 /* vendor step 10 */
2815 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2816 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2817 continue;
2818
2819 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
2820 RK3308_ADC_CH1_ALC_WORK |
2821 RK3308_ADC_CH2_ALC_WORK,
2822 RK3308_ADC_CH1_ALC_WORK |
2823 RK3308_ADC_CH2_ALC_WORK);
2824 }
2825
2826 /* vendor step 11 */
2827 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2828 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2829 continue;
2830
2831 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
2832 RK3308_ADC_CH1_MIC_WORK |
2833 RK3308_ADC_CH2_MIC_WORK,
2834 RK3308_ADC_CH1_MIC_WORK |
2835 RK3308_ADC_CH2_MIC_WORK);
2836 }
2837
2838 /* vendor step 12 */
2839
2840 /* vendor step 13 */
2841
2842 /* vendor step 14 */
2843 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2844 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2845 continue;
2846
2847 regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp),
2848 &agc_func_en);
2849 if (rk3308->adc_zerocross ||
2850 agc_func_en & RK3308_AGC_FUNC_SEL_EN) {
2851 regmap_update_bits(rk3308->regmap,
2852 RK3308_ADC_ANA_CON02(grp),
2853 RK3308_ADC_CH1_ZEROCROSS_DET_EN,
2854 RK3308_ADC_CH1_ZEROCROSS_DET_EN);
2855 }
2856 regmap_read(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp),
2857 &agc_func_en);
2858 if (rk3308->adc_zerocross ||
2859 agc_func_en & RK3308_AGC_FUNC_SEL_EN) {
2860 regmap_update_bits(rk3308->regmap,
2861 RK3308_ADC_ANA_CON02(grp),
2862 RK3308_ADC_CH2_ZEROCROSS_DET_EN,
2863 RK3308_ADC_CH2_ZEROCROSS_DET_EN);
2864 }
2865 }
2866
2867 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2868 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2869 continue;
2870
2871 rk3308->adc_grps_endisable[grp] = true;
2872 }
2873
2874 return 0;
2875 }
2876
rk3308_codec_adc_ana_disable(struct rk3308_codec_priv * rk3308,int type)2877 static int rk3308_codec_adc_ana_disable(struct rk3308_codec_priv *rk3308,
2878 int type)
2879 {
2880 int idx, grp;
2881
2882 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2883 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2884 continue;
2885
2886 /* vendor step 1 */
2887 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
2888 RK3308_ADC_CH1_ZEROCROSS_DET_EN |
2889 RK3308_ADC_CH2_ZEROCROSS_DET_EN,
2890 RK3308_ADC_CH1_ZEROCROSS_DET_DIS |
2891 RK3308_ADC_CH2_ZEROCROSS_DET_DIS);
2892 }
2893
2894 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2895 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2896 continue;
2897
2898 /* vendor step 2 */
2899 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
2900 RK3308_ADC_CH1_ADC_EN |
2901 RK3308_ADC_CH2_ADC_EN,
2902 RK3308_ADC_CH1_ADC_DIS |
2903 RK3308_ADC_CH2_ADC_DIS);
2904 }
2905
2906 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2907 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2908 continue;
2909
2910 /* vendor step 3 */
2911 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
2912 RK3308_ADC_CH1_CLK_EN |
2913 RK3308_ADC_CH2_CLK_EN,
2914 RK3308_ADC_CH1_CLK_DIS |
2915 RK3308_ADC_CH2_CLK_DIS);
2916 }
2917
2918 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2919 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2920 continue;
2921
2922 /* vendor step 4 */
2923 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
2924 RK3308_ADC_CH1_ALC_EN |
2925 RK3308_ADC_CH2_ALC_EN,
2926 RK3308_ADC_CH1_ALC_DIS |
2927 RK3308_ADC_CH2_ALC_DIS);
2928 }
2929
2930 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2931 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2932 continue;
2933
2934 /* vendor step 5 */
2935 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
2936 RK3308_ADC_CH1_MIC_EN |
2937 RK3308_ADC_CH2_MIC_EN,
2938 RK3308_ADC_CH1_MIC_DIS |
2939 RK3308_ADC_CH2_MIC_DIS);
2940 }
2941
2942 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2943 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2944 continue;
2945
2946 /* vendor step 6 */
2947 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
2948 RK3308_ADC_CH1_BUF_REF_EN |
2949 RK3308_ADC_CH2_BUF_REF_EN,
2950 RK3308_ADC_CH1_BUF_REF_DIS |
2951 RK3308_ADC_CH2_BUF_REF_DIS);
2952 }
2953
2954 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2955 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2956 continue;
2957
2958 /* vendor step 7 */
2959 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(grp),
2960 RK3308_ADC_CURRENT_MSK,
2961 RK3308_ADC_CURRENT_DIS);
2962 }
2963
2964 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2965 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2966 continue;
2967
2968 /* vendor step 8 */
2969 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp),
2970 RK3308_ADC_CH1_ADC_WORK |
2971 RK3308_ADC_CH2_ADC_WORK,
2972 RK3308_ADC_CH1_ADC_INIT |
2973 RK3308_ADC_CH2_ADC_INIT);
2974 }
2975
2976 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2977 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2978 continue;
2979
2980 /* vendor step 9 */
2981 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp),
2982 RK3308_ADC_CH1_ALC_WORK |
2983 RK3308_ADC_CH2_ALC_WORK,
2984 RK3308_ADC_CH1_ALC_INIT |
2985 RK3308_ADC_CH2_ALC_INIT);
2986 }
2987
2988 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
2989 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
2990 continue;
2991
2992 /* vendor step 10 */
2993 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp),
2994 RK3308_ADC_CH1_MIC_WORK |
2995 RK3308_ADC_CH2_MIC_WORK,
2996 RK3308_ADC_CH1_MIC_INIT |
2997 RK3308_ADC_CH2_MIC_INIT);
2998 }
2999
3000 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
3001 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
3002 continue;
3003
3004 rk3308->adc_grps_endisable[grp] = false;
3005 }
3006
3007 return 0;
3008 }
3009
rk3308_codec_open_capture(struct rk3308_codec_priv * rk3308)3010 static int rk3308_codec_open_capture(struct rk3308_codec_priv *rk3308)
3011 {
3012 int idx, grp = 0;
3013 int type = ADC_TYPE_NORMAL;
3014
3015 rk3308_codec_adc_ana_enable(rk3308, type);
3016 rk3308_codec_adc_reinit_mics(rk3308, type);
3017
3018 if (rk3308->adc_grp0_using_linein) {
3019 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(0),
3020 RK3308_ADC_L_CH_BIST_MSK,
3021 RK3308_ADC_L_CH_NORMAL_RIGHT);
3022 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(0),
3023 RK3308_ADC_R_CH_BIST_MSK,
3024 RK3308_ADC_R_CH_NORMAL_LEFT);
3025 } else {
3026 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
3027 if (handle_loopback(rk3308) &&
3028 idx == rk3308->loopback_grp &&
3029 grp == ADC_GRP_SKIP_MAGIC) {
3030 /*
3031 * Switch to dummy BIST mode (BIST keep reset
3032 * now) to keep the zero input data in I2S bus.
3033 *
3034 * It may cause the glitch if we hold the ADC
3035 * digtital i2s module in codec.
3036 *
3037 * Then, the grp which is set from loopback_grp.
3038 */
3039 regmap_update_bits(rk3308->regmap,
3040 RK3308_ADC_DIG_CON03(rk3308->loopback_grp),
3041 RK3308_ADC_L_CH_BIST_MSK,
3042 RK3308_ADC_L_CH_BIST_SINE);
3043 regmap_update_bits(rk3308->regmap,
3044 RK3308_ADC_DIG_CON03(rk3308->loopback_grp),
3045 RK3308_ADC_R_CH_BIST_MSK,
3046 RK3308_ADC_R_CH_BIST_SINE);
3047 } else {
3048 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
3049 continue;
3050
3051 regmap_update_bits(rk3308->regmap,
3052 RK3308_ADC_DIG_CON03(grp),
3053 RK3308_ADC_L_CH_BIST_MSK,
3054 RK3308_ADC_L_CH_NORMAL_LEFT);
3055 regmap_update_bits(rk3308->regmap,
3056 RK3308_ADC_DIG_CON03(grp),
3057 RK3308_ADC_R_CH_BIST_MSK,
3058 RK3308_ADC_R_CH_NORMAL_RIGHT);
3059 }
3060 }
3061 }
3062
3063 return 0;
3064 }
3065
rk3308_codec_adc_mclk_disable(struct rk3308_codec_priv * rk3308)3066 static void rk3308_codec_adc_mclk_disable(struct rk3308_codec_priv *rk3308)
3067 {
3068 regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
3069 RK3308_ADC_MCLK_MSK,
3070 RK3308_ADC_MCLK_DIS);
3071 }
3072
rk3308_codec_adc_mclk_enable(struct rk3308_codec_priv * rk3308)3073 static void rk3308_codec_adc_mclk_enable(struct rk3308_codec_priv *rk3308)
3074 {
3075 regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
3076 RK3308_ADC_MCLK_MSK,
3077 RK3308_ADC_MCLK_EN);
3078 udelay(20);
3079 }
3080
rk3308_codec_dac_mclk_disable(struct rk3308_codec_priv * rk3308)3081 static void rk3308_codec_dac_mclk_disable(struct rk3308_codec_priv *rk3308)
3082 {
3083 if (!rk3308->no_hp_det && rk3308->codec_ver == ACODEC_VERSION_C)
3084 return;
3085
3086 regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
3087 RK3308_DAC_MCLK_MSK,
3088 RK3308_DAC_MCLK_DIS);
3089 }
3090
rk3308_codec_dac_mclk_enable(struct rk3308_codec_priv * rk3308)3091 static void rk3308_codec_dac_mclk_enable(struct rk3308_codec_priv *rk3308)
3092 {
3093 regmap_update_bits(rk3308->regmap, RK3308_GLB_CON,
3094 RK3308_DAC_MCLK_MSK,
3095 RK3308_DAC_MCLK_EN);
3096 udelay(20);
3097 }
3098
rk3308_codec_open_dbg_capture(struct rk3308_codec_priv * rk3308)3099 static int rk3308_codec_open_dbg_capture(struct rk3308_codec_priv *rk3308)
3100 {
3101 rk3308_codec_adc_ana_enable(rk3308, ADC_TYPE_DBG);
3102
3103 return 0;
3104 }
3105
rk3308_codec_close_dbg_capture(struct rk3308_codec_priv * rk3308)3106 static int rk3308_codec_close_dbg_capture(struct rk3308_codec_priv *rk3308)
3107 {
3108 rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_DBG);
3109
3110 return 0;
3111 }
3112
rk3308_codec_close_all_capture(struct rk3308_codec_priv * rk3308)3113 static int rk3308_codec_close_all_capture(struct rk3308_codec_priv *rk3308)
3114 {
3115 rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_ALL);
3116
3117 return 0;
3118 }
3119
rk3308_codec_close_capture(struct rk3308_codec_priv * rk3308)3120 static int rk3308_codec_close_capture(struct rk3308_codec_priv *rk3308)
3121 {
3122 rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_NORMAL);
3123
3124 return 0;
3125 }
3126
rk3308_codec_open_playback(struct rk3308_codec_priv * rk3308)3127 static int rk3308_codec_open_playback(struct rk3308_codec_priv *rk3308)
3128 {
3129 rk3308_codec_dac_enable(rk3308);
3130
3131 return 0;
3132 }
3133
rk3308_codec_close_playback(struct rk3308_codec_priv * rk3308)3134 static int rk3308_codec_close_playback(struct rk3308_codec_priv *rk3308)
3135 {
3136 rk3308_codec_dac_disable(rk3308);
3137
3138 return 0;
3139 }
3140
rk3308_codec_llp_down(struct rk3308_codec_priv * rk3308)3141 static int rk3308_codec_llp_down(struct rk3308_codec_priv *rk3308)
3142 {
3143 rk3308_codec_adc_mclk_disable(rk3308);
3144 rk3308_codec_dac_mclk_disable(rk3308);
3145
3146 return 0;
3147 }
3148
rk3308_codec_llp_up(struct rk3308_codec_priv * rk3308)3149 static int rk3308_codec_llp_up(struct rk3308_codec_priv *rk3308)
3150 {
3151 rk3308_codec_adc_mclk_enable(rk3308);
3152 rk3308_codec_dac_mclk_enable(rk3308);
3153
3154 return 0;
3155 }
3156
rk3308_codec_dlp_down(struct rk3308_codec_priv * rk3308)3157 static int rk3308_codec_dlp_down(struct rk3308_codec_priv *rk3308)
3158 {
3159 rk3308_codec_micbias_disable(rk3308);
3160 rk3308_codec_power_off(rk3308);
3161
3162 return 0;
3163 }
3164
rk3308_codec_dlp_up(struct rk3308_codec_priv * rk3308)3165 static int rk3308_codec_dlp_up(struct rk3308_codec_priv *rk3308)
3166 {
3167 rk3308_codec_power_on(rk3308);
3168 rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt);
3169
3170 return 0;
3171 }
3172
3173 /* Just used for debug and trace power state */
rk3308_codec_set_pm_state(struct rk3308_codec_priv * rk3308,int pm_state)3174 static void rk3308_codec_set_pm_state(struct rk3308_codec_priv *rk3308,
3175 int pm_state)
3176 {
3177 int ret;
3178
3179 switch (pm_state) {
3180 case PM_LLP_DOWN:
3181 rk3308_codec_llp_down(rk3308);
3182 break;
3183 case PM_LLP_UP:
3184 rk3308_codec_llp_up(rk3308);
3185 break;
3186 case PM_DLP_DOWN:
3187 rk3308_codec_dlp_down(rk3308);
3188 break;
3189 case PM_DLP_UP:
3190 rk3308_codec_dlp_up(rk3308);
3191 break;
3192 case PM_DLP_DOWN2:
3193 clk_disable_unprepare(rk3308->mclk_rx);
3194 clk_disable_unprepare(rk3308->mclk_tx);
3195 clk_disable_unprepare(rk3308->pclk);
3196 break;
3197 case PM_DLP_UP2:
3198 ret = clk_prepare_enable(rk3308->pclk);
3199 if (ret < 0) {
3200 dev_err(rk3308->plat_dev,
3201 "Failed to enable acodec pclk: %d\n", ret);
3202 goto err;
3203 }
3204
3205 ret = clk_prepare_enable(rk3308->mclk_rx);
3206 if (ret < 0) {
3207 dev_err(rk3308->plat_dev,
3208 "Failed to enable i2s mclk_rx: %d\n", ret);
3209 goto err;
3210 }
3211
3212 ret = clk_prepare_enable(rk3308->mclk_tx);
3213 if (ret < 0) {
3214 dev_err(rk3308->plat_dev,
3215 "Failed to enable i2s mclk_tx: %d\n", ret);
3216 goto err;
3217 }
3218 break;
3219 default:
3220 dev_err(rk3308->plat_dev, "Invalid pm_state: %d\n", pm_state);
3221 goto err;
3222 }
3223
3224 rk3308->pm_state = pm_state;
3225
3226 err:
3227 return;
3228 }
3229
rk3308_codec_update_adcs_status(struct rk3308_codec_priv * rk3308,int state)3230 static void rk3308_codec_update_adcs_status(struct rk3308_codec_priv *rk3308,
3231 int state)
3232 {
3233 int idx, grp;
3234
3235 /* Update skip_grps flags if the ADCs need to be enabled always. */
3236 if (state == PATH_BUSY) {
3237 for (idx = 0; idx < rk3308->used_adc_grps; idx++) {
3238 u32 mapped_grp = to_mapped_grp(rk3308, idx);
3239
3240 for (grp = 0; grp < rk3308->en_always_grps_num; grp++) {
3241 u32 en_always_grp = rk3308->en_always_grps[grp];
3242
3243 if (mapped_grp == en_always_grp)
3244 rk3308->skip_grps[en_always_grp] = 1;
3245 }
3246 }
3247 }
3248 }
3249
rk3308_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)3250 static int rk3308_hw_params(struct snd_pcm_substream *substream,
3251 struct snd_pcm_hw_params *params,
3252 struct snd_soc_dai *dai)
3253 {
3254 struct snd_soc_component *component = dai->component;
3255 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
3256 struct snd_pcm_str *playback_str =
3257 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
3258 int type = ADC_TYPE_LOOPBACK;
3259 int idx, grp;
3260 int ret;
3261
3262 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3263 /* DAC only supports 2 channels */
3264 rk3308_codec_dac_mclk_enable(rk3308);
3265 rk3308_codec_open_playback(rk3308);
3266 rk3308_codec_dac_dig_config(rk3308, params);
3267 rk3308_codec_set_dac_path_state(rk3308, PATH_BUSY);
3268 } else {
3269 if (rk3308->micbias_num &&
3270 !rk3308->enable_micbias)
3271 rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt);
3272
3273 rk3308_codec_adc_mclk_enable(rk3308);
3274 ret = rk3308_codec_update_adc_grps(rk3308, params);
3275 if (ret < 0)
3276 return ret;
3277
3278 if (handle_loopback(rk3308)) {
3279 if (rk3308->micbias_num &&
3280 (params_channels(params) == 2) &&
3281 to_mapped_grp(rk3308, 0) == rk3308->loopback_grp)
3282 rk3308_codec_micbias_disable(rk3308);
3283
3284 /* Check the DACs are opened */
3285 if (playback_str->substream_opened) {
3286 rk3308->loopback_dacs_enabled = true;
3287 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
3288 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
3289 continue;
3290
3291 regmap_update_bits(rk3308->regmap,
3292 RK3308_ADC_DIG_CON03(grp),
3293 RK3308_ADC_L_CH_BIST_MSK,
3294 RK3308_ADC_L_CH_NORMAL_LEFT);
3295 regmap_update_bits(rk3308->regmap,
3296 RK3308_ADC_DIG_CON03(grp),
3297 RK3308_ADC_R_CH_BIST_MSK,
3298 RK3308_ADC_R_CH_NORMAL_RIGHT);
3299 }
3300 } else {
3301 rk3308->loopback_dacs_enabled = false;
3302 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
3303 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
3304 continue;
3305
3306 regmap_update_bits(rk3308->regmap,
3307 RK3308_ADC_DIG_CON03(grp),
3308 RK3308_ADC_L_CH_BIST_MSK,
3309 RK3308_ADC_L_CH_BIST_SINE);
3310 regmap_update_bits(rk3308->regmap,
3311 RK3308_ADC_DIG_CON03(grp),
3312 RK3308_ADC_R_CH_BIST_MSK,
3313 RK3308_ADC_R_CH_BIST_SINE);
3314 }
3315 }
3316 }
3317
3318 rk3308_codec_open_capture(rk3308);
3319 rk3308_codec_adc_dig_config(rk3308, params);
3320 rk3308_codec_update_adcs_status(rk3308, PATH_BUSY);
3321 }
3322
3323 return 0;
3324 }
3325
rk3308_pcm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)3326 static int rk3308_pcm_trigger(struct snd_pcm_substream *substream,
3327 int cmd, struct snd_soc_dai *dai)
3328 {
3329 struct snd_soc_component *component = dai->component;
3330 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
3331 int type = ADC_TYPE_LOOPBACK;
3332 int idx, grp;
3333
3334 if (handle_loopback(rk3308) &&
3335 rk3308->dac_output == DAC_LINEOUT &&
3336 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3337 if (cmd == SNDRV_PCM_TRIGGER_START) {
3338 struct snd_pcm_str *capture_str =
3339 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
3340
3341 if (capture_str->substream_opened)
3342 queue_delayed_work(system_power_efficient_wq,
3343 &rk3308->loopback_work,
3344 msecs_to_jiffies(rk3308->delay_loopback_handle_ms));
3345 } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
3346 /*
3347 * Switch to dummy bist mode to kick the glitch during disable
3348 * ADCs and keep zero input data
3349 */
3350 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
3351 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
3352 continue;
3353
3354 regmap_update_bits(rk3308->regmap,
3355 RK3308_ADC_DIG_CON03(grp),
3356 RK3308_ADC_L_CH_BIST_MSK,
3357 RK3308_ADC_L_CH_BIST_SINE);
3358 regmap_update_bits(rk3308->regmap,
3359 RK3308_ADC_DIG_CON03(grp),
3360 RK3308_ADC_R_CH_BIST_MSK,
3361 RK3308_ADC_R_CH_BIST_SINE);
3362 }
3363 rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_LOOPBACK);
3364 }
3365 }
3366
3367 return 0;
3368 }
3369
rk3308_pcm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)3370 static void rk3308_pcm_shutdown(struct snd_pcm_substream *substream,
3371 struct snd_soc_dai *dai)
3372 {
3373 struct snd_soc_component *component = dai->component;
3374 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
3375
3376 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3377 rk3308_codec_close_playback(rk3308);
3378 rk3308_codec_dac_mclk_disable(rk3308);
3379 regcache_cache_only(rk3308->regmap, false);
3380 regcache_sync(rk3308->regmap);
3381 rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE);
3382 } else {
3383 rk3308_codec_close_capture(rk3308);
3384 if (!has_en_always_grps(rk3308)) {
3385 rk3308_codec_adc_mclk_disable(rk3308);
3386 rk3308_codec_update_adcs_status(rk3308, PATH_IDLE);
3387 if (rk3308->micbias_num &&
3388 rk3308->enable_micbias)
3389 rk3308_codec_micbias_disable(rk3308);
3390 }
3391
3392 regcache_cache_only(rk3308->regmap, false);
3393 regcache_sync(rk3308->regmap);
3394 }
3395 }
3396
3397 static struct snd_soc_dai_ops rk3308_dai_ops = {
3398 .hw_params = rk3308_hw_params,
3399 .set_fmt = rk3308_set_dai_fmt,
3400 .mute_stream = rk3308_mute_stream,
3401 .trigger = rk3308_pcm_trigger,
3402 .shutdown = rk3308_pcm_shutdown,
3403 };
3404
3405 static struct snd_soc_dai_driver rk3308_dai[] = {
3406 {
3407 .name = "rk3308-hifi",
3408 .id = RK3308_HIFI,
3409 .playback = {
3410 .stream_name = "HiFi Playback",
3411 .channels_min = 2,
3412 .channels_max = 2,
3413 .rates = SNDRV_PCM_RATE_8000_192000,
3414 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
3415 SNDRV_PCM_FMTBIT_S20_3LE |
3416 SNDRV_PCM_FMTBIT_S24_LE |
3417 SNDRV_PCM_FMTBIT_S32_LE),
3418 },
3419 .capture = {
3420 .stream_name = "HiFi Capture",
3421 .channels_min = 1,
3422 .channels_max = 8,
3423 .rates = SNDRV_PCM_RATE_8000_192000,
3424 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
3425 SNDRV_PCM_FMTBIT_S20_3LE |
3426 SNDRV_PCM_FMTBIT_S24_LE |
3427 SNDRV_PCM_FMTBIT_S32_LE),
3428 },
3429 .ops = &rk3308_dai_ops,
3430 },
3431 };
3432
rk3308_suspend(struct snd_soc_component * component)3433 static int rk3308_suspend(struct snd_soc_component *component)
3434 {
3435 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
3436
3437 if (rk3308->no_deep_low_power)
3438 goto out;
3439
3440 rk3308_codec_dlp_down(rk3308);
3441 clk_disable_unprepare(rk3308->mclk_rx);
3442 clk_disable_unprepare(rk3308->mclk_tx);
3443 clk_disable_unprepare(rk3308->pclk);
3444
3445 out:
3446 rk3308_set_bias_level(component, SND_SOC_BIAS_OFF);
3447 return 0;
3448 }
3449
rk3308_resume(struct snd_soc_component * component)3450 static int rk3308_resume(struct snd_soc_component *component)
3451 {
3452 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
3453 int ret = 0;
3454
3455 if (rk3308->no_deep_low_power)
3456 goto out;
3457
3458 ret = clk_prepare_enable(rk3308->pclk);
3459 if (ret < 0) {
3460 dev_err(rk3308->plat_dev,
3461 "Failed to enable acodec pclk: %d\n", ret);
3462 goto out;
3463 }
3464
3465 ret = clk_prepare_enable(rk3308->mclk_rx);
3466 if (ret < 0) {
3467 dev_err(rk3308->plat_dev,
3468 "Failed to enable i2s mclk_rx: %d\n", ret);
3469 goto out;
3470 }
3471
3472 ret = clk_prepare_enable(rk3308->mclk_tx);
3473 if (ret < 0) {
3474 dev_err(rk3308->plat_dev,
3475 "Failed to enable i2s mclk_tx: %d\n", ret);
3476 goto out;
3477 }
3478
3479 rk3308_codec_dlp_up(rk3308);
3480 out:
3481 rk3308_set_bias_level(component, SND_SOC_BIAS_STANDBY);
3482 return ret;
3483 }
3484
rk3308_codec_default_gains(struct rk3308_codec_priv * rk3308)3485 static int rk3308_codec_default_gains(struct rk3308_codec_priv *rk3308)
3486 {
3487 int grp;
3488
3489 /* Prepare ADC gains */
3490 /* vendor step 12, set MIC PGA default gains */
3491 for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) {
3492 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON01(grp),
3493 RK3308_ADC_CH1_MIC_GAIN_MSK |
3494 RK3308_ADC_CH2_MIC_GAIN_MSK,
3495 RK3308_ADC_CH1_MIC_GAIN_0DB |
3496 RK3308_ADC_CH2_MIC_GAIN_0DB);
3497 }
3498
3499 /* vendor step 13, set ALC default gains */
3500 for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) {
3501 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON03(grp),
3502 RK3308_ADC_CH1_ALC_GAIN_MSK,
3503 RK3308_ADC_CH1_ALC_GAIN_0DB);
3504 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON04(grp),
3505 RK3308_ADC_CH2_ALC_GAIN_MSK,
3506 RK3308_ADC_CH2_ALC_GAIN_0DB);
3507 }
3508
3509 if (rk3308->codec_ver == ACODEC_VERSION_C) {
3510 /* recover ADC digtial volume to 0dB */
3511 for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) {
3512 /* DIG_VOL: -97dB ~ +32dB */
3513 regmap_write(rk3308->regmap, RK3308BS_ADC_DIG_CON05(grp),
3514 RK3308_ADC_DIG_VOL_CON_L(RK3308_ADC_DIG_VOL_0DB));
3515 regmap_write(rk3308->regmap, RK3308BS_ADC_DIG_CON06(grp),
3516 RK3308_ADC_DIG_VOL_CON_R(RK3308_ADC_DIG_VOL_0DB));
3517 }
3518 }
3519
3520 /* Prepare DAC gains */
3521 /* Step 15, set HPMIX default gains */
3522 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12,
3523 RK3308_DAC_L_HPMIX_GAIN_MSK |
3524 RK3308_DAC_R_HPMIX_GAIN_MSK,
3525 RK3308_DAC_L_HPMIX_GAIN_0DB |
3526 RK3308_DAC_R_HPMIX_GAIN_0DB);
3527
3528 /* Step 18, set HPOUT default gains */
3529 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05,
3530 RK3308_DAC_L_HPOUT_GAIN_MSK,
3531 RK3308_DAC_L_HPOUT_GAIN_0DB);
3532 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06,
3533 RK3308_DAC_R_HPOUT_GAIN_MSK,
3534 RK3308_DAC_R_HPOUT_GAIN_0DB);
3535
3536 /* Using the same gain to HPOUT LR channels */
3537 rk3308->hpout_l_dgain = RK3308_DAC_L_HPOUT_GAIN_0DB;
3538 rk3308->hpout_r_dgain = RK3308_DAC_R_HPOUT_GAIN_0DB;
3539
3540 /* Step 19, set LINEOUT default gains */
3541 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04,
3542 RK3308_DAC_L_LINEOUT_GAIN_MSK |
3543 RK3308_DAC_R_LINEOUT_GAIN_MSK,
3544 RK3308_DAC_L_LINEOUT_GAIN_0DB |
3545 RK3308_DAC_R_LINEOUT_GAIN_0DB);
3546
3547 if (rk3308->codec_ver == ACODEC_VERSION_C) {
3548 /* recover DAC digtial gain to 0dB */
3549 regmap_write(rk3308->regmap, RK3308BS_DAC_DIG_CON04,
3550 RK3308BS_DAC_DIG_GAIN(RK3308BS_DAC_DIG_0DB));
3551 }
3552
3553 return 0;
3554 }
3555
rk3308_codec_setup_en_always_adcs(struct rk3308_codec_priv * rk3308,struct device_node * np)3556 static int rk3308_codec_setup_en_always_adcs(struct rk3308_codec_priv *rk3308,
3557 struct device_node *np)
3558 {
3559 int num, ret;
3560
3561 num = of_count_phandle_with_args(np, "rockchip,en-always-grps", NULL);
3562 if (num < 0) {
3563 if (num == -ENOENT) {
3564 /*
3565 * If there is note use 'rockchip,en-always-grps'
3566 * property, return 0 is also right.
3567 */
3568 ret = 0;
3569 } else {
3570 dev_err(rk3308->plat_dev,
3571 "Failed to read 'rockchip,adc-grps-route' num: %d\n",
3572 num);
3573 ret = num;
3574 }
3575
3576 rk3308->en_always_grps_num = 0;
3577 return ret;
3578 }
3579
3580 rk3308->en_always_grps_num = num;
3581
3582 ret = of_property_read_u32_array(np, "rockchip,en-always-grps",
3583 rk3308->en_always_grps, num);
3584 if (ret < 0) {
3585 dev_err(rk3308->plat_dev,
3586 "Failed to read 'rockchip,en-always-grps': %d\n",
3587 ret);
3588 return ret;
3589 }
3590
3591 /* Clear all of skip_grps flags. */
3592 for (num = 0; num < ADC_LR_GROUP_MAX; num++)
3593 rk3308->skip_grps[num] = 0;
3594
3595 /* The loopback grp should not be enabled always. */
3596 for (num = 0; num < rk3308->en_always_grps_num; num++) {
3597 if (rk3308->en_always_grps[num] == rk3308->loopback_grp) {
3598 dev_err(rk3308->plat_dev,
3599 "loopback_grp: %d should not be enabled always!\n",
3600 rk3308->loopback_grp);
3601 ret = -EINVAL;
3602 return ret;
3603 }
3604 }
3605
3606 return 0;
3607 }
3608
rk3308_codec_dapm_mic_gains(struct rk3308_codec_priv * rk3308)3609 static int rk3308_codec_dapm_mic_gains(struct rk3308_codec_priv *rk3308)
3610 {
3611 int ret;
3612
3613 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
3614 ret = snd_soc_add_component_controls(rk3308->component,
3615 mic_gains_b,
3616 ARRAY_SIZE(mic_gains_b));
3617 if (ret) {
3618 dev_err(rk3308->plat_dev,
3619 "%s: add mic_gains_b failed: %d\n",
3620 __func__, ret);
3621 return ret;
3622 }
3623 } else {
3624 ret = snd_soc_add_component_controls(rk3308->component,
3625 mic_gains_a,
3626 ARRAY_SIZE(mic_gains_a));
3627 if (ret) {
3628 dev_err(rk3308->plat_dev,
3629 "%s: add mic_gains_a failed: %d\n",
3630 __func__, ret);
3631 return ret;
3632 }
3633 }
3634
3635 return 0;
3636 }
3637
rk3308_codec_check_micbias(struct rk3308_codec_priv * rk3308,struct device_node * np)3638 static int rk3308_codec_check_micbias(struct rk3308_codec_priv *rk3308,
3639 struct device_node *np)
3640 {
3641 struct device *dev = (struct device *)rk3308->plat_dev;
3642 int num = 0, ret;
3643
3644 /* Check internal micbias */
3645 rk3308->micbias1 =
3646 of_property_read_bool(np, "rockchip,micbias1");
3647 if (rk3308->micbias1)
3648 num++;
3649
3650 rk3308->micbias2 =
3651 of_property_read_bool(np, "rockchip,micbias2");
3652 if (rk3308->micbias2)
3653 num++;
3654
3655 rk3308->micbias_volt = RK3308_ADC_MICBIAS_VOLT_0_85; /* by default */
3656 rk3308->micbias_num = num;
3657
3658 /* Check external micbias */
3659 rk3308->ext_micbias = EXT_MICBIAS_NONE;
3660
3661 rk3308->micbias_en_gpio = devm_gpiod_get_optional(dev,
3662 "micbias-en",
3663 GPIOD_IN);
3664 if (!rk3308->micbias_en_gpio) {
3665 dev_info(dev, "Don't need micbias-en gpio\n");
3666 } else if (IS_ERR(rk3308->micbias_en_gpio)) {
3667 ret = PTR_ERR(rk3308->micbias_en_gpio);
3668 dev_err(dev, "Unable to claim gpio micbias-en\n");
3669 return ret;
3670 } else if (gpiod_get_value(rk3308->micbias_en_gpio)) {
3671 rk3308->ext_micbias = EXT_MICBIAS_FUNC1;
3672 }
3673
3674 rk3308->vcc_micbias = devm_regulator_get_optional(dev,
3675 "vmicbias");
3676 if (IS_ERR(rk3308->vcc_micbias)) {
3677 if (PTR_ERR(rk3308->vcc_micbias) == -EPROBE_DEFER)
3678 return -EPROBE_DEFER;
3679 dev_info(dev, "no vmicbias regulator found\n");
3680 } else {
3681 ret = regulator_enable(rk3308->vcc_micbias);
3682 if (ret) {
3683 dev_err(dev, "Can't enable vmicbias: %d\n", ret);
3684 return ret;
3685 }
3686 rk3308->ext_micbias = EXT_MICBIAS_FUNC2;
3687 }
3688
3689 dev_info(dev, "Check ext_micbias: %d\n", rk3308->ext_micbias);
3690
3691 return 0;
3692 }
3693
rk3308_codec_dapm_controls_prepare(struct rk3308_codec_priv * rk3308)3694 static int rk3308_codec_dapm_controls_prepare(struct rk3308_codec_priv *rk3308)
3695 {
3696 int grp;
3697
3698 for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++)
3699 rk3308->hpf_cutoff[grp] = 0;
3700
3701 rk3308_codec_dapm_mic_gains(rk3308);
3702
3703 return 0;
3704 }
3705
rk3308_codec_prepare(struct rk3308_codec_priv * rk3308)3706 static int rk3308_codec_prepare(struct rk3308_codec_priv *rk3308)
3707 {
3708 /* Clear registers for ADC and DAC */
3709 rk3308_codec_close_playback(rk3308);
3710 rk3308_codec_close_all_capture(rk3308);
3711 rk3308_codec_default_gains(rk3308);
3712 rk3308_codec_llp_down(rk3308);
3713 rk3308_codec_dapm_controls_prepare(rk3308);
3714
3715 return 0;
3716 }
3717
rk3308_probe(struct snd_soc_component * component)3718 static int rk3308_probe(struct snd_soc_component *component)
3719 {
3720 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
3721 int ext_micbias;
3722
3723 rk3308->component = component;
3724 rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE);
3725
3726 rk3308_codec_reset(component);
3727 rk3308_codec_power_on(rk3308);
3728
3729 /* From vendor recommend, disable micbias at first. */
3730 ext_micbias = rk3308->ext_micbias;
3731 rk3308->ext_micbias = EXT_MICBIAS_NONE;
3732 rk3308_codec_micbias_disable(rk3308);
3733 rk3308->ext_micbias = ext_micbias;
3734
3735 rk3308_codec_prepare(rk3308);
3736 if (!rk3308->no_hp_det)
3737 rk3308_codec_headset_detect_enable(rk3308);
3738
3739 regcache_cache_only(rk3308->regmap, false);
3740 regcache_sync(rk3308->regmap);
3741
3742 return 0;
3743 }
3744
rk3308_remove(struct snd_soc_component * component)3745 static void rk3308_remove(struct snd_soc_component *component)
3746 {
3747 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
3748
3749 rk3308_headphone_ctl(rk3308, 0);
3750 rk3308_speaker_ctl(rk3308, 0);
3751 if (!rk3308->no_hp_det)
3752 rk3308_codec_headset_detect_disable(rk3308);
3753 rk3308_codec_micbias_disable(rk3308);
3754 rk3308_codec_power_off(rk3308);
3755
3756 rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE);
3757
3758 regcache_cache_only(rk3308->regmap, false);
3759 regcache_sync(rk3308->regmap);
3760 }
3761
rk3308_codec_set_jack(struct snd_soc_component * component,struct snd_soc_jack * jack,void * data)3762 static int rk3308_codec_set_jack(struct snd_soc_component *component,
3763 struct snd_soc_jack *jack, void *data)
3764 {
3765 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
3766
3767 /* Return directly if the DUT don't need to support headphone detection */
3768 if (rk3308->no_hp_det)
3769 return 0;
3770
3771 rk3308->hpdet_jack = jack;
3772
3773 /* To detect jack once during startup */
3774 disable_irq_nosync(rk3308->irq);
3775 queue_delayed_work(system_power_efficient_wq,
3776 &rk3308->hpdet_work, msecs_to_jiffies(10));
3777
3778 dev_info(rk3308->plat_dev, "%s: Request detect hp jack once\n",
3779 __func__);
3780
3781 return 0;
3782 }
3783
3784 static const struct snd_soc_component_driver soc_codec_dev_rk3308 = {
3785 .probe = rk3308_probe,
3786 .remove = rk3308_remove,
3787 .suspend = rk3308_suspend,
3788 .resume = rk3308_resume,
3789 .set_bias_level = rk3308_set_bias_level,
3790 .controls = rk3308_codec_dapm_controls,
3791 .num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls),
3792 .set_jack = rk3308_codec_set_jack,
3793 };
3794
3795 static const struct reg_default rk3308_codec_reg_defaults[] = {
3796 { RK3308_GLB_CON, 0x07 },
3797 };
3798
rk3308_codec_write_read_reg(struct device * dev,unsigned int reg)3799 static bool rk3308_codec_write_read_reg(struct device *dev, unsigned int reg)
3800 {
3801 /* All registers can be read / write */
3802 return true;
3803 }
3804
rk3308_codec_volatile_reg(struct device * dev,unsigned int reg)3805 static bool rk3308_codec_volatile_reg(struct device *dev, unsigned int reg)
3806 {
3807 return true;
3808 }
3809
rk3308_codec_hpdetect_work(struct work_struct * work)3810 static void rk3308_codec_hpdetect_work(struct work_struct *work)
3811 {
3812 struct rk3308_codec_priv *rk3308 =
3813 container_of(work, struct rk3308_codec_priv, hpdet_work.work);
3814 unsigned int val, headphone_con = RK3308_CODEC_HEADPHONE_CON;
3815 int need_poll = 0, need_irq = 0;
3816 int need_report = 0, report_type = 0;
3817 int dac_output = DAC_LINEOUT;
3818
3819 if (rk3308->codec_ver == ACODEC_VERSION_C)
3820 headphone_con = RK3308BS_CODEC_HEADPHONE_CON;
3821
3822 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
3823 /* Check headphone plugged/unplugged directly. */
3824 regmap_read(rk3308->detect_grf,
3825 DETECT_GRF_ACODEC_HPDET_STATUS, &val);
3826 regmap_write(rk3308->detect_grf,
3827 DETECT_GRF_ACODEC_HPDET_STATUS_CLR, val);
3828
3829 if (rk3308->hp_jack_reversed) {
3830 switch (val) {
3831 case 0x0:
3832 case 0x2:
3833 dac_output = DAC_HPOUT;
3834 report_type = SND_JACK_HEADPHONE;
3835 break;
3836 default:
3837 break;
3838 }
3839 } else {
3840 switch (val) {
3841 case 0x1:
3842 dac_output = DAC_HPOUT;
3843 report_type = SND_JACK_HEADPHONE;
3844 break;
3845 default:
3846 /* Includes val == 2 or others. */
3847 break;
3848 }
3849 }
3850
3851 rk3308_codec_dac_switch(rk3308, dac_output);
3852 if (rk3308->hpdet_jack)
3853 snd_soc_jack_report(rk3308->hpdet_jack,
3854 report_type,
3855 SND_JACK_HEADPHONE);
3856
3857 enable_irq(rk3308->irq);
3858
3859 return;
3860 }
3861
3862 /* Check headphone unplugged via poll. */
3863 regmap_read(rk3308->regmap, headphone_con, &val);
3864
3865 if (rk3308->hp_jack_reversed) {
3866 if (!val) {
3867 rk3308->hp_plugged = true;
3868 report_type = SND_JACK_HEADPHONE;
3869
3870 need_report = 1;
3871 need_irq = 1;
3872 } else {
3873 if (rk3308->hp_plugged) {
3874 rk3308->hp_plugged = false;
3875 need_report = 1;
3876 }
3877 need_poll = 1;
3878 }
3879 } else {
3880 if (!val) {
3881 rk3308->hp_plugged = false;
3882
3883 need_report = 1;
3884 need_irq = 1;
3885 } else {
3886 if (!rk3308->hp_plugged) {
3887 rk3308->hp_plugged = true;
3888 report_type = SND_JACK_HEADPHONE;
3889 need_report = 1;
3890 }
3891 need_poll = 1;
3892 }
3893 }
3894
3895 if (need_poll)
3896 queue_delayed_work(system_power_efficient_wq,
3897 &rk3308->hpdet_work,
3898 msecs_to_jiffies(HPDET_POLL_MS));
3899
3900 if (need_report) {
3901 if (report_type)
3902 dac_output = DAC_HPOUT;
3903
3904 rk3308_codec_dac_switch(rk3308, dac_output);
3905
3906 if (rk3308->hpdet_jack)
3907 snd_soc_jack_report(rk3308->hpdet_jack,
3908 report_type,
3909 SND_JACK_HEADPHONE);
3910 }
3911
3912 if (need_irq)
3913 enable_irq(rk3308->irq);
3914 }
3915
rk3308_codec_loopback_work(struct work_struct * work)3916 static void rk3308_codec_loopback_work(struct work_struct *work)
3917 {
3918 struct rk3308_codec_priv *rk3308 =
3919 container_of(work, struct rk3308_codec_priv, loopback_work.work);
3920 int type = ADC_TYPE_LOOPBACK;
3921 int idx, grp;
3922
3923 /* Prepare loopback ADCs */
3924 rk3308_codec_adc_ana_enable(rk3308, type);
3925
3926 /* Waiting ADCs are stable */
3927 msleep(ADC_STABLE_MS);
3928
3929 /* Recover normal mode after enable ADCs */
3930 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) {
3931 if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1)
3932 continue;
3933
3934 regmap_update_bits(rk3308->regmap,
3935 RK3308_ADC_DIG_CON03(grp),
3936 RK3308_ADC_L_CH_BIST_MSK,
3937 RK3308_ADC_L_CH_NORMAL_LEFT);
3938 regmap_update_bits(rk3308->regmap,
3939 RK3308_ADC_DIG_CON03(grp),
3940 RK3308_ADC_R_CH_BIST_MSK,
3941 RK3308_ADC_R_CH_NORMAL_RIGHT);
3942 }
3943 }
3944
rk3308_codec_hpdet_isr(int irq,void * data)3945 static irqreturn_t rk3308_codec_hpdet_isr(int irq, void *data)
3946 {
3947 struct rk3308_codec_priv *rk3308 = data;
3948
3949 /*
3950 * For the high level irq trigger, disable irq and avoid a lot of
3951 * repeated irq handlers entry.
3952 */
3953 disable_irq_nosync(rk3308->irq);
3954 queue_delayed_work(system_power_efficient_wq,
3955 &rk3308->hpdet_work, msecs_to_jiffies(10));
3956
3957 return IRQ_HANDLED;
3958 }
3959
3960 static const struct regmap_config rk3308_codec_regmap_config = {
3961 .reg_bits = 32,
3962 .reg_stride = 4,
3963 .val_bits = 32,
3964 .max_register = RK3308_DAC_ANA_CON15,
3965 .writeable_reg = rk3308_codec_write_read_reg,
3966 .readable_reg = rk3308_codec_write_read_reg,
3967 .volatile_reg = rk3308_codec_volatile_reg,
3968 .reg_defaults = rk3308_codec_reg_defaults,
3969 .num_reg_defaults = ARRAY_SIZE(rk3308_codec_reg_defaults),
3970 .cache_type = REGCACHE_FLAT,
3971 };
3972
pm_state_show(struct device * dev,struct device_attribute * attr,char * buf)3973 static ssize_t pm_state_show(struct device *dev,
3974 struct device_attribute *attr,
3975 char *buf)
3976 {
3977 struct rk3308_codec_priv *rk3308 =
3978 container_of(dev, struct rk3308_codec_priv, dev);
3979
3980 return sprintf(buf, "pm_state: %d\n", rk3308->pm_state);
3981 }
3982
pm_state_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3983 static ssize_t pm_state_store(struct device *dev,
3984 struct device_attribute *attr,
3985 const char *buf, size_t count)
3986 {
3987 struct rk3308_codec_priv *rk3308 =
3988 container_of(dev, struct rk3308_codec_priv, dev);
3989 unsigned long pm_state;
3990 int ret = kstrtoul(buf, 10, &pm_state);
3991
3992 if (ret < 0) {
3993 dev_err(dev, "Invalid pm_state: %ld, ret: %d\n",
3994 pm_state, ret);
3995 return -EINVAL;
3996 }
3997
3998 rk3308_codec_set_pm_state(rk3308, pm_state);
3999
4000 dev_info(dev, "Store pm_state: %d\n", rk3308->pm_state);
4001
4002 return count;
4003 }
4004
adc_grps_show(struct device * dev,struct device_attribute * attr,char * buf)4005 static ssize_t adc_grps_show(struct device *dev,
4006 struct device_attribute *attr,
4007 char *buf)
4008 {
4009 struct rk3308_codec_priv *rk3308 =
4010 container_of(dev, struct rk3308_codec_priv, dev);
4011 u32 grp;
4012 int type = ADC_TYPE_NORMAL, count = 0;
4013 int idx;
4014
4015 count += sprintf(buf + count, "current used adc_grps:\n");
4016 count += sprintf(buf + count, "- normal:");
4017 for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++)
4018 count += sprintf(buf + count, " %d", grp);
4019 count += sprintf(buf + count, "\n");
4020 count += sprintf(buf + count, "- loopback: %d\n",
4021 rk3308->loopback_grp);
4022
4023 return count;
4024 }
4025
adc_grps_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)4026 static ssize_t adc_grps_store(struct device *dev,
4027 struct device_attribute *attr,
4028 const char *buf, size_t count)
4029 {
4030 struct rk3308_codec_priv *rk3308 =
4031 container_of(dev, struct rk3308_codec_priv, dev);
4032 char adc_type;
4033 int grps, ret;
4034
4035 ret = sscanf(buf, "%c,%d", &adc_type, &grps);
4036 if (ret != 2) {
4037 dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n",
4038 __func__, ret);
4039 return -EFAULT;
4040 }
4041
4042 if (adc_type == 'n')
4043 rk3308->used_adc_grps = grps;
4044 else if (adc_type == 'l')
4045 rk3308->loopback_grp = grps;
4046
4047 return count;
4048 }
4049
adc_grps_route_show(struct device * dev,struct device_attribute * attr,char * buf)4050 static ssize_t adc_grps_route_show(struct device *dev,
4051 struct device_attribute *attr,
4052 char *buf)
4053 {
4054 struct rk3308_codec_priv *rk3308 =
4055 container_of(dev, struct rk3308_codec_priv, dev);
4056 char which_i2s[32] = {0};
4057 int count = 0;
4058 u32 grp;
4059
4060 switch (rk3308->which_i2s) {
4061 case ACODEC_TO_I2S1_2CH:
4062 strcpy(which_i2s, "i2s1_2ch");
4063 break;
4064 case ACODEC_TO_I2S3_4CH:
4065 strcpy(which_i2s, "i2s3_4ch");
4066 break;
4067 default:
4068 strcpy(which_i2s, "i2s2_8ch");
4069 break;
4070 }
4071
4072 count += sprintf(buf + count, "%s from acodec route mapping:\n",
4073 which_i2s);
4074 for (grp = 0; grp < rk3308->to_i2s_grps; grp++) {
4075 count += sprintf(buf + count, "* sdi_%d <-- sdo_%d\n",
4076 grp, rk3308->i2s_sdis[grp]);
4077 }
4078
4079 return count;
4080 }
4081
adc_grps_route_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)4082 static ssize_t adc_grps_route_store(struct device *dev,
4083 struct device_attribute *attr,
4084 const char *buf, size_t count)
4085 {
4086 struct rk3308_codec_priv *rk3308 =
4087 container_of(dev, struct rk3308_codec_priv, dev);
4088 int which_i2s, idx, i2s_sdis[ADC_LR_GROUP_MAX];
4089 int ret;
4090
4091 ret = sscanf(buf, "%d,%d,%d,%d,%d", &which_i2s,
4092 &i2s_sdis[0], &i2s_sdis[1], &i2s_sdis[2], &i2s_sdis[3]);
4093 if (ret != 5) {
4094 dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n",
4095 __func__, ret);
4096 goto err;
4097 }
4098
4099 if (which_i2s < ACODEC_TO_I2S2_8CH ||
4100 which_i2s > ACODEC_TO_I2S1_2CH) {
4101 dev_err(rk3308->plat_dev, "Invalid i2s type: %d\n", which_i2s);
4102 goto err;
4103 }
4104
4105 rk3308->which_i2s = which_i2s;
4106
4107 switch (rk3308->which_i2s) {
4108 case ACODEC_TO_I2S1_2CH:
4109 rk3308->to_i2s_grps = 1;
4110 break;
4111 case ACODEC_TO_I2S3_4CH:
4112 rk3308->to_i2s_grps = 2;
4113 break;
4114 default:
4115 rk3308->to_i2s_grps = 4;
4116 break;
4117 }
4118
4119 for (idx = 0; idx < rk3308->to_i2s_grps; idx++)
4120 rk3308->i2s_sdis[idx] = i2s_sdis[idx];
4121
4122 rk3308_codec_adc_grps_route_config(rk3308);
4123
4124 err:
4125 return count;
4126 }
4127
adc_grp0_in_show(struct device * dev,struct device_attribute * attr,char * buf)4128 static ssize_t adc_grp0_in_show(struct device *dev,
4129 struct device_attribute *attr,
4130 char *buf)
4131 {
4132 struct rk3308_codec_priv *rk3308 =
4133 container_of(dev, struct rk3308_codec_priv, dev);
4134
4135 return sprintf(buf, "adc ch0 using: %s\n",
4136 rk3308->adc_grp0_using_linein ? "line in" : "mic in");
4137 }
4138
adc_grp0_in_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)4139 static ssize_t adc_grp0_in_store(struct device *dev,
4140 struct device_attribute *attr,
4141 const char *buf, size_t count)
4142 {
4143 struct rk3308_codec_priv *rk3308 =
4144 container_of(dev, struct rk3308_codec_priv, dev);
4145 unsigned long using_linein;
4146 int ret = kstrtoul(buf, 10, &using_linein);
4147
4148 if (ret < 0 || using_linein > 1) {
4149 dev_err(dev, "Invalid input status: %ld, ret: %d\n",
4150 using_linein, ret);
4151 return -EINVAL;
4152 }
4153
4154 rk3308->adc_grp0_using_linein = using_linein;
4155
4156 dev_info(dev, "store using_linein: %d\n",
4157 rk3308->adc_grp0_using_linein);
4158
4159 return count;
4160 }
4161
adc_zerocross_show(struct device * dev,struct device_attribute * attr,char * buf)4162 static ssize_t adc_zerocross_show(struct device *dev,
4163 struct device_attribute *attr,
4164 char *buf)
4165 {
4166 struct rk3308_codec_priv *rk3308 =
4167 container_of(dev, struct rk3308_codec_priv, dev);
4168
4169 return sprintf(buf, "adc zerocross: %s\n",
4170 rk3308->adc_zerocross ? "enabled" : "disabled");
4171 }
4172
adc_zerocross_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)4173 static ssize_t adc_zerocross_store(struct device *dev,
4174 struct device_attribute *attr,
4175 const char *buf, size_t count)
4176 {
4177 struct rk3308_codec_priv *rk3308 =
4178 container_of(dev, struct rk3308_codec_priv, dev);
4179 unsigned long zerocross;
4180 int ret = kstrtoul(buf, 10, &zerocross);
4181
4182 if (ret < 0 || zerocross > 1) {
4183 dev_err(dev, "Invalid zerocross: %ld, ret: %d\n",
4184 zerocross, ret);
4185 return -EINVAL;
4186 }
4187
4188 rk3308->adc_zerocross = zerocross;
4189
4190 dev_info(dev, "store adc zerocross: %d\n", rk3308->adc_zerocross);
4191
4192 return count;
4193 }
4194
adc_grps_endisable_show(struct device * dev,struct device_attribute * attr,char * buf)4195 static ssize_t adc_grps_endisable_show(struct device *dev,
4196 struct device_attribute *attr,
4197 char *buf)
4198 {
4199 struct rk3308_codec_priv *rk3308 =
4200 container_of(dev, struct rk3308_codec_priv, dev);
4201 int count = 0, i;
4202
4203 count += sprintf(buf + count, "enabled adc grps:");
4204 for (i = 0; i < ADC_LR_GROUP_MAX; i++)
4205 count += sprintf(buf + count, "%d ",
4206 rk3308->adc_grps_endisable[i]);
4207
4208 count += sprintf(buf + count, "\n");
4209 return count;
4210 }
4211
adc_grps_endisable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)4212 static ssize_t adc_grps_endisable_store(struct device *dev,
4213 struct device_attribute *attr,
4214 const char *buf, size_t count)
4215 {
4216 struct rk3308_codec_priv *rk3308 =
4217 container_of(dev, struct rk3308_codec_priv, dev);
4218 int grp, endisable, ret;
4219
4220 ret = sscanf(buf, "%d,%d", &grp, &endisable);
4221 if (ret != 2) {
4222 dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n",
4223 __func__, ret);
4224 return -EFAULT;
4225 }
4226
4227 rk3308->cur_dbg_grp = grp;
4228
4229 if (endisable)
4230 rk3308_codec_open_dbg_capture(rk3308);
4231 else
4232 rk3308_codec_close_dbg_capture(rk3308);
4233
4234 dev_info(dev, "ADC grp %d endisable: %d\n", grp, endisable);
4235
4236 return count;
4237 }
4238
dac_endisable_show(struct device * dev,struct device_attribute * attr,char * buf)4239 static ssize_t dac_endisable_show(struct device *dev,
4240 struct device_attribute *attr,
4241 char *buf)
4242 {
4243 struct rk3308_codec_priv *rk3308 =
4244 container_of(dev, struct rk3308_codec_priv, dev);
4245
4246 return sprintf(buf, "%d\n", rk3308->dac_endisable);
4247 }
4248
dac_endisable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)4249 static ssize_t dac_endisable_store(struct device *dev,
4250 struct device_attribute *attr,
4251 const char *buf, size_t count)
4252 {
4253 struct rk3308_codec_priv *rk3308 =
4254 container_of(dev, struct rk3308_codec_priv, dev);
4255 unsigned long endisable;
4256 int ret = kstrtoul(buf, 10, &endisable);
4257
4258 if (ret < 0) {
4259 dev_err(dev, "Invalid endisable: %ld, ret: %d\n",
4260 endisable, ret);
4261 return -EINVAL;
4262 }
4263
4264 if (endisable)
4265 rk3308_codec_open_playback(rk3308);
4266 else
4267 rk3308_codec_close_playback(rk3308);
4268
4269 dev_info(dev, "DAC endisable: %ld\n", endisable);
4270
4271 return count;
4272 }
4273
dac_output_show(struct device * dev,struct device_attribute * attr,char * buf)4274 static ssize_t dac_output_show(struct device *dev,
4275 struct device_attribute *attr,
4276 char *buf)
4277 {
4278 struct rk3308_codec_priv *rk3308 =
4279 container_of(dev, struct rk3308_codec_priv, dev);
4280 ssize_t ret = 0;
4281
4282 switch (rk3308->dac_output) {
4283 case DAC_LINEOUT:
4284 ret = sprintf(buf, "dac path: %s\n", "line out");
4285 break;
4286 case DAC_HPOUT:
4287 ret = sprintf(buf, "dac path: %s\n", "hp out");
4288 break;
4289 case DAC_LINEOUT_HPOUT:
4290 ret = sprintf(buf, "dac path: %s\n",
4291 "both line out and hp out");
4292 break;
4293 default:
4294 pr_err("Invalid dac path: %d ?\n", rk3308->dac_output);
4295 break;
4296 }
4297
4298 return ret;
4299 }
4300
dac_output_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)4301 static ssize_t dac_output_store(struct device *dev,
4302 struct device_attribute *attr,
4303 const char *buf, size_t count)
4304 {
4305 struct rk3308_codec_priv *rk3308 =
4306 container_of(dev, struct rk3308_codec_priv, dev);
4307 unsigned long dac_output;
4308 int ret = kstrtoul(buf, 10, &dac_output);
4309
4310 if (ret < 0) {
4311 dev_err(dev, "Invalid input status: %ld, ret: %d\n",
4312 dac_output, ret);
4313 return -EINVAL;
4314 }
4315
4316 rk3308_codec_dac_switch(rk3308, dac_output);
4317
4318 dev_info(dev, "Store dac_output: %d\n", rk3308->dac_output);
4319
4320 return count;
4321 }
4322
enable_all_adcs_show(struct device * dev,struct device_attribute * attr,char * buf)4323 static ssize_t enable_all_adcs_show(struct device *dev,
4324 struct device_attribute *attr,
4325 char *buf)
4326 {
4327 struct rk3308_codec_priv *rk3308 =
4328 container_of(dev, struct rk3308_codec_priv, dev);
4329
4330 return sprintf(buf, "%d\n", rk3308->enable_all_adcs);
4331 }
4332
enable_all_adcs_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)4333 static ssize_t enable_all_adcs_store(struct device *dev,
4334 struct device_attribute *attr,
4335 const char *buf, size_t count)
4336 {
4337 struct rk3308_codec_priv *rk3308 =
4338 container_of(dev, struct rk3308_codec_priv, dev);
4339 unsigned long enable;
4340 int ret = kstrtoul(buf, 10, &enable);
4341
4342 if (ret < 0) {
4343 dev_err(dev, "Invalid enable value: %ld, ret: %d\n",
4344 enable, ret);
4345 return -EINVAL;
4346 }
4347
4348 rk3308->enable_all_adcs = enable;
4349
4350 return count;
4351 }
4352
4353 static const struct device_attribute acodec_attrs[] = {
4354 __ATTR_RW(adc_grps),
4355 __ATTR_RW(adc_grps_endisable),
4356 __ATTR_RW(adc_grps_route),
4357 __ATTR_RW(adc_grp0_in),
4358 __ATTR_RW(adc_zerocross),
4359 __ATTR_RW(dac_endisable),
4360 __ATTR_RW(dac_output),
4361 __ATTR_RW(enable_all_adcs),
4362 __ATTR_RW(pm_state),
4363 };
4364
rk3308_codec_device_release(struct device * dev)4365 static void rk3308_codec_device_release(struct device *dev)
4366 {
4367 /* Do nothing */
4368 }
4369
rk3308_codec_sysfs_init(struct platform_device * pdev,struct rk3308_codec_priv * rk3308)4370 static int rk3308_codec_sysfs_init(struct platform_device *pdev,
4371 struct rk3308_codec_priv *rk3308)
4372 {
4373 struct device *dev = &rk3308->dev;
4374 int i;
4375
4376 dev->release = rk3308_codec_device_release;
4377 dev->parent = &pdev->dev;
4378 set_dev_node(dev, dev_to_node(&pdev->dev));
4379 dev_set_name(dev, "rk3308-acodec-dev");
4380
4381 if (device_register(dev)) {
4382 dev_err(&pdev->dev,
4383 "Register 'rk3308-acodec-dev' failed\n");
4384 dev->parent = NULL;
4385 return -ENOMEM;
4386 }
4387
4388 for (i = 0; i < ARRAY_SIZE(acodec_attrs); i++) {
4389 if (device_create_file(dev, &acodec_attrs[i])) {
4390 dev_err(&pdev->dev,
4391 "Create 'rk3308-acodec-dev' attr failed\n");
4392 device_unregister(dev);
4393 return -ENOMEM;
4394 }
4395 }
4396
4397 return 0;
4398 }
4399
rk3308_codec_sysfs_exit(struct rk3308_codec_priv * rk3308)4400 static void rk3308_codec_sysfs_exit(struct rk3308_codec_priv *rk3308)
4401 {
4402 struct device *dev = &rk3308->dev;
4403 unsigned int i;
4404
4405 for (i = 0; i < ARRAY_SIZE(acodec_attrs); i++)
4406 device_remove_file(dev, &acodec_attrs[i]);
4407 device_unregister(dev);
4408 }
4409
4410 #if defined(CONFIG_DEBUG_FS)
rk3308_codec_debugfs_reg_show(struct seq_file * s,void * v)4411 static int rk3308_codec_debugfs_reg_show(struct seq_file *s, void *v)
4412 {
4413 struct rk3308_codec_priv *rk3308 = s->private;
4414 unsigned int i;
4415 unsigned int val;
4416
4417 for (i = RK3308_GLB_CON; i <= RK3308_DAC_ANA_CON13; i += 4) {
4418 regmap_read(rk3308->regmap, i, &val);
4419 if (!(i % 16))
4420 seq_printf(s, "\nR:%04x: ", i);
4421 seq_printf(s, "%08x ", val);
4422 }
4423
4424 seq_puts(s, "\n");
4425
4426 return 0;
4427 }
4428
rk3308_codec_debugfs_reg_operate(struct file * file,const char __user * buf,size_t count,loff_t * ppos)4429 static ssize_t rk3308_codec_debugfs_reg_operate(struct file *file,
4430 const char __user *buf,
4431 size_t count, loff_t *ppos)
4432 {
4433 struct rk3308_codec_priv *rk3308 =
4434 ((struct seq_file *)file->private_data)->private;
4435 unsigned int reg, val;
4436 char op;
4437 char kbuf[32];
4438 int ret;
4439
4440 if (count >= sizeof(kbuf))
4441 return -EINVAL;
4442
4443 if (copy_from_user(kbuf, buf, count))
4444 return -EFAULT;
4445 kbuf[count] = '\0';
4446
4447 ret = sscanf(kbuf, "%c,%x,%x", &op, ®, &val);
4448 if (ret != 3) {
4449 pr_err("sscanf failed: %d\n", ret);
4450 return -EFAULT;
4451 }
4452
4453 if (op == 'w') {
4454 pr_info("Write reg: 0x%04x with val: 0x%08x\n", reg, val);
4455 regmap_write(rk3308->regmap, reg, val);
4456 regcache_cache_only(rk3308->regmap, false);
4457 regcache_sync(rk3308->regmap);
4458 pr_info("Read back reg: 0x%04x with val: 0x%08x\n", reg, val);
4459 } else if (op == 'r') {
4460 regmap_read(rk3308->regmap, reg, &val);
4461 pr_info("Read reg: 0x%04x with val: 0x%08x\n", reg, val);
4462 } else {
4463 pr_err("This is an invalid operation: %c\n", op);
4464 }
4465
4466 return count;
4467 }
4468
rk3308_codec_debugfs_open(struct inode * inode,struct file * file)4469 static int rk3308_codec_debugfs_open(struct inode *inode, struct file *file)
4470 {
4471 return single_open(file,
4472 rk3308_codec_debugfs_reg_show, inode->i_private);
4473 }
4474
4475 static const struct file_operations rk3308_codec_reg_debugfs_fops = {
4476 .owner = THIS_MODULE,
4477 .open = rk3308_codec_debugfs_open,
4478 .read = seq_read,
4479 .write = rk3308_codec_debugfs_reg_operate,
4480 .llseek = seq_lseek,
4481 .release = single_release,
4482 };
4483 #endif /* CONFIG_DEBUG_FS */
4484
rk3308_codec_get_version(struct rk3308_codec_priv * rk3308)4485 static int rk3308_codec_get_version(struct rk3308_codec_priv *rk3308)
4486 {
4487 unsigned int chip_id;
4488
4489 regmap_read(rk3308->grf, GRF_CHIP_ID, &chip_id);
4490 switch (chip_id) {
4491 case 3306:
4492 rk3308->codec_ver = ACODEC_VERSION_A;
4493 break;
4494 case 0x3308:
4495 rk3308->codec_ver = ACODEC_VERSION_B;
4496 break;
4497 case 0x3308c:
4498 rk3308->codec_ver = ACODEC_VERSION_C;
4499 break;
4500 default:
4501 pr_err("Unknown chip_id: %d / 0x%x\n", chip_id, chip_id);
4502 return -EFAULT;
4503 }
4504
4505 pr_info("The acodec version is: %x\n", rk3308->codec_ver);
4506 return 0;
4507 }
4508
rk3308_platform_probe(struct platform_device * pdev)4509 static int rk3308_platform_probe(struct platform_device *pdev)
4510 {
4511 struct device_node *np = pdev->dev.of_node;
4512 struct rk3308_codec_priv *rk3308;
4513 struct resource *res;
4514 void __iomem *base;
4515 int ret;
4516
4517 rk3308 = devm_kzalloc(&pdev->dev, sizeof(*rk3308), GFP_KERNEL);
4518 if (!rk3308)
4519 return -ENOMEM;
4520
4521 rk3308->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4522 if (IS_ERR(rk3308->grf)) {
4523 dev_err(&pdev->dev,
4524 "Missing 'rockchip,grf' property\n");
4525 return PTR_ERR(rk3308->grf);
4526 }
4527
4528 ret = rk3308_codec_get_version(rk3308);
4529 if (ret < 0)
4530 return dev_err_probe(&pdev->dev, ret, "Failed to get acodec version\n");
4531
4532 ret = rk3308_codec_sysfs_init(pdev, rk3308);
4533 if (ret < 0) {
4534 dev_err(&pdev->dev, "Sysfs init failed\n");
4535 return ret;
4536 }
4537
4538 #if defined(CONFIG_DEBUG_FS)
4539 rk3308->dbg_codec = debugfs_create_dir(CODEC_DRV_NAME, NULL);
4540 if (IS_ERR(rk3308->dbg_codec))
4541 dev_err(&pdev->dev,
4542 "Failed to create debugfs dir for rk3308!\n");
4543 else
4544 debugfs_create_file("reg", 0644, rk3308->dbg_codec,
4545 rk3308, &rk3308_codec_reg_debugfs_fops);
4546 #endif
4547 rk3308->plat_dev = &pdev->dev;
4548
4549 rk3308->reset = devm_reset_control_get(&pdev->dev, "acodec-reset");
4550 if (IS_ERR(rk3308->reset)) {
4551 ret = PTR_ERR(rk3308->reset);
4552 if (ret != -ENOENT)
4553 goto out_sysfs;
4554
4555 dev_dbg(&pdev->dev, "No reset control found\n");
4556 rk3308->reset = NULL;
4557 }
4558
4559 rk3308->hp_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "hp-ctl",
4560 GPIOD_OUT_LOW);
4561 if (!rk3308->hp_ctl_gpio) {
4562 dev_info(&pdev->dev, "Don't need hp-ctl gpio\n");
4563 } else if (IS_ERR(rk3308->hp_ctl_gpio)) {
4564 ret = PTR_ERR(rk3308->hp_ctl_gpio);
4565 dev_err(&pdev->dev, "Unable to claim gpio hp-ctl\n");
4566 goto out_sysfs;
4567 }
4568
4569 rk3308->spk_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "spk-ctl",
4570 GPIOD_OUT_LOW);
4571
4572 if (!rk3308->spk_ctl_gpio) {
4573 dev_info(&pdev->dev, "Don't need spk-ctl gpio\n");
4574 } else if (IS_ERR(rk3308->spk_ctl_gpio)) {
4575 ret = PTR_ERR(rk3308->spk_ctl_gpio);
4576 dev_err(&pdev->dev, "Unable to claim gpio spk-ctl\n");
4577 goto out_sysfs;
4578 }
4579
4580 rk3308->pa_drv_gpio = devm_gpiod_get_optional(&pdev->dev, "pa-drv",
4581 GPIOD_OUT_LOW);
4582
4583 if (!rk3308->pa_drv_gpio) {
4584 dev_info(&pdev->dev, "Don't need pa-drv gpio\n");
4585 } else if (IS_ERR(rk3308->pa_drv_gpio)) {
4586 ret = PTR_ERR(rk3308->pa_drv_gpio);
4587 dev_err(&pdev->dev, "Unable to claim gpio pa-drv\n");
4588 goto out_sysfs;
4589 }
4590
4591 if (rk3308->pa_drv_gpio) {
4592 rk3308->delay_pa_drv_ms = PA_DRV_MS;
4593 ret = of_property_read_u32(np, "rockchip,delay-pa-drv-ms",
4594 &rk3308->delay_pa_drv_ms);
4595 }
4596
4597 #if DEBUG_POP_ALWAYS
4598 dev_info(&pdev->dev, "Enable all ctl gpios always for debugging pop\n");
4599 rk3308_headphone_ctl(rk3308, 1);
4600 rk3308_speaker_ctl(rk3308, 1);
4601 #else
4602 dev_info(&pdev->dev, "De-pop as much as possible\n");
4603 rk3308_headphone_ctl(rk3308, 0);
4604 rk3308_speaker_ctl(rk3308, 0);
4605 #endif
4606
4607 rk3308->pclk = devm_clk_get(&pdev->dev, "acodec");
4608 if (IS_ERR(rk3308->pclk)) {
4609 dev_err(&pdev->dev, "Can't get acodec pclk\n");
4610 ret = PTR_ERR(rk3308->pclk);
4611 goto out_sysfs;
4612 }
4613
4614 rk3308->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
4615 if (IS_ERR(rk3308->mclk_rx)) {
4616 dev_err(&pdev->dev, "Can't get acodec mclk_rx\n");
4617 ret = PTR_ERR(rk3308->mclk_rx);
4618 goto out_sysfs;
4619 }
4620
4621 rk3308->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
4622 if (IS_ERR(rk3308->mclk_tx)) {
4623 dev_err(&pdev->dev, "Can't get acodec mclk_tx\n");
4624 ret = PTR_ERR(rk3308->mclk_tx);
4625 goto out_sysfs;
4626 }
4627
4628 ret = clk_prepare_enable(rk3308->pclk);
4629 if (ret < 0) {
4630 dev_err(&pdev->dev, "Failed to enable acodec pclk: %d\n", ret);
4631 goto out_sysfs;
4632 }
4633
4634 ret = clk_prepare_enable(rk3308->mclk_rx);
4635 if (ret < 0) {
4636 dev_err(&pdev->dev, "Failed to enable i2s mclk_rx: %d\n", ret);
4637 goto out_pclk;
4638 }
4639
4640 ret = clk_prepare_enable(rk3308->mclk_tx);
4641 if (ret < 0) {
4642 dev_err(&pdev->dev, "Failed to enable i2s mclk_tx: %d\n", ret);
4643 goto out_mclk_rx;
4644 }
4645
4646 rk3308_codec_check_micbias(rk3308, np);
4647
4648 rk3308->enable_all_adcs =
4649 of_property_read_bool(np, "rockchip,enable-all-adcs");
4650
4651 rk3308->hp_jack_reversed =
4652 of_property_read_bool(np, "rockchip,hp-jack-reversed");
4653
4654 rk3308->no_deep_low_power =
4655 of_property_read_bool(np, "rockchip,no-deep-low-power");
4656
4657 rk3308->no_hp_det =
4658 of_property_read_bool(np, "rockchip,no-hp-det");
4659
4660 rk3308->delay_loopback_handle_ms = LOOPBACK_HANDLE_MS;
4661 ret = of_property_read_u32(np, "rockchip,delay-loopback-handle-ms",
4662 &rk3308->delay_loopback_handle_ms);
4663
4664 rk3308->delay_start_play_ms = 0;
4665 ret = of_property_read_u32(np, "rockchip,delay-start-play-ms",
4666 &rk3308->delay_start_play_ms);
4667
4668 rk3308->loopback_grp = NOT_USED;
4669 ret = of_property_read_u32(np, "rockchip,loopback-grp",
4670 &rk3308->loopback_grp);
4671 /*
4672 * If there is no loopback on some board, the -EINVAL indicates that
4673 * we don't need add the node, and it is not an error.
4674 */
4675 if (ret < 0 && ret != -EINVAL) {
4676 dev_err(&pdev->dev, "Failed to read loopback property: %d\n",
4677 ret);
4678 goto failed;
4679 }
4680
4681 ret = rk3308_codec_adc_grps_route(rk3308, np);
4682 if (ret < 0) {
4683 dev_err(&pdev->dev, "Failed to route ADC groups: %d\n",
4684 ret);
4685 goto failed;
4686 }
4687
4688 ret = rk3308_codec_setup_en_always_adcs(rk3308, np);
4689 if (ret < 0) {
4690 dev_err(&pdev->dev, "Failed to setup enabled always ADCs: %d\n",
4691 ret);
4692 goto failed;
4693 }
4694
4695 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4696 base = devm_ioremap_resource(&pdev->dev, res);
4697 if (IS_ERR(base)) {
4698 ret = PTR_ERR(base);
4699 dev_err(&pdev->dev, "Failed to ioremap resource\n");
4700 goto failed;
4701 }
4702
4703 rk3308->regmap = devm_regmap_init_mmio(&pdev->dev, base,
4704 &rk3308_codec_regmap_config);
4705 if (IS_ERR(rk3308->regmap)) {
4706 ret = PTR_ERR(rk3308->regmap);
4707 dev_err(&pdev->dev, "Failed to regmap mmio\n");
4708 goto failed;
4709 }
4710
4711 if (!rk3308->no_hp_det) {
4712 int index = 0;
4713
4714 if (rk3308->codec_ver >= ACODEC_VERSION_B)
4715 index = 1;
4716
4717 rk3308->irq = platform_get_irq(pdev, index);
4718 if (rk3308->irq < 0) {
4719 dev_err(&pdev->dev, "Can not get codec irq\n");
4720 goto failed;
4721 }
4722
4723 INIT_DELAYED_WORK(&rk3308->hpdet_work, rk3308_codec_hpdetect_work);
4724
4725 ret = devm_request_irq(&pdev->dev, rk3308->irq,
4726 rk3308_codec_hpdet_isr,
4727 0,
4728 "acodec-hpdet",
4729 rk3308);
4730 if (ret < 0) {
4731 dev_err(&pdev->dev, "Failed to request IRQ: %d\n", ret);
4732 goto failed;
4733 }
4734
4735 if (rk3308->codec_ver >= ACODEC_VERSION_B) {
4736 rk3308->detect_grf =
4737 syscon_regmap_lookup_by_phandle(np, "rockchip,detect-grf");
4738 if (IS_ERR(rk3308->detect_grf)) {
4739 dev_err(&pdev->dev,
4740 "Missing 'rockchip,detect-grf' property\n");
4741 ret = PTR_ERR(rk3308->detect_grf);
4742 goto failed;
4743 }
4744
4745 /* Configure filter count and enable hpdet irq. */
4746 regmap_write(rk3308->detect_grf,
4747 DETECT_GRF_ACODEC_HPDET_COUNTER,
4748 DEFAULT_HPDET_COUNT);
4749 regmap_write(rk3308->detect_grf,
4750 DETECT_GRF_ACODEC_HPDET_CON,
4751 (HPDET_BOTH_NEG_POS << 16) |
4752 HPDET_BOTH_NEG_POS);
4753 }
4754 }
4755
4756 if (rk3308->codec_ver == ACODEC_VERSION_A)
4757 INIT_DELAYED_WORK(&rk3308->loopback_work,
4758 rk3308_codec_loopback_work);
4759
4760 rk3308->adc_grp0_using_linein = ADC_GRP0_MICIN;
4761 rk3308->dac_output = DAC_LINEOUT;
4762 rk3308->adc_zerocross = 0;
4763 rk3308->pm_state = PM_NORMAL;
4764
4765 platform_set_drvdata(pdev, rk3308);
4766
4767 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk3308,
4768 rk3308_dai, ARRAY_SIZE(rk3308_dai));
4769 if (ret < 0) {
4770 dev_err(&pdev->dev, "Failed to register codec: %d\n", ret);
4771 goto failed;
4772 }
4773
4774 return ret;
4775
4776 failed:
4777 clk_disable_unprepare(rk3308->mclk_tx);
4778 out_mclk_rx:
4779 clk_disable_unprepare(rk3308->mclk_rx);
4780 out_pclk:
4781 clk_disable_unprepare(rk3308->pclk);
4782 out_sysfs:
4783 rk3308_codec_sysfs_exit(rk3308);
4784
4785 return ret;
4786 }
4787
rk3308_platform_remove(struct platform_device * pdev)4788 static int rk3308_platform_remove(struct platform_device *pdev)
4789 {
4790 struct rk3308_codec_priv *rk3308 =
4791 (struct rk3308_codec_priv *)platform_get_drvdata(pdev);
4792
4793 clk_disable_unprepare(rk3308->mclk_rx);
4794 clk_disable_unprepare(rk3308->mclk_tx);
4795 clk_disable_unprepare(rk3308->pclk);
4796 device_unregister(&rk3308->dev);
4797
4798 return 0;
4799 }
4800
4801 static const struct of_device_id rk3308codec_of_match[] = {
4802 { .compatible = "rockchip,rk3308-codec", },
4803 {},
4804 };
4805 MODULE_DEVICE_TABLE(of, rk3308codec_of_match);
4806
4807 static struct platform_driver rk3308_codec_driver = {
4808 .driver = {
4809 .name = CODEC_DRV_NAME,
4810 .of_match_table = of_match_ptr(rk3308codec_of_match),
4811 },
4812 .probe = rk3308_platform_probe,
4813 .remove = rk3308_platform_remove,
4814 };
4815 module_platform_driver(rk3308_codec_driver);
4816
4817 MODULE_AUTHOR("Xing Zheng <zhengxing@rock-chips.com>");
4818 MODULE_DESCRIPTION("ASoC RK3308 Codec Driver");
4819 MODULE_LICENSE("GPL v2");
4820