xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/pcm3060.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // PCM3060 codec driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2018 Kirill Marinushkin <kmarinushkin@birdec.com>
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <sound/pcm_params.h>
9*4882a593Smuzhiyun #include <sound/soc.h>
10*4882a593Smuzhiyun #include <sound/tlv.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include "pcm3060.h"
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun /* dai */
15*4882a593Smuzhiyun 
pcm3060_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)16*4882a593Smuzhiyun static int pcm3060_set_sysclk(struct snd_soc_dai *dai, int clk_id,
17*4882a593Smuzhiyun 			      unsigned int freq, int dir)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun 	struct snd_soc_component *comp = dai->component;
20*4882a593Smuzhiyun 	struct pcm3060_priv *priv = snd_soc_component_get_drvdata(comp);
21*4882a593Smuzhiyun 	unsigned int reg;
22*4882a593Smuzhiyun 	unsigned int val;
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun 	if (dir != SND_SOC_CLOCK_IN) {
25*4882a593Smuzhiyun 		dev_err(comp->dev, "unsupported sysclock dir: %d\n", dir);
26*4882a593Smuzhiyun 		return -EINVAL;
27*4882a593Smuzhiyun 	}
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	switch (clk_id) {
30*4882a593Smuzhiyun 	case PCM3060_CLK_DEF:
31*4882a593Smuzhiyun 		val = 0;
32*4882a593Smuzhiyun 		break;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	case PCM3060_CLK1:
35*4882a593Smuzhiyun 		val = (dai->id == PCM3060_DAI_ID_DAC ? PCM3060_REG_CSEL : 0);
36*4882a593Smuzhiyun 		break;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	case PCM3060_CLK2:
39*4882a593Smuzhiyun 		val = (dai->id == PCM3060_DAI_ID_DAC ? 0 : PCM3060_REG_CSEL);
40*4882a593Smuzhiyun 		break;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	default:
43*4882a593Smuzhiyun 		dev_err(comp->dev, "unsupported sysclock id: %d\n", clk_id);
44*4882a593Smuzhiyun 		return -EINVAL;
45*4882a593Smuzhiyun 	}
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	if (dai->id == PCM3060_DAI_ID_DAC)
48*4882a593Smuzhiyun 		reg = PCM3060_REG67;
49*4882a593Smuzhiyun 	else
50*4882a593Smuzhiyun 		reg = PCM3060_REG72;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	regmap_update_bits(priv->regmap, reg, PCM3060_REG_CSEL, val);
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	priv->dai[dai->id].sclk_freq = freq;
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
pcm3060_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)59*4882a593Smuzhiyun static int pcm3060_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	struct snd_soc_component *comp = dai->component;
62*4882a593Smuzhiyun 	struct pcm3060_priv *priv = snd_soc_component_get_drvdata(comp);
63*4882a593Smuzhiyun 	unsigned int reg;
64*4882a593Smuzhiyun 	unsigned int val;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
67*4882a593Smuzhiyun 		dev_err(comp->dev, "unsupported DAI polarity: 0x%x\n", fmt);
68*4882a593Smuzhiyun 		return -EINVAL;
69*4882a593Smuzhiyun 	}
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
72*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
73*4882a593Smuzhiyun 		priv->dai[dai->id].is_master = true;
74*4882a593Smuzhiyun 		break;
75*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
76*4882a593Smuzhiyun 		priv->dai[dai->id].is_master = false;
77*4882a593Smuzhiyun 		break;
78*4882a593Smuzhiyun 	default:
79*4882a593Smuzhiyun 		dev_err(comp->dev, "unsupported DAI master mode: 0x%x\n", fmt);
80*4882a593Smuzhiyun 		return -EINVAL;
81*4882a593Smuzhiyun 	}
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
84*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_I2S:
85*4882a593Smuzhiyun 		val = PCM3060_REG_FMT_I2S;
86*4882a593Smuzhiyun 		break;
87*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_RIGHT_J:
88*4882a593Smuzhiyun 		val = PCM3060_REG_FMT_RJ;
89*4882a593Smuzhiyun 		break;
90*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_LEFT_J:
91*4882a593Smuzhiyun 		val = PCM3060_REG_FMT_LJ;
92*4882a593Smuzhiyun 		break;
93*4882a593Smuzhiyun 	default:
94*4882a593Smuzhiyun 		dev_err(comp->dev, "unsupported DAI format: 0x%x\n", fmt);
95*4882a593Smuzhiyun 		return -EINVAL;
96*4882a593Smuzhiyun 	}
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	if (dai->id == PCM3060_DAI_ID_DAC)
99*4882a593Smuzhiyun 		reg = PCM3060_REG67;
100*4882a593Smuzhiyun 	else
101*4882a593Smuzhiyun 		reg = PCM3060_REG72;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	regmap_update_bits(priv->regmap, reg, PCM3060_REG_MASK_FMT, val);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	return 0;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun 
pcm3060_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)108*4882a593Smuzhiyun static int pcm3060_hw_params(struct snd_pcm_substream *substream,
109*4882a593Smuzhiyun 			     struct snd_pcm_hw_params *params,
110*4882a593Smuzhiyun 			     struct snd_soc_dai *dai)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	struct snd_soc_component *comp = dai->component;
113*4882a593Smuzhiyun 	struct pcm3060_priv *priv = snd_soc_component_get_drvdata(comp);
114*4882a593Smuzhiyun 	unsigned int rate;
115*4882a593Smuzhiyun 	unsigned int ratio;
116*4882a593Smuzhiyun 	unsigned int reg;
117*4882a593Smuzhiyun 	unsigned int val;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	if (!priv->dai[dai->id].is_master) {
120*4882a593Smuzhiyun 		val = PCM3060_REG_MS_S;
121*4882a593Smuzhiyun 		goto val_ready;
122*4882a593Smuzhiyun 	}
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	rate = params_rate(params);
125*4882a593Smuzhiyun 	if (!rate) {
126*4882a593Smuzhiyun 		dev_err(comp->dev, "rate is not configured\n");
127*4882a593Smuzhiyun 		return -EINVAL;
128*4882a593Smuzhiyun 	}
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	ratio = priv->dai[dai->id].sclk_freq / rate;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	switch (ratio) {
133*4882a593Smuzhiyun 	case 768:
134*4882a593Smuzhiyun 		val = PCM3060_REG_MS_M768;
135*4882a593Smuzhiyun 		break;
136*4882a593Smuzhiyun 	case 512:
137*4882a593Smuzhiyun 		val = PCM3060_REG_MS_M512;
138*4882a593Smuzhiyun 		break;
139*4882a593Smuzhiyun 	case 384:
140*4882a593Smuzhiyun 		val = PCM3060_REG_MS_M384;
141*4882a593Smuzhiyun 		break;
142*4882a593Smuzhiyun 	case 256:
143*4882a593Smuzhiyun 		val = PCM3060_REG_MS_M256;
144*4882a593Smuzhiyun 		break;
145*4882a593Smuzhiyun 	case 192:
146*4882a593Smuzhiyun 		val = PCM3060_REG_MS_M192;
147*4882a593Smuzhiyun 		break;
148*4882a593Smuzhiyun 	case 128:
149*4882a593Smuzhiyun 		val = PCM3060_REG_MS_M128;
150*4882a593Smuzhiyun 		break;
151*4882a593Smuzhiyun 	default:
152*4882a593Smuzhiyun 		dev_err(comp->dev, "unsupported ratio: %d\n", ratio);
153*4882a593Smuzhiyun 		return -EINVAL;
154*4882a593Smuzhiyun 	}
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun val_ready:
157*4882a593Smuzhiyun 	if (dai->id == PCM3060_DAI_ID_DAC)
158*4882a593Smuzhiyun 		reg = PCM3060_REG67;
159*4882a593Smuzhiyun 	else
160*4882a593Smuzhiyun 		reg = PCM3060_REG72;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	regmap_update_bits(priv->regmap, reg, PCM3060_REG_MASK_MS, val);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	return 0;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun static const struct snd_soc_dai_ops pcm3060_dai_ops = {
168*4882a593Smuzhiyun 	.set_sysclk = pcm3060_set_sysclk,
169*4882a593Smuzhiyun 	.set_fmt = pcm3060_set_fmt,
170*4882a593Smuzhiyun 	.hw_params = pcm3060_hw_params,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun #define PCM3060_DAI_RATES_ADC	(SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | \
174*4882a593Smuzhiyun 				 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
175*4882a593Smuzhiyun 				 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun #define PCM3060_DAI_RATES_DAC	(PCM3060_DAI_RATES_ADC | \
178*4882a593Smuzhiyun 				 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun static struct snd_soc_dai_driver pcm3060_dai[] = {
181*4882a593Smuzhiyun 	{
182*4882a593Smuzhiyun 		.name = "pcm3060-dac",
183*4882a593Smuzhiyun 		.id = PCM3060_DAI_ID_DAC,
184*4882a593Smuzhiyun 		.playback = {
185*4882a593Smuzhiyun 			.stream_name = "Playback",
186*4882a593Smuzhiyun 			.channels_min = 2,
187*4882a593Smuzhiyun 			.channels_max = 2,
188*4882a593Smuzhiyun 			.rates = PCM3060_DAI_RATES_DAC,
189*4882a593Smuzhiyun 			.formats = SNDRV_PCM_FMTBIT_S24_LE,
190*4882a593Smuzhiyun 		},
191*4882a593Smuzhiyun 		.ops = &pcm3060_dai_ops,
192*4882a593Smuzhiyun 	},
193*4882a593Smuzhiyun 	{
194*4882a593Smuzhiyun 		.name = "pcm3060-adc",
195*4882a593Smuzhiyun 		.id = PCM3060_DAI_ID_ADC,
196*4882a593Smuzhiyun 		.capture = {
197*4882a593Smuzhiyun 			.stream_name = "Capture",
198*4882a593Smuzhiyun 			.channels_min = 2,
199*4882a593Smuzhiyun 			.channels_max = 2,
200*4882a593Smuzhiyun 			.rates = PCM3060_DAI_RATES_ADC,
201*4882a593Smuzhiyun 			.formats = SNDRV_PCM_FMTBIT_S24_LE,
202*4882a593Smuzhiyun 		},
203*4882a593Smuzhiyun 		.ops = &pcm3060_dai_ops,
204*4882a593Smuzhiyun 	},
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun /* dapm */
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(pcm3060_dapm_tlv, -10050, 50, 1);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun static const struct snd_kcontrol_new pcm3060_dapm_controls[] = {
212*4882a593Smuzhiyun 	SOC_DOUBLE_R_RANGE_TLV("Master Playback Volume",
213*4882a593Smuzhiyun 			       PCM3060_REG65, PCM3060_REG66, 0,
214*4882a593Smuzhiyun 			       PCM3060_REG_AT2_MIN, PCM3060_REG_AT2_MAX,
215*4882a593Smuzhiyun 			       0, pcm3060_dapm_tlv),
216*4882a593Smuzhiyun 	SOC_DOUBLE("Master Playback Switch", PCM3060_REG68,
217*4882a593Smuzhiyun 		   PCM3060_REG_SHIFT_MUT21, PCM3060_REG_SHIFT_MUT22, 1, 1),
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	SOC_DOUBLE_R_RANGE_TLV("Master Capture Volume",
220*4882a593Smuzhiyun 			       PCM3060_REG70, PCM3060_REG71, 0,
221*4882a593Smuzhiyun 			       PCM3060_REG_AT1_MIN, PCM3060_REG_AT1_MAX,
222*4882a593Smuzhiyun 			       0, pcm3060_dapm_tlv),
223*4882a593Smuzhiyun 	SOC_DOUBLE("Master Capture Switch", PCM3060_REG73,
224*4882a593Smuzhiyun 		   PCM3060_REG_SHIFT_MUT11, PCM3060_REG_SHIFT_MUT12, 1, 1),
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun static const struct snd_soc_dapm_widget pcm3060_dapm_widgets[] = {
228*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DAC", "Playback", PCM3060_REG64,
229*4882a593Smuzhiyun 			 PCM3060_REG_SHIFT_DAPSV, 1),
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("OUTL"),
232*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("OUTR"),
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("INL"),
235*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("INR"),
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADC", "Capture", PCM3060_REG64,
238*4882a593Smuzhiyun 			 PCM3060_REG_SHIFT_ADPSV, 1),
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun static const struct snd_soc_dapm_route pcm3060_dapm_map[] = {
242*4882a593Smuzhiyun 	{ "OUTL", NULL, "DAC" },
243*4882a593Smuzhiyun 	{ "OUTR", NULL, "DAC" },
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	{ "ADC", NULL, "INL" },
246*4882a593Smuzhiyun 	{ "ADC", NULL, "INR" },
247*4882a593Smuzhiyun };
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun /* soc component */
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun static const struct snd_soc_component_driver pcm3060_soc_comp_driver = {
252*4882a593Smuzhiyun 	.controls = pcm3060_dapm_controls,
253*4882a593Smuzhiyun 	.num_controls = ARRAY_SIZE(pcm3060_dapm_controls),
254*4882a593Smuzhiyun 	.dapm_widgets = pcm3060_dapm_widgets,
255*4882a593Smuzhiyun 	.num_dapm_widgets = ARRAY_SIZE(pcm3060_dapm_widgets),
256*4882a593Smuzhiyun 	.dapm_routes = pcm3060_dapm_map,
257*4882a593Smuzhiyun 	.num_dapm_routes = ARRAY_SIZE(pcm3060_dapm_map),
258*4882a593Smuzhiyun };
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun /* regmap */
261*4882a593Smuzhiyun 
pcm3060_reg_writeable(struct device * dev,unsigned int reg)262*4882a593Smuzhiyun static bool pcm3060_reg_writeable(struct device *dev, unsigned int reg)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun 	return (reg >= PCM3060_REG64);
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
pcm3060_reg_readable(struct device * dev,unsigned int reg)267*4882a593Smuzhiyun static bool pcm3060_reg_readable(struct device *dev, unsigned int reg)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun 	return (reg >= PCM3060_REG64);
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun 
pcm3060_reg_volatile(struct device * dev,unsigned int reg)272*4882a593Smuzhiyun static bool pcm3060_reg_volatile(struct device *dev, unsigned int reg)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun 	/* PCM3060_REG64 is volatile */
275*4882a593Smuzhiyun 	return (reg == PCM3060_REG64);
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun static const struct reg_default pcm3060_reg_defaults[] = {
279*4882a593Smuzhiyun 	{ PCM3060_REG64,  0xF0 },
280*4882a593Smuzhiyun 	{ PCM3060_REG65,  0xFF },
281*4882a593Smuzhiyun 	{ PCM3060_REG66,  0xFF },
282*4882a593Smuzhiyun 	{ PCM3060_REG67,  0x00 },
283*4882a593Smuzhiyun 	{ PCM3060_REG68,  0x00 },
284*4882a593Smuzhiyun 	{ PCM3060_REG69,  0x00 },
285*4882a593Smuzhiyun 	{ PCM3060_REG70,  0xD7 },
286*4882a593Smuzhiyun 	{ PCM3060_REG71,  0xD7 },
287*4882a593Smuzhiyun 	{ PCM3060_REG72,  0x00 },
288*4882a593Smuzhiyun 	{ PCM3060_REG73,  0x00 },
289*4882a593Smuzhiyun };
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun const struct regmap_config pcm3060_regmap = {
292*4882a593Smuzhiyun 	.reg_bits = 8,
293*4882a593Smuzhiyun 	.val_bits = 8,
294*4882a593Smuzhiyun 	.writeable_reg = pcm3060_reg_writeable,
295*4882a593Smuzhiyun 	.readable_reg = pcm3060_reg_readable,
296*4882a593Smuzhiyun 	.volatile_reg = pcm3060_reg_volatile,
297*4882a593Smuzhiyun 	.max_register = PCM3060_REG73,
298*4882a593Smuzhiyun 	.reg_defaults = pcm3060_reg_defaults,
299*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(pcm3060_reg_defaults),
300*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun EXPORT_SYMBOL(pcm3060_regmap);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun /* device */
305*4882a593Smuzhiyun 
pcm3060_parse_dt(const struct device_node * np,struct pcm3060_priv * priv)306*4882a593Smuzhiyun static void pcm3060_parse_dt(const struct device_node *np,
307*4882a593Smuzhiyun 			     struct pcm3060_priv *priv)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun 	priv->out_se = of_property_read_bool(np, "ti,out-single-ended");
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun 
pcm3060_probe(struct device * dev)312*4882a593Smuzhiyun int pcm3060_probe(struct device *dev)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun 	int rc;
315*4882a593Smuzhiyun 	struct pcm3060_priv *priv = dev_get_drvdata(dev);
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	/* soft reset */
318*4882a593Smuzhiyun 	rc = regmap_update_bits(priv->regmap, PCM3060_REG64,
319*4882a593Smuzhiyun 				PCM3060_REG_MRST, 0);
320*4882a593Smuzhiyun 	if (rc) {
321*4882a593Smuzhiyun 		dev_err(dev, "failed to reset component, rc=%d\n", rc);
322*4882a593Smuzhiyun 		return rc;
323*4882a593Smuzhiyun 	}
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	if (dev->of_node)
326*4882a593Smuzhiyun 		pcm3060_parse_dt(dev->of_node, priv);
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	if (priv->out_se)
329*4882a593Smuzhiyun 		regmap_update_bits(priv->regmap, PCM3060_REG64,
330*4882a593Smuzhiyun 				   PCM3060_REG_SE, PCM3060_REG_SE);
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	rc = devm_snd_soc_register_component(dev, &pcm3060_soc_comp_driver,
333*4882a593Smuzhiyun 					     pcm3060_dai,
334*4882a593Smuzhiyun 					     ARRAY_SIZE(pcm3060_dai));
335*4882a593Smuzhiyun 	if (rc) {
336*4882a593Smuzhiyun 		dev_err(dev, "failed to register component, rc=%d\n", rc);
337*4882a593Smuzhiyun 		return rc;
338*4882a593Smuzhiyun 	}
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	return 0;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun EXPORT_SYMBOL(pcm3060_probe);
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun MODULE_DESCRIPTION("PCM3060 codec driver");
345*4882a593Smuzhiyun MODULE_AUTHOR("Kirill Marinushkin <kmarinushkin@birdec.com>");
346*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
347