1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Texas Instruments PCM186x Universal Audio ADC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com 6*4882a593Smuzhiyun * Andreas Dannenberg <dannenberg@ti.com> 7*4882a593Smuzhiyun * Andrew F. Davis <afd@ti.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _PCM186X_H_ 11*4882a593Smuzhiyun #define _PCM186X_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/pm.h> 14*4882a593Smuzhiyun #include <linux/regmap.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun enum pcm186x_type { 17*4882a593Smuzhiyun PCM1862, 18*4882a593Smuzhiyun PCM1863, 19*4882a593Smuzhiyun PCM1864, 20*4882a593Smuzhiyun PCM1865, 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define PCM186X_RATES SNDRV_PCM_RATE_8000_192000 24*4882a593Smuzhiyun #define PCM186X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 25*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S20_3LE |\ 26*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | \ 27*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PCM186X_PAGE_LEN 0x0100 30*4882a593Smuzhiyun #define PCM186X_PAGE_BASE(n) (PCM186X_PAGE_LEN * n) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* The page selection register address is the same on all pages */ 33*4882a593Smuzhiyun #define PCM186X_PAGE 0 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Register Definitions - Page 0 */ 36*4882a593Smuzhiyun #define PCM186X_PGA_VAL_CH1_L (PCM186X_PAGE_BASE(0) + 1) 37*4882a593Smuzhiyun #define PCM186X_PGA_VAL_CH1_R (PCM186X_PAGE_BASE(0) + 2) 38*4882a593Smuzhiyun #define PCM186X_PGA_VAL_CH2_L (PCM186X_PAGE_BASE(0) + 3) 39*4882a593Smuzhiyun #define PCM186X_PGA_VAL_CH2_R (PCM186X_PAGE_BASE(0) + 4) 40*4882a593Smuzhiyun #define PCM186X_PGA_CTRL (PCM186X_PAGE_BASE(0) + 5) 41*4882a593Smuzhiyun #define PCM186X_ADC1_INPUT_SEL_L (PCM186X_PAGE_BASE(0) + 6) 42*4882a593Smuzhiyun #define PCM186X_ADC1_INPUT_SEL_R (PCM186X_PAGE_BASE(0) + 7) 43*4882a593Smuzhiyun #define PCM186X_ADC2_INPUT_SEL_L (PCM186X_PAGE_BASE(0) + 8) 44*4882a593Smuzhiyun #define PCM186X_ADC2_INPUT_SEL_R (PCM186X_PAGE_BASE(0) + 9) 45*4882a593Smuzhiyun #define PCM186X_AUXADC_INPUT_SEL (PCM186X_PAGE_BASE(0) + 10) 46*4882a593Smuzhiyun #define PCM186X_PCM_CFG (PCM186X_PAGE_BASE(0) + 11) 47*4882a593Smuzhiyun #define PCM186X_TDM_TX_SEL (PCM186X_PAGE_BASE(0) + 12) 48*4882a593Smuzhiyun #define PCM186X_TDM_TX_OFFSET (PCM186X_PAGE_BASE(0) + 13) 49*4882a593Smuzhiyun #define PCM186X_TDM_RX_OFFSET (PCM186X_PAGE_BASE(0) + 14) 50*4882a593Smuzhiyun #define PCM186X_DPGA_VAL_CH1_L (PCM186X_PAGE_BASE(0) + 15) 51*4882a593Smuzhiyun #define PCM186X_GPIO1_0_CTRL (PCM186X_PAGE_BASE(0) + 16) 52*4882a593Smuzhiyun #define PCM186X_GPIO3_2_CTRL (PCM186X_PAGE_BASE(0) + 17) 53*4882a593Smuzhiyun #define PCM186X_GPIO1_0_DIR_CTRL (PCM186X_PAGE_BASE(0) + 18) 54*4882a593Smuzhiyun #define PCM186X_GPIO3_2_DIR_CTRL (PCM186X_PAGE_BASE(0) + 19) 55*4882a593Smuzhiyun #define PCM186X_GPIO_IN_OUT (PCM186X_PAGE_BASE(0) + 20) 56*4882a593Smuzhiyun #define PCM186X_GPIO_PULL_CTRL (PCM186X_PAGE_BASE(0) + 21) 57*4882a593Smuzhiyun #define PCM186X_DPGA_VAL_CH1_R (PCM186X_PAGE_BASE(0) + 22) 58*4882a593Smuzhiyun #define PCM186X_DPGA_VAL_CH2_L (PCM186X_PAGE_BASE(0) + 23) 59*4882a593Smuzhiyun #define PCM186X_DPGA_VAL_CH2_R (PCM186X_PAGE_BASE(0) + 24) 60*4882a593Smuzhiyun #define PCM186X_DPGA_GAIN_CTRL (PCM186X_PAGE_BASE(0) + 25) 61*4882a593Smuzhiyun #define PCM186X_DPGA_MIC_CTRL (PCM186X_PAGE_BASE(0) + 26) 62*4882a593Smuzhiyun #define PCM186X_DIN_RESAMP_CTRL (PCM186X_PAGE_BASE(0) + 27) 63*4882a593Smuzhiyun #define PCM186X_CLK_CTRL (PCM186X_PAGE_BASE(0) + 32) 64*4882a593Smuzhiyun #define PCM186X_DSP1_CLK_DIV (PCM186X_PAGE_BASE(0) + 33) 65*4882a593Smuzhiyun #define PCM186X_DSP2_CLK_DIV (PCM186X_PAGE_BASE(0) + 34) 66*4882a593Smuzhiyun #define PCM186X_ADC_CLK_DIV (PCM186X_PAGE_BASE(0) + 35) 67*4882a593Smuzhiyun #define PCM186X_PLL_SCK_DIV (PCM186X_PAGE_BASE(0) + 37) 68*4882a593Smuzhiyun #define PCM186X_BCK_DIV (PCM186X_PAGE_BASE(0) + 38) 69*4882a593Smuzhiyun #define PCM186X_LRK_DIV (PCM186X_PAGE_BASE(0) + 39) 70*4882a593Smuzhiyun #define PCM186X_PLL_CTRL (PCM186X_PAGE_BASE(0) + 40) 71*4882a593Smuzhiyun #define PCM186X_PLL_P_DIV (PCM186X_PAGE_BASE(0) + 41) 72*4882a593Smuzhiyun #define PCM186X_PLL_R_DIV (PCM186X_PAGE_BASE(0) + 42) 73*4882a593Smuzhiyun #define PCM186X_PLL_J_DIV (PCM186X_PAGE_BASE(0) + 43) 74*4882a593Smuzhiyun #define PCM186X_PLL_D_DIV_LSB (PCM186X_PAGE_BASE(0) + 44) 75*4882a593Smuzhiyun #define PCM186X_PLL_D_DIV_MSB (PCM186X_PAGE_BASE(0) + 45) 76*4882a593Smuzhiyun #define PCM186X_SIGDET_MODE (PCM186X_PAGE_BASE(0) + 48) 77*4882a593Smuzhiyun #define PCM186X_SIGDET_MASK (PCM186X_PAGE_BASE(0) + 49) 78*4882a593Smuzhiyun #define PCM186X_SIGDET_STAT (PCM186X_PAGE_BASE(0) + 50) 79*4882a593Smuzhiyun #define PCM186X_SIGDET_LOSS_TIME (PCM186X_PAGE_BASE(0) + 52) 80*4882a593Smuzhiyun #define PCM186X_SIGDET_SCAN_TIME (PCM186X_PAGE_BASE(0) + 53) 81*4882a593Smuzhiyun #define PCM186X_SIGDET_INT_INTVL (PCM186X_PAGE_BASE(0) + 54) 82*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_REF_CH1_L (PCM186X_PAGE_BASE(0) + 64) 83*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_DIFF_CH1_L (PCM186X_PAGE_BASE(0) + 65) 84*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_LEV_CH1_L (PCM186X_PAGE_BASE(0) + 66) 85*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_REF_CH1_R (PCM186X_PAGE_BASE(0) + 67) 86*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_DIFF_CH1_R (PCM186X_PAGE_BASE(0) + 68) 87*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_LEV_CH1_R (PCM186X_PAGE_BASE(0) + 69) 88*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_REF_CH2_L (PCM186X_PAGE_BASE(0) + 70) 89*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_DIFF_CH2_L (PCM186X_PAGE_BASE(0) + 71) 90*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_LEV_CH2_L (PCM186X_PAGE_BASE(0) + 72) 91*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_REF_CH2_R (PCM186X_PAGE_BASE(0) + 73) 92*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_DIFF_CH2_R (PCM186X_PAGE_BASE(0) + 74) 93*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_LEV_CH2_R (PCM186X_PAGE_BASE(0) + 75) 94*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_REF_CH3_L (PCM186X_PAGE_BASE(0) + 76) 95*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_DIFF_CH3_L (PCM186X_PAGE_BASE(0) + 77) 96*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_LEV_CH3_L (PCM186X_PAGE_BASE(0) + 78) 97*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_REF_CH3_R (PCM186X_PAGE_BASE(0) + 79) 98*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_DIFF_CH3_R (PCM186X_PAGE_BASE(0) + 80) 99*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_LEV_CH3_R (PCM186X_PAGE_BASE(0) + 81) 100*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_REF_CH4_L (PCM186X_PAGE_BASE(0) + 82) 101*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_DIFF_CH4_L (PCM186X_PAGE_BASE(0) + 83) 102*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_LEV_CH4_L (PCM186X_PAGE_BASE(0) + 84) 103*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_REF_CH4_R (PCM186X_PAGE_BASE(0) + 85) 104*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_DIFF_CH4_R (PCM186X_PAGE_BASE(0) + 86) 105*4882a593Smuzhiyun #define PCM186X_SIGDET_DC_LEV_CH4_R (PCM186X_PAGE_BASE(0) + 87) 106*4882a593Smuzhiyun #define PCM186X_AUXADC_DATA_CTRL (PCM186X_PAGE_BASE(0) + 88) 107*4882a593Smuzhiyun #define PCM186X_AUXADC_DATA_LSB (PCM186X_PAGE_BASE(0) + 89) 108*4882a593Smuzhiyun #define PCM186X_AUXADC_DATA_MSB (PCM186X_PAGE_BASE(0) + 90) 109*4882a593Smuzhiyun #define PCM186X_INT_ENABLE (PCM186X_PAGE_BASE(0) + 96) 110*4882a593Smuzhiyun #define PCM186X_INT_FLAG (PCM186X_PAGE_BASE(0) + 97) 111*4882a593Smuzhiyun #define PCM186X_INT_POL_WIDTH (PCM186X_PAGE_BASE(0) + 98) 112*4882a593Smuzhiyun #define PCM186X_POWER_CTRL (PCM186X_PAGE_BASE(0) + 112) 113*4882a593Smuzhiyun #define PCM186X_FILTER_MUTE_CTRL (PCM186X_PAGE_BASE(0) + 113) 114*4882a593Smuzhiyun #define PCM186X_DEVICE_STATUS (PCM186X_PAGE_BASE(0) + 114) 115*4882a593Smuzhiyun #define PCM186X_FSAMPLE_STATUS (PCM186X_PAGE_BASE(0) + 115) 116*4882a593Smuzhiyun #define PCM186X_DIV_STATUS (PCM186X_PAGE_BASE(0) + 116) 117*4882a593Smuzhiyun #define PCM186X_CLK_STATUS (PCM186X_PAGE_BASE(0) + 117) 118*4882a593Smuzhiyun #define PCM186X_SUPPLY_STATUS (PCM186X_PAGE_BASE(0) + 120) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* Register Definitions - Page 1 */ 121*4882a593Smuzhiyun #define PCM186X_MMAP_STAT_CTRL (PCM186X_PAGE_BASE(1) + 1) 122*4882a593Smuzhiyun #define PCM186X_MMAP_ADDRESS (PCM186X_PAGE_BASE(1) + 2) 123*4882a593Smuzhiyun #define PCM186X_MEM_WDATA0 (PCM186X_PAGE_BASE(1) + 4) 124*4882a593Smuzhiyun #define PCM186X_MEM_WDATA1 (PCM186X_PAGE_BASE(1) + 5) 125*4882a593Smuzhiyun #define PCM186X_MEM_WDATA2 (PCM186X_PAGE_BASE(1) + 6) 126*4882a593Smuzhiyun #define PCM186X_MEM_WDATA3 (PCM186X_PAGE_BASE(1) + 7) 127*4882a593Smuzhiyun #define PCM186X_MEM_RDATA0 (PCM186X_PAGE_BASE(1) + 8) 128*4882a593Smuzhiyun #define PCM186X_MEM_RDATA1 (PCM186X_PAGE_BASE(1) + 9) 129*4882a593Smuzhiyun #define PCM186X_MEM_RDATA2 (PCM186X_PAGE_BASE(1) + 10) 130*4882a593Smuzhiyun #define PCM186X_MEM_RDATA3 (PCM186X_PAGE_BASE(1) + 11) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* Register Definitions - Page 3 */ 133*4882a593Smuzhiyun #define PCM186X_OSC_PWR_DOWN_CTRL (PCM186X_PAGE_BASE(3) + 18) 134*4882a593Smuzhiyun #define PCM186X_MIC_BIAS_CTRL (PCM186X_PAGE_BASE(3) + 21) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Register Definitions - Page 253 */ 137*4882a593Smuzhiyun #define PCM186X_CURR_TRIM_CTRL (PCM186X_PAGE_BASE(253) + 20) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define PCM186X_MAX_REGISTER PCM186X_CURR_TRIM_CTRL 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* PCM186X_PAGE */ 142*4882a593Smuzhiyun #define PCM186X_RESET 0xfe 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* PCM186X_ADCX_INPUT_SEL_X */ 145*4882a593Smuzhiyun #define PCM186X_ADC_INPUT_SEL_POL BIT(7) 146*4882a593Smuzhiyun #define PCM186X_ADC_INPUT_SEL_MASK GENMASK(5, 0) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* PCM186X_PCM_CFG */ 149*4882a593Smuzhiyun #define PCM186X_PCM_CFG_RX_WLEN_MASK GENMASK(7, 6) 150*4882a593Smuzhiyun #define PCM186X_PCM_CFG_RX_WLEN_SHIFT 6 151*4882a593Smuzhiyun #define PCM186X_PCM_CFG_RX_WLEN_32 0x00 152*4882a593Smuzhiyun #define PCM186X_PCM_CFG_RX_WLEN_24 0x01 153*4882a593Smuzhiyun #define PCM186X_PCM_CFG_RX_WLEN_20 0x02 154*4882a593Smuzhiyun #define PCM186X_PCM_CFG_RX_WLEN_16 0x03 155*4882a593Smuzhiyun #define PCM186X_PCM_CFG_TDM_LRCK_MODE BIT(4) 156*4882a593Smuzhiyun #define PCM186X_PCM_CFG_TX_WLEN_MASK GENMASK(3, 2) 157*4882a593Smuzhiyun #define PCM186X_PCM_CFG_TX_WLEN_SHIFT 2 158*4882a593Smuzhiyun #define PCM186X_PCM_CFG_TX_WLEN_32 0x00 159*4882a593Smuzhiyun #define PCM186X_PCM_CFG_TX_WLEN_24 0x01 160*4882a593Smuzhiyun #define PCM186X_PCM_CFG_TX_WLEN_20 0x02 161*4882a593Smuzhiyun #define PCM186X_PCM_CFG_TX_WLEN_16 0x03 162*4882a593Smuzhiyun #define PCM186X_PCM_CFG_FMT_MASK GENMASK(1, 0) 163*4882a593Smuzhiyun #define PCM186X_PCM_CFG_FMT_SHIFT 0 164*4882a593Smuzhiyun #define PCM186X_PCM_CFG_FMT_I2S 0x00 165*4882a593Smuzhiyun #define PCM186X_PCM_CFG_FMT_LEFTJ 0x01 166*4882a593Smuzhiyun #define PCM186X_PCM_CFG_FMT_RIGHTJ 0x02 167*4882a593Smuzhiyun #define PCM186X_PCM_CFG_FMT_TDM 0x03 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* PCM186X_TDM_TX_SEL */ 170*4882a593Smuzhiyun #define PCM186X_TDM_TX_SEL_2CH 0x00 171*4882a593Smuzhiyun #define PCM186X_TDM_TX_SEL_4CH 0x01 172*4882a593Smuzhiyun #define PCM186X_TDM_TX_SEL_6CH 0x02 173*4882a593Smuzhiyun #define PCM186X_TDM_TX_SEL_MASK 0x03 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* PCM186X_CLK_CTRL */ 176*4882a593Smuzhiyun #define PCM186X_CLK_CTRL_SCK_XI_SEL1 BIT(7) 177*4882a593Smuzhiyun #define PCM186X_CLK_CTRL_SCK_XI_SEL0 BIT(6) 178*4882a593Smuzhiyun #define PCM186X_CLK_CTRL_SCK_SRC_PLL BIT(5) 179*4882a593Smuzhiyun #define PCM186X_CLK_CTRL_MST_MODE BIT(4) 180*4882a593Smuzhiyun #define PCM186X_CLK_CTRL_ADC_SRC_PLL BIT(3) 181*4882a593Smuzhiyun #define PCM186X_CLK_CTRL_DSP2_SRC_PLL BIT(2) 182*4882a593Smuzhiyun #define PCM186X_CLK_CTRL_DSP1_SRC_PLL BIT(1) 183*4882a593Smuzhiyun #define PCM186X_CLK_CTRL_CLKDET_EN BIT(0) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* PCM186X_PLL_CTRL */ 186*4882a593Smuzhiyun #define PCM186X_PLL_CTRL_LOCK BIT(4) 187*4882a593Smuzhiyun #define PCM186X_PLL_CTRL_REF_SEL BIT(1) 188*4882a593Smuzhiyun #define PCM186X_PLL_CTRL_EN BIT(0) 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun /* PCM186X_POWER_CTRL */ 191*4882a593Smuzhiyun #define PCM186X_PWR_CTRL_PWRDN BIT(2) 192*4882a593Smuzhiyun #define PCM186X_PWR_CTRL_SLEEP BIT(1) 193*4882a593Smuzhiyun #define PCM186X_PWR_CTRL_STBY BIT(0) 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* PCM186X_CLK_STATUS */ 196*4882a593Smuzhiyun #define PCM186X_CLK_STATUS_LRCKHLT BIT(6) 197*4882a593Smuzhiyun #define PCM186X_CLK_STATUS_BCKHLT BIT(5) 198*4882a593Smuzhiyun #define PCM186X_CLK_STATUS_SCKHLT BIT(4) 199*4882a593Smuzhiyun #define PCM186X_CLK_STATUS_LRCKERR BIT(2) 200*4882a593Smuzhiyun #define PCM186X_CLK_STATUS_BCKERR BIT(1) 201*4882a593Smuzhiyun #define PCM186X_CLK_STATUS_SCKERR BIT(0) 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* PCM186X_SUPPLY_STATUS */ 204*4882a593Smuzhiyun #define PCM186X_SUPPLY_STATUS_DVDD BIT(2) 205*4882a593Smuzhiyun #define PCM186X_SUPPLY_STATUS_AVDD BIT(1) 206*4882a593Smuzhiyun #define PCM186X_SUPPLY_STATUS_LDO BIT(0) 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* PCM186X_MMAP_STAT_CTRL */ 209*4882a593Smuzhiyun #define PCM186X_MMAP_STAT_DONE BIT(4) 210*4882a593Smuzhiyun #define PCM186X_MMAP_STAT_BUSY BIT(2) 211*4882a593Smuzhiyun #define PCM186X_MMAP_STAT_R_REQ BIT(1) 212*4882a593Smuzhiyun #define PCM186X_MMAP_STAT_W_REQ BIT(0) 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun extern const struct regmap_config pcm186x_regmap; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun int pcm186x_probe(struct device *dev, enum pcm186x_type type, int irq, 217*4882a593Smuzhiyun struct regmap *regmap); 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun #endif /* _PCM186X_H_ */ 220