1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __SND_SOC_MT6660_H 7*4882a593Smuzhiyun #define __SND_SOC_MT6660_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/mutex.h> 10*4882a593Smuzhiyun #include <linux/regmap.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #pragma pack(push, 1) 13*4882a593Smuzhiyun struct mt6660_platform_data { 14*4882a593Smuzhiyun u8 init_setting_num; 15*4882a593Smuzhiyun u32 *init_setting_addr; 16*4882a593Smuzhiyun u32 *init_setting_mask; 17*4882a593Smuzhiyun u32 *init_setting_val; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct mt6660_chip { 21*4882a593Smuzhiyun struct i2c_client *i2c; 22*4882a593Smuzhiyun struct device *dev; 23*4882a593Smuzhiyun struct platform_device *param_dev; 24*4882a593Smuzhiyun struct mt6660_platform_data plat_data; 25*4882a593Smuzhiyun struct mutex io_lock; 26*4882a593Smuzhiyun struct regmap *regmap; 27*4882a593Smuzhiyun u16 chip_rev; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun #pragma pack(pop) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define MT6660_REG_DEVID (0x00) 32*4882a593Smuzhiyun #define MT6660_REG_SYSTEM_CTRL (0x03) 33*4882a593Smuzhiyun #define MT6660_REG_IRQ_STATUS1 (0x05) 34*4882a593Smuzhiyun #define MT6660_REG_ADDA_CLOCK (0x07) 35*4882a593Smuzhiyun #define MT6660_REG_SERIAL_CFG1 (0x10) 36*4882a593Smuzhiyun #define MT6660_REG_DATAO_SEL (0x12) 37*4882a593Smuzhiyun #define MT6660_REG_TDM_CFG3 (0x15) 38*4882a593Smuzhiyun #define MT6660_REG_HPF_CTRL (0x18) 39*4882a593Smuzhiyun #define MT6660_REG_HPF1_COEF (0x1A) 40*4882a593Smuzhiyun #define MT6660_REG_HPF2_COEF (0x1B) 41*4882a593Smuzhiyun #define MT6660_REG_PATH_BYPASS (0x1E) 42*4882a593Smuzhiyun #define MT6660_REG_WDT_CTRL (0x20) 43*4882a593Smuzhiyun #define MT6660_REG_HCLIP_CTRL (0x24) 44*4882a593Smuzhiyun #define MT6660_REG_VOL_CTRL (0x29) 45*4882a593Smuzhiyun #define MT6660_REG_SPS_CTRL (0x30) 46*4882a593Smuzhiyun #define MT6660_REG_SIGMAX (0x33) 47*4882a593Smuzhiyun #define MT6660_REG_CALI_T0 (0x3F) 48*4882a593Smuzhiyun #define MT6660_REG_BST_CTRL (0x40) 49*4882a593Smuzhiyun #define MT6660_REG_PROTECTION_CFG (0x46) 50*4882a593Smuzhiyun #define MT6660_REG_DA_GAIN (0x4c) 51*4882a593Smuzhiyun #define MT6660_REG_AUDIO_IN2_SEL (0x50) 52*4882a593Smuzhiyun #define MT6660_REG_SIG_GAIN (0x51) 53*4882a593Smuzhiyun #define MT6660_REG_PLL_CFG1 (0x60) 54*4882a593Smuzhiyun #define MT6660_REG_DRE_CTRL (0x68) 55*4882a593Smuzhiyun #define MT6660_REG_DRE_THDMODE (0x69) 56*4882a593Smuzhiyun #define MT6660_REG_DRE_CORASE (0x6B) 57*4882a593Smuzhiyun #define MT6660_REG_PWM_CTRL (0x70) 58*4882a593Smuzhiyun #define MT6660_REG_DC_PROTECT_CTRL (0x74) 59*4882a593Smuzhiyun #define MT6660_REG_ADC_USB_MODE (0x7c) 60*4882a593Smuzhiyun #define MT6660_REG_INTERNAL_CFG (0x88) 61*4882a593Smuzhiyun #define MT6660_REG_RESV0 (0x98) 62*4882a593Smuzhiyun #define MT6660_REG_RESV1 (0x99) 63*4882a593Smuzhiyun #define MT6660_REG_RESV2 (0x9A) 64*4882a593Smuzhiyun #define MT6660_REG_RESV3 (0x9B) 65*4882a593Smuzhiyun #define MT6660_REG_RESV6 (0xA2) 66*4882a593Smuzhiyun #define MT6660_REG_RESV7 (0xA3) 67*4882a593Smuzhiyun #define MT6660_REG_RESV10 (0xB0) 68*4882a593Smuzhiyun #define MT6660_REG_RESV11 (0xB1) 69*4882a593Smuzhiyun #define MT6660_REG_RESV16 (0xB6) 70*4882a593Smuzhiyun #define MT6660_REG_RESV17 (0xB7) 71*4882a593Smuzhiyun #define MT6660_REG_RESV19 (0xB9) 72*4882a593Smuzhiyun #define MT6660_REG_RESV21 (0xBB) 73*4882a593Smuzhiyun #define MT6660_REG_RESV23 (0xBD) 74*4882a593Smuzhiyun #define MT6660_REG_RESV31 (0xD3) 75*4882a593Smuzhiyun #define MT6660_REG_RESV40 (0xE0) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif /* __SND_SOC_MT6660_H */ 78