xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/mt6660.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun 
3*4882a593Smuzhiyun // Copyright (c) 2019 MediaTek Inc.
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include <linux/module.h>
6*4882a593Smuzhiyun #include <linux/kernel.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/i2c.h>
9*4882a593Smuzhiyun #include <linux/pm_runtime.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <sound/soc.h>
12*4882a593Smuzhiyun #include <sound/tlv.h>
13*4882a593Smuzhiyun #include <sound/pcm_params.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include "mt6660.h"
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun struct reg_size_table {
18*4882a593Smuzhiyun 	u32 addr;
19*4882a593Smuzhiyun 	u8 size;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun static const struct reg_size_table mt6660_reg_size_table[] = {
23*4882a593Smuzhiyun 	{ MT6660_REG_HPF1_COEF, 4 },
24*4882a593Smuzhiyun 	{ MT6660_REG_HPF2_COEF, 4 },
25*4882a593Smuzhiyun 	{ MT6660_REG_TDM_CFG3, 2 },
26*4882a593Smuzhiyun 	{ MT6660_REG_RESV17, 2 },
27*4882a593Smuzhiyun 	{ MT6660_REG_RESV23, 2 },
28*4882a593Smuzhiyun 	{ MT6660_REG_SIGMAX, 2 },
29*4882a593Smuzhiyun 	{ MT6660_REG_DEVID, 2 },
30*4882a593Smuzhiyun 	{ MT6660_REG_HCLIP_CTRL, 2 },
31*4882a593Smuzhiyun 	{ MT6660_REG_DA_GAIN, 2 },
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
mt6660_get_reg_size(uint32_t addr)34*4882a593Smuzhiyun static int mt6660_get_reg_size(uint32_t addr)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	int i;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(mt6660_reg_size_table); i++) {
39*4882a593Smuzhiyun 		if (mt6660_reg_size_table[i].addr == addr)
40*4882a593Smuzhiyun 			return mt6660_reg_size_table[i].size;
41*4882a593Smuzhiyun 	}
42*4882a593Smuzhiyun 	return 1;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun 
mt6660_reg_write(void * context,unsigned int reg,unsigned int val)45*4882a593Smuzhiyun static int mt6660_reg_write(void *context, unsigned int reg, unsigned int val)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	struct mt6660_chip *chip = context;
48*4882a593Smuzhiyun 	int size = mt6660_get_reg_size(reg);
49*4882a593Smuzhiyun 	u8 reg_data[4];
50*4882a593Smuzhiyun 	int i, ret;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	for (i = 0; i < size; i++)
53*4882a593Smuzhiyun 		reg_data[size - i - 1] = (val >> (8 * i)) & 0xff;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	ret = i2c_smbus_write_i2c_block_data(chip->i2c, reg, size, reg_data);
56*4882a593Smuzhiyun 	return ret;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
mt6660_reg_read(void * context,unsigned int reg,unsigned int * val)59*4882a593Smuzhiyun static int mt6660_reg_read(void *context, unsigned int reg, unsigned int *val)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	struct mt6660_chip *chip = context;
62*4882a593Smuzhiyun 	int size = mt6660_get_reg_size(reg);
63*4882a593Smuzhiyun 	int i, ret;
64*4882a593Smuzhiyun 	u8 data[4];
65*4882a593Smuzhiyun 	u32 reg_data = 0;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	ret = i2c_smbus_read_i2c_block_data(chip->i2c, reg, size, data);
68*4882a593Smuzhiyun 	if (ret < 0)
69*4882a593Smuzhiyun 		return ret;
70*4882a593Smuzhiyun 	for (i = 0; i < size; i++) {
71*4882a593Smuzhiyun 		reg_data <<= 8;
72*4882a593Smuzhiyun 		reg_data |= data[i];
73*4882a593Smuzhiyun 	}
74*4882a593Smuzhiyun 	*val = reg_data;
75*4882a593Smuzhiyun 	return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun static const struct regmap_config mt6660_regmap_config = {
79*4882a593Smuzhiyun 	.reg_bits = 8,
80*4882a593Smuzhiyun 	.val_bits = 32,
81*4882a593Smuzhiyun 	.reg_write = mt6660_reg_write,
82*4882a593Smuzhiyun 	.reg_read = mt6660_reg_read,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
mt6660_codec_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)85*4882a593Smuzhiyun static int mt6660_codec_dac_event(struct snd_soc_dapm_widget *w,
86*4882a593Smuzhiyun 	struct snd_kcontrol *kcontrol, int event)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	if (event == SND_SOC_DAPM_POST_PMU)
89*4882a593Smuzhiyun 		usleep_range(1000, 1100);
90*4882a593Smuzhiyun 	return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
mt6660_codec_classd_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)93*4882a593Smuzhiyun static int mt6660_codec_classd_event(struct snd_soc_dapm_widget *w,
94*4882a593Smuzhiyun 	struct snd_kcontrol *kcontrol, int event)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun 	struct snd_soc_component *component =
97*4882a593Smuzhiyun 		snd_soc_dapm_to_component(w->dapm);
98*4882a593Smuzhiyun 	int ret;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	switch (event) {
101*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMU:
102*4882a593Smuzhiyun 		dev_dbg(component->dev,
103*4882a593Smuzhiyun 			"%s: before classd turn on\n", __func__);
104*4882a593Smuzhiyun 		/* config to adaptive mode */
105*4882a593Smuzhiyun 		ret = snd_soc_component_update_bits(component,
106*4882a593Smuzhiyun 			MT6660_REG_BST_CTRL, 0x03, 0x03);
107*4882a593Smuzhiyun 		if (ret < 0) {
108*4882a593Smuzhiyun 			dev_err(component->dev, "config mode adaptive fail\n");
109*4882a593Smuzhiyun 			return ret;
110*4882a593Smuzhiyun 		}
111*4882a593Smuzhiyun 		break;
112*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMU:
113*4882a593Smuzhiyun 		/* voltage sensing enable */
114*4882a593Smuzhiyun 		ret = snd_soc_component_update_bits(component,
115*4882a593Smuzhiyun 			MT6660_REG_RESV7, 0x04, 0x04);
116*4882a593Smuzhiyun 		if (ret < 0) {
117*4882a593Smuzhiyun 			dev_err(component->dev,
118*4882a593Smuzhiyun 				"enable voltage sensing fail\n");
119*4882a593Smuzhiyun 			return ret;
120*4882a593Smuzhiyun 		}
121*4882a593Smuzhiyun 		dev_dbg(component->dev, "Amp on\n");
122*4882a593Smuzhiyun 		break;
123*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMD:
124*4882a593Smuzhiyun 		dev_dbg(component->dev, "Amp off\n");
125*4882a593Smuzhiyun 		/* voltage sensing disable */
126*4882a593Smuzhiyun 		ret = snd_soc_component_update_bits(component,
127*4882a593Smuzhiyun 			MT6660_REG_RESV7, 0x04, 0x00);
128*4882a593Smuzhiyun 		if (ret < 0) {
129*4882a593Smuzhiyun 			dev_err(component->dev,
130*4882a593Smuzhiyun 				"disable voltage sensing fail\n");
131*4882a593Smuzhiyun 			return ret;
132*4882a593Smuzhiyun 		}
133*4882a593Smuzhiyun 		/* pop-noise improvement 1 */
134*4882a593Smuzhiyun 		ret = snd_soc_component_update_bits(component,
135*4882a593Smuzhiyun 			MT6660_REG_RESV10, 0x10, 0x10);
136*4882a593Smuzhiyun 		if (ret < 0) {
137*4882a593Smuzhiyun 			dev_err(component->dev,
138*4882a593Smuzhiyun 				"pop-noise improvement 1 fail\n");
139*4882a593Smuzhiyun 			return ret;
140*4882a593Smuzhiyun 		}
141*4882a593Smuzhiyun 		break;
142*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:
143*4882a593Smuzhiyun 		dev_dbg(component->dev,
144*4882a593Smuzhiyun 			"%s: after classd turn off\n", __func__);
145*4882a593Smuzhiyun 		/* pop-noise improvement 2 */
146*4882a593Smuzhiyun 		ret = snd_soc_component_update_bits(component,
147*4882a593Smuzhiyun 			MT6660_REG_RESV10, 0x10, 0x00);
148*4882a593Smuzhiyun 		if (ret < 0) {
149*4882a593Smuzhiyun 			dev_err(component->dev,
150*4882a593Smuzhiyun 				"pop-noise improvement 2 fail\n");
151*4882a593Smuzhiyun 			return ret;
152*4882a593Smuzhiyun 		}
153*4882a593Smuzhiyun 		/* config to off mode */
154*4882a593Smuzhiyun 		ret = snd_soc_component_update_bits(component,
155*4882a593Smuzhiyun 			MT6660_REG_BST_CTRL, 0x03, 0x00);
156*4882a593Smuzhiyun 		if (ret < 0) {
157*4882a593Smuzhiyun 			dev_err(component->dev, "config mode off fail\n");
158*4882a593Smuzhiyun 			return ret;
159*4882a593Smuzhiyun 		}
160*4882a593Smuzhiyun 		break;
161*4882a593Smuzhiyun 	}
162*4882a593Smuzhiyun 	return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun static const struct snd_soc_dapm_widget mt6660_component_dapm_widgets[] = {
166*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC_E("DAC", NULL, MT6660_REG_PLL_CFG1,
167*4882a593Smuzhiyun 		0, 1, mt6660_codec_dac_event, SND_SOC_DAPM_POST_PMU),
168*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("VI ADC", NULL, SND_SOC_NOPM, 0, 0),
169*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
170*4882a593Smuzhiyun 	SND_SOC_DAPM_OUT_DRV_E("ClassD", MT6660_REG_SYSTEM_CTRL, 2, 0,
171*4882a593Smuzhiyun 			       NULL, 0, mt6660_codec_classd_event,
172*4882a593Smuzhiyun 			       SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
173*4882a593Smuzhiyun 			       SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
174*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("OUTP"),
175*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("OUTN"),
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun static const struct snd_soc_dapm_route mt6660_component_dapm_routes[] = {
179*4882a593Smuzhiyun 	{ "DAC", NULL, "aif_playback" },
180*4882a593Smuzhiyun 	{ "PGA", NULL, "DAC" },
181*4882a593Smuzhiyun 	{ "ClassD", NULL, "PGA" },
182*4882a593Smuzhiyun 	{ "OUTP", NULL, "ClassD" },
183*4882a593Smuzhiyun 	{ "OUTN", NULL, "ClassD" },
184*4882a593Smuzhiyun 	{ "VI ADC", NULL, "ClassD" },
185*4882a593Smuzhiyun 	{ "aif_capture", NULL, "VI ADC" },
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun 
mt6660_component_get_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)188*4882a593Smuzhiyun static int mt6660_component_get_volsw(struct snd_kcontrol *kcontrol,
189*4882a593Smuzhiyun 				  struct snd_ctl_elem_value *ucontrol)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun 	struct snd_soc_component *component =
192*4882a593Smuzhiyun 		snd_soc_kcontrol_component(kcontrol);
193*4882a593Smuzhiyun 	struct mt6660_chip *chip = (struct mt6660_chip *)
194*4882a593Smuzhiyun 		snd_soc_component_get_drvdata(component);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = chip->chip_rev & 0x0f;
197*4882a593Smuzhiyun 	return 0;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(vol_ctl_tlv, -1155, 5, 0);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static const struct snd_kcontrol_new mt6660_component_snd_controls[] = {
203*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Digital Volume", MT6660_REG_VOL_CTRL, 0, 255,
204*4882a593Smuzhiyun 			   1, vol_ctl_tlv),
205*4882a593Smuzhiyun 	SOC_SINGLE("Hard Clip Switch", MT6660_REG_HCLIP_CTRL, 8, 1, 0),
206*4882a593Smuzhiyun 	SOC_SINGLE("Clip Switch", MT6660_REG_SPS_CTRL, 0, 1, 0),
207*4882a593Smuzhiyun 	SOC_SINGLE("Boost Mode", MT6660_REG_BST_CTRL, 0, 3, 0),
208*4882a593Smuzhiyun 	SOC_SINGLE("DRE Switch", MT6660_REG_DRE_CTRL, 0, 1, 0),
209*4882a593Smuzhiyun 	SOC_SINGLE("DC Protect Switch",	MT6660_REG_DC_PROTECT_CTRL, 3, 1, 0),
210*4882a593Smuzhiyun 	SOC_SINGLE("Data Output Left Channel Selection",
211*4882a593Smuzhiyun 		   MT6660_REG_DATAO_SEL, 3, 7, 0),
212*4882a593Smuzhiyun 	SOC_SINGLE("Data Output Right Channel Selection",
213*4882a593Smuzhiyun 		   MT6660_REG_DATAO_SEL, 0, 7, 0),
214*4882a593Smuzhiyun 	SOC_SINGLE_EXT("T0 SEL", MT6660_REG_CALI_T0, 0, 7, 0,
215*4882a593Smuzhiyun 		       snd_soc_get_volsw, NULL),
216*4882a593Smuzhiyun 	SOC_SINGLE_EXT("Chip Rev", MT6660_REG_DEVID, 8, 15, 0,
217*4882a593Smuzhiyun 		       mt6660_component_get_volsw, NULL),
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun 
_mt6660_chip_power_on(struct mt6660_chip * chip,int on_off)220*4882a593Smuzhiyun static int _mt6660_chip_power_on(struct mt6660_chip *chip, int on_off)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	return regmap_write_bits(chip->regmap, MT6660_REG_SYSTEM_CTRL,
223*4882a593Smuzhiyun 				 0x01, on_off ? 0x00 : 0x01);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun struct reg_table {
227*4882a593Smuzhiyun 	uint32_t addr;
228*4882a593Smuzhiyun 	uint32_t mask;
229*4882a593Smuzhiyun 	uint32_t val;
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun static const struct reg_table mt6660_setting_table[] = {
233*4882a593Smuzhiyun 	{ 0x20, 0x80, 0x00 },
234*4882a593Smuzhiyun 	{ 0x30, 0x01, 0x00 },
235*4882a593Smuzhiyun 	{ 0x50, 0x1c, 0x04 },
236*4882a593Smuzhiyun 	{ 0xB1, 0x0c, 0x00 },
237*4882a593Smuzhiyun 	{ 0xD3, 0x03, 0x03 },
238*4882a593Smuzhiyun 	{ 0xE0, 0x01, 0x00 },
239*4882a593Smuzhiyun 	{ 0x98, 0x44, 0x04 },
240*4882a593Smuzhiyun 	{ 0xB9, 0xff, 0x82 },
241*4882a593Smuzhiyun 	{ 0xB7, 0x7777, 0x7273 },
242*4882a593Smuzhiyun 	{ 0xB6, 0x07, 0x03 },
243*4882a593Smuzhiyun 	{ 0x6B, 0xe0, 0x20 },
244*4882a593Smuzhiyun 	{ 0x07, 0xff, 0x70 },
245*4882a593Smuzhiyun 	{ 0xBB, 0xff, 0x20 },
246*4882a593Smuzhiyun 	{ 0x69, 0xff, 0x40 },
247*4882a593Smuzhiyun 	{ 0xBD, 0xffff, 0x17f8 },
248*4882a593Smuzhiyun 	{ 0x70, 0xff, 0x15 },
249*4882a593Smuzhiyun 	{ 0x7C, 0xff, 0x00 },
250*4882a593Smuzhiyun 	{ 0x46, 0xff, 0x1d },
251*4882a593Smuzhiyun 	{ 0x1A, 0xffffffff, 0x7fdb7ffe },
252*4882a593Smuzhiyun 	{ 0x1B, 0xffffffff, 0x7fdb7ffe },
253*4882a593Smuzhiyun 	{ 0x51, 0xff, 0x58 },
254*4882a593Smuzhiyun 	{ 0xA2, 0xff, 0xce },
255*4882a593Smuzhiyun 	{ 0x33, 0xffff, 0x7fff },
256*4882a593Smuzhiyun 	{ 0x4C, 0xffff, 0x0116 },
257*4882a593Smuzhiyun 	{ 0x16, 0x1800, 0x0800 },
258*4882a593Smuzhiyun 	{ 0x68, 0x1f, 0x07 },
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun 
mt6660_component_setting(struct snd_soc_component * component)261*4882a593Smuzhiyun static int mt6660_component_setting(struct snd_soc_component *component)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun 	struct mt6660_chip *chip = snd_soc_component_get_drvdata(component);
264*4882a593Smuzhiyun 	int ret = 0;
265*4882a593Smuzhiyun 	size_t i = 0;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	ret = _mt6660_chip_power_on(chip, 1);
268*4882a593Smuzhiyun 	if (ret < 0) {
269*4882a593Smuzhiyun 		dev_err(component->dev, "%s chip power on failed\n", __func__);
270*4882a593Smuzhiyun 		return ret;
271*4882a593Smuzhiyun 	}
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(mt6660_setting_table); i++) {
274*4882a593Smuzhiyun 		ret = snd_soc_component_update_bits(component,
275*4882a593Smuzhiyun 				mt6660_setting_table[i].addr,
276*4882a593Smuzhiyun 				mt6660_setting_table[i].mask,
277*4882a593Smuzhiyun 				mt6660_setting_table[i].val);
278*4882a593Smuzhiyun 		if (ret < 0) {
279*4882a593Smuzhiyun 			dev_err(component->dev, "%s update 0x%02x failed\n",
280*4882a593Smuzhiyun 				__func__, mt6660_setting_table[i].addr);
281*4882a593Smuzhiyun 			return ret;
282*4882a593Smuzhiyun 		}
283*4882a593Smuzhiyun 	}
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	ret = _mt6660_chip_power_on(chip, 0);
286*4882a593Smuzhiyun 	if (ret < 0) {
287*4882a593Smuzhiyun 		dev_err(component->dev, "%s chip power off failed\n", __func__);
288*4882a593Smuzhiyun 		return ret;
289*4882a593Smuzhiyun 	}
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	return 0;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun 
mt6660_component_probe(struct snd_soc_component * component)294*4882a593Smuzhiyun static int mt6660_component_probe(struct snd_soc_component *component)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun 	struct mt6660_chip *chip = snd_soc_component_get_drvdata(component);
297*4882a593Smuzhiyun 	int ret;
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	dev_dbg(component->dev, "%s\n", __func__);
300*4882a593Smuzhiyun 	snd_soc_component_init_regmap(component, chip->regmap);
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	ret = mt6660_component_setting(component);
303*4882a593Smuzhiyun 	if (ret < 0)
304*4882a593Smuzhiyun 		dev_err(chip->dev, "mt6660 component setting failed\n");
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	return ret;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun 
mt6660_component_remove(struct snd_soc_component * component)309*4882a593Smuzhiyun static void mt6660_component_remove(struct snd_soc_component *component)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun 	dev_dbg(component->dev, "%s\n", __func__);
312*4882a593Smuzhiyun 	snd_soc_component_exit_regmap(component);
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun static const struct snd_soc_component_driver mt6660_component_driver = {
316*4882a593Smuzhiyun 	.probe = mt6660_component_probe,
317*4882a593Smuzhiyun 	.remove = mt6660_component_remove,
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	.controls = mt6660_component_snd_controls,
320*4882a593Smuzhiyun 	.num_controls = ARRAY_SIZE(mt6660_component_snd_controls),
321*4882a593Smuzhiyun 	.dapm_widgets = mt6660_component_dapm_widgets,
322*4882a593Smuzhiyun 	.num_dapm_widgets = ARRAY_SIZE(mt6660_component_dapm_widgets),
323*4882a593Smuzhiyun 	.dapm_routes = mt6660_component_dapm_routes,
324*4882a593Smuzhiyun 	.num_dapm_routes = ARRAY_SIZE(mt6660_component_dapm_routes),
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	.idle_bias_on = false, /* idle_bias_off = true */
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun 
mt6660_component_aif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params,struct snd_soc_dai * dai)329*4882a593Smuzhiyun static int mt6660_component_aif_hw_params(struct snd_pcm_substream *substream,
330*4882a593Smuzhiyun 	struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *dai)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun 	int word_len = params_physical_width(hw_params);
333*4882a593Smuzhiyun 	int aud_bit = params_width(hw_params);
334*4882a593Smuzhiyun 	u16 reg_data = 0;
335*4882a593Smuzhiyun 	int ret;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	dev_dbg(dai->dev, "%s: ++\n", __func__);
338*4882a593Smuzhiyun 	dev_dbg(dai->dev, "format: 0x%08x\n", params_format(hw_params));
339*4882a593Smuzhiyun 	dev_dbg(dai->dev, "rate: 0x%08x\n", params_rate(hw_params));
340*4882a593Smuzhiyun 	dev_dbg(dai->dev, "word_len: %d, aud_bit: %d\n", word_len, aud_bit);
341*4882a593Smuzhiyun 	if (word_len > 32 || word_len < 16) {
342*4882a593Smuzhiyun 		dev_err(dai->dev, "not supported word length\n");
343*4882a593Smuzhiyun 		return -ENOTSUPP;
344*4882a593Smuzhiyun 	}
345*4882a593Smuzhiyun 	switch (aud_bit) {
346*4882a593Smuzhiyun 	case 16:
347*4882a593Smuzhiyun 		reg_data = 3;
348*4882a593Smuzhiyun 		break;
349*4882a593Smuzhiyun 	case 18:
350*4882a593Smuzhiyun 		reg_data = 2;
351*4882a593Smuzhiyun 		break;
352*4882a593Smuzhiyun 	case 20:
353*4882a593Smuzhiyun 		reg_data = 1;
354*4882a593Smuzhiyun 		break;
355*4882a593Smuzhiyun 	case 24:
356*4882a593Smuzhiyun 	case 32:
357*4882a593Smuzhiyun 		reg_data = 0;
358*4882a593Smuzhiyun 		break;
359*4882a593Smuzhiyun 	default:
360*4882a593Smuzhiyun 		return -ENOTSUPP;
361*4882a593Smuzhiyun 	}
362*4882a593Smuzhiyun 	ret = snd_soc_component_update_bits(dai->component,
363*4882a593Smuzhiyun 		MT6660_REG_SERIAL_CFG1, 0xc0, (reg_data << 6));
364*4882a593Smuzhiyun 	if (ret < 0) {
365*4882a593Smuzhiyun 		dev_err(dai->dev, "config aud bit fail\n");
366*4882a593Smuzhiyun 		return ret;
367*4882a593Smuzhiyun 	}
368*4882a593Smuzhiyun 	ret = snd_soc_component_update_bits(dai->component,
369*4882a593Smuzhiyun 		MT6660_REG_TDM_CFG3, 0x3f0, word_len << 4);
370*4882a593Smuzhiyun 	if (ret < 0) {
371*4882a593Smuzhiyun 		dev_err(dai->dev, "config word len fail\n");
372*4882a593Smuzhiyun 		return ret;
373*4882a593Smuzhiyun 	}
374*4882a593Smuzhiyun 	dev_dbg(dai->dev, "%s: --\n", __func__);
375*4882a593Smuzhiyun 	return 0;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun static const struct snd_soc_dai_ops mt6660_component_aif_ops = {
379*4882a593Smuzhiyun 	.hw_params = mt6660_component_aif_hw_params,
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun #define STUB_RATES	SNDRV_PCM_RATE_8000_192000
383*4882a593Smuzhiyun #define STUB_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE | \
384*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_U16_LE | \
385*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S24_LE | \
386*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_U24_LE | \
387*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S32_LE | \
388*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_U32_LE)
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun static struct snd_soc_dai_driver mt6660_codec_dai = {
391*4882a593Smuzhiyun 	.name = "mt6660-aif",
392*4882a593Smuzhiyun 	.playback = {
393*4882a593Smuzhiyun 		.stream_name	= "aif_playback",
394*4882a593Smuzhiyun 		.channels_min	= 1,
395*4882a593Smuzhiyun 		.channels_max	= 2,
396*4882a593Smuzhiyun 		.rates		= STUB_RATES,
397*4882a593Smuzhiyun 		.formats	= STUB_FORMATS,
398*4882a593Smuzhiyun 	},
399*4882a593Smuzhiyun 	.capture = {
400*4882a593Smuzhiyun 		.stream_name	= "aif_capture",
401*4882a593Smuzhiyun 		.channels_min	= 1,
402*4882a593Smuzhiyun 		.channels_max	= 2,
403*4882a593Smuzhiyun 		.rates = STUB_RATES,
404*4882a593Smuzhiyun 		.formats = STUB_FORMATS,
405*4882a593Smuzhiyun 	},
406*4882a593Smuzhiyun 	/* dai properties */
407*4882a593Smuzhiyun 	.symmetric_rates = 1,
408*4882a593Smuzhiyun 	.symmetric_channels = 1,
409*4882a593Smuzhiyun 	.symmetric_samplebits = 1,
410*4882a593Smuzhiyun 	/* dai operations */
411*4882a593Smuzhiyun 	.ops = &mt6660_component_aif_ops,
412*4882a593Smuzhiyun };
413*4882a593Smuzhiyun 
_mt6660_chip_id_check(struct mt6660_chip * chip)414*4882a593Smuzhiyun static int _mt6660_chip_id_check(struct mt6660_chip *chip)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun 	int ret;
417*4882a593Smuzhiyun 	unsigned int val;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	ret = regmap_read(chip->regmap, MT6660_REG_DEVID, &val);
420*4882a593Smuzhiyun 	if (ret < 0)
421*4882a593Smuzhiyun 		return ret;
422*4882a593Smuzhiyun 	val &= 0x0ff0;
423*4882a593Smuzhiyun 	if (val != 0x00e0 && val != 0x01e0) {
424*4882a593Smuzhiyun 		dev_err(chip->dev, "%s id(%x) not match\n", __func__, val);
425*4882a593Smuzhiyun 		return -ENODEV;
426*4882a593Smuzhiyun 	}
427*4882a593Smuzhiyun 	return 0;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun 
_mt6660_chip_sw_reset(struct mt6660_chip * chip)430*4882a593Smuzhiyun static int _mt6660_chip_sw_reset(struct mt6660_chip *chip)
431*4882a593Smuzhiyun {
432*4882a593Smuzhiyun 	int ret;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	/* turn on main pll first, then trigger reset */
435*4882a593Smuzhiyun 	ret = regmap_write(chip->regmap, MT6660_REG_SYSTEM_CTRL, 0x00);
436*4882a593Smuzhiyun 	if (ret < 0)
437*4882a593Smuzhiyun 		return ret;
438*4882a593Smuzhiyun 	ret = regmap_write(chip->regmap, MT6660_REG_SYSTEM_CTRL, 0x80);
439*4882a593Smuzhiyun 	if (ret < 0)
440*4882a593Smuzhiyun 		return ret;
441*4882a593Smuzhiyun 	msleep(30);
442*4882a593Smuzhiyun 	return 0;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun 
_mt6660_read_chip_revision(struct mt6660_chip * chip)445*4882a593Smuzhiyun static int _mt6660_read_chip_revision(struct mt6660_chip *chip)
446*4882a593Smuzhiyun {
447*4882a593Smuzhiyun 	int ret;
448*4882a593Smuzhiyun 	unsigned int val;
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	ret = regmap_read(chip->regmap, MT6660_REG_DEVID, &val);
451*4882a593Smuzhiyun 	if (ret < 0) {
452*4882a593Smuzhiyun 		dev_err(chip->dev, "get chip revision fail\n");
453*4882a593Smuzhiyun 		return ret;
454*4882a593Smuzhiyun 	}
455*4882a593Smuzhiyun 	chip->chip_rev = val&0xff;
456*4882a593Smuzhiyun 	dev_info(chip->dev, "%s chip_rev = %x\n", __func__, chip->chip_rev);
457*4882a593Smuzhiyun 	return 0;
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun 
mt6660_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)460*4882a593Smuzhiyun static int mt6660_i2c_probe(struct i2c_client *client,
461*4882a593Smuzhiyun 			    const struct i2c_device_id *id)
462*4882a593Smuzhiyun {
463*4882a593Smuzhiyun 	struct mt6660_chip *chip = NULL;
464*4882a593Smuzhiyun 	int ret;
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	dev_dbg(&client->dev, "%s\n", __func__);
467*4882a593Smuzhiyun 	chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
468*4882a593Smuzhiyun 	if (!chip)
469*4882a593Smuzhiyun 		return -ENOMEM;
470*4882a593Smuzhiyun 	chip->i2c = client;
471*4882a593Smuzhiyun 	chip->dev = &client->dev;
472*4882a593Smuzhiyun 	mutex_init(&chip->io_lock);
473*4882a593Smuzhiyun 	i2c_set_clientdata(client, chip);
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	chip->regmap = devm_regmap_init(&client->dev,
476*4882a593Smuzhiyun 		NULL, chip, &mt6660_regmap_config);
477*4882a593Smuzhiyun 	if (IS_ERR(chip->regmap)) {
478*4882a593Smuzhiyun 		ret = PTR_ERR(chip->regmap);
479*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to initialise regmap: %d\n", ret);
480*4882a593Smuzhiyun 		return ret;
481*4882a593Smuzhiyun 	}
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	/* chip reset first */
484*4882a593Smuzhiyun 	ret = _mt6660_chip_sw_reset(chip);
485*4882a593Smuzhiyun 	if (ret < 0) {
486*4882a593Smuzhiyun 		dev_err(chip->dev, "chip reset fail\n");
487*4882a593Smuzhiyun 		goto probe_fail;
488*4882a593Smuzhiyun 	}
489*4882a593Smuzhiyun 	/* chip power on */
490*4882a593Smuzhiyun 	ret = _mt6660_chip_power_on(chip, 1);
491*4882a593Smuzhiyun 	if (ret < 0) {
492*4882a593Smuzhiyun 		dev_err(chip->dev, "chip power on 2 fail\n");
493*4882a593Smuzhiyun 		goto probe_fail;
494*4882a593Smuzhiyun 	}
495*4882a593Smuzhiyun 	/* chip devid check */
496*4882a593Smuzhiyun 	ret = _mt6660_chip_id_check(chip);
497*4882a593Smuzhiyun 	if (ret < 0) {
498*4882a593Smuzhiyun 		dev_err(chip->dev, "chip id check fail\n");
499*4882a593Smuzhiyun 		goto probe_fail;
500*4882a593Smuzhiyun 	}
501*4882a593Smuzhiyun 	/* chip revision get */
502*4882a593Smuzhiyun 	ret = _mt6660_read_chip_revision(chip);
503*4882a593Smuzhiyun 	if (ret < 0) {
504*4882a593Smuzhiyun 		dev_err(chip->dev, "read chip revision fail\n");
505*4882a593Smuzhiyun 		goto probe_fail;
506*4882a593Smuzhiyun 	}
507*4882a593Smuzhiyun 	pm_runtime_set_active(chip->dev);
508*4882a593Smuzhiyun 	pm_runtime_enable(chip->dev);
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(chip->dev,
511*4882a593Smuzhiyun 					       &mt6660_component_driver,
512*4882a593Smuzhiyun 					       &mt6660_codec_dai, 1);
513*4882a593Smuzhiyun 	if (ret)
514*4882a593Smuzhiyun 		pm_runtime_disable(chip->dev);
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	return ret;
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun probe_fail:
519*4882a593Smuzhiyun 	_mt6660_chip_power_on(chip, 0);
520*4882a593Smuzhiyun 	mutex_destroy(&chip->io_lock);
521*4882a593Smuzhiyun 	return ret;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun 
mt6660_i2c_remove(struct i2c_client * client)524*4882a593Smuzhiyun static int mt6660_i2c_remove(struct i2c_client *client)
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun 	struct mt6660_chip *chip = i2c_get_clientdata(client);
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun 	pm_runtime_disable(chip->dev);
529*4882a593Smuzhiyun 	pm_runtime_set_suspended(chip->dev);
530*4882a593Smuzhiyun 	mutex_destroy(&chip->io_lock);
531*4882a593Smuzhiyun 	return 0;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun 
mt6660_i2c_runtime_suspend(struct device * dev)534*4882a593Smuzhiyun static int __maybe_unused mt6660_i2c_runtime_suspend(struct device *dev)
535*4882a593Smuzhiyun {
536*4882a593Smuzhiyun 	struct mt6660_chip *chip = dev_get_drvdata(dev);
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	dev_dbg(dev, "enter low power mode\n");
539*4882a593Smuzhiyun 	return regmap_update_bits(chip->regmap,
540*4882a593Smuzhiyun 		MT6660_REG_SYSTEM_CTRL, 0x01, 0x01);
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun 
mt6660_i2c_runtime_resume(struct device * dev)543*4882a593Smuzhiyun static int __maybe_unused mt6660_i2c_runtime_resume(struct device *dev)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun 	struct mt6660_chip *chip = dev_get_drvdata(dev);
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 	dev_dbg(dev, "exit low power mode\n");
548*4882a593Smuzhiyun 	return regmap_update_bits(chip->regmap,
549*4882a593Smuzhiyun 		MT6660_REG_SYSTEM_CTRL, 0x01, 0x00);
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun static const struct dev_pm_ops mt6660_dev_pm_ops = {
553*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(mt6660_i2c_runtime_suspend,
554*4882a593Smuzhiyun 			   mt6660_i2c_runtime_resume, NULL)
555*4882a593Smuzhiyun };
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun static const struct of_device_id __maybe_unused mt6660_of_id[] = {
558*4882a593Smuzhiyun 	{ .compatible = "mediatek,mt6660",},
559*4882a593Smuzhiyun 	{},
560*4882a593Smuzhiyun };
561*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mt6660_of_id);
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun static const struct i2c_device_id mt6660_i2c_id[] = {
564*4882a593Smuzhiyun 	{"mt6660", 0 },
565*4882a593Smuzhiyun 	{},
566*4882a593Smuzhiyun };
567*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mt6660_i2c_id);
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun static struct i2c_driver mt6660_i2c_driver = {
570*4882a593Smuzhiyun 	.driver = {
571*4882a593Smuzhiyun 		.name = "mt6660",
572*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(mt6660_of_id),
573*4882a593Smuzhiyun 		.pm = &mt6660_dev_pm_ops,
574*4882a593Smuzhiyun 	},
575*4882a593Smuzhiyun 	.probe = mt6660_i2c_probe,
576*4882a593Smuzhiyun 	.remove = mt6660_i2c_remove,
577*4882a593Smuzhiyun 	.id_table = mt6660_i2c_id,
578*4882a593Smuzhiyun };
579*4882a593Smuzhiyun module_i2c_driver(mt6660_i2c_driver);
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun MODULE_AUTHOR("Jeff Chang <jeff_chang@richtek.com>");
582*4882a593Smuzhiyun MODULE_DESCRIPTION("MT6660 SPKAMP Driver");
583*4882a593Smuzhiyun MODULE_LICENSE("GPL");
584*4882a593Smuzhiyun MODULE_VERSION("1.0.8_G");
585