1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mt6351.h -- mt6351 ALSA SoC audio codec driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 6*4882a593Smuzhiyun * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MT6351_H__ 10*4882a593Smuzhiyun #define __MT6351_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000) 13*4882a593Smuzhiyun #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002) 14*4882a593Smuzhiyun #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004) 15*4882a593Smuzhiyun #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006) 16*4882a593Smuzhiyun #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008) 17*4882a593Smuzhiyun #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a) 18*4882a593Smuzhiyun #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c) 19*4882a593Smuzhiyun #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e) 20*4882a593Smuzhiyun #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010) 21*4882a593Smuzhiyun #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012) 22*4882a593Smuzhiyun #define MT6351_AUDIO_TOP_CON0 (0x2000 + 0x0014) 23*4882a593Smuzhiyun #define MT6351_AFE_DL_SRC_MON0 (0x2000 + 0x0016) 24*4882a593Smuzhiyun #define MT6351_AFE_DL_SDM_TEST0 (0x2000 + 0x0018) 25*4882a593Smuzhiyun #define MT6351_AFE_MON_DEBUG0 (0x2000 + 0x001a) 26*4882a593Smuzhiyun #define MT6351_AFUNC_AUD_CON0 (0x2000 + 0x001c) 27*4882a593Smuzhiyun #define MT6351_AFUNC_AUD_CON1 (0x2000 + 0x001e) 28*4882a593Smuzhiyun #define MT6351_AFUNC_AUD_CON2 (0x2000 + 0x0020) 29*4882a593Smuzhiyun #define MT6351_AFUNC_AUD_CON3 (0x2000 + 0x0022) 30*4882a593Smuzhiyun #define MT6351_AFUNC_AUD_CON4 (0x2000 + 0x0024) 31*4882a593Smuzhiyun #define MT6351_AFUNC_AUD_MON0 (0x2000 + 0x0026) 32*4882a593Smuzhiyun #define MT6351_AFUNC_AUD_MON1 (0x2000 + 0x0028) 33*4882a593Smuzhiyun #define MT6351_AFE_UP8X_FIFO_CFG0 (0x2000 + 0x002c) 34*4882a593Smuzhiyun #define MT6351_AFE_UP8X_FIFO_LOG_MON0 (0x2000 + 0x002e) 35*4882a593Smuzhiyun #define MT6351_AFE_UP8X_FIFO_LOG_MON1 (0x2000 + 0x0030) 36*4882a593Smuzhiyun #define MT6351_AFE_DL_DC_COMP_CFG0 (0x2000 + 0x0032) 37*4882a593Smuzhiyun #define MT6351_AFE_DL_DC_COMP_CFG1 (0x2000 + 0x0034) 38*4882a593Smuzhiyun #define MT6351_AFE_DL_DC_COMP_CFG2 (0x2000 + 0x0036) 39*4882a593Smuzhiyun #define MT6351_AFE_PMIC_NEWIF_CFG0 (0x2000 + 0x0038) 40*4882a593Smuzhiyun #define MT6351_AFE_PMIC_NEWIF_CFG1 (0x2000 + 0x003a) 41*4882a593Smuzhiyun #define MT6351_AFE_PMIC_NEWIF_CFG2 (0x2000 + 0x003c) 42*4882a593Smuzhiyun #define MT6351_AFE_PMIC_NEWIF_CFG3 (0x2000 + 0x003e) 43*4882a593Smuzhiyun #define MT6351_AFE_SGEN_CFG0 (0x2000 + 0x0040) 44*4882a593Smuzhiyun #define MT6351_AFE_SGEN_CFG1 (0x2000 + 0x0042) 45*4882a593Smuzhiyun #define MT6351_AFE_ADDA2_UP8X_FIFO_LOG_MON0 (0x2000 + 0x004c) 46*4882a593Smuzhiyun #define MT6351_AFE_ADDA2_UP8X_FIFO_LOG_MON1 (0x2000 + 0x004e) 47*4882a593Smuzhiyun #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG0 (0x2000 + 0x0050) 48*4882a593Smuzhiyun #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG1 (0x2000 + 0x0052) 49*4882a593Smuzhiyun #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG2 (0x2000 + 0x0054) 50*4882a593Smuzhiyun #define MT6351_AFE_DCCLK_CFG0 (0x2000 + 0x0090) 51*4882a593Smuzhiyun #define MT6351_AFE_DCCLK_CFG1 (0x2000 + 0x0092) 52*4882a593Smuzhiyun #define MT6351_AFE_HPANC_CFG0 (0x2000 + 0x0094) 53*4882a593Smuzhiyun #define MT6351_AFE_NCP_CFG0 (0x2000 + 0x0096) 54*4882a593Smuzhiyun #define MT6351_AFE_NCP_CFG1 (0x2000 + 0x0098) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define MT6351_TOP_CKPDN_CON0 0x023A 57*4882a593Smuzhiyun #define MT6351_TOP_CKPDN_CON0_SET 0x023C 58*4882a593Smuzhiyun #define MT6351_TOP_CKPDN_CON0_CLR 0x023E 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define MT6351_TOP_CLKSQ 0x029A 61*4882a593Smuzhiyun #define MT6351_TOP_CLKSQ_SET 0x029C 62*4882a593Smuzhiyun #define MT6351_TOP_CLKSQ_CLR 0x029E 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define MT6351_ZCD_CON0 0x0800 65*4882a593Smuzhiyun #define MT6351_ZCD_CON1 0x0802 66*4882a593Smuzhiyun #define MT6351_ZCD_CON2 0x0804 67*4882a593Smuzhiyun #define MT6351_ZCD_CON3 0x0806 68*4882a593Smuzhiyun #define MT6351_ZCD_CON4 0x0808 69*4882a593Smuzhiyun #define MT6351_ZCD_CON5 0x080A 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define MT6351_LDO_VA18_CON0 0x0A00 72*4882a593Smuzhiyun #define MT6351_LDO_VA18_CON1 0x0A02 73*4882a593Smuzhiyun #define MT6351_LDO_VUSB33_CON0 0x0A16 74*4882a593Smuzhiyun #define MT6351_LDO_VUSB33_CON1 0x0A18 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON0 0x0CF2 77*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON1 0x0CF4 78*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON2 0x0CF6 79*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON3 0x0CF8 80*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON4 0x0CFA 81*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON5 0x0CFC 82*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON6 0x0CFE 83*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON7 0x0D00 84*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON8 0x0D02 85*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON9 0x0D04 86*4882a593Smuzhiyun #define MT6351_AUDDEC_ANA_CON10 0x0D06 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON0 0x0D08 89*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON1 0x0D0A 90*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON2 0x0D0C 91*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON3 0x0D0E 92*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON4 0x0D10 93*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON5 0x0D12 94*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON6 0x0D14 95*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON7 0x0D16 96*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON8 0x0D18 97*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON9 0x0D1A 98*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON10 0x0D1C 99*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON11 0x0D1E 100*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON12 0x0D20 101*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON13 0x0D22 102*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON14 0x0D24 103*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON15 0x0D26 104*4882a593Smuzhiyun #define MT6351_AUDENC_ANA_CON16 0x0D28 105*4882a593Smuzhiyun #endif 106