1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * max98926.h -- MAX98926 ALSA SoC Audio driver 4*4882a593Smuzhiyun * Copyright 2013-2015 Maxim Integrated Products 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _MAX98926_H 8*4882a593Smuzhiyun #define _MAX98926_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MAX98926_CHIP_VERSION 0x40 11*4882a593Smuzhiyun #define MAX98926_CHIP_VERSION1 0x50 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define MAX98926_VBAT_DATA 0x00 14*4882a593Smuzhiyun #define MAX98926_VBST_DATA 0x01 15*4882a593Smuzhiyun #define MAX98926_LIVE_STATUS0 0x02 16*4882a593Smuzhiyun #define MAX98926_LIVE_STATUS1 0x03 17*4882a593Smuzhiyun #define MAX98926_LIVE_STATUS2 0x04 18*4882a593Smuzhiyun #define MAX98926_STATE0 0x05 19*4882a593Smuzhiyun #define MAX98926_STATE1 0x06 20*4882a593Smuzhiyun #define MAX98926_STATE2 0x07 21*4882a593Smuzhiyun #define MAX98926_FLAG0 0x08 22*4882a593Smuzhiyun #define MAX98926_FLAG1 0x09 23*4882a593Smuzhiyun #define MAX98926_FLAG2 0x0A 24*4882a593Smuzhiyun #define MAX98926_IRQ_ENABLE0 0x0B 25*4882a593Smuzhiyun #define MAX98926_IRQ_ENABLE1 0x0C 26*4882a593Smuzhiyun #define MAX98926_IRQ_ENABLE2 0x0D 27*4882a593Smuzhiyun #define MAX98926_IRQ_CLEAR0 0x0E 28*4882a593Smuzhiyun #define MAX98926_IRQ_CLEAR1 0x0F 29*4882a593Smuzhiyun #define MAX98926_IRQ_CLEAR2 0x10 30*4882a593Smuzhiyun #define MAX98926_MAP0 0x11 31*4882a593Smuzhiyun #define MAX98926_MAP1 0x12 32*4882a593Smuzhiyun #define MAX98926_MAP2 0x13 33*4882a593Smuzhiyun #define MAX98926_MAP3 0x14 34*4882a593Smuzhiyun #define MAX98926_MAP4 0x15 35*4882a593Smuzhiyun #define MAX98926_MAP5 0x16 36*4882a593Smuzhiyun #define MAX98926_MAP6 0x17 37*4882a593Smuzhiyun #define MAX98926_MAP7 0x18 38*4882a593Smuzhiyun #define MAX98926_MAP8 0x19 39*4882a593Smuzhiyun #define MAX98926_DAI_CLK_MODE1 0x1A 40*4882a593Smuzhiyun #define MAX98926_DAI_CLK_MODE2 0x1B 41*4882a593Smuzhiyun #define MAX98926_DAI_CLK_DIV_M_MSBS 0x1C 42*4882a593Smuzhiyun #define MAX98926_DAI_CLK_DIV_M_LSBS 0x1D 43*4882a593Smuzhiyun #define MAX98926_DAI_CLK_DIV_N_MSBS 0x1E 44*4882a593Smuzhiyun #define MAX98926_DAI_CLK_DIV_N_LSBS 0x1F 45*4882a593Smuzhiyun #define MAX98926_FORMAT 0x20 46*4882a593Smuzhiyun #define MAX98926_TDM_SLOT_SELECT 0x21 47*4882a593Smuzhiyun #define MAX98926_DOUT_CFG_VMON 0x22 48*4882a593Smuzhiyun #define MAX98926_DOUT_CFG_IMON 0x23 49*4882a593Smuzhiyun #define MAX98926_DOUT_CFG_VBAT 0x24 50*4882a593Smuzhiyun #define MAX98926_DOUT_CFG_VBST 0x25 51*4882a593Smuzhiyun #define MAX98926_DOUT_CFG_FLAG 0x26 52*4882a593Smuzhiyun #define MAX98926_DOUT_HIZ_CFG1 0x27 53*4882a593Smuzhiyun #define MAX98926_DOUT_HIZ_CFG2 0x28 54*4882a593Smuzhiyun #define MAX98926_DOUT_HIZ_CFG3 0x29 55*4882a593Smuzhiyun #define MAX98926_DOUT_HIZ_CFG4 0x2A 56*4882a593Smuzhiyun #define MAX98926_DOUT_DRV_STRENGTH 0x2B 57*4882a593Smuzhiyun #define MAX98926_FILTERS 0x2C 58*4882a593Smuzhiyun #define MAX98926_GAIN 0x2D 59*4882a593Smuzhiyun #define MAX98926_GAIN_RAMPING 0x2E 60*4882a593Smuzhiyun #define MAX98926_SPK_AMP 0x2F 61*4882a593Smuzhiyun #define MAX98926_THRESHOLD 0x30 62*4882a593Smuzhiyun #define MAX98926_ALC_ATTACK 0x31 63*4882a593Smuzhiyun #define MAX98926_ALC_ATTEN_RLS 0x32 64*4882a593Smuzhiyun #define MAX98926_ALC_HOLD_RLS 0x33 65*4882a593Smuzhiyun #define MAX98926_ALC_CONFIGURATION 0x34 66*4882a593Smuzhiyun #define MAX98926_BOOST_CONVERTER 0x35 67*4882a593Smuzhiyun #define MAX98926_BLOCK_ENABLE 0x36 68*4882a593Smuzhiyun #define MAX98926_CONFIGURATION 0x37 69*4882a593Smuzhiyun #define MAX98926_GLOBAL_ENABLE 0x38 70*4882a593Smuzhiyun #define MAX98926_BOOST_LIMITER 0x3A 71*4882a593Smuzhiyun #define MAX98926_VERSION 0xFF 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define MAX98926_REG_CNT (MAX98926_R03A_BOOST_LIMITER+1) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define MAX98926_PDM_CURRENT_MASK (1<<7) 76*4882a593Smuzhiyun #define MAX98926_PDM_CURRENT_SHIFT 7 77*4882a593Smuzhiyun #define MAX98926_PDM_VOLTAGE_MASK (1<<3) 78*4882a593Smuzhiyun #define MAX98926_PDM_VOLTAGE_SHIFT 3 79*4882a593Smuzhiyun #define MAX98926_PDM_CHANNEL_0_MASK (1<<2) 80*4882a593Smuzhiyun #define MAX98926_PDM_CHANNEL_0_SHIFT 2 81*4882a593Smuzhiyun #define MAX98926_PDM_CHANNEL_1_MASK (1<<6) 82*4882a593Smuzhiyun #define MAX98926_PDM_CHANNEL_1_SHIFT 6 83*4882a593Smuzhiyun #define MAX98926_PDM_CHANNEL_1_HIZ 5 84*4882a593Smuzhiyun #define MAX98926_PDM_CHANNEL_0_HIZ 1 85*4882a593Smuzhiyun #define MAX98926_PDM_SOURCE_0_SHIFT 0 86*4882a593Smuzhiyun #define MAX98926_PDM_SOURCE_0_MASK (1<<0) 87*4882a593Smuzhiyun #define MAX98926_PDM_SOURCE_1_MASK (1<<4) 88*4882a593Smuzhiyun #define MAX98926_PDM_SOURCE_1_SHIFT 4 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* MAX98926 Register Bit Fields */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* MAX98926_R002_LIVE_STATUS0 */ 93*4882a593Smuzhiyun #define MAX98926_THERMWARN_STATUS_MASK (1<<3) 94*4882a593Smuzhiyun #define MAX98926_THERMWARN_STATUS_SHIFT 3 95*4882a593Smuzhiyun #define MAX98926_THERMWARN_STATUS_WIDTH 1 96*4882a593Smuzhiyun #define MAX98926_THERMSHDN_STATUS_MASK (1<<1) 97*4882a593Smuzhiyun #define MAX98926_THERMSHDN_STATUS_SHIFT 1 98*4882a593Smuzhiyun #define MAX98926_THERMSHDN_STATUS_WIDTH 1 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* MAX98926_R003_LIVE_STATUS1 */ 101*4882a593Smuzhiyun #define MAX98926_SPKCURNT_STATUS_MASK (1<<5) 102*4882a593Smuzhiyun #define MAX98926_SPKCURNT_STATUS_SHIFT 5 103*4882a593Smuzhiyun #define MAX98926_SPKCURNT_STATUS_WIDTH 1 104*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_STATUS_MASK (1<<4) 105*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_STATUS_SHIFT 4 106*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_STATUS_WIDTH 1 107*4882a593Smuzhiyun #define MAX98926_ALCINFH_STATUS_MASK (1<<3) 108*4882a593Smuzhiyun #define MAX98926_ALCINFH_STATUS_SHIFT 3 109*4882a593Smuzhiyun #define MAX98926_ALCINFH_STATUS_WIDTH 1 110*4882a593Smuzhiyun #define MAX98926_ALCACT_STATUS_MASK (1<<2) 111*4882a593Smuzhiyun #define MAX98926_ALCACT_STATUS_SHIFT 2 112*4882a593Smuzhiyun #define MAX98926_ALCACT_STATUS_WIDTH 1 113*4882a593Smuzhiyun #define MAX98926_ALCMUT_STATUS_MASK (1<<1) 114*4882a593Smuzhiyun #define MAX98926_ALCMUT_STATUS_SHIFT 1 115*4882a593Smuzhiyun #define MAX98926_ALCMUT_STATUS_WIDTH 1 116*4882a593Smuzhiyun #define MAX98926_ACLP_STATUS_MASK (1<<0) 117*4882a593Smuzhiyun #define MAX98926_ACLP_STATUS_SHIFT 0 118*4882a593Smuzhiyun #define MAX98926_ACLP_STATUS_WIDTH 1 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* MAX98926_R004_LIVE_STATUS2 */ 121*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_STATUS_MASK (1<<6) 122*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_STATUS_SHIFT 6 123*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_STATUS_WIDTH 1 124*4882a593Smuzhiyun #define MAX98926_INVALSLOT_STATUS_MASK (1<<5) 125*4882a593Smuzhiyun #define MAX98926_INVALSLOT_STATUS_SHIFT 5 126*4882a593Smuzhiyun #define MAX98926_INVALSLOT_STATUS_WIDTH 1 127*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_STATUS_MASK (1<<4) 128*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_STATUS_SHIFT 4 129*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_STATUS_WIDTH 1 130*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_STATUS_MASK (1<<3) 131*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_STATUS_SHIFT 3 132*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_STATUS_WIDTH 1 133*4882a593Smuzhiyun #define MAX98926_VBATOVFL_STATUS_MASK (1<<2) 134*4882a593Smuzhiyun #define MAX98926_VBATOVFL_STATUS_SHIFT 2 135*4882a593Smuzhiyun #define MAX98926_VBATOVFL_STATUS_WIDTH 1 136*4882a593Smuzhiyun #define MAX98926_IMONOVFL_STATUS_MASK (1<<1) 137*4882a593Smuzhiyun #define MAX98926_IMONOVFL_STATUS_SHIFT 1 138*4882a593Smuzhiyun #define MAX98926_IMONOVFL_STATUS_WIDTH 1 139*4882a593Smuzhiyun #define MAX98926_VMONOVFL_STATUS_MASK (1<<0) 140*4882a593Smuzhiyun #define MAX98926_VMONOVFL_STATUS_SHIFT 0 141*4882a593Smuzhiyun #define MAX98926_VMONOVFL_STATUS_WIDTH 1 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* MAX98926_R005_STATE0 */ 144*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_STATE_MASK (1<<3) 145*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_STATE_SHIFT 3 146*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_STATE_WIDTH 1 147*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_STATE_MASK (1<<2) 148*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_STATE_SHIFT 1 149*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_STATE_WIDTH 1 150*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_STATE_MASK (1<<1) 151*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_STATE_SHIFT 1 152*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_STATE_WIDTH 1 153*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_STATE_MASK (1<<0) 154*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_STATE_SHIFT 0 155*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_STATE_WIDTH 1 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* MAX98926_R006_STATE1 */ 158*4882a593Smuzhiyun #define MAX98926_SPRCURNT_STATE_MASK (1<<5) 159*4882a593Smuzhiyun #define MAX98926_SPRCURNT_STATE_SHIFT 5 160*4882a593Smuzhiyun #define MAX98926_SPRCURNT_STATE_WIDTH 1 161*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_STATE_MASK (1<<4) 162*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_STATE_SHIFT 4 163*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_STATE_WIDTH 1 164*4882a593Smuzhiyun #define MAX98926_ALCINFH_STATE_MASK (1<<3) 165*4882a593Smuzhiyun #define MAX98926_ALCINFH_STATE_SHIFT 3 166*4882a593Smuzhiyun #define MAX98926_ALCINFH_STATE_WIDTH 1 167*4882a593Smuzhiyun #define MAX98926_ALCACT_STATE_MASK (1<<2) 168*4882a593Smuzhiyun #define MAX98926_ALCACT_STATE_SHIFT 2 169*4882a593Smuzhiyun #define MAX98926_ALCACT_STATE_WIDTH 1 170*4882a593Smuzhiyun #define MAX98926_ALCMUT_STATE_MASK (1<<1) 171*4882a593Smuzhiyun #define MAX98926_ALCMUT_STATE_SHIFT 1 172*4882a593Smuzhiyun #define MAX98926_ALCMUT_STATE_WIDTH 1 173*4882a593Smuzhiyun #define MAX98926_ALCP_STATE_MASK (1<<0) 174*4882a593Smuzhiyun #define MAX98926_ALCP_STATE_SHIFT 0 175*4882a593Smuzhiyun #define MAX98926_ALCP_STATE_WIDTH 1 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* MAX98926_R007_STATE2 */ 178*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_STATE_MASK (1<<6) 179*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_STATE_SHIFT 6 180*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_STATE_WIDTH 1 181*4882a593Smuzhiyun #define MAX98926_INVALSLOT_STATE_MASK (1<<5) 182*4882a593Smuzhiyun #define MAX98926_INVALSLOT_STATE_SHIFT 5 183*4882a593Smuzhiyun #define MAX98926_INVALSLOT_STATE_WIDTH 1 184*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_STATE_MASK (1<<4) 185*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_STATE_SHIFT 4 186*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_STATE_WIDTH 1 187*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_STATE_MASK (1<<3) 188*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_STATE_SHIFT 3 189*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_STATE_WIDTH 1 190*4882a593Smuzhiyun #define MAX98926_VBATOVFL_STATE_MASK (1<<2) 191*4882a593Smuzhiyun #define MAX98926_VBATOVFL_STATE_SHIFT 2 192*4882a593Smuzhiyun #define MAX98926_VBATOVFL_STATE_WIDTH 1 193*4882a593Smuzhiyun #define MAX98926_IMONOVFL_STATE_MASK (1<<1) 194*4882a593Smuzhiyun #define MAX98926_IMONOVFL_STATE_SHIFT 1 195*4882a593Smuzhiyun #define MAX98926_IMONOVFL_STATE_WIDTH 1 196*4882a593Smuzhiyun #define MAX98926_VMONOVFL_STATE_MASK (1<<0) 197*4882a593Smuzhiyun #define MAX98926_VMONOVFL_STATE_SHIFT 0 198*4882a593Smuzhiyun #define MAX98926_VMONOVFL_STATE_WIDTH 1 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* MAX98926_R008_FLAG0 */ 201*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_FLAG_MASK (1<<3) 202*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_FLAG_SHIFT 3 203*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_FLAG_WIDTH 1 204*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_FLAG_MASK (1<<2) 205*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_FLAG_SHIFT 2 206*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_FLAG_WIDTH 1 207*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_FLAG_MASK (1<<1) 208*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_FLAG_SHIFT 1 209*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_FLAG_WIDTH 1 210*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_FLAG_MASK (1<<0) 211*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_FLAG_SHIFT 0 212*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_FLAG_WIDTH 1 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* MAX98926_R009_FLAG1 */ 215*4882a593Smuzhiyun #define MAX98926_SPKCURNT_FLAG_MASK (1<<5) 216*4882a593Smuzhiyun #define MAX98926_SPKCURNT_FLAG_SHIFT 5 217*4882a593Smuzhiyun #define MAX98926_SPKCURNT_FLAG_WIDTH 1 218*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_FLAG_MASK (1<<4) 219*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_FLAG_SHIFT 4 220*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_FLAG_WIDTH 1 221*4882a593Smuzhiyun #define MAX98926_ALCINFH_FLAG_MASK (1<<3) 222*4882a593Smuzhiyun #define MAX98926_ALCINFH_FLAG_SHIFT 3 223*4882a593Smuzhiyun #define MAX98926_ALCINFH_FLAG_WIDTH 1 224*4882a593Smuzhiyun #define MAX98926_ALCACT_FLAG_MASK (1<<2) 225*4882a593Smuzhiyun #define MAX98926_ALCACT_FLAG_SHIFT 2 226*4882a593Smuzhiyun #define MAX98926_ALCACT_FLAG_WIDTH 1 227*4882a593Smuzhiyun #define MAX98926_ALCMUT_FLAG_MASK (1<<1) 228*4882a593Smuzhiyun #define MAX98926_ALCMUT_FLAG_SHIFT 1 229*4882a593Smuzhiyun #define MAX98926_ALCMUT_FLAG_WIDTH 1 230*4882a593Smuzhiyun #define MAX98926_ALCP_FLAG_MASK (1<<0) 231*4882a593Smuzhiyun #define MAX98926_ALCP_FLAG_SHIFT 0 232*4882a593Smuzhiyun #define MAX98926_ALCP_FLAG_WIDTH 1 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* MAX98926_R00A_FLAG2 */ 235*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_FLAG_MASK (1<<6) 236*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_FLAG_SHIFT 6 237*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_FLAG_WIDTH 1 238*4882a593Smuzhiyun #define MAX98926_INVALSLOT_FLAG_MASK (1<<5) 239*4882a593Smuzhiyun #define MAX98926_INVALSLOT_FLAG_SHIFT 5 240*4882a593Smuzhiyun #define MAX98926_INVALSLOT_FLAG_WIDTH 1 241*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_FLAG_MASK (1<<4) 242*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_FLAG_SHIFT 4 243*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_FLAG_WIDTH 1 244*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_FLAG_MASK (1<<3) 245*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_FLAG_SHIFT 3 246*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_FLAG_WIDTH 1 247*4882a593Smuzhiyun #define MAX98926_VBATOVFL_FLAG_MASK (1<<2) 248*4882a593Smuzhiyun #define MAX98926_VBATOVFL_FLAG_SHIFT 2 249*4882a593Smuzhiyun #define MAX98926_VBATOVFL_FLAG_WIDTH 1 250*4882a593Smuzhiyun #define MAX98926_IMONOVFL_FLAG_MASK (1<<1) 251*4882a593Smuzhiyun #define MAX98926_IMONOVFL_FLAG_SHIFT 1 252*4882a593Smuzhiyun #define MAX98926_IMONOVFL_FLAG_WIDTH 1 253*4882a593Smuzhiyun #define MAX98926_VMONOVFL_FLAG_MASK (1<<0) 254*4882a593Smuzhiyun #define MAX98926_VMONOVFL_FLAG_SHIFT 0 255*4882a593Smuzhiyun #define MAX98926_VMONOVFL_FLAG_WIDTH 1 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun /* MAX98926_R00B_IRQ_ENABLE0 */ 258*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_EN_MASK (1<<3) 259*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_EN_SHIFT 3 260*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_EN_WIDTH 1 261*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_EN_MASK (1<<2) 262*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_EN_SHIFT 2 263*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_EN_WIDTH 1 264*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_EN_MASK (1<<1) 265*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_EN_SHIFT 1 266*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_EN_WIDTH 1 267*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_EN_MASK (1<<0) 268*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_EN_SHIFT 0 269*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_EN_WIDTH 1 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun /* MAX98926_R00C_IRQ_ENABLE1 */ 272*4882a593Smuzhiyun #define MAX98926_SPKCURNT_EN_MASK (1<<5) 273*4882a593Smuzhiyun #define MAX98926_SPKCURNT_EN_SHIFT 5 274*4882a593Smuzhiyun #define MAX98926_SPKCURNT_EN_WIDTH 1 275*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_EN_MASK (1<<4) 276*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_EN_SHIFT 4 277*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_EN_WIDTH 1 278*4882a593Smuzhiyun #define MAX98926_ALCINFH_EN_MASK (1<<3) 279*4882a593Smuzhiyun #define MAX98926_ALCINFH_EN_SHIFT 3 280*4882a593Smuzhiyun #define MAX98926_ALCINFH_EN_WIDTH 1 281*4882a593Smuzhiyun #define MAX98926_ALCACT_EN_MASK (1<<2) 282*4882a593Smuzhiyun #define MAX98926_ALCACT_EN_SHIFT 2 283*4882a593Smuzhiyun #define MAX98926_ALCACT_EN_WIDTH 1 284*4882a593Smuzhiyun #define MAX98926_ALCMUT_EN_MASK (1<<1) 285*4882a593Smuzhiyun #define MAX98926_ALCMUT_EN_SHIFT 1 286*4882a593Smuzhiyun #define MAX98926_ALCMUT_EN_WIDTH 1 287*4882a593Smuzhiyun #define MAX98926_ALCP_EN_MASK (1<<0) 288*4882a593Smuzhiyun #define MAX98926_ALCP_EN_SHIFT 0 289*4882a593Smuzhiyun #define MAX98926_ALCP_EN_WIDTH 1 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /* MAX98926_R00D_IRQ_ENABLE2 */ 292*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_EN_MASK (1<<6) 293*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_EN_SHIFT 6 294*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_EN_WIDTH 1 295*4882a593Smuzhiyun #define MAX98926_INVALSLOT_EN_MASK (1<<5) 296*4882a593Smuzhiyun #define MAX98926_INVALSLOT_EN_SHIFT 5 297*4882a593Smuzhiyun #define MAX98926_INVALSLOT_EN_WIDTH 1 298*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_EN_MASK (1<<4) 299*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_EN_SHIFT 4 300*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_EN_WIDTH 1 301*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_EN_MASK (1<<3) 302*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_EN_SHIFT 3 303*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_EN_WIDTH 1 304*4882a593Smuzhiyun #define MAX98926_VBATOVFL_EN_MASK (1<<2) 305*4882a593Smuzhiyun #define MAX98926_VBATOVFL_EN_SHIFT 2 306*4882a593Smuzhiyun #define MAX98926_VBATOVFL_EN_WIDTH 1 307*4882a593Smuzhiyun #define MAX98926_IMONOVFL_EN_MASK (1<<1) 308*4882a593Smuzhiyun #define MAX98926_IMONOVFL_EN_SHIFT 1 309*4882a593Smuzhiyun #define MAX98926_IMONOVFL_EN_WIDTH 1 310*4882a593Smuzhiyun #define MAX98926_VMONOVFL_EN_MASK (1<<0) 311*4882a593Smuzhiyun #define MAX98926_VMONOVFL_EN_SHIFT 0 312*4882a593Smuzhiyun #define MAX98926_VMONOVFL_EN_WIDTH 1 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* MAX98926_R00E_IRQ_CLEAR0 */ 315*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_CLR_MASK (1<<3) 316*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_CLR_SHIFT 3 317*4882a593Smuzhiyun #define MAX98926_THERMWARN_END_CLR_WIDTH 1 318*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_CLR_MASK (1<<2) 319*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_CLR_SHIFT 2 320*4882a593Smuzhiyun #define MAX98926_THERMWARN_BGN_CLR_WIDTH 1 321*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_CLR_MASK (1<<1) 322*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_CLR_SHIFT 1 323*4882a593Smuzhiyun #define MAX98926_THERMSHDN_END_CLR_WIDTH 1 324*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_CLR_MASK (1<<0) 325*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_CLR_SHIFT 0 326*4882a593Smuzhiyun #define MAX98926_THERMSHDN_BGN_CLR_WIDTH 1 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun /* MAX98926_R00F_IRQ_CLEAR1 */ 329*4882a593Smuzhiyun #define MAX98926_SPKCURNT_CLR_MASK (1<<5) 330*4882a593Smuzhiyun #define MAX98926_SPKCURNT_CLR_SHIFT 5 331*4882a593Smuzhiyun #define MAX98926_SPKCURNT_CLR_WIDTH 1 332*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_CLR_MASK (1<<4) 333*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_CLR_SHIFT 4 334*4882a593Smuzhiyun #define MAX98926_WATCHFAIL_CLR_WIDTH 1 335*4882a593Smuzhiyun #define MAX98926_ALCINFH_CLR_MASK (1<<3) 336*4882a593Smuzhiyun #define MAX98926_ALCINFH_CLR_SHIFT 3 337*4882a593Smuzhiyun #define MAX98926_ALCINFH_CLR_WIDTH 1 338*4882a593Smuzhiyun #define MAX98926_ALCACT_CLR_MASK (1<<2) 339*4882a593Smuzhiyun #define MAX98926_ALCACT_CLR_SHIFT 2 340*4882a593Smuzhiyun #define MAX98926_ALCACT_CLR_WIDTH 1 341*4882a593Smuzhiyun #define MAX98926_ALCMUT_CLR_MASK (1<<1) 342*4882a593Smuzhiyun #define MAX98926_ALCMUT_CLR_SHIFT 1 343*4882a593Smuzhiyun #define MAX98926_ALCMUT_CLR_WIDTH 1 344*4882a593Smuzhiyun #define MAX98926_ALCP_CLR_MASK (1<<0) 345*4882a593Smuzhiyun #define MAX98926_ALCP_CLR_SHIFT 0 346*4882a593Smuzhiyun #define MAX98926_ALCP_CLR_WIDTH 1 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun /* MAX98926_R010_IRQ_CLEAR2 */ 349*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_CLR_MASK (1<<6) 350*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_CLR_SHIFT 6 351*4882a593Smuzhiyun #define MAX98926_SLOTOVRN_CLR_WIDTH 1 352*4882a593Smuzhiyun #define MAX98926_INVALSLOT_CLR_MASK (1<<5) 353*4882a593Smuzhiyun #define MAX98926_INVALSLOT_CLR_SHIFT 5 354*4882a593Smuzhiyun #define MAX98926_INVALSLOT_CLR_WIDTH 1 355*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_CLR_MASK (1<<4) 356*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_CLR_SHIFT 4 357*4882a593Smuzhiyun #define MAX98926_SLOTCNFLT_CLR_WIDTH 1 358*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_CLR_MASK (1<<3) 359*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_CLR_SHIFT 3 360*4882a593Smuzhiyun #define MAX98926_VBSTOVFL_CLR_WIDTH 1 361*4882a593Smuzhiyun #define MAX98926_VBATOVFL_CLR_MASK (1<<2) 362*4882a593Smuzhiyun #define MAX98926_VBATOVFL_CLR_SHIFT 2 363*4882a593Smuzhiyun #define MAX98926_VBATOVFL_CLR_WIDTH 1 364*4882a593Smuzhiyun #define MAX98926_IMONOVFL_CLR_MASK (1<<1) 365*4882a593Smuzhiyun #define MAX98926_IMONOVFL_CLR_SHIFT 1 366*4882a593Smuzhiyun #define MAX98926_IMONOVFL_CLR_WIDTH 1 367*4882a593Smuzhiyun #define MAX98926_VMONOVFL_CLR_MASK (1<<0) 368*4882a593Smuzhiyun #define MAX98926_VMONOVFL_CLR_SHIFT 0 369*4882a593Smuzhiyun #define MAX98926_VMONOVFL_CLR_WIDTH 1 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun /* MAX98926_R011_MAP0 */ 372*4882a593Smuzhiyun #define MAX98926_ER_THERMWARN_EN_MASK (1<<7) 373*4882a593Smuzhiyun #define MAX98926_ER_THERMWARN_EN_SHIFT 7 374*4882a593Smuzhiyun #define MAX98926_ER_THERMWARN_EN_WIDTH 1 375*4882a593Smuzhiyun #define MAX98926_ER_THERMWARN_MAP_MASK (0x07<<4) 376*4882a593Smuzhiyun #define MAX98926_ER_THERMWARN_MAP_SHIFT 4 377*4882a593Smuzhiyun #define MAX98926_ER_THERMWARN_MAP_WIDTH 3 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun /* MAX98926_R012_MAP1 */ 380*4882a593Smuzhiyun #define MAX98926_ER_ALCMUT_EN_MASK (1<<7) 381*4882a593Smuzhiyun #define MAX98926_ER_ALCMUT_EN_SHIFT 7 382*4882a593Smuzhiyun #define MAX98926_ER_ALCMUT_EN_WIDTH 1 383*4882a593Smuzhiyun #define MAX98926_ER_ALCMUT_MAP_MASK (0x07<<4) 384*4882a593Smuzhiyun #define MAX98926_ER_ALCMUT_MAP_SHIFT 4 385*4882a593Smuzhiyun #define MAX98926_ER_ALCMUT_MAP_WIDTH 3 386*4882a593Smuzhiyun #define MAX98926_ER_ALCP_EN_MASK (1<<3) 387*4882a593Smuzhiyun #define MAX98926_ER_ALCP_EN_SHIFT 3 388*4882a593Smuzhiyun #define MAX98926_ER_ALCP_EN_WIDTH 1 389*4882a593Smuzhiyun #define MAX98926_ER_ALCP_MAP_MASK (0x07<<0) 390*4882a593Smuzhiyun #define MAX98926_ER_ALCP_MAP_SHIFT 0 391*4882a593Smuzhiyun #define MAX98926_ER_ALCP_MAP_WIDTH 3 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun /* MAX98926_R013_MAP2 */ 394*4882a593Smuzhiyun #define MAX98926_ER_ALCINFH_EN_MASK (1<<7) 395*4882a593Smuzhiyun #define MAX98926_ER_ALCINFH_EN_SHIFT 7 396*4882a593Smuzhiyun #define MAX98926_ER_ALCINFH_EN_WIDTH 1 397*4882a593Smuzhiyun #define MAX98926_ER_ALCINFH_MAP_MASK (0x07<<4) 398*4882a593Smuzhiyun #define MAX98926_ER_ALCINFH_MAP_SHIFT 4 399*4882a593Smuzhiyun #define MAX98926_ER_ALCINFH_MAP_WIDTH 3 400*4882a593Smuzhiyun #define MAX98926_ER_ALCACT_EN_MASK (1<<3) 401*4882a593Smuzhiyun #define MAX98926_ER_ALCACT_EN_SHIFT 3 402*4882a593Smuzhiyun #define MAX98926_ER_ALCACT_EN_WIDTH 1 403*4882a593Smuzhiyun #define MAX98926_ER_ALCACT_MAP_MASK (0x07<<0) 404*4882a593Smuzhiyun #define MAX98926_ER_ALCACT_MAP_SHIFT 0 405*4882a593Smuzhiyun #define MAX98926_ER_ALCACT_MAP_WIDTH 3 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun /* MAX98926_R014_MAP3 */ 408*4882a593Smuzhiyun #define MAX98926_ER_SPKCURNT_EN_MASK (1<<7) 409*4882a593Smuzhiyun #define MAX98926_ER_SPKCURNT_EN_SHIFT 7 410*4882a593Smuzhiyun #define MAX98926_ER_SPKCURNT_EN_WIDTH 1 411*4882a593Smuzhiyun #define MAX98926_ER_SPKCURNT_MAP_MASK (0x07<<4) 412*4882a593Smuzhiyun #define MAX98926_ER_SPKCURNT_MAP_SHIFT 4 413*4882a593Smuzhiyun #define MAX98926_ER_SPKCURNT_MAP_WIDTH 3 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun /* MAX98926_R015_MAP4 */ 416*4882a593Smuzhiyun /* RESERVED */ 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun /* MAX98926_R016_MAP5 */ 419*4882a593Smuzhiyun #define MAX98926_ER_IMONOVFL_EN_MASK (1<<7) 420*4882a593Smuzhiyun #define MAX98926_ER_IMONOVFL_EN_SHIFT 7 421*4882a593Smuzhiyun #define MAX98926_ER_IMONOVFL_EN_WIDTH 1 422*4882a593Smuzhiyun #define MAX98926_ER_IMONOVFL_MAP_MASK (0x07<<4) 423*4882a593Smuzhiyun #define MAX98926_ER_IMONOVFL_MAP_SHIFT 4 424*4882a593Smuzhiyun #define MAX98926_ER_IMONOVFL_MAP_WIDTH 3 425*4882a593Smuzhiyun #define MAX98926_ER_VMONOVFL_EN_MASK (1<<3) 426*4882a593Smuzhiyun #define MAX98926_ER_VMONOVFL_EN_SHIFT 3 427*4882a593Smuzhiyun #define MAX98926_ER_VMONOVFL_EN_WIDTH 1 428*4882a593Smuzhiyun #define MAX98926_ER_VMONOVFL_MAP_MASK (0x07<<0) 429*4882a593Smuzhiyun #define MAX98926_ER_VMONOVFL_MAP_SHIFT 0 430*4882a593Smuzhiyun #define MAX98926_ER_VMONOVFL_MAP_WIDTH 3 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun /* MAX98926_R017_MAP6 */ 433*4882a593Smuzhiyun #define MAX98926_ER_VBSTOVFL_EN_MASK (1<<7) 434*4882a593Smuzhiyun #define MAX98926_ER_VBSTOVFL_EN_SHIFT 7 435*4882a593Smuzhiyun #define MAX98926_ER_VBSTOVFL_EN_WIDTH 1 436*4882a593Smuzhiyun #define MAX98926_ER_VBSTOVFL_MAP_MASK (0x07<<4) 437*4882a593Smuzhiyun #define MAX98926_ER_VBSTOVFL_MAP_SHIFT 4 438*4882a593Smuzhiyun #define MAX98926_ER_VBSTOVFL_MAP_WIDTH 3 439*4882a593Smuzhiyun #define MAX98926_ER_VBATOVFL_EN_MASK (1<<3) 440*4882a593Smuzhiyun #define MAX98926_ER_VBATOVFL_EN_SHIFT 3 441*4882a593Smuzhiyun #define MAX98926_ER_VBATOVFL_EN_WIDTH 1 442*4882a593Smuzhiyun #define MAX98926_ER_VBATOVFL_MAP_MASK (0x07<<0) 443*4882a593Smuzhiyun #define MAX98926_ER_VBATOVFL_MAP_SHIFT 0 444*4882a593Smuzhiyun #define MAX98926_ER_VBATOVFL_MAP_WIDTH 3 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun /* MAX98926_R018_MAP7 */ 447*4882a593Smuzhiyun #define MAX98926_ER_INVALSLOT_EN_MASK (1<<7) 448*4882a593Smuzhiyun #define MAX98926_ER_INVALSLOT_EN_SHIFT 7 449*4882a593Smuzhiyun #define MAX98926_ER_INVALSLOT_EN_WIDTH 1 450*4882a593Smuzhiyun #define MAX98926_ER_INVALSLOT_MAP_MASK (0x07<<4) 451*4882a593Smuzhiyun #define MAX98926_ER_INVALSLOT_MAP_SHIFT 4 452*4882a593Smuzhiyun #define MAX98926_ER_INVALSLOT_MAP_WIDTH 3 453*4882a593Smuzhiyun #define MAX98926_ER_SLOTCNFLT_EN_MASK (1<<3) 454*4882a593Smuzhiyun #define MAX98926_ER_SLOTCNFLT_EN_SHIFT 3 455*4882a593Smuzhiyun #define MAX98926_ER_SLOTCNFLT_EN_WIDTH 1 456*4882a593Smuzhiyun #define MAX98926_ER_SLOTCNFLT_MAP_MASK (0x07<<0) 457*4882a593Smuzhiyun #define MAX98926_ER_SLOTCNFLT_MAP_SHIFT 0 458*4882a593Smuzhiyun #define MAX98926_ER_SLOTCNFLT_MAP_WIDTH 3 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun /* MAX98926_R019_MAP8 */ 461*4882a593Smuzhiyun #define MAX98926_ER_SLOTOVRN_EN_MASK (1<<3) 462*4882a593Smuzhiyun #define MAX98926_ER_SLOTOVRN_EN_SHIFT 3 463*4882a593Smuzhiyun #define MAX98926_ER_SLOTOVRN_EN_WIDTH 1 464*4882a593Smuzhiyun #define MAX98926_ER_SLOTOVRN_MAP_MASK (0x07<<0) 465*4882a593Smuzhiyun #define MAX98926_ER_SLOTOVRN_MAP_SHIFT 0 466*4882a593Smuzhiyun #define MAX98926_ER_SLOTOVRN_MAP_WIDTH 3 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun /* MAX98926_R01A_DAI_CLK_MODE1 */ 469*4882a593Smuzhiyun #define MAX98926_DAI_CLK_SOURCE_MASK (1<<6) 470*4882a593Smuzhiyun #define MAX98926_DAI_CLK_SOURCE_SHIFT 6 471*4882a593Smuzhiyun #define MAX98926_DAI_CLK_SOURCE_WIDTH 1 472*4882a593Smuzhiyun #define MAX98926_MDLL_MULT_MASK (0x0F<<0) 473*4882a593Smuzhiyun #define MAX98926_MDLL_MULT_SHIFT 0 474*4882a593Smuzhiyun #define MAX98926_MDLL_MULT_WIDTH 4 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun #define MAX98926_MDLL_MULT_MCLKx8 6 477*4882a593Smuzhiyun #define MAX98926_MDLL_MULT_MCLKx16 8 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun /* MAX98926_R01B_DAI_CLK_MODE2 */ 480*4882a593Smuzhiyun #define MAX98926_DAI_SR_MASK (0x0F<<4) 481*4882a593Smuzhiyun #define MAX98926_DAI_SR_SHIFT 4 482*4882a593Smuzhiyun #define MAX98926_DAI_SR_WIDTH 4 483*4882a593Smuzhiyun #define MAX98926_DAI_MAS_MASK (1<<3) 484*4882a593Smuzhiyun #define MAX98926_DAI_MAS_SHIFT 3 485*4882a593Smuzhiyun #define MAX98926_DAI_MAS_WIDTH 1 486*4882a593Smuzhiyun #define MAX98926_DAI_BSEL_MASK (0x07<<0) 487*4882a593Smuzhiyun #define MAX98926_DAI_BSEL_SHIFT 0 488*4882a593Smuzhiyun #define MAX98926_DAI_BSEL_WIDTH 3 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun #define MAX98926_DAI_BSEL_32 (0 << MAX98926_DAI_BSEL_SHIFT) 491*4882a593Smuzhiyun #define MAX98926_DAI_BSEL_48 (1 << MAX98926_DAI_BSEL_SHIFT) 492*4882a593Smuzhiyun #define MAX98926_DAI_BSEL_64 (2 << MAX98926_DAI_BSEL_SHIFT) 493*4882a593Smuzhiyun #define MAX98926_DAI_BSEL_256 (6 << MAX98926_DAI_BSEL_SHIFT) 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun /* MAX98926_R01C_DAI_CLK_DIV_M_MSBS */ 496*4882a593Smuzhiyun #define MAX98926_DAI_M_MSBS_MASK (0xFF<<0) 497*4882a593Smuzhiyun #define MAX98926_DAI_M_MSBS_SHIFT 0 498*4882a593Smuzhiyun #define MAX98926_DAI_M_MSBS_WIDTH 8 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun /* MAX98926_R01D_DAI_CLK_DIV_M_LSBS */ 501*4882a593Smuzhiyun #define MAX98926_DAI_M_LSBS_MASK (0xFF<<0) 502*4882a593Smuzhiyun #define MAX98926_DAI_M_LSBS_SHIFT 0 503*4882a593Smuzhiyun #define MAX98926_DAI_M_LSBS_WIDTH 8 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun /* MAX98926_R01E_DAI_CLK_DIV_N_MSBS */ 506*4882a593Smuzhiyun #define MAX98926_DAI_N_MSBS_MASK (0x7F<<0) 507*4882a593Smuzhiyun #define MAX98926_DAI_N_MSBS_SHIFT 0 508*4882a593Smuzhiyun #define MAX98926_DAI_N_MSBS_WIDTH 7 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun /* MAX98926_R01F_DAI_CLK_DIV_N_LSBS */ 511*4882a593Smuzhiyun #define MAX98926_DAI_N_LSBS_MASK (0xFF<<0) 512*4882a593Smuzhiyun #define MAX98926_DAI_N_LSBS_SHIFT 0 513*4882a593Smuzhiyun #define MAX98926_DAI_N_LSBS_WIDTH 8 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun /* MAX98926_R020_FORMAT */ 516*4882a593Smuzhiyun #define MAX98926_DAI_CHANSZ_MASK (0x03<<6) 517*4882a593Smuzhiyun #define MAX98926_DAI_CHANSZ_SHIFT 6 518*4882a593Smuzhiyun #define MAX98926_DAI_CHANSZ_WIDTH 2 519*4882a593Smuzhiyun #define MAX98926_DAI_INTERLEAVE_MASK (1<<5) 520*4882a593Smuzhiyun #define MAX98926_DAI_INTERLEAVE_SHIFT 5 521*4882a593Smuzhiyun #define MAX98926_DAI_INTERLEAVE_WIDTH 1 522*4882a593Smuzhiyun #define MAX98926_DAI_EXTBCLK_HIZ_MASK (1<<4) 523*4882a593Smuzhiyun #define MAX98926_DAI_EXTBCLK_HIZ_SHIFT 4 524*4882a593Smuzhiyun #define MAX98926_DAI_EXTBCLK_HIZ_WIDTH 1 525*4882a593Smuzhiyun #define MAX98926_DAI_WCI_MASK (1<<3) 526*4882a593Smuzhiyun #define MAX98926_DAI_WCI_SHIFT 3 527*4882a593Smuzhiyun #define MAX98926_DAI_WCI_WIDTH 1 528*4882a593Smuzhiyun #define MAX98926_DAI_BCI_MASK (1<<2) 529*4882a593Smuzhiyun #define MAX98926_DAI_BCI_SHIFT 2 530*4882a593Smuzhiyun #define MAX98926_DAI_BCI_WIDTH 1 531*4882a593Smuzhiyun #define MAX98926_DAI_DLY_MASK (1<<1) 532*4882a593Smuzhiyun #define MAX98926_DAI_DLY_SHIFT 1 533*4882a593Smuzhiyun #define MAX98926_DAI_DLY_WIDTH 1 534*4882a593Smuzhiyun #define MAX98926_DAI_TDM_MASK (1<<0) 535*4882a593Smuzhiyun #define MAX98926_DAI_TDM_SHIFT 0 536*4882a593Smuzhiyun #define MAX98926_DAI_TDM_WIDTH 1 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun #define MAX98926_DAI_CHANSZ_16 (1 << MAX98926_DAI_CHANSZ_SHIFT) 539*4882a593Smuzhiyun #define MAX98926_DAI_CHANSZ_24 (2 << MAX98926_DAI_CHANSZ_SHIFT) 540*4882a593Smuzhiyun #define MAX98926_DAI_CHANSZ_32 (3 << MAX98926_DAI_CHANSZ_SHIFT) 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun /* MAX98926_R021_TDM_SLOT_SELECT */ 543*4882a593Smuzhiyun #define MAX98926_DAI_DO_EN_MASK (1<<7) 544*4882a593Smuzhiyun #define MAX98926_DAI_DO_EN_SHIFT 7 545*4882a593Smuzhiyun #define MAX98926_DAI_DO_EN_WIDTH 1 546*4882a593Smuzhiyun #define MAX98926_DAI_DIN_EN_MASK (1<<6) 547*4882a593Smuzhiyun #define MAX98926_DAI_DIN_EN_SHIFT 6 548*4882a593Smuzhiyun #define MAX98926_DAI_DIN_EN_WIDTH 1 549*4882a593Smuzhiyun #define MAX98926_DAI_INR_SOURCE_MASK (0x07<<3) 550*4882a593Smuzhiyun #define MAX98926_DAI_INR_SOURCE_SHIFT 3 551*4882a593Smuzhiyun #define MAX98926_DAI_INR_SOURCE_WIDTH 3 552*4882a593Smuzhiyun #define MAX98926_DAI_INL_SOURCE_MASK (0x07<<0) 553*4882a593Smuzhiyun #define MAX98926_DAI_INL_SOURCE_SHIFT 0 554*4882a593Smuzhiyun #define MAX98926_DAI_INL_SOURCE_WIDTH 3 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun /* MAX98926_R022_DOUT_CFG_VMON */ 557*4882a593Smuzhiyun #define MAX98926_DAI_VMON_EN_MASK (1<<5) 558*4882a593Smuzhiyun #define MAX98926_DAI_VMON_EN_SHIFT 5 559*4882a593Smuzhiyun #define MAX98926_DAI_VMON_EN_WIDTH 1 560*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_MASK (0x1F<<0) 561*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_SHIFT 0 562*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_WIDTH 5 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_00_01 (0 << MAX98926_DAI_VMON_SLOT_SHIFT) 565*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_01_02 (1 << MAX98926_DAI_VMON_SLOT_SHIFT) 566*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_02_03 (2 << MAX98926_DAI_VMON_SLOT_SHIFT) 567*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_03_04 (3 << MAX98926_DAI_VMON_SLOT_SHIFT) 568*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_04_05 (4 << MAX98926_DAI_VMON_SLOT_SHIFT) 569*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_05_06 (5 << MAX98926_DAI_VMON_SLOT_SHIFT) 570*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_06_07 (6 << MAX98926_DAI_VMON_SLOT_SHIFT) 571*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_07_08 (7 << MAX98926_DAI_VMON_SLOT_SHIFT) 572*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_08_09 (8 << MAX98926_DAI_VMON_SLOT_SHIFT) 573*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_09_0A (9 << MAX98926_DAI_VMON_SLOT_SHIFT) 574*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_0A_0B (10 << MAX98926_DAI_VMON_SLOT_SHIFT) 575*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_0B_0C (11 << MAX98926_DAI_VMON_SLOT_SHIFT) 576*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_0C_0D (12 << MAX98926_DAI_VMON_SLOT_SHIFT) 577*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_0D_0E (13 << MAX98926_DAI_VMON_SLOT_SHIFT) 578*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_0E_0F (14 << MAX98926_DAI_VMON_SLOT_SHIFT) 579*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_0F_10 (15 << MAX98926_DAI_VMON_SLOT_SHIFT) 580*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_10_11 (16 << MAX98926_DAI_VMON_SLOT_SHIFT) 581*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_11_12 (17 << MAX98926_DAI_VMON_SLOT_SHIFT) 582*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_12_13 (18 << MAX98926_DAI_VMON_SLOT_SHIFT) 583*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_13_14 (19 << MAX98926_DAI_VMON_SLOT_SHIFT) 584*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_14_15 (20 << MAX98926_DAI_VMON_SLOT_SHIFT) 585*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_15_16 (21 << MAX98926_DAI_VMON_SLOT_SHIFT) 586*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_16_17 (22 << MAX98926_DAI_VMON_SLOT_SHIFT) 587*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_17_18 (23 << MAX98926_DAI_VMON_SLOT_SHIFT) 588*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_18_19 (24 << MAX98926_DAI_VMON_SLOT_SHIFT) 589*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_19_1A (25 << MAX98926_DAI_VMON_SLOT_SHIFT) 590*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_1A_1B (26 << MAX98926_DAI_VMON_SLOT_SHIFT) 591*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_1B_1C (27 << MAX98926_DAI_VMON_SLOT_SHIFT) 592*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_1C_1D (28 << MAX98926_DAI_VMON_SLOT_SHIFT) 593*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_1D_1E (29 << MAX98926_DAI_VMON_SLOT_SHIFT) 594*4882a593Smuzhiyun #define MAX98926_DAI_VMON_SLOT_1E_1F (30 << MAX98926_DAI_VMON_SLOT_SHIFT) 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun /* MAX98926_R023_DOUT_CFG_IMON */ 597*4882a593Smuzhiyun #define MAX98926_DAI_IMON_EN_MASK (1<<5) 598*4882a593Smuzhiyun #define MAX98926_DAI_IMON_EN_SHIFT 5 599*4882a593Smuzhiyun #define MAX98926_DAI_IMON_EN_WIDTH 1 600*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_MASK (0x1F<<0) 601*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_SHIFT 0 602*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_WIDTH 5 603*4882a593Smuzhiyun 604*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_00_01 (0 << MAX98926_DAI_IMON_SLOT_SHIFT) 605*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_01_02 (1 << MAX98926_DAI_IMON_SLOT_SHIFT) 606*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_02_03 (2 << MAX98926_DAI_IMON_SLOT_SHIFT) 607*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_03_04 (3 << MAX98926_DAI_IMON_SLOT_SHIFT) 608*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_04_05 (4 << MAX98926_DAI_IMON_SLOT_SHIFT) 609*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_05_06 (5 << MAX98926_DAI_IMON_SLOT_SHIFT) 610*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_06_07 (6 << MAX98926_DAI_IMON_SLOT_SHIFT) 611*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_07_08 (7 << MAX98926_DAI_IMON_SLOT_SHIFT) 612*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_08_09 (8 << MAX98926_DAI_IMON_SLOT_SHIFT) 613*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_09_0A (9 << MAX98926_DAI_IMON_SLOT_SHIFT) 614*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_0A_0B (10 << MAX98926_DAI_IMON_SLOT_SHIFT) 615*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_0B_0C (11 << MAX98926_DAI_IMON_SLOT_SHIFT) 616*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_0C_0D (12 << MAX98926_DAI_IMON_SLOT_SHIFT) 617*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_0D_0E (13 << MAX98926_DAI_IMON_SLOT_SHIFT) 618*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_0E_0F (14 << MAX98926_DAI_IMON_SLOT_SHIFT) 619*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_0F_10 (15 << MAX98926_DAI_IMON_SLOT_SHIFT) 620*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_10_11 (16 << MAX98926_DAI_IMON_SLOT_SHIFT) 621*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_11_12 (17 << MAX98926_DAI_IMON_SLOT_SHIFT) 622*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_12_13 (18 << MAX98926_DAI_IMON_SLOT_SHIFT) 623*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_13_14 (19 << MAX98926_DAI_IMON_SLOT_SHIFT) 624*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_14_15 (20 << MAX98926_DAI_IMON_SLOT_SHIFT) 625*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_15_16 (21 << MAX98926_DAI_IMON_SLOT_SHIFT) 626*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_16_17 (22 << MAX98926_DAI_IMON_SLOT_SHIFT) 627*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_17_18 (23 << MAX98926_DAI_IMON_SLOT_SHIFT) 628*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_18_19 (24 << MAX98926_DAI_IMON_SLOT_SHIFT) 629*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_19_1A (25 << MAX98926_DAI_IMON_SLOT_SHIFT) 630*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_1A_1B (26 << MAX98926_DAI_IMON_SLOT_SHIFT) 631*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_1B_1C (27 << MAX98926_DAI_IMON_SLOT_SHIFT) 632*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_1C_1D (28 << MAX98926_DAI_IMON_SLOT_SHIFT) 633*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_1D_1E (29 << MAX98926_DAI_IMON_SLOT_SHIFT) 634*4882a593Smuzhiyun #define MAX98926_DAI_IMON_SLOT_1E_1F (30 << MAX98926_DAI_IMON_SLOT_SHIFT) 635*4882a593Smuzhiyun 636*4882a593Smuzhiyun /* MAX98926_R024_DOUT_CFG_VBAT */ 637*4882a593Smuzhiyun #define MAX98926_DAI_INTERLEAVE_SLOT_MASK (0x1F<<0) 638*4882a593Smuzhiyun #define MAX98926_DAI_INTERLEAVE_SLOT_SHIFT 0 639*4882a593Smuzhiyun #define MAX98926_DAI_INTERLEAVE_SLOT_WIDTH 5 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun /* MAX98926_R025_DOUT_CFG_VBST */ 642*4882a593Smuzhiyun #define MAX98926_DAI_VBST_EN_MASK (1<<5) 643*4882a593Smuzhiyun #define MAX98926_DAI_VBST_EN_SHIFT 5 644*4882a593Smuzhiyun #define MAX98926_DAI_VBST_EN_WIDTH 1 645*4882a593Smuzhiyun #define MAX98926_DAI_VBST_SLOT_MASK (0x1F<<0) 646*4882a593Smuzhiyun #define MAX98926_DAI_VBST_SLOT_SHIFT 0 647*4882a593Smuzhiyun #define MAX98926_DAI_VBST_SLOT_WIDTH 5 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun /* MAX98926_R026_DOUT_CFG_FLAG */ 650*4882a593Smuzhiyun #define MAX98926_DAI_FLAG_EN_MASK (1<<5) 651*4882a593Smuzhiyun #define MAX98926_DAI_FLAG_EN_SHIFT 5 652*4882a593Smuzhiyun #define MAX98926_DAI_FLAG_EN_WIDTH 1 653*4882a593Smuzhiyun #define MAX98926_DAI_FLAG_SLOT_MASK (0x1F<<0) 654*4882a593Smuzhiyun #define MAX98926_DAI_FLAG_SLOT_SHIFT 0 655*4882a593Smuzhiyun #define MAX98926_DAI_FLAG_SLOT_WIDTH 5 656*4882a593Smuzhiyun 657*4882a593Smuzhiyun /* MAX98926_R027_DOUT_HIZ_CFG1 */ 658*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0) 659*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG1_SHIFT 0 660*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG1_WIDTH 8 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun /* MAX98926_R028_DOUT_HIZ_CFG2 */ 663*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0) 664*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG2_SHIFT 0 665*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG2_WIDTH 8 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun /* MAX98926_R029_DOUT_HIZ_CFG3 */ 668*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0) 669*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG3_SHIFT 0 670*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG3_WIDTH 8 671*4882a593Smuzhiyun 672*4882a593Smuzhiyun /* MAX98926_R02A_DOUT_HIZ_CFG4 */ 673*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0) 674*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG4_SHIFT 0 675*4882a593Smuzhiyun #define MAX98926_DAI_SLOT_HIZ_CFG4_WIDTH 8 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun /* MAX98926_R02B_DOUT_DRV_STRENGTH */ 678*4882a593Smuzhiyun #define MAX98926_DAI_OUT_DRIVE_MASK (0x03<<0) 679*4882a593Smuzhiyun #define MAX98926_DAI_OUT_DRIVE_SHIFT 0 680*4882a593Smuzhiyun #define MAX98926_DAI_OUT_DRIVE_WIDTH 2 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun /* MAX98926_R02C_FILTERS */ 683*4882a593Smuzhiyun #define MAX98926_ADC_DITHER_EN_MASK (1<<7) 684*4882a593Smuzhiyun #define MAX98926_ADC_DITHER_EN_SHIFT 7 685*4882a593Smuzhiyun #define MAX98926_ADC_DITHER_EN_WIDTH 1 686*4882a593Smuzhiyun #define MAX98926_IV_DCB_EN_MASK (1<<6) 687*4882a593Smuzhiyun #define MAX98926_IV_DCB_EN_SHIFT 6 688*4882a593Smuzhiyun #define MAX98926_IV_DCB_EN_WIDTH 1 689*4882a593Smuzhiyun #define MAX98926_DAC_DITHER_EN_MASK (1<<4) 690*4882a593Smuzhiyun #define MAX98926_DAC_DITHER_EN_SHIFT 4 691*4882a593Smuzhiyun #define MAX98926_DAC_DITHER_EN_WIDTH 1 692*4882a593Smuzhiyun #define MAX98926_DAC_FILTER_MODE_MASK (1<<3) 693*4882a593Smuzhiyun #define MAX98926_DAC_FILTER_MODE_SHIFT 3 694*4882a593Smuzhiyun #define MAX98926_DAC_FILTER_MODE_WIDTH 1 695*4882a593Smuzhiyun #define MAX98926_DAC_HPF_MASK (0x07<<0) 696*4882a593Smuzhiyun #define MAX98926_DAC_HPF_SHIFT 0 697*4882a593Smuzhiyun #define MAX98926_DAC_HPF_WIDTH 3 698*4882a593Smuzhiyun #define MAX98926_DAC_HPF_DISABLE (0 << MAX98926_DAC_HPF_SHIFT) 699*4882a593Smuzhiyun #define MAX98926_DAC_HPF_DC_BLOCK (1 << MAX98926_DAC_HPF_SHIFT) 700*4882a593Smuzhiyun #define MAX98926_DAC_HPF_EN_100 (2 << MAX98926_DAC_HPF_SHIFT) 701*4882a593Smuzhiyun #define MAX98926_DAC_HPF_EN_200 (3 << MAX98926_DAC_HPF_SHIFT) 702*4882a593Smuzhiyun #define MAX98926_DAC_HPF_EN_400 (4 << MAX98926_DAC_HPF_SHIFT) 703*4882a593Smuzhiyun #define MAX98926_DAC_HPF_EN_800 (5 << MAX98926_DAC_HPF_SHIFT) 704*4882a593Smuzhiyun 705*4882a593Smuzhiyun /* MAX98926_R02D_GAIN */ 706*4882a593Smuzhiyun #define MAX98926_DAC_IN_SEL_MASK (0x03<<5) 707*4882a593Smuzhiyun #define MAX98926_DAC_IN_SEL_SHIFT 5 708*4882a593Smuzhiyun #define MAX98926_DAC_IN_SEL_WIDTH 2 709*4882a593Smuzhiyun #define MAX98926_SPK_GAIN_MASK (0x1F<<0) 710*4882a593Smuzhiyun #define MAX98926_SPK_GAIN_SHIFT 0 711*4882a593Smuzhiyun #define MAX98926_SPK_GAIN_WIDTH 5 712*4882a593Smuzhiyun 713*4882a593Smuzhiyun #define MAX98926_DAC_IN_SEL_LEFT_DAI (0 << MAX98926_DAC_IN_SEL_SHIFT) 714*4882a593Smuzhiyun #define MAX98926_DAC_IN_SEL_RIGHT_DAI (1 << MAX98926_DAC_IN_SEL_SHIFT) 715*4882a593Smuzhiyun #define MAX98926_DAC_IN_SEL_SUMMED_DAI (2 << MAX98926_DAC_IN_SEL_SHIFT) 716*4882a593Smuzhiyun #define MAX98926_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << MAX98926_DAC_IN_SEL_SHIFT) 717*4882a593Smuzhiyun 718*4882a593Smuzhiyun /* MAX98926_R02E_GAIN_RAMPING */ 719*4882a593Smuzhiyun #define MAX98926_SPK_RMP_EN_MASK (1<<1) 720*4882a593Smuzhiyun #define MAX98926_SPK_RMP_EN_SHIFT 1 721*4882a593Smuzhiyun #define MAX98926_SPK_RMP_EN_WIDTH 1 722*4882a593Smuzhiyun #define MAX98926_SPK_ZCD_EN_MASK (1<<0) 723*4882a593Smuzhiyun #define MAX98926_SPK_ZCD_EN_SHIFT 0 724*4882a593Smuzhiyun #define MAX98926_SPK_ZCD_EN_WIDTH 1 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun /* MAX98926_R02F_SPK_AMP */ 727*4882a593Smuzhiyun #define MAX98926_SPK_MODE_MASK (1<<0) 728*4882a593Smuzhiyun #define MAX98926_SPK_MODE_SHIFT 0 729*4882a593Smuzhiyun #define MAX98926_SPK_MODE_WIDTH 1 730*4882a593Smuzhiyun #define MAX98926_INSELECT_MODE_MASK (1<<1) 731*4882a593Smuzhiyun #define MAX98926_INSELECT_MODE_SHIFT 1 732*4882a593Smuzhiyun #define MAX98926_INSELECT_MODE_WIDTH 1 733*4882a593Smuzhiyun 734*4882a593Smuzhiyun /* MAX98926_R030_THRESHOLD */ 735*4882a593Smuzhiyun #define MAX98926_ALC_EN_MASK (1<<5) 736*4882a593Smuzhiyun #define MAX98926_ALC_EN_SHIFT 5 737*4882a593Smuzhiyun #define MAX98926_ALC_EN_WIDTH 1 738*4882a593Smuzhiyun #define MAX98926_ALC_TH_MASK (0x1F<<0) 739*4882a593Smuzhiyun #define MAX98926_ALC_TH_SHIFT 0 740*4882a593Smuzhiyun #define MAX98926_ALC_TH_WIDTH 5 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun /* MAX98926_R031_ALC_ATTACK */ 743*4882a593Smuzhiyun #define MAX98926_ALC_ATK_STEP_MASK (0x0F<<4) 744*4882a593Smuzhiyun #define MAX98926_ALC_ATK_STEP_SHIFT 4 745*4882a593Smuzhiyun #define MAX98926_ALC_ATK_STEP_WIDTH 4 746*4882a593Smuzhiyun #define MAX98926_ALC_ATK_RATE_MASK (0x7<<0) 747*4882a593Smuzhiyun #define MAX98926_ALC_ATK_RATE_SHIFT 0 748*4882a593Smuzhiyun #define MAX98926_ALC_ATK_RATE_WIDTH 3 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun /* MAX98926_R032_ALC_ATTEN_RLS */ 751*4882a593Smuzhiyun #define MAX98926_ALC_MAX_ATTEN_MASK (0x0F<<4) 752*4882a593Smuzhiyun #define MAX98926_ALC_MAX_ATTEN_SHIFT 4 753*4882a593Smuzhiyun #define MAX98926_ALC_MAX_ATTEN_WIDTH 4 754*4882a593Smuzhiyun #define MAX98926_ALC_RLS_RATE_MASK (0x7<<0) 755*4882a593Smuzhiyun #define MAX98926_ALC_RLS_RATE_SHIFT 0 756*4882a593Smuzhiyun #define MAX98926_ALC_RLS_RATE_WIDTH 3 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun /* MAX98926_R033_ALC_HOLD_RLS */ 759*4882a593Smuzhiyun #define MAX98926_ALC_RLS_TGR_MASK (1<<0) 760*4882a593Smuzhiyun #define MAX98926_ALC_RLS_TGR_SHIFT 0 761*4882a593Smuzhiyun #define MAX98926_ALC_RLS_TGR_WIDTH 1 762*4882a593Smuzhiyun 763*4882a593Smuzhiyun /* MAX98926_R034_ALC_CONFIGURATION */ 764*4882a593Smuzhiyun #define MAX98926_ALC_MUTE_EN_MASK (1<<7) 765*4882a593Smuzhiyun #define MAX98926_ALC_MUTE_EN_SHIFT 7 766*4882a593Smuzhiyun #define MAX98926_ALC_MUTE_EN_WIDTH 1 767*4882a593Smuzhiyun #define MAX98926_ALC_MUTE_DLY_MASK (0x07<<4) 768*4882a593Smuzhiyun #define MAX98926_ALC_MUTE_DLY_SHIFT 4 769*4882a593Smuzhiyun #define MAX98926_ALC_MUTE_DLY_WIDTH 3 770*4882a593Smuzhiyun #define MAX98926_ALC_RLS_DBT_MASK (0x07<<0) 771*4882a593Smuzhiyun #define MAX98926_ALC_RLS_DBT_SHIFT 0 772*4882a593Smuzhiyun #define MAX98926_ALC_RLS_DBT_WIDTH 3 773*4882a593Smuzhiyun 774*4882a593Smuzhiyun /* MAX98926_R035_BOOST_CONVERTER */ 775*4882a593Smuzhiyun #define MAX98926_BST_SYNC_MASK (1<<7) 776*4882a593Smuzhiyun #define MAX98926_BST_SYNC_SHIFT 7 777*4882a593Smuzhiyun #define MAX98926_BST_SYNC_WIDTH 1 778*4882a593Smuzhiyun #define MAX98926_BST_PHASE_MASK (0x03<<4) 779*4882a593Smuzhiyun #define MAX98926_BST_PHASE_SHIFT 4 780*4882a593Smuzhiyun #define MAX98926_BST_PHASE_WIDTH 2 781*4882a593Smuzhiyun #define MAX98926_BST_SKIP_MODE_MASK (0x03<<0) 782*4882a593Smuzhiyun #define MAX98926_BST_SKIP_MODE_SHIFT 0 783*4882a593Smuzhiyun #define MAX98926_BST_SKIP_MODE_WIDTH 2 784*4882a593Smuzhiyun 785*4882a593Smuzhiyun /* MAX98926_R036_BLOCK_ENABLE */ 786*4882a593Smuzhiyun #define MAX98926_BST_EN_MASK (1<<7) 787*4882a593Smuzhiyun #define MAX98926_BST_EN_SHIFT 7 788*4882a593Smuzhiyun #define MAX98926_BST_EN_WIDTH 1 789*4882a593Smuzhiyun #define MAX98926_WATCH_EN_MASK (1<<6) 790*4882a593Smuzhiyun #define MAX98926_WATCH_EN_SHIFT 6 791*4882a593Smuzhiyun #define MAX98926_WATCH_EN_WIDTH 1 792*4882a593Smuzhiyun #define MAX98926_CLKMON_EN_MASK (1<<5) 793*4882a593Smuzhiyun #define MAX98926_CLKMON_EN_SHIFT 5 794*4882a593Smuzhiyun #define MAX98926_CLKMON_EN_WIDTH 1 795*4882a593Smuzhiyun #define MAX98926_SPK_EN_MASK (1<<4) 796*4882a593Smuzhiyun #define MAX98926_SPK_EN_SHIFT 4 797*4882a593Smuzhiyun #define MAX98926_SPK_EN_WIDTH 1 798*4882a593Smuzhiyun #define MAX98926_ADC_VBST_EN_MASK (1<<3) 799*4882a593Smuzhiyun #define MAX98926_ADC_VBST_EN_SHIFT 3 800*4882a593Smuzhiyun #define MAX98926_ADC_VBST_EN_WIDTH 1 801*4882a593Smuzhiyun #define MAX98926_ADC_VBAT_EN_MASK (1<<2) 802*4882a593Smuzhiyun #define MAX98926_ADC_VBAT_EN_SHIFT 2 803*4882a593Smuzhiyun #define MAX98926_ADC_VBAT_EN_WIDTH 1 804*4882a593Smuzhiyun #define MAX98926_ADC_IMON_EN_MASK (1<<1) 805*4882a593Smuzhiyun #define MAX98926_ADC_IMON_EN_SHIFT 1 806*4882a593Smuzhiyun #define MAX98926_ADC_IMON_EN_WIDTH 1 807*4882a593Smuzhiyun #define MAX98926_ADC_VMON_EN_MASK (1<<0) 808*4882a593Smuzhiyun #define MAX98926_ADC_VMON_EN_SHIFT 0 809*4882a593Smuzhiyun #define MAX98926_ADC_VMON_EN_WIDTH 1 810*4882a593Smuzhiyun 811*4882a593Smuzhiyun /* MAX98926_R037_CONFIGURATION */ 812*4882a593Smuzhiyun #define MAX98926_BST_VOUT_MASK (0x0F<<4) 813*4882a593Smuzhiyun #define MAX98926_BST_VOUT_SHIFT 4 814*4882a593Smuzhiyun #define MAX98926_BST_VOUT_WIDTH 4 815*4882a593Smuzhiyun #define MAX98926_THERMWARN_LEVEL_MASK (0x03<<2) 816*4882a593Smuzhiyun #define MAX98926_THERMWARN_LEVEL_SHIFT 2 817*4882a593Smuzhiyun #define MAX98926_THERMWARN_LEVEL_WIDTH 2 818*4882a593Smuzhiyun #define MAX98926_WATCH_TIME_MASK (0x03<<0) 819*4882a593Smuzhiyun #define MAX98926_WATCH_TIME_SHIFT 0 820*4882a593Smuzhiyun #define MAX98926_WATCH_TIME_WIDTH 2 821*4882a593Smuzhiyun 822*4882a593Smuzhiyun /* MAX98926_R038_GLOBAL_ENABLE */ 823*4882a593Smuzhiyun #define MAX98926_EN_MASK (1<<7) 824*4882a593Smuzhiyun #define MAX98926_EN_SHIFT 7 825*4882a593Smuzhiyun #define MAX98926_EN_WIDTH 1 826*4882a593Smuzhiyun 827*4882a593Smuzhiyun /* MAX98926_R03A_BOOST_LIMITER */ 828*4882a593Smuzhiyun #define MAX98926_BST_ILIM_MASK (0xF<<4) 829*4882a593Smuzhiyun #define MAX98926_BST_ILIM_SHIFT 4 830*4882a593Smuzhiyun #define MAX98926_BST_ILIM_WIDTH 4 831*4882a593Smuzhiyun 832*4882a593Smuzhiyun /* MAX98926_R0FF_VERSION */ 833*4882a593Smuzhiyun #define MAX98926_REV_ID_MASK (0xFF<<0) 834*4882a593Smuzhiyun #define MAX98926_REV_ID_SHIFT 0 835*4882a593Smuzhiyun #define MAX98926_REV_ID_WIDTH 8 836*4882a593Smuzhiyun 837*4882a593Smuzhiyun struct max98926_priv { 838*4882a593Smuzhiyun struct regmap *regmap; 839*4882a593Smuzhiyun struct snd_soc_component *component; 840*4882a593Smuzhiyun unsigned int sysclk; 841*4882a593Smuzhiyun unsigned int v_slot; 842*4882a593Smuzhiyun unsigned int i_slot; 843*4882a593Smuzhiyun unsigned int ch_size; 844*4882a593Smuzhiyun unsigned int interleave_mode; 845*4882a593Smuzhiyun }; 846*4882a593Smuzhiyun #endif 847