1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * max98926.c -- ALSA SoC MAX98926 driver
4*4882a593Smuzhiyun * Copyright 2013-15 Maxim Integrated Products
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun #include <linux/i2c.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/cdev.h>
12*4882a593Smuzhiyun #include <sound/pcm.h>
13*4882a593Smuzhiyun #include <sound/pcm_params.h>
14*4882a593Smuzhiyun #include <sound/soc.h>
15*4882a593Smuzhiyun #include <sound/tlv.h>
16*4882a593Smuzhiyun #include "max98926.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static const char * const max98926_boost_voltage_txt[] = {
19*4882a593Smuzhiyun "8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
20*4882a593Smuzhiyun "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static const char *const max98926_pdm_ch_text[] = {
24*4882a593Smuzhiyun "Current", "Voltage",
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static const char *const max98926_hpf_cutoff_txt[] = {
28*4882a593Smuzhiyun "Disable", "DC Block", "100Hz",
29*4882a593Smuzhiyun "200Hz", "400Hz", "800Hz",
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const struct reg_default max98926_reg[] = {
33*4882a593Smuzhiyun { 0x0B, 0x00 }, /* IRQ Enable0 */
34*4882a593Smuzhiyun { 0x0C, 0x00 }, /* IRQ Enable1 */
35*4882a593Smuzhiyun { 0x0D, 0x00 }, /* IRQ Enable2 */
36*4882a593Smuzhiyun { 0x0E, 0x00 }, /* IRQ Clear0 */
37*4882a593Smuzhiyun { 0x0F, 0x00 }, /* IRQ Clear1 */
38*4882a593Smuzhiyun { 0x10, 0x00 }, /* IRQ Clear2 */
39*4882a593Smuzhiyun { 0x11, 0xC0 }, /* Map0 */
40*4882a593Smuzhiyun { 0x12, 0x00 }, /* Map1 */
41*4882a593Smuzhiyun { 0x13, 0x00 }, /* Map2 */
42*4882a593Smuzhiyun { 0x14, 0xF0 }, /* Map3 */
43*4882a593Smuzhiyun { 0x15, 0x00 }, /* Map4 */
44*4882a593Smuzhiyun { 0x16, 0xAB }, /* Map5 */
45*4882a593Smuzhiyun { 0x17, 0x89 }, /* Map6 */
46*4882a593Smuzhiyun { 0x18, 0x00 }, /* Map7 */
47*4882a593Smuzhiyun { 0x19, 0x00 }, /* Map8 */
48*4882a593Smuzhiyun { 0x1A, 0x04 }, /* DAI Clock Mode 1 */
49*4882a593Smuzhiyun { 0x1B, 0x00 }, /* DAI Clock Mode 2 */
50*4882a593Smuzhiyun { 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
51*4882a593Smuzhiyun { 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
52*4882a593Smuzhiyun { 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
53*4882a593Smuzhiyun { 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
54*4882a593Smuzhiyun { 0x20, 0x50 }, /* Format */
55*4882a593Smuzhiyun { 0x21, 0x00 }, /* TDM Slot Select */
56*4882a593Smuzhiyun { 0x22, 0x00 }, /* DOUT Configuration VMON */
57*4882a593Smuzhiyun { 0x23, 0x00 }, /* DOUT Configuration IMON */
58*4882a593Smuzhiyun { 0x24, 0x00 }, /* DOUT Configuration VBAT */
59*4882a593Smuzhiyun { 0x25, 0x00 }, /* DOUT Configuration VBST */
60*4882a593Smuzhiyun { 0x26, 0x00 }, /* DOUT Configuration FLAG */
61*4882a593Smuzhiyun { 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
62*4882a593Smuzhiyun { 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
63*4882a593Smuzhiyun { 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
64*4882a593Smuzhiyun { 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
65*4882a593Smuzhiyun { 0x2B, 0x02 }, /* DOUT Drive Strength */
66*4882a593Smuzhiyun { 0x2C, 0x90 }, /* Filters */
67*4882a593Smuzhiyun { 0x2D, 0x00 }, /* Gain */
68*4882a593Smuzhiyun { 0x2E, 0x02 }, /* Gain Ramping */
69*4882a593Smuzhiyun { 0x2F, 0x00 }, /* Speaker Amplifier */
70*4882a593Smuzhiyun { 0x30, 0x0A }, /* Threshold */
71*4882a593Smuzhiyun { 0x31, 0x00 }, /* ALC Attack */
72*4882a593Smuzhiyun { 0x32, 0x80 }, /* ALC Atten and Release */
73*4882a593Smuzhiyun { 0x33, 0x00 }, /* ALC Infinite Hold Release */
74*4882a593Smuzhiyun { 0x34, 0x92 }, /* ALC Configuration */
75*4882a593Smuzhiyun { 0x35, 0x01 }, /* Boost Converter */
76*4882a593Smuzhiyun { 0x36, 0x00 }, /* Block Enable */
77*4882a593Smuzhiyun { 0x37, 0x00 }, /* Configuration */
78*4882a593Smuzhiyun { 0x38, 0x00 }, /* Global Enable */
79*4882a593Smuzhiyun { 0x3A, 0x00 }, /* Boost Limiter */
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const struct soc_enum max98926_voltage_enum[] = {
83*4882a593Smuzhiyun SOC_ENUM_SINGLE(MAX98926_DAI_CLK_DIV_N_LSBS, 0,
84*4882a593Smuzhiyun ARRAY_SIZE(max98926_pdm_ch_text),
85*4882a593Smuzhiyun max98926_pdm_ch_text),
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static const struct snd_kcontrol_new max98926_voltage_control =
89*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", max98926_voltage_enum);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static const struct soc_enum max98926_current_enum[] = {
92*4882a593Smuzhiyun SOC_ENUM_SINGLE(MAX98926_DAI_CLK_DIV_N_LSBS,
93*4882a593Smuzhiyun MAX98926_PDM_SOURCE_1_SHIFT,
94*4882a593Smuzhiyun ARRAY_SIZE(max98926_pdm_ch_text),
95*4882a593Smuzhiyun max98926_pdm_ch_text),
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static const struct snd_kcontrol_new max98926_current_control =
99*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", max98926_current_enum);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const struct snd_kcontrol_new max98926_mixer_controls[] = {
102*4882a593Smuzhiyun SOC_DAPM_SINGLE("PCM Single Switch", MAX98926_SPK_AMP,
103*4882a593Smuzhiyun MAX98926_INSELECT_MODE_SHIFT, 0, 0),
104*4882a593Smuzhiyun SOC_DAPM_SINGLE("PDM Single Switch", MAX98926_SPK_AMP,
105*4882a593Smuzhiyun MAX98926_INSELECT_MODE_SHIFT, 1, 0),
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const struct snd_kcontrol_new max98926_dai_controls[] = {
109*4882a593Smuzhiyun SOC_DAPM_SINGLE("Left", MAX98926_GAIN,
110*4882a593Smuzhiyun MAX98926_DAC_IN_SEL_SHIFT, 0, 0),
111*4882a593Smuzhiyun SOC_DAPM_SINGLE("Right", MAX98926_GAIN,
112*4882a593Smuzhiyun MAX98926_DAC_IN_SEL_SHIFT, 1, 0),
113*4882a593Smuzhiyun SOC_DAPM_SINGLE("LeftRight", MAX98926_GAIN,
114*4882a593Smuzhiyun MAX98926_DAC_IN_SEL_SHIFT, 2, 0),
115*4882a593Smuzhiyun SOC_DAPM_SINGLE("(Left+Right)/2 Switch", MAX98926_GAIN,
116*4882a593Smuzhiyun MAX98926_DAC_IN_SEL_SHIFT, 3, 0),
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun static const struct snd_soc_dapm_widget max98926_dapm_widgets[] = {
120*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0,
121*4882a593Smuzhiyun SND_SOC_NOPM, 0, 0),
122*4882a593Smuzhiyun SND_SOC_DAPM_DAC("Amp Enable", NULL, MAX98926_BLOCK_ENABLE,
123*4882a593Smuzhiyun MAX98926_SPK_EN_SHIFT, 0),
124*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Global Enable", MAX98926_GLOBAL_ENABLE,
125*4882a593Smuzhiyun MAX98926_EN_SHIFT, 0, NULL, 0),
126*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("VI Enable", MAX98926_BLOCK_ENABLE,
127*4882a593Smuzhiyun MAX98926_ADC_IMON_EN_WIDTH |
128*4882a593Smuzhiyun MAX98926_ADC_VMON_EN_SHIFT,
129*4882a593Smuzhiyun 0, NULL, 0),
130*4882a593Smuzhiyun SND_SOC_DAPM_PGA("BST Enable", MAX98926_BLOCK_ENABLE,
131*4882a593Smuzhiyun MAX98926_BST_EN_SHIFT, 0, NULL, 0),
132*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("BE_OUT"),
133*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("PCM Sel", MAX98926_SPK_AMP,
134*4882a593Smuzhiyun MAX98926_INSELECT_MODE_SHIFT, 0,
135*4882a593Smuzhiyun &max98926_mixer_controls[0],
136*4882a593Smuzhiyun ARRAY_SIZE(max98926_mixer_controls)),
137*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("DAI Sel",
138*4882a593Smuzhiyun MAX98926_GAIN, MAX98926_DAC_IN_SEL_SHIFT, 0,
139*4882a593Smuzhiyun &max98926_dai_controls[0],
140*4882a593Smuzhiyun ARRAY_SIZE(max98926_dai_controls)),
141*4882a593Smuzhiyun SND_SOC_DAPM_MUX("PDM CH1 Source",
142*4882a593Smuzhiyun MAX98926_DAI_CLK_DIV_N_LSBS,
143*4882a593Smuzhiyun MAX98926_PDM_CURRENT_SHIFT,
144*4882a593Smuzhiyun 0, &max98926_current_control),
145*4882a593Smuzhiyun SND_SOC_DAPM_MUX("PDM CH0 Source",
146*4882a593Smuzhiyun MAX98926_DAI_CLK_DIV_N_LSBS,
147*4882a593Smuzhiyun MAX98926_PDM_VOLTAGE_SHIFT,
148*4882a593Smuzhiyun 0, &max98926_voltage_control),
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const struct snd_soc_dapm_route max98926_audio_map[] = {
152*4882a593Smuzhiyun {"VI Enable", NULL, "DAI_OUT"},
153*4882a593Smuzhiyun {"DAI Sel", "Left", "VI Enable"},
154*4882a593Smuzhiyun {"DAI Sel", "Right", "VI Enable"},
155*4882a593Smuzhiyun {"DAI Sel", "LeftRight", "VI Enable"},
156*4882a593Smuzhiyun {"DAI Sel", "LeftRightDiv2", "VI Enable"},
157*4882a593Smuzhiyun {"PCM Sel", "PCM", "DAI Sel"},
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun {"PDM CH1 Source", "Current", "DAI_OUT"},
160*4882a593Smuzhiyun {"PDM CH1 Source", "Voltage", "DAI_OUT"},
161*4882a593Smuzhiyun {"PDM CH0 Source", "Current", "DAI_OUT"},
162*4882a593Smuzhiyun {"PDM CH0 Source", "Voltage", "DAI_OUT"},
163*4882a593Smuzhiyun {"PCM Sel", "Analog", "PDM CH1 Source"},
164*4882a593Smuzhiyun {"PCM Sel", "Analog", "PDM CH0 Source"},
165*4882a593Smuzhiyun {"Amp Enable", NULL, "PCM Sel"},
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun {"BST Enable", NULL, "Amp Enable"},
168*4882a593Smuzhiyun {"BE_OUT", NULL, "BST Enable"},
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
max98926_volatile_register(struct device * dev,unsigned int reg)171*4882a593Smuzhiyun static bool max98926_volatile_register(struct device *dev, unsigned int reg)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun switch (reg) {
174*4882a593Smuzhiyun case MAX98926_VBAT_DATA:
175*4882a593Smuzhiyun case MAX98926_VBST_DATA:
176*4882a593Smuzhiyun case MAX98926_LIVE_STATUS0:
177*4882a593Smuzhiyun case MAX98926_LIVE_STATUS1:
178*4882a593Smuzhiyun case MAX98926_LIVE_STATUS2:
179*4882a593Smuzhiyun case MAX98926_STATE0:
180*4882a593Smuzhiyun case MAX98926_STATE1:
181*4882a593Smuzhiyun case MAX98926_STATE2:
182*4882a593Smuzhiyun case MAX98926_FLAG0:
183*4882a593Smuzhiyun case MAX98926_FLAG1:
184*4882a593Smuzhiyun case MAX98926_FLAG2:
185*4882a593Smuzhiyun case MAX98926_VERSION:
186*4882a593Smuzhiyun return true;
187*4882a593Smuzhiyun default:
188*4882a593Smuzhiyun return false;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
max98926_readable_register(struct device * dev,unsigned int reg)192*4882a593Smuzhiyun static bool max98926_readable_register(struct device *dev, unsigned int reg)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun switch (reg) {
195*4882a593Smuzhiyun case MAX98926_IRQ_CLEAR0:
196*4882a593Smuzhiyun case MAX98926_IRQ_CLEAR1:
197*4882a593Smuzhiyun case MAX98926_IRQ_CLEAR2:
198*4882a593Smuzhiyun case MAX98926_ALC_HOLD_RLS:
199*4882a593Smuzhiyun return false;
200*4882a593Smuzhiyun default:
201*4882a593Smuzhiyun return true;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(max98926_spk_tlv, -600, 100, 0);
206*4882a593Smuzhiyun static DECLARE_TLV_DB_RANGE(max98926_current_tlv,
207*4882a593Smuzhiyun 0, 11, TLV_DB_SCALE_ITEM(20, 20, 0),
208*4882a593Smuzhiyun 12, 15, TLV_DB_SCALE_ITEM(320, 40, 0),
209*4882a593Smuzhiyun );
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(max98926_dac_hpf_cutoff,
212*4882a593Smuzhiyun MAX98926_FILTERS, MAX98926_DAC_HPF_SHIFT,
213*4882a593Smuzhiyun max98926_hpf_cutoff_txt);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(max98926_boost_voltage,
216*4882a593Smuzhiyun MAX98926_CONFIGURATION, MAX98926_BST_VOUT_SHIFT,
217*4882a593Smuzhiyun max98926_boost_voltage_txt);
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun static const struct snd_kcontrol_new max98926_snd_controls[] = {
220*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker Volume", MAX98926_GAIN,
221*4882a593Smuzhiyun MAX98926_SPK_GAIN_SHIFT,
222*4882a593Smuzhiyun (1<<MAX98926_SPK_GAIN_WIDTH)-1, 0,
223*4882a593Smuzhiyun max98926_spk_tlv),
224*4882a593Smuzhiyun SOC_SINGLE("Ramp Switch", MAX98926_GAIN_RAMPING,
225*4882a593Smuzhiyun MAX98926_SPK_RMP_EN_SHIFT, 1, 0),
226*4882a593Smuzhiyun SOC_SINGLE("ZCD Switch", MAX98926_GAIN_RAMPING,
227*4882a593Smuzhiyun MAX98926_SPK_ZCD_EN_SHIFT, 1, 0),
228*4882a593Smuzhiyun SOC_SINGLE("ALC Switch", MAX98926_THRESHOLD,
229*4882a593Smuzhiyun MAX98926_ALC_EN_SHIFT, 1, 0),
230*4882a593Smuzhiyun SOC_SINGLE("ALC Threshold", MAX98926_THRESHOLD,
231*4882a593Smuzhiyun MAX98926_ALC_TH_SHIFT,
232*4882a593Smuzhiyun (1<<MAX98926_ALC_TH_WIDTH)-1, 0),
233*4882a593Smuzhiyun SOC_ENUM("Boost Output Voltage", max98926_boost_voltage),
234*4882a593Smuzhiyun SOC_SINGLE_TLV("Boost Current Limit", MAX98926_BOOST_LIMITER,
235*4882a593Smuzhiyun MAX98926_BST_ILIM_SHIFT,
236*4882a593Smuzhiyun (1<<MAX98926_BST_ILIM_SHIFT)-1, 0,
237*4882a593Smuzhiyun max98926_current_tlv),
238*4882a593Smuzhiyun SOC_ENUM("DAC HPF Cutoff", max98926_dac_hpf_cutoff),
239*4882a593Smuzhiyun SOC_DOUBLE("PDM Channel One", MAX98926_DAI_CLK_DIV_N_LSBS,
240*4882a593Smuzhiyun MAX98926_PDM_CHANNEL_1_SHIFT,
241*4882a593Smuzhiyun MAX98926_PDM_CHANNEL_1_HIZ, 1, 0),
242*4882a593Smuzhiyun SOC_DOUBLE("PDM Channel Zero", MAX98926_DAI_CLK_DIV_N_LSBS,
243*4882a593Smuzhiyun MAX98926_PDM_CHANNEL_0_SHIFT,
244*4882a593Smuzhiyun MAX98926_PDM_CHANNEL_0_HIZ, 1, 0),
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun static const struct {
248*4882a593Smuzhiyun int rate;
249*4882a593Smuzhiyun int sr;
250*4882a593Smuzhiyun } rate_table[] = {
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun .rate = 8000,
253*4882a593Smuzhiyun .sr = 0,
254*4882a593Smuzhiyun },
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun .rate = 11025,
257*4882a593Smuzhiyun .sr = 1,
258*4882a593Smuzhiyun },
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun .rate = 12000,
261*4882a593Smuzhiyun .sr = 2,
262*4882a593Smuzhiyun },
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun .rate = 16000,
265*4882a593Smuzhiyun .sr = 3,
266*4882a593Smuzhiyun },
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun .rate = 22050,
269*4882a593Smuzhiyun .sr = 4,
270*4882a593Smuzhiyun },
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun .rate = 24000,
273*4882a593Smuzhiyun .sr = 5,
274*4882a593Smuzhiyun },
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun .rate = 32000,
277*4882a593Smuzhiyun .sr = 6,
278*4882a593Smuzhiyun },
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun .rate = 44100,
281*4882a593Smuzhiyun .sr = 7,
282*4882a593Smuzhiyun },
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun .rate = 48000,
285*4882a593Smuzhiyun .sr = 8,
286*4882a593Smuzhiyun },
287*4882a593Smuzhiyun };
288*4882a593Smuzhiyun
max98926_set_sense_data(struct max98926_priv * max98926)289*4882a593Smuzhiyun static void max98926_set_sense_data(struct max98926_priv *max98926)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
292*4882a593Smuzhiyun MAX98926_DOUT_CFG_VMON,
293*4882a593Smuzhiyun MAX98926_DAI_VMON_EN_MASK,
294*4882a593Smuzhiyun MAX98926_DAI_VMON_EN_MASK);
295*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
296*4882a593Smuzhiyun MAX98926_DOUT_CFG_IMON,
297*4882a593Smuzhiyun MAX98926_DAI_IMON_EN_MASK,
298*4882a593Smuzhiyun MAX98926_DAI_IMON_EN_MASK);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (!max98926->interleave_mode) {
301*4882a593Smuzhiyun /* set VMON slots */
302*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
303*4882a593Smuzhiyun MAX98926_DOUT_CFG_VMON,
304*4882a593Smuzhiyun MAX98926_DAI_VMON_SLOT_MASK,
305*4882a593Smuzhiyun max98926->v_slot);
306*4882a593Smuzhiyun /* set IMON slots */
307*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
308*4882a593Smuzhiyun MAX98926_DOUT_CFG_IMON,
309*4882a593Smuzhiyun MAX98926_DAI_IMON_SLOT_MASK,
310*4882a593Smuzhiyun max98926->i_slot);
311*4882a593Smuzhiyun } else {
312*4882a593Smuzhiyun /* enable interleave mode */
313*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
314*4882a593Smuzhiyun MAX98926_FORMAT,
315*4882a593Smuzhiyun MAX98926_DAI_INTERLEAVE_MASK,
316*4882a593Smuzhiyun MAX98926_DAI_INTERLEAVE_MASK);
317*4882a593Smuzhiyun /* set interleave slots */
318*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
319*4882a593Smuzhiyun MAX98926_DOUT_CFG_VBAT,
320*4882a593Smuzhiyun MAX98926_DAI_INTERLEAVE_SLOT_MASK,
321*4882a593Smuzhiyun max98926->v_slot);
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
max98926_dai_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)325*4882a593Smuzhiyun static int max98926_dai_set_fmt(struct snd_soc_dai *codec_dai,
326*4882a593Smuzhiyun unsigned int fmt)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
329*4882a593Smuzhiyun struct max98926_priv *max98926 = snd_soc_component_get_drvdata(component);
330*4882a593Smuzhiyun unsigned int invert = 0;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
335*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
336*4882a593Smuzhiyun max98926_set_sense_data(max98926);
337*4882a593Smuzhiyun break;
338*4882a593Smuzhiyun default:
339*4882a593Smuzhiyun dev_err(component->dev, "DAI clock mode unsupported\n");
340*4882a593Smuzhiyun return -EINVAL;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
344*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
345*4882a593Smuzhiyun break;
346*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
347*4882a593Smuzhiyun invert = MAX98926_DAI_WCI_MASK;
348*4882a593Smuzhiyun break;
349*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
350*4882a593Smuzhiyun invert = MAX98926_DAI_BCI_MASK;
351*4882a593Smuzhiyun break;
352*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
353*4882a593Smuzhiyun invert = MAX98926_DAI_BCI_MASK | MAX98926_DAI_WCI_MASK;
354*4882a593Smuzhiyun break;
355*4882a593Smuzhiyun default:
356*4882a593Smuzhiyun dev_err(component->dev, "DAI invert mode unsupported\n");
357*4882a593Smuzhiyun return -EINVAL;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun regmap_write(max98926->regmap,
361*4882a593Smuzhiyun MAX98926_FORMAT, MAX98926_DAI_DLY_MASK);
362*4882a593Smuzhiyun regmap_update_bits(max98926->regmap, MAX98926_FORMAT,
363*4882a593Smuzhiyun MAX98926_DAI_BCI_MASK, invert);
364*4882a593Smuzhiyun return 0;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
max98926_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)367*4882a593Smuzhiyun static int max98926_dai_hw_params(struct snd_pcm_substream *substream,
368*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
369*4882a593Smuzhiyun struct snd_soc_dai *dai)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun int dai_sr = -EINVAL;
372*4882a593Smuzhiyun int rate = params_rate(params), i;
373*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
374*4882a593Smuzhiyun struct max98926_priv *max98926 = snd_soc_component_get_drvdata(component);
375*4882a593Smuzhiyun int blr_clk_ratio;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun switch (params_format(params)) {
378*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S16_LE:
379*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
380*4882a593Smuzhiyun MAX98926_FORMAT,
381*4882a593Smuzhiyun MAX98926_DAI_CHANSZ_MASK,
382*4882a593Smuzhiyun MAX98926_DAI_CHANSZ_16);
383*4882a593Smuzhiyun max98926->ch_size = 16;
384*4882a593Smuzhiyun break;
385*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S24_LE:
386*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
387*4882a593Smuzhiyun MAX98926_FORMAT,
388*4882a593Smuzhiyun MAX98926_DAI_CHANSZ_MASK,
389*4882a593Smuzhiyun MAX98926_DAI_CHANSZ_24);
390*4882a593Smuzhiyun max98926->ch_size = 24;
391*4882a593Smuzhiyun break;
392*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S32_LE:
393*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
394*4882a593Smuzhiyun MAX98926_FORMAT,
395*4882a593Smuzhiyun MAX98926_DAI_CHANSZ_MASK,
396*4882a593Smuzhiyun MAX98926_DAI_CHANSZ_32);
397*4882a593Smuzhiyun max98926->ch_size = 32;
398*4882a593Smuzhiyun break;
399*4882a593Smuzhiyun default:
400*4882a593Smuzhiyun dev_dbg(component->dev, "format unsupported %d\n",
401*4882a593Smuzhiyun params_format(params));
402*4882a593Smuzhiyun return -EINVAL;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun /* BCLK/LRCLK ratio calculation */
406*4882a593Smuzhiyun blr_clk_ratio = params_channels(params) * max98926->ch_size;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun switch (blr_clk_ratio) {
409*4882a593Smuzhiyun case 32:
410*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
411*4882a593Smuzhiyun MAX98926_DAI_CLK_MODE2,
412*4882a593Smuzhiyun MAX98926_DAI_BSEL_MASK,
413*4882a593Smuzhiyun MAX98926_DAI_BSEL_32);
414*4882a593Smuzhiyun break;
415*4882a593Smuzhiyun case 48:
416*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
417*4882a593Smuzhiyun MAX98926_DAI_CLK_MODE2,
418*4882a593Smuzhiyun MAX98926_DAI_BSEL_MASK,
419*4882a593Smuzhiyun MAX98926_DAI_BSEL_48);
420*4882a593Smuzhiyun break;
421*4882a593Smuzhiyun case 64:
422*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
423*4882a593Smuzhiyun MAX98926_DAI_CLK_MODE2,
424*4882a593Smuzhiyun MAX98926_DAI_BSEL_MASK,
425*4882a593Smuzhiyun MAX98926_DAI_BSEL_64);
426*4882a593Smuzhiyun break;
427*4882a593Smuzhiyun default:
428*4882a593Smuzhiyun return -EINVAL;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun /* find the closest rate */
432*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
433*4882a593Smuzhiyun if (rate_table[i].rate >= rate) {
434*4882a593Smuzhiyun dai_sr = rate_table[i].sr;
435*4882a593Smuzhiyun break;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun if (dai_sr < 0)
439*4882a593Smuzhiyun return -EINVAL;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun /* set DAI_SR to correct LRCLK frequency */
442*4882a593Smuzhiyun regmap_update_bits(max98926->regmap,
443*4882a593Smuzhiyun MAX98926_DAI_CLK_MODE2,
444*4882a593Smuzhiyun MAX98926_DAI_SR_MASK, dai_sr << MAX98926_DAI_SR_SHIFT);
445*4882a593Smuzhiyun return 0;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun #define MAX98926_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
449*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun static const struct snd_soc_dai_ops max98926_dai_ops = {
452*4882a593Smuzhiyun .set_fmt = max98926_dai_set_fmt,
453*4882a593Smuzhiyun .hw_params = max98926_dai_hw_params,
454*4882a593Smuzhiyun };
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun static struct snd_soc_dai_driver max98926_dai[] = {
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun .name = "max98926-aif1",
459*4882a593Smuzhiyun .playback = {
460*4882a593Smuzhiyun .stream_name = "HiFi Playback",
461*4882a593Smuzhiyun .channels_min = 1,
462*4882a593Smuzhiyun .channels_max = 2,
463*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_48000,
464*4882a593Smuzhiyun .formats = MAX98926_FORMATS,
465*4882a593Smuzhiyun },
466*4882a593Smuzhiyun .capture = {
467*4882a593Smuzhiyun .stream_name = "HiFi Capture",
468*4882a593Smuzhiyun .channels_min = 1,
469*4882a593Smuzhiyun .channels_max = 2,
470*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_48000,
471*4882a593Smuzhiyun .formats = MAX98926_FORMATS,
472*4882a593Smuzhiyun },
473*4882a593Smuzhiyun .ops = &max98926_dai_ops,
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun };
476*4882a593Smuzhiyun
max98926_probe(struct snd_soc_component * component)477*4882a593Smuzhiyun static int max98926_probe(struct snd_soc_component *component)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun struct max98926_priv *max98926 = snd_soc_component_get_drvdata(component);
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun max98926->component = component;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun /* Hi-Z all the slots */
484*4882a593Smuzhiyun regmap_write(max98926->regmap, MAX98926_DOUT_HIZ_CFG4, 0xF0);
485*4882a593Smuzhiyun return 0;
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_max98926 = {
489*4882a593Smuzhiyun .probe = max98926_probe,
490*4882a593Smuzhiyun .controls = max98926_snd_controls,
491*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(max98926_snd_controls),
492*4882a593Smuzhiyun .dapm_routes = max98926_audio_map,
493*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(max98926_audio_map),
494*4882a593Smuzhiyun .dapm_widgets = max98926_dapm_widgets,
495*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(max98926_dapm_widgets),
496*4882a593Smuzhiyun .idle_bias_on = 1,
497*4882a593Smuzhiyun .use_pmdown_time = 1,
498*4882a593Smuzhiyun .endianness = 1,
499*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
500*4882a593Smuzhiyun };
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun static const struct regmap_config max98926_regmap = {
503*4882a593Smuzhiyun .reg_bits = 8,
504*4882a593Smuzhiyun .val_bits = 8,
505*4882a593Smuzhiyun .max_register = MAX98926_VERSION,
506*4882a593Smuzhiyun .reg_defaults = max98926_reg,
507*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(max98926_reg),
508*4882a593Smuzhiyun .volatile_reg = max98926_volatile_register,
509*4882a593Smuzhiyun .readable_reg = max98926_readable_register,
510*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
511*4882a593Smuzhiyun };
512*4882a593Smuzhiyun
max98926_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)513*4882a593Smuzhiyun static int max98926_i2c_probe(struct i2c_client *i2c,
514*4882a593Smuzhiyun const struct i2c_device_id *id)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun int ret, reg;
517*4882a593Smuzhiyun u32 value;
518*4882a593Smuzhiyun struct max98926_priv *max98926;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun max98926 = devm_kzalloc(&i2c->dev,
521*4882a593Smuzhiyun sizeof(*max98926), GFP_KERNEL);
522*4882a593Smuzhiyun if (!max98926)
523*4882a593Smuzhiyun return -ENOMEM;
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun i2c_set_clientdata(i2c, max98926);
526*4882a593Smuzhiyun max98926->regmap = devm_regmap_init_i2c(i2c, &max98926_regmap);
527*4882a593Smuzhiyun if (IS_ERR(max98926->regmap)) {
528*4882a593Smuzhiyun ret = PTR_ERR(max98926->regmap);
529*4882a593Smuzhiyun dev_err(&i2c->dev,
530*4882a593Smuzhiyun "Failed to allocate regmap: %d\n", ret);
531*4882a593Smuzhiyun goto err_out;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun if (of_property_read_bool(i2c->dev.of_node, "interleave-mode"))
534*4882a593Smuzhiyun max98926->interleave_mode = true;
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
537*4882a593Smuzhiyun if (value > MAX98926_DAI_VMON_SLOT_1E_1F) {
538*4882a593Smuzhiyun dev_err(&i2c->dev, "vmon slot number is wrong:\n");
539*4882a593Smuzhiyun return -EINVAL;
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun max98926->v_slot = value;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
544*4882a593Smuzhiyun if (value > MAX98926_DAI_IMON_SLOT_1E_1F) {
545*4882a593Smuzhiyun dev_err(&i2c->dev, "imon slot number is wrong:\n");
546*4882a593Smuzhiyun return -EINVAL;
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun max98926->i_slot = value;
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun ret = regmap_read(max98926->regmap,
551*4882a593Smuzhiyun MAX98926_VERSION, ®);
552*4882a593Smuzhiyun if (ret < 0) {
553*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to read: %x\n", reg);
554*4882a593Smuzhiyun return ret;
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev,
558*4882a593Smuzhiyun &soc_component_dev_max98926,
559*4882a593Smuzhiyun max98926_dai, ARRAY_SIZE(max98926_dai));
560*4882a593Smuzhiyun if (ret < 0)
561*4882a593Smuzhiyun dev_err(&i2c->dev,
562*4882a593Smuzhiyun "Failed to register component: %d\n", ret);
563*4882a593Smuzhiyun dev_info(&i2c->dev, "device version: %x\n", reg);
564*4882a593Smuzhiyun err_out:
565*4882a593Smuzhiyun return ret;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun static const struct i2c_device_id max98926_i2c_id[] = {
569*4882a593Smuzhiyun { "max98926", 0 },
570*4882a593Smuzhiyun { }
571*4882a593Smuzhiyun };
572*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, max98926_i2c_id);
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun static const struct of_device_id max98926_of_match[] = {
575*4882a593Smuzhiyun { .compatible = "maxim,max98926", },
576*4882a593Smuzhiyun { }
577*4882a593Smuzhiyun };
578*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max98926_of_match);
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun static struct i2c_driver max98926_i2c_driver = {
581*4882a593Smuzhiyun .driver = {
582*4882a593Smuzhiyun .name = "max98926",
583*4882a593Smuzhiyun .of_match_table = of_match_ptr(max98926_of_match),
584*4882a593Smuzhiyun .pm = NULL,
585*4882a593Smuzhiyun },
586*4882a593Smuzhiyun .probe = max98926_i2c_probe,
587*4882a593Smuzhiyun .id_table = max98926_i2c_id,
588*4882a593Smuzhiyun };
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun module_i2c_driver(max98926_i2c_driver)
591*4882a593Smuzhiyun MODULE_DESCRIPTION("ALSA SoC MAX98926 driver");
592*4882a593Smuzhiyun MODULE_AUTHOR("Anish kumar <anish.kumar@maximintegrated.com>");
593*4882a593Smuzhiyun MODULE_LICENSE("GPL");
594