xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/max98925.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * max98925.c -- ALSA SoC Stereo MAX98925 driver
4*4882a593Smuzhiyun  * Copyright 2013-15 Maxim Integrated Products
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun #include <linux/i2c.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/cdev.h>
12*4882a593Smuzhiyun #include <sound/pcm.h>
13*4882a593Smuzhiyun #include <sound/pcm_params.h>
14*4882a593Smuzhiyun #include <sound/soc.h>
15*4882a593Smuzhiyun #include <sound/tlv.h>
16*4882a593Smuzhiyun #include "max98925.h"
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun static const char *const dai_text[] = {
19*4882a593Smuzhiyun 	"Left", "Right", "LeftRight", "LeftRightDiv2",
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun static const char * const max98925_boost_voltage_text[] = {
23*4882a593Smuzhiyun 	"8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
24*4882a593Smuzhiyun 	"6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V",	"6.5V", "6.5V"
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(max98925_boost_voltage,
28*4882a593Smuzhiyun 	MAX98925_CONFIGURATION, M98925_BST_VOUT_SHIFT,
29*4882a593Smuzhiyun 	max98925_boost_voltage_text);
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun static const char *const hpf_text[] = {
32*4882a593Smuzhiyun 	"Disable", "DC Block", "100Hz",	"200Hz", "400Hz", "800Hz",
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun static const struct reg_default max98925_reg[] = {
36*4882a593Smuzhiyun 	{ 0x0B, 0x00 }, /* IRQ Enable0 */
37*4882a593Smuzhiyun 	{ 0x0C, 0x00 }, /* IRQ Enable1 */
38*4882a593Smuzhiyun 	{ 0x0D, 0x00 }, /* IRQ Enable2 */
39*4882a593Smuzhiyun 	{ 0x0E, 0x00 }, /* IRQ Clear0 */
40*4882a593Smuzhiyun 	{ 0x0F, 0x00 }, /* IRQ Clear1 */
41*4882a593Smuzhiyun 	{ 0x10, 0x00 }, /* IRQ Clear2 */
42*4882a593Smuzhiyun 	{ 0x11, 0xC0 }, /* Map0 */
43*4882a593Smuzhiyun 	{ 0x12, 0x00 }, /* Map1 */
44*4882a593Smuzhiyun 	{ 0x13, 0x00 }, /* Map2 */
45*4882a593Smuzhiyun 	{ 0x14, 0xF0 }, /* Map3 */
46*4882a593Smuzhiyun 	{ 0x15, 0x00 }, /* Map4 */
47*4882a593Smuzhiyun 	{ 0x16, 0xAB }, /* Map5 */
48*4882a593Smuzhiyun 	{ 0x17, 0x89 }, /* Map6 */
49*4882a593Smuzhiyun 	{ 0x18, 0x00 }, /* Map7 */
50*4882a593Smuzhiyun 	{ 0x19, 0x00 }, /* Map8 */
51*4882a593Smuzhiyun 	{ 0x1A, 0x06 }, /* DAI Clock Mode 1 */
52*4882a593Smuzhiyun 	{ 0x1B, 0xC0 }, /* DAI Clock Mode 2 */
53*4882a593Smuzhiyun 	{ 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
54*4882a593Smuzhiyun 	{ 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
55*4882a593Smuzhiyun 	{ 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
56*4882a593Smuzhiyun 	{ 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
57*4882a593Smuzhiyun 	{ 0x20, 0x50 }, /* Format */
58*4882a593Smuzhiyun 	{ 0x21, 0x00 }, /* TDM Slot Select */
59*4882a593Smuzhiyun 	{ 0x22, 0x00 }, /* DOUT Configuration VMON */
60*4882a593Smuzhiyun 	{ 0x23, 0x00 }, /* DOUT Configuration IMON */
61*4882a593Smuzhiyun 	{ 0x24, 0x00 }, /* DOUT Configuration VBAT */
62*4882a593Smuzhiyun 	{ 0x25, 0x00 }, /* DOUT Configuration VBST */
63*4882a593Smuzhiyun 	{ 0x26, 0x00 }, /* DOUT Configuration FLAG */
64*4882a593Smuzhiyun 	{ 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
65*4882a593Smuzhiyun 	{ 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
66*4882a593Smuzhiyun 	{ 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
67*4882a593Smuzhiyun 	{ 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
68*4882a593Smuzhiyun 	{ 0x2B, 0x02 }, /* DOUT Drive Strength */
69*4882a593Smuzhiyun 	{ 0x2C, 0x90 }, /* Filters */
70*4882a593Smuzhiyun 	{ 0x2D, 0x00 }, /* Gain */
71*4882a593Smuzhiyun 	{ 0x2E, 0x02 }, /* Gain Ramping */
72*4882a593Smuzhiyun 	{ 0x2F, 0x00 }, /* Speaker Amplifier */
73*4882a593Smuzhiyun 	{ 0x30, 0x0A }, /* Threshold */
74*4882a593Smuzhiyun 	{ 0x31, 0x00 }, /* ALC Attack */
75*4882a593Smuzhiyun 	{ 0x32, 0x80 }, /* ALC Atten and Release */
76*4882a593Smuzhiyun 	{ 0x33, 0x00 }, /* ALC Infinite Hold Release */
77*4882a593Smuzhiyun 	{ 0x34, 0x92 }, /* ALC Configuration */
78*4882a593Smuzhiyun 	{ 0x35, 0x01 }, /* Boost Converter */
79*4882a593Smuzhiyun 	{ 0x36, 0x00 }, /* Block Enable */
80*4882a593Smuzhiyun 	{ 0x37, 0x00 }, /* Configuration */
81*4882a593Smuzhiyun 	{ 0x38, 0x00 }, /* Global Enable */
82*4882a593Smuzhiyun 	{ 0x3A, 0x00 }, /* Boost Limiter */
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun static const struct soc_enum max98925_dai_enum =
86*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(MAX98925_GAIN, 5, ARRAY_SIZE(dai_text), dai_text);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun static const struct soc_enum max98925_hpf_enum =
89*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(MAX98925_FILTERS, 0, ARRAY_SIZE(hpf_text), hpf_text);
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun static const struct snd_kcontrol_new max98925_hpf_sel_mux =
92*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Rc Filter MUX Mux", max98925_hpf_enum);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun static const struct snd_kcontrol_new max98925_dai_sel_mux =
95*4882a593Smuzhiyun 	SOC_DAPM_ENUM("DAI IN MUX Mux", max98925_dai_enum);
96*4882a593Smuzhiyun 
max98925_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)97*4882a593Smuzhiyun static int max98925_dac_event(struct snd_soc_dapm_widget *w,
98*4882a593Smuzhiyun 		struct snd_kcontrol *kcontrol, int event)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
101*4882a593Smuzhiyun 	struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	switch (event) {
104*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMU:
105*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
106*4882a593Smuzhiyun 			MAX98925_BLOCK_ENABLE,
107*4882a593Smuzhiyun 			M98925_BST_EN_MASK |
108*4882a593Smuzhiyun 			M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK,
109*4882a593Smuzhiyun 			M98925_BST_EN_MASK |
110*4882a593Smuzhiyun 			M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK);
111*4882a593Smuzhiyun 		break;
112*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:
113*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
114*4882a593Smuzhiyun 			MAX98925_BLOCK_ENABLE, M98925_BST_EN_MASK |
115*4882a593Smuzhiyun 			M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK, 0);
116*4882a593Smuzhiyun 		break;
117*4882a593Smuzhiyun 	default:
118*4882a593Smuzhiyun 		return 0;
119*4882a593Smuzhiyun 	}
120*4882a593Smuzhiyun 	return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun static const struct snd_soc_dapm_widget max98925_dapm_widgets[] = {
124*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
125*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("DAI IN MUX", SND_SOC_NOPM, 0, 0,
126*4882a593Smuzhiyun 				&max98925_dai_sel_mux),
127*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("Rc Filter MUX", SND_SOC_NOPM, 0, 0,
128*4882a593Smuzhiyun 				&max98925_hpf_sel_mux),
129*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC_E("Amp Enable", NULL, MAX98925_BLOCK_ENABLE,
130*4882a593Smuzhiyun 			M98925_SPK_EN_SHIFT, 0, max98925_dac_event,
131*4882a593Smuzhiyun 			SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
132*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Global Enable", MAX98925_GLOBAL_ENABLE,
133*4882a593Smuzhiyun 			M98925_EN_SHIFT, 0, NULL, 0),
134*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("BE_OUT"),
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun static const struct snd_soc_dapm_route max98925_audio_map[] = {
138*4882a593Smuzhiyun 	{"DAI IN MUX", "Left", "DAI_OUT"},
139*4882a593Smuzhiyun 	{"DAI IN MUX", "Right", "DAI_OUT"},
140*4882a593Smuzhiyun 	{"DAI IN MUX", "LeftRight", "DAI_OUT"},
141*4882a593Smuzhiyun 	{"DAI IN MUX", "LeftRightDiv2", "DAI_OUT"},
142*4882a593Smuzhiyun 	{"Rc Filter MUX", "Disable", "DAI IN MUX"},
143*4882a593Smuzhiyun 	{"Rc Filter MUX", "DC Block", "DAI IN MUX"},
144*4882a593Smuzhiyun 	{"Rc Filter MUX", "100Hz", "DAI IN MUX"},
145*4882a593Smuzhiyun 	{"Rc Filter MUX", "200Hz", "DAI IN MUX"},
146*4882a593Smuzhiyun 	{"Rc Filter MUX", "400Hz", "DAI IN MUX"},
147*4882a593Smuzhiyun 	{"Rc Filter MUX", "800Hz", "DAI IN MUX"},
148*4882a593Smuzhiyun 	{"Amp Enable", NULL, "Rc Filter MUX"},
149*4882a593Smuzhiyun 	{"BE_OUT", NULL, "Amp Enable"},
150*4882a593Smuzhiyun 	{"BE_OUT", NULL, "Global Enable"},
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun 
max98925_volatile_register(struct device * dev,unsigned int reg)153*4882a593Smuzhiyun static bool max98925_volatile_register(struct device *dev, unsigned int reg)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun 	switch (reg) {
156*4882a593Smuzhiyun 	case MAX98925_VBAT_DATA:
157*4882a593Smuzhiyun 	case MAX98925_VBST_DATA:
158*4882a593Smuzhiyun 	case MAX98925_LIVE_STATUS0:
159*4882a593Smuzhiyun 	case MAX98925_LIVE_STATUS1:
160*4882a593Smuzhiyun 	case MAX98925_LIVE_STATUS2:
161*4882a593Smuzhiyun 	case MAX98925_STATE0:
162*4882a593Smuzhiyun 	case MAX98925_STATE1:
163*4882a593Smuzhiyun 	case MAX98925_STATE2:
164*4882a593Smuzhiyun 	case MAX98925_FLAG0:
165*4882a593Smuzhiyun 	case MAX98925_FLAG1:
166*4882a593Smuzhiyun 	case MAX98925_FLAG2:
167*4882a593Smuzhiyun 	case MAX98925_REV_VERSION:
168*4882a593Smuzhiyun 		return true;
169*4882a593Smuzhiyun 	default:
170*4882a593Smuzhiyun 		return false;
171*4882a593Smuzhiyun 	}
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
max98925_readable_register(struct device * dev,unsigned int reg)174*4882a593Smuzhiyun static bool max98925_readable_register(struct device *dev, unsigned int reg)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	switch (reg) {
177*4882a593Smuzhiyun 	case MAX98925_IRQ_CLEAR0:
178*4882a593Smuzhiyun 	case MAX98925_IRQ_CLEAR1:
179*4882a593Smuzhiyun 	case MAX98925_IRQ_CLEAR2:
180*4882a593Smuzhiyun 	case MAX98925_ALC_HOLD_RLS:
181*4882a593Smuzhiyun 		return false;
182*4882a593Smuzhiyun 	default:
183*4882a593Smuzhiyun 		return true;
184*4882a593Smuzhiyun 	}
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(max98925_spk_tlv, -600, 100, 0);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun static const struct snd_kcontrol_new max98925_snd_controls[] = {
190*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Speaker Volume", MAX98925_GAIN,
191*4882a593Smuzhiyun 		M98925_SPK_GAIN_SHIFT, (1<<M98925_SPK_GAIN_WIDTH)-1, 0,
192*4882a593Smuzhiyun 		max98925_spk_tlv),
193*4882a593Smuzhiyun 	SOC_SINGLE("Ramp Switch", MAX98925_GAIN_RAMPING,
194*4882a593Smuzhiyun 				M98925_SPK_RMP_EN_SHIFT, 1, 0),
195*4882a593Smuzhiyun 	SOC_SINGLE("ZCD Switch", MAX98925_GAIN_RAMPING,
196*4882a593Smuzhiyun 				M98925_SPK_ZCD_EN_SHIFT, 1, 0),
197*4882a593Smuzhiyun 	SOC_SINGLE("ALC Switch", MAX98925_THRESHOLD,
198*4882a593Smuzhiyun 				M98925_ALC_EN_SHIFT, 1, 0),
199*4882a593Smuzhiyun 	SOC_SINGLE("ALC Threshold", MAX98925_THRESHOLD, M98925_ALC_TH_SHIFT,
200*4882a593Smuzhiyun 				(1<<M98925_ALC_TH_WIDTH)-1, 0),
201*4882a593Smuzhiyun 	SOC_ENUM("Boost Output Voltage", max98925_boost_voltage),
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun /* codec sample rate and n/m dividers parameter table */
205*4882a593Smuzhiyun static const struct {
206*4882a593Smuzhiyun 	int rate;
207*4882a593Smuzhiyun 	int  sr;
208*4882a593Smuzhiyun 	int divisors[3][2];
209*4882a593Smuzhiyun } rate_table[] = {
210*4882a593Smuzhiyun 	{
211*4882a593Smuzhiyun 		.rate = 8000,
212*4882a593Smuzhiyun 		.sr = 0,
213*4882a593Smuzhiyun 		.divisors = { {1, 375}, {5, 1764}, {1, 384} }
214*4882a593Smuzhiyun 	},
215*4882a593Smuzhiyun 	{
216*4882a593Smuzhiyun 		.rate = 11025,
217*4882a593Smuzhiyun 		.sr = 1,
218*4882a593Smuzhiyun 		.divisors = { {147, 40000}, {1, 256}, {147, 40960} }
219*4882a593Smuzhiyun 	},
220*4882a593Smuzhiyun 	{
221*4882a593Smuzhiyun 		.rate = 12000,
222*4882a593Smuzhiyun 		.sr = 2,
223*4882a593Smuzhiyun 		.divisors = { {1, 250}, {5, 1176}, {1, 256} }
224*4882a593Smuzhiyun 	},
225*4882a593Smuzhiyun 	{
226*4882a593Smuzhiyun 		.rate = 16000,
227*4882a593Smuzhiyun 		.sr = 3,
228*4882a593Smuzhiyun 		.divisors = { {2, 375}, {5, 882}, {1, 192} }
229*4882a593Smuzhiyun 	},
230*4882a593Smuzhiyun 	{
231*4882a593Smuzhiyun 		.rate = 22050,
232*4882a593Smuzhiyun 		.sr = 4,
233*4882a593Smuzhiyun 		.divisors = { {147, 20000}, {1, 128}, {147, 20480} }
234*4882a593Smuzhiyun 	},
235*4882a593Smuzhiyun 	{
236*4882a593Smuzhiyun 		.rate = 24000,
237*4882a593Smuzhiyun 		.sr = 5,
238*4882a593Smuzhiyun 		.divisors = { {1, 125}, {5, 588}, {1, 128} }
239*4882a593Smuzhiyun 	},
240*4882a593Smuzhiyun 	{
241*4882a593Smuzhiyun 		.rate = 32000,
242*4882a593Smuzhiyun 		.sr = 6,
243*4882a593Smuzhiyun 		.divisors = { {4, 375}, {5, 441}, {1, 96} }
244*4882a593Smuzhiyun 	},
245*4882a593Smuzhiyun 	{
246*4882a593Smuzhiyun 		.rate = 44100,
247*4882a593Smuzhiyun 		.sr = 7,
248*4882a593Smuzhiyun 		.divisors = { {147, 10000}, {1, 64}, {147, 10240} }
249*4882a593Smuzhiyun 	},
250*4882a593Smuzhiyun 	{
251*4882a593Smuzhiyun 		.rate = 48000,
252*4882a593Smuzhiyun 		.sr = 8,
253*4882a593Smuzhiyun 		.divisors = { {2, 125}, {5, 294}, {1, 64} }
254*4882a593Smuzhiyun 	},
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
max98925_rate_value(struct snd_soc_component * component,int rate,int clock,int * value,int * n,int * m)257*4882a593Smuzhiyun static inline int max98925_rate_value(struct snd_soc_component *component,
258*4882a593Smuzhiyun 		int rate, int clock, int *value, int *n, int *m)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	int ret = -EINVAL;
261*4882a593Smuzhiyun 	int i;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
264*4882a593Smuzhiyun 		if (rate_table[i].rate >= rate) {
265*4882a593Smuzhiyun 			*value = rate_table[i].sr;
266*4882a593Smuzhiyun 			*n = rate_table[i].divisors[clock][0];
267*4882a593Smuzhiyun 			*m = rate_table[i].divisors[clock][1];
268*4882a593Smuzhiyun 			ret = 0;
269*4882a593Smuzhiyun 			break;
270*4882a593Smuzhiyun 		}
271*4882a593Smuzhiyun 	}
272*4882a593Smuzhiyun 	return ret;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun 
max98925_set_sense_data(struct max98925_priv * max98925)275*4882a593Smuzhiyun static void max98925_set_sense_data(struct max98925_priv *max98925)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun 	/* set VMON slots */
278*4882a593Smuzhiyun 	regmap_update_bits(max98925->regmap,
279*4882a593Smuzhiyun 		MAX98925_DOUT_CFG_VMON,
280*4882a593Smuzhiyun 		M98925_DAI_VMON_EN_MASK, M98925_DAI_VMON_EN_MASK);
281*4882a593Smuzhiyun 	regmap_update_bits(max98925->regmap,
282*4882a593Smuzhiyun 		MAX98925_DOUT_CFG_VMON,
283*4882a593Smuzhiyun 		M98925_DAI_VMON_SLOT_MASK,
284*4882a593Smuzhiyun 		max98925->v_slot << M98925_DAI_VMON_SLOT_SHIFT);
285*4882a593Smuzhiyun 	/* set IMON slots */
286*4882a593Smuzhiyun 	regmap_update_bits(max98925->regmap,
287*4882a593Smuzhiyun 		MAX98925_DOUT_CFG_IMON,
288*4882a593Smuzhiyun 		M98925_DAI_IMON_EN_MASK, M98925_DAI_IMON_EN_MASK);
289*4882a593Smuzhiyun 	regmap_update_bits(max98925->regmap,
290*4882a593Smuzhiyun 		MAX98925_DOUT_CFG_IMON,
291*4882a593Smuzhiyun 		M98925_DAI_IMON_SLOT_MASK,
292*4882a593Smuzhiyun 		max98925->i_slot << M98925_DAI_IMON_SLOT_SHIFT);
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun 
max98925_dai_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)295*4882a593Smuzhiyun static int max98925_dai_set_fmt(struct snd_soc_dai *codec_dai,
296*4882a593Smuzhiyun 				 unsigned int fmt)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
299*4882a593Smuzhiyun 	struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
300*4882a593Smuzhiyun 	unsigned int invert = 0;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
303*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
304*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
305*4882a593Smuzhiyun 		/* set DAI to slave mode */
306*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
307*4882a593Smuzhiyun 			MAX98925_DAI_CLK_MODE2,
308*4882a593Smuzhiyun 			M98925_DAI_MAS_MASK, 0);
309*4882a593Smuzhiyun 		max98925_set_sense_data(max98925);
310*4882a593Smuzhiyun 		break;
311*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
312*4882a593Smuzhiyun 		/*
313*4882a593Smuzhiyun 		 * set left channel DAI to master mode,
314*4882a593Smuzhiyun 		 * right channel always slave
315*4882a593Smuzhiyun 		 */
316*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
317*4882a593Smuzhiyun 			MAX98925_DAI_CLK_MODE2,
318*4882a593Smuzhiyun 			M98925_DAI_MAS_MASK, M98925_DAI_MAS_MASK);
319*4882a593Smuzhiyun 		break;
320*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFM:
321*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFS:
322*4882a593Smuzhiyun 	default:
323*4882a593Smuzhiyun 		dev_err(component->dev, "DAI clock mode unsupported");
324*4882a593Smuzhiyun 		return -EINVAL;
325*4882a593Smuzhiyun 	}
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
328*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_NB_NF:
329*4882a593Smuzhiyun 		break;
330*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_NB_IF:
331*4882a593Smuzhiyun 		invert = M98925_DAI_WCI_MASK;
332*4882a593Smuzhiyun 		break;
333*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_IB_NF:
334*4882a593Smuzhiyun 		invert = M98925_DAI_BCI_MASK;
335*4882a593Smuzhiyun 		break;
336*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_IB_IF:
337*4882a593Smuzhiyun 		invert = M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK;
338*4882a593Smuzhiyun 		break;
339*4882a593Smuzhiyun 	default:
340*4882a593Smuzhiyun 		dev_err(component->dev, "DAI invert mode unsupported");
341*4882a593Smuzhiyun 		return -EINVAL;
342*4882a593Smuzhiyun 	}
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	regmap_update_bits(max98925->regmap, MAX98925_FORMAT,
345*4882a593Smuzhiyun 			M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK, invert);
346*4882a593Smuzhiyun 	return 0;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun 
max98925_set_clock(struct max98925_priv * max98925,struct snd_pcm_hw_params * params)349*4882a593Smuzhiyun static int max98925_set_clock(struct max98925_priv *max98925,
350*4882a593Smuzhiyun 		struct snd_pcm_hw_params *params)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun 	unsigned int dai_sr = 0, clock, mdll, n, m;
353*4882a593Smuzhiyun 	struct snd_soc_component *component = max98925->component;
354*4882a593Smuzhiyun 	int rate = params_rate(params);
355*4882a593Smuzhiyun 	/* BCLK/LRCLK ratio calculation */
356*4882a593Smuzhiyun 	int blr_clk_ratio = params_channels(params) * max98925->ch_size;
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	switch (blr_clk_ratio) {
359*4882a593Smuzhiyun 	case 32:
360*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
361*4882a593Smuzhiyun 			MAX98925_DAI_CLK_MODE2,
362*4882a593Smuzhiyun 			M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_32);
363*4882a593Smuzhiyun 		break;
364*4882a593Smuzhiyun 	case 48:
365*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
366*4882a593Smuzhiyun 			MAX98925_DAI_CLK_MODE2,
367*4882a593Smuzhiyun 			M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_48);
368*4882a593Smuzhiyun 		break;
369*4882a593Smuzhiyun 	case 64:
370*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
371*4882a593Smuzhiyun 			MAX98925_DAI_CLK_MODE2,
372*4882a593Smuzhiyun 			M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_64);
373*4882a593Smuzhiyun 		break;
374*4882a593Smuzhiyun 	default:
375*4882a593Smuzhiyun 		return -EINVAL;
376*4882a593Smuzhiyun 	}
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	switch (max98925->sysclk) {
379*4882a593Smuzhiyun 	case 6000000:
380*4882a593Smuzhiyun 		clock = 0;
381*4882a593Smuzhiyun 		mdll  = M98925_MDLL_MULT_MCLKx16;
382*4882a593Smuzhiyun 		break;
383*4882a593Smuzhiyun 	case 11289600:
384*4882a593Smuzhiyun 		clock = 1;
385*4882a593Smuzhiyun 		mdll  = M98925_MDLL_MULT_MCLKx8;
386*4882a593Smuzhiyun 		break;
387*4882a593Smuzhiyun 	case 12000000:
388*4882a593Smuzhiyun 		clock = 0;
389*4882a593Smuzhiyun 		mdll  = M98925_MDLL_MULT_MCLKx8;
390*4882a593Smuzhiyun 		break;
391*4882a593Smuzhiyun 	case 12288000:
392*4882a593Smuzhiyun 		clock = 2;
393*4882a593Smuzhiyun 		mdll  = M98925_MDLL_MULT_MCLKx8;
394*4882a593Smuzhiyun 		break;
395*4882a593Smuzhiyun 	default:
396*4882a593Smuzhiyun 		dev_info(max98925->component->dev, "unsupported sysclk %d\n",
397*4882a593Smuzhiyun 					max98925->sysclk);
398*4882a593Smuzhiyun 		return -EINVAL;
399*4882a593Smuzhiyun 	}
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	if (max98925_rate_value(component, rate, clock, &dai_sr, &n, &m))
402*4882a593Smuzhiyun 		return -EINVAL;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	/* set DAI_SR to correct LRCLK frequency */
405*4882a593Smuzhiyun 	regmap_update_bits(max98925->regmap,
406*4882a593Smuzhiyun 			MAX98925_DAI_CLK_MODE2,
407*4882a593Smuzhiyun 			M98925_DAI_SR_MASK, dai_sr << M98925_DAI_SR_SHIFT);
408*4882a593Smuzhiyun 	/* set DAI m divider */
409*4882a593Smuzhiyun 	regmap_write(max98925->regmap,
410*4882a593Smuzhiyun 		MAX98925_DAI_CLK_DIV_M_MSBS, m >> 8);
411*4882a593Smuzhiyun 	regmap_write(max98925->regmap,
412*4882a593Smuzhiyun 		MAX98925_DAI_CLK_DIV_M_LSBS, m & 0xFF);
413*4882a593Smuzhiyun 	/* set DAI n divider */
414*4882a593Smuzhiyun 	regmap_write(max98925->regmap,
415*4882a593Smuzhiyun 		MAX98925_DAI_CLK_DIV_N_MSBS, n >> 8);
416*4882a593Smuzhiyun 	regmap_write(max98925->regmap,
417*4882a593Smuzhiyun 		MAX98925_DAI_CLK_DIV_N_LSBS, n & 0xFF);
418*4882a593Smuzhiyun 	/* set MDLL */
419*4882a593Smuzhiyun 	regmap_update_bits(max98925->regmap, MAX98925_DAI_CLK_MODE1,
420*4882a593Smuzhiyun 			M98925_MDLL_MULT_MASK, mdll << M98925_MDLL_MULT_SHIFT);
421*4882a593Smuzhiyun 	return 0;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun 
max98925_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)424*4882a593Smuzhiyun static int max98925_dai_hw_params(struct snd_pcm_substream *substream,
425*4882a593Smuzhiyun 				   struct snd_pcm_hw_params *params,
426*4882a593Smuzhiyun 				   struct snd_soc_dai *dai)
427*4882a593Smuzhiyun {
428*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
429*4882a593Smuzhiyun 	struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	switch (params_width(params)) {
432*4882a593Smuzhiyun 	case 16:
433*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
434*4882a593Smuzhiyun 				MAX98925_FORMAT,
435*4882a593Smuzhiyun 				M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_16);
436*4882a593Smuzhiyun 		max98925->ch_size = 16;
437*4882a593Smuzhiyun 		break;
438*4882a593Smuzhiyun 	case 24:
439*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
440*4882a593Smuzhiyun 				MAX98925_FORMAT,
441*4882a593Smuzhiyun 				M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_24);
442*4882a593Smuzhiyun 		max98925->ch_size = 24;
443*4882a593Smuzhiyun 		break;
444*4882a593Smuzhiyun 	case 32:
445*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
446*4882a593Smuzhiyun 				MAX98925_FORMAT,
447*4882a593Smuzhiyun 				M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_32);
448*4882a593Smuzhiyun 		max98925->ch_size = 32;
449*4882a593Smuzhiyun 		break;
450*4882a593Smuzhiyun 	default:
451*4882a593Smuzhiyun 		pr_err("%s: format unsupported %d",
452*4882a593Smuzhiyun 				__func__, params_format(params));
453*4882a593Smuzhiyun 		return -EINVAL;
454*4882a593Smuzhiyun 	}
455*4882a593Smuzhiyun 	dev_dbg(component->dev, "%s: format supported %d",
456*4882a593Smuzhiyun 				__func__, params_format(params));
457*4882a593Smuzhiyun 	return max98925_set_clock(max98925, params);
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun 
max98925_dai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)460*4882a593Smuzhiyun static int max98925_dai_set_sysclk(struct snd_soc_dai *dai,
461*4882a593Smuzhiyun 				   int clk_id, unsigned int freq, int dir)
462*4882a593Smuzhiyun {
463*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
464*4882a593Smuzhiyun 	struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	switch (clk_id) {
467*4882a593Smuzhiyun 	case 0:
468*4882a593Smuzhiyun 		/* use MCLK for Left channel, right channel always BCLK */
469*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
470*4882a593Smuzhiyun 				MAX98925_DAI_CLK_MODE1,
471*4882a593Smuzhiyun 				M98925_DAI_CLK_SOURCE_MASK, 0);
472*4882a593Smuzhiyun 		break;
473*4882a593Smuzhiyun 	case 1:
474*4882a593Smuzhiyun 		/* configure dai clock source to BCLK instead of MCLK */
475*4882a593Smuzhiyun 		regmap_update_bits(max98925->regmap,
476*4882a593Smuzhiyun 				MAX98925_DAI_CLK_MODE1,
477*4882a593Smuzhiyun 				M98925_DAI_CLK_SOURCE_MASK,
478*4882a593Smuzhiyun 				M98925_DAI_CLK_SOURCE_MASK);
479*4882a593Smuzhiyun 		break;
480*4882a593Smuzhiyun 	default:
481*4882a593Smuzhiyun 		return -EINVAL;
482*4882a593Smuzhiyun 	}
483*4882a593Smuzhiyun 	max98925->sysclk = freq;
484*4882a593Smuzhiyun 	return 0;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun #define MAX98925_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
488*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun static const struct snd_soc_dai_ops max98925_dai_ops = {
491*4882a593Smuzhiyun 	.set_sysclk = max98925_dai_set_sysclk,
492*4882a593Smuzhiyun 	.set_fmt = max98925_dai_set_fmt,
493*4882a593Smuzhiyun 	.hw_params = max98925_dai_hw_params,
494*4882a593Smuzhiyun };
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun static struct snd_soc_dai_driver max98925_dai[] = {
497*4882a593Smuzhiyun 	{
498*4882a593Smuzhiyun 		.name = "max98925-aif1",
499*4882a593Smuzhiyun 		.playback = {
500*4882a593Smuzhiyun 			.stream_name = "HiFi Playback",
501*4882a593Smuzhiyun 			.channels_min = 1,
502*4882a593Smuzhiyun 			.channels_max = 2,
503*4882a593Smuzhiyun 			.rates = SNDRV_PCM_RATE_8000_48000,
504*4882a593Smuzhiyun 			.formats = MAX98925_FORMATS,
505*4882a593Smuzhiyun 		},
506*4882a593Smuzhiyun 		.capture = {
507*4882a593Smuzhiyun 			.stream_name = "HiFi Capture",
508*4882a593Smuzhiyun 			.channels_min = 1,
509*4882a593Smuzhiyun 			.channels_max = 2,
510*4882a593Smuzhiyun 			.rates = SNDRV_PCM_RATE_8000_48000,
511*4882a593Smuzhiyun 			.formats = MAX98925_FORMATS,
512*4882a593Smuzhiyun 		},
513*4882a593Smuzhiyun 		.ops = &max98925_dai_ops,
514*4882a593Smuzhiyun 	}
515*4882a593Smuzhiyun };
516*4882a593Smuzhiyun 
max98925_probe(struct snd_soc_component * component)517*4882a593Smuzhiyun static int max98925_probe(struct snd_soc_component *component)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun 	struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	max98925->component = component;
522*4882a593Smuzhiyun 	regmap_write(max98925->regmap, MAX98925_GLOBAL_ENABLE, 0x00);
523*4882a593Smuzhiyun 	/* It's not the default but we need to set DAI_DLY */
524*4882a593Smuzhiyun 	regmap_write(max98925->regmap,
525*4882a593Smuzhiyun 			MAX98925_FORMAT, M98925_DAI_DLY_MASK);
526*4882a593Smuzhiyun 	regmap_write(max98925->regmap, MAX98925_TDM_SLOT_SELECT, 0xC8);
527*4882a593Smuzhiyun 	regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG1, 0xFF);
528*4882a593Smuzhiyun 	regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG2, 0xFF);
529*4882a593Smuzhiyun 	regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG3, 0xFF);
530*4882a593Smuzhiyun 	regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG4, 0xF0);
531*4882a593Smuzhiyun 	regmap_write(max98925->regmap, MAX98925_FILTERS, 0xD8);
532*4882a593Smuzhiyun 	regmap_write(max98925->regmap, MAX98925_ALC_CONFIGURATION, 0xF8);
533*4882a593Smuzhiyun 	regmap_write(max98925->regmap, MAX98925_CONFIGURATION, 0xF0);
534*4882a593Smuzhiyun 	/* Disable ALC muting */
535*4882a593Smuzhiyun 	regmap_write(max98925->regmap, MAX98925_BOOST_LIMITER, 0xF8);
536*4882a593Smuzhiyun 	return 0;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_max98925 = {
540*4882a593Smuzhiyun 	.probe			= max98925_probe,
541*4882a593Smuzhiyun 	.controls		= max98925_snd_controls,
542*4882a593Smuzhiyun 	.num_controls		= ARRAY_SIZE(max98925_snd_controls),
543*4882a593Smuzhiyun 	.dapm_routes		= max98925_audio_map,
544*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(max98925_audio_map),
545*4882a593Smuzhiyun 	.dapm_widgets		= max98925_dapm_widgets,
546*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(max98925_dapm_widgets),
547*4882a593Smuzhiyun 	.idle_bias_on		= 1,
548*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
549*4882a593Smuzhiyun 	.endianness		= 1,
550*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
551*4882a593Smuzhiyun };
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun static const struct regmap_config max98925_regmap = {
554*4882a593Smuzhiyun 	.reg_bits         = 8,
555*4882a593Smuzhiyun 	.val_bits         = 8,
556*4882a593Smuzhiyun 	.max_register     = MAX98925_REV_VERSION,
557*4882a593Smuzhiyun 	.reg_defaults     = max98925_reg,
558*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(max98925_reg),
559*4882a593Smuzhiyun 	.volatile_reg     = max98925_volatile_register,
560*4882a593Smuzhiyun 	.readable_reg     = max98925_readable_register,
561*4882a593Smuzhiyun 	.cache_type       = REGCACHE_RBTREE,
562*4882a593Smuzhiyun };
563*4882a593Smuzhiyun 
max98925_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)564*4882a593Smuzhiyun static int max98925_i2c_probe(struct i2c_client *i2c,
565*4882a593Smuzhiyun 			     const struct i2c_device_id *id)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun 	int ret, reg;
568*4882a593Smuzhiyun 	u32 value;
569*4882a593Smuzhiyun 	struct max98925_priv *max98925;
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	max98925 = devm_kzalloc(&i2c->dev,
572*4882a593Smuzhiyun 			sizeof(*max98925), GFP_KERNEL);
573*4882a593Smuzhiyun 	if (!max98925)
574*4882a593Smuzhiyun 		return -ENOMEM;
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun 	i2c_set_clientdata(i2c, max98925);
577*4882a593Smuzhiyun 	max98925->regmap = devm_regmap_init_i2c(i2c, &max98925_regmap);
578*4882a593Smuzhiyun 	if (IS_ERR(max98925->regmap)) {
579*4882a593Smuzhiyun 		ret = PTR_ERR(max98925->regmap);
580*4882a593Smuzhiyun 		dev_err(&i2c->dev,
581*4882a593Smuzhiyun 				"Failed to allocate regmap: %d\n", ret);
582*4882a593Smuzhiyun 		return ret;
583*4882a593Smuzhiyun 	}
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
586*4882a593Smuzhiyun 		if (value > M98925_DAI_VMON_SLOT_1E_1F) {
587*4882a593Smuzhiyun 			dev_err(&i2c->dev, "vmon slot number is wrong:\n");
588*4882a593Smuzhiyun 			return -EINVAL;
589*4882a593Smuzhiyun 		}
590*4882a593Smuzhiyun 		max98925->v_slot = value;
591*4882a593Smuzhiyun 	}
592*4882a593Smuzhiyun 	if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
593*4882a593Smuzhiyun 		if (value > M98925_DAI_IMON_SLOT_1E_1F) {
594*4882a593Smuzhiyun 			dev_err(&i2c->dev, "imon slot number is wrong:\n");
595*4882a593Smuzhiyun 			return -EINVAL;
596*4882a593Smuzhiyun 		}
597*4882a593Smuzhiyun 		max98925->i_slot = value;
598*4882a593Smuzhiyun 	}
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun 	ret = regmap_read(max98925->regmap, MAX98925_REV_VERSION, &reg);
601*4882a593Smuzhiyun 	if (ret < 0) {
602*4882a593Smuzhiyun 		dev_err(&i2c->dev, "Read revision failed\n");
603*4882a593Smuzhiyun 		return ret;
604*4882a593Smuzhiyun 	}
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	if ((reg != MAX98925_VERSION) && (reg != MAX98925_VERSION1)) {
607*4882a593Smuzhiyun 		ret = -ENODEV;
608*4882a593Smuzhiyun 		dev_err(&i2c->dev, "Invalid revision (%d 0x%02X)\n",
609*4882a593Smuzhiyun 			ret, reg);
610*4882a593Smuzhiyun 		return ret;
611*4882a593Smuzhiyun 	}
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	dev_info(&i2c->dev, "device version 0x%02X\n", reg);
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(&i2c->dev,
616*4882a593Smuzhiyun 			&soc_component_dev_max98925,
617*4882a593Smuzhiyun 			max98925_dai, ARRAY_SIZE(max98925_dai));
618*4882a593Smuzhiyun 	if (ret < 0)
619*4882a593Smuzhiyun 		dev_err(&i2c->dev,
620*4882a593Smuzhiyun 				"Failed to register component: %d\n", ret);
621*4882a593Smuzhiyun 	return ret;
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun static const struct i2c_device_id max98925_i2c_id[] = {
625*4882a593Smuzhiyun 	{ "max98925", 0 },
626*4882a593Smuzhiyun 	{ }
627*4882a593Smuzhiyun };
628*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, max98925_i2c_id);
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun static const struct of_device_id max98925_of_match[] = {
631*4882a593Smuzhiyun 	{ .compatible = "maxim,max98925", },
632*4882a593Smuzhiyun 	{ }
633*4882a593Smuzhiyun };
634*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max98925_of_match);
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun static struct i2c_driver max98925_i2c_driver = {
637*4882a593Smuzhiyun 	.driver = {
638*4882a593Smuzhiyun 		.name = "max98925",
639*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(max98925_of_match),
640*4882a593Smuzhiyun 		.pm = NULL,
641*4882a593Smuzhiyun 	},
642*4882a593Smuzhiyun 	.probe  = max98925_i2c_probe,
643*4882a593Smuzhiyun 	.id_table = max98925_i2c_id,
644*4882a593Smuzhiyun };
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun module_i2c_driver(max98925_i2c_driver)
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun MODULE_DESCRIPTION("ALSA SoC MAX98925 driver");
649*4882a593Smuzhiyun MODULE_AUTHOR("Ralph Birt <rdbirt@gmail.com>, Anish kumar <anish.kumar@maximintegrated.com>");
650*4882a593Smuzhiyun MODULE_LICENSE("GPL");
651