1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * max9867.h -- MAX9867 ALSA SoC Audio driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2013-2015 Maxim Integrated Products 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _MAX9867_H 9*4882a593Smuzhiyun #define _MAX9867_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* MAX9867 register space */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define MAX9867_STATUS 0x00 14*4882a593Smuzhiyun #define MAX9867_JACKSTATUS 0x01 15*4882a593Smuzhiyun #define MAX9867_AUXHIGH 0x02 16*4882a593Smuzhiyun #define MAX9867_AUXLOW 0x03 17*4882a593Smuzhiyun #define MAX9867_INTEN 0x04 18*4882a593Smuzhiyun #define MAX9867_SYSCLK 0x05 19*4882a593Smuzhiyun #define MAX9867_FREQ_MASK 0xF 20*4882a593Smuzhiyun #define MAX9867_PSCLK_SHIFT 0x4 21*4882a593Smuzhiyun #define MAX9867_PSCLK_WIDTH 0x2 22*4882a593Smuzhiyun #define MAX9867_PSCLK_MASK (0x03<<MAX9867_PSCLK_SHIFT) 23*4882a593Smuzhiyun #define MAX9867_PSCLK_10_20 0x1 24*4882a593Smuzhiyun #define MAX9867_PSCLK_20_40 0x2 25*4882a593Smuzhiyun #define MAX9867_PSCLK_40_60 0x3 26*4882a593Smuzhiyun #define MAX9867_AUDIOCLKHIGH 0x06 27*4882a593Smuzhiyun #define MAX9867_NI_HIGH_MASK 0x7F 28*4882a593Smuzhiyun #define MAX9867_NI_LOW_MASK 0xFE 29*4882a593Smuzhiyun #define MAX9867_PLL (1<<7) 30*4882a593Smuzhiyun #define MAX9867_AUDIOCLKLOW 0x07 31*4882a593Smuzhiyun #define MAX9867_RAPID_LOCK 0x01 32*4882a593Smuzhiyun #define MAX9867_IFC1A 0x08 33*4882a593Smuzhiyun #define MAX9867_MASTER (1<<7) 34*4882a593Smuzhiyun #define MAX9867_I2S_DLY (1<<4) 35*4882a593Smuzhiyun #define MAX9867_SDOUT_HIZ (1<<3) 36*4882a593Smuzhiyun #define MAX9867_TDM_MODE (1<<2) 37*4882a593Smuzhiyun #define MAX9867_WCI_MODE (1<<6) 38*4882a593Smuzhiyun #define MAX9867_BCI_MODE (1<<5) 39*4882a593Smuzhiyun #define MAX9867_IFC1B 0x09 40*4882a593Smuzhiyun #define MAX9867_IFC1B_BCLK_MASK 7 41*4882a593Smuzhiyun #define MAX9867_IFC1B_64X 0x01 42*4882a593Smuzhiyun #define MAX9867_IFC1B_48X 0x02 43*4882a593Smuzhiyun #define MAX9867_IFC1B_PCLK_2 0x04 44*4882a593Smuzhiyun #define MAX9867_IFC1B_PCLK_4 0x05 45*4882a593Smuzhiyun #define MAX9867_IFC1B_PCLK_8 0x06 46*4882a593Smuzhiyun #define MAX9867_IFC1B_PCLK_16 0x07 47*4882a593Smuzhiyun #define MAX9867_CODECFLTR 0x0a 48*4882a593Smuzhiyun #define MAX9867_CODECFLTR_MODE (1<<7) 49*4882a593Smuzhiyun #define MAX9867_SIDETONE 0x0b 50*4882a593Smuzhiyun #define MAX9867_DACLEVEL 0x0c 51*4882a593Smuzhiyun #define MAX9867_ADCLEVEL 0x0d 52*4882a593Smuzhiyun #define MAX9867_LEFTLINELVL 0x0e 53*4882a593Smuzhiyun #define MAX9867_RIGHTLINELVL 0x0f 54*4882a593Smuzhiyun #define MAX9867_LEFTVOL 0x10 55*4882a593Smuzhiyun #define MAX9867_RIGHTVOL 0x11 56*4882a593Smuzhiyun #define MAX9867_LEFTMICGAIN 0x12 57*4882a593Smuzhiyun #define MAX9867_RIGHTMICGAIN 0x13 58*4882a593Smuzhiyun #define MAX9867_INPUTCONFIG 0x14 59*4882a593Smuzhiyun #define MAX9867_MICCONFIG 0x15 60*4882a593Smuzhiyun #define MAX9867_MODECONFIG 0x16 61*4882a593Smuzhiyun #define MAX9867_PWRMAN 0x17 62*4882a593Smuzhiyun #define MAX9867_PWRMAN_SHDN (1<<7) 63*4882a593Smuzhiyun #define MAX9867_REVISION 0xff 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define MAX9867_CACHEREGNUM 10 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif 68