1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // MAX9867 ALSA SoC codec driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright 2013-2015 Maxim Integrated Products
6*4882a593Smuzhiyun // Copyright 2018 Ladislav Michl <ladis@linux-mips.org>
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/i2c.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <sound/pcm_params.h>
14*4882a593Smuzhiyun #include <sound/soc.h>
15*4882a593Smuzhiyun #include <sound/tlv.h>
16*4882a593Smuzhiyun #include "max9867.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct max9867_priv {
19*4882a593Smuzhiyun struct regmap *regmap;
20*4882a593Smuzhiyun const struct snd_pcm_hw_constraint_list *constraints;
21*4882a593Smuzhiyun unsigned int sysclk, pclk;
22*4882a593Smuzhiyun bool master, dsp_a;
23*4882a593Smuzhiyun unsigned int adc_dac_active;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static const char *const max9867_spmode[] = {
27*4882a593Smuzhiyun "Stereo Diff", "Mono Diff",
28*4882a593Smuzhiyun "Stereo Cap", "Mono Cap",
29*4882a593Smuzhiyun "Stereo Single", "Mono Single",
30*4882a593Smuzhiyun "Stereo Single Fast", "Mono Single Fast"
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun static const char *const max9867_filter_text[] = {"IIR", "FIR"};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static const char *const max9867_adc_dac_filter_text[] = {
35*4882a593Smuzhiyun "Disabled",
36*4882a593Smuzhiyun "Elliptical/16/256",
37*4882a593Smuzhiyun "Butterworth/16/500",
38*4882a593Smuzhiyun "Elliptical/8/256",
39*4882a593Smuzhiyun "Butterworth/8/500",
40*4882a593Smuzhiyun "Butterworth/8-24"
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun enum max9867_adc_dac {
44*4882a593Smuzhiyun MAX9867_ADC_LEFT,
45*4882a593Smuzhiyun MAX9867_ADC_RIGHT,
46*4882a593Smuzhiyun MAX9867_DAC_LEFT,
47*4882a593Smuzhiyun MAX9867_DAC_RIGHT,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
max9867_adc_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)50*4882a593Smuzhiyun static int max9867_adc_dac_event(struct snd_soc_dapm_widget *w,
51*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
54*4882a593Smuzhiyun struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
55*4882a593Smuzhiyun enum max9867_adc_dac adc_dac;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (!strcmp(w->name, "ADCL"))
58*4882a593Smuzhiyun adc_dac = MAX9867_ADC_LEFT;
59*4882a593Smuzhiyun else if (!strcmp(w->name, "ADCR"))
60*4882a593Smuzhiyun adc_dac = MAX9867_ADC_RIGHT;
61*4882a593Smuzhiyun else if (!strcmp(w->name, "DACL"))
62*4882a593Smuzhiyun adc_dac = MAX9867_DAC_LEFT;
63*4882a593Smuzhiyun else if (!strcmp(w->name, "DACR"))
64*4882a593Smuzhiyun adc_dac = MAX9867_DAC_RIGHT;
65*4882a593Smuzhiyun else
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (SND_SOC_DAPM_EVENT_ON(event))
69*4882a593Smuzhiyun max9867->adc_dac_active |= BIT(adc_dac);
70*4882a593Smuzhiyun else if (SND_SOC_DAPM_EVENT_OFF(event))
71*4882a593Smuzhiyun max9867->adc_dac_active &= ~BIT(adc_dac);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
max9867_filter_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)76*4882a593Smuzhiyun static int max9867_filter_get(struct snd_kcontrol *kcontrol,
77*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
80*4882a593Smuzhiyun struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
81*4882a593Smuzhiyun unsigned int reg;
82*4882a593Smuzhiyun int ret;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun ret = regmap_read(max9867->regmap, MAX9867_CODECFLTR, ®);
85*4882a593Smuzhiyun if (ret)
86*4882a593Smuzhiyun return -EINVAL;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun if (reg & MAX9867_CODECFLTR_MODE)
89*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = 1;
90*4882a593Smuzhiyun else
91*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = 0;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return 0;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
max9867_filter_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)96*4882a593Smuzhiyun static int max9867_filter_set(struct snd_kcontrol *kcontrol,
97*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
100*4882a593Smuzhiyun struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
101*4882a593Smuzhiyun unsigned int reg, mode = ucontrol->value.enumerated.item[0];
102*4882a593Smuzhiyun int ret;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if (mode > 1)
105*4882a593Smuzhiyun return -EINVAL;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* don't allow change if ADC/DAC active */
108*4882a593Smuzhiyun if (max9867->adc_dac_active)
109*4882a593Smuzhiyun return -EBUSY;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* read current filter mode */
112*4882a593Smuzhiyun ret = regmap_read(max9867->regmap, MAX9867_CODECFLTR, ®);
113*4882a593Smuzhiyun if (ret)
114*4882a593Smuzhiyun return -EINVAL;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun if (mode)
117*4882a593Smuzhiyun mode = MAX9867_CODECFLTR_MODE;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* check if change is needed */
120*4882a593Smuzhiyun if ((reg & MAX9867_CODECFLTR_MODE) == mode)
121*4882a593Smuzhiyun return 0;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* shutdown codec before switching filter mode */
124*4882a593Smuzhiyun regmap_update_bits(max9867->regmap, MAX9867_PWRMAN,
125*4882a593Smuzhiyun MAX9867_PWRMAN_SHDN, 0);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* switch filter mode */
128*4882a593Smuzhiyun regmap_update_bits(max9867->regmap, MAX9867_CODECFLTR,
129*4882a593Smuzhiyun MAX9867_CODECFLTR_MODE, mode);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* out of shutdown now */
132*4882a593Smuzhiyun regmap_update_bits(max9867->regmap, MAX9867_PWRMAN,
133*4882a593Smuzhiyun MAX9867_PWRMAN_SHDN, MAX9867_PWRMAN_SHDN);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun static SOC_ENUM_SINGLE_EXT_DECL(max9867_filter, max9867_filter_text);
139*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(max9867_dac_filter, MAX9867_CODECFLTR, 0,
140*4882a593Smuzhiyun max9867_adc_dac_filter_text);
141*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(max9867_adc_filter, MAX9867_CODECFLTR, 4,
142*4882a593Smuzhiyun max9867_adc_dac_filter_text);
143*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(max9867_spkmode, MAX9867_MODECONFIG, 0,
144*4882a593Smuzhiyun max9867_spmode);
145*4882a593Smuzhiyun static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(max9867_master_tlv,
146*4882a593Smuzhiyun 0, 2, TLV_DB_SCALE_ITEM(-8600, 200, 1),
147*4882a593Smuzhiyun 3, 17, TLV_DB_SCALE_ITEM(-7800, 400, 0),
148*4882a593Smuzhiyun 18, 25, TLV_DB_SCALE_ITEM(-2000, 200, 0),
149*4882a593Smuzhiyun 26, 34, TLV_DB_SCALE_ITEM( -500, 100, 0),
150*4882a593Smuzhiyun 35, 40, TLV_DB_SCALE_ITEM( 350, 50, 0),
151*4882a593Smuzhiyun );
152*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(max9867_mic_tlv, 0, 100, 0);
153*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(max9867_line_tlv, -600, 200, 0);
154*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(max9867_adc_tlv, -1200, 100, 0);
155*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(max9867_dac_tlv, -1500, 100, 0);
156*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(max9867_dacboost_tlv, 0, 600, 0);
157*4882a593Smuzhiyun static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(max9867_micboost_tlv,
158*4882a593Smuzhiyun 0, 2, TLV_DB_SCALE_ITEM(-2000, 2000, 1),
159*4882a593Smuzhiyun 3, 3, TLV_DB_SCALE_ITEM(3000, 0, 0),
160*4882a593Smuzhiyun );
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun static const struct snd_kcontrol_new max9867_snd_controls[] = {
163*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Master Playback Volume", MAX9867_LEFTVOL,
164*4882a593Smuzhiyun MAX9867_RIGHTVOL, 0, 40, 1, max9867_master_tlv),
165*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Line Capture Volume", MAX9867_LEFTLINELVL,
166*4882a593Smuzhiyun MAX9867_RIGHTLINELVL, 0, 15, 1, max9867_line_tlv),
167*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Mic Capture Volume", MAX9867_LEFTMICGAIN,
168*4882a593Smuzhiyun MAX9867_RIGHTMICGAIN, 0, 20, 1, max9867_mic_tlv),
169*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Mic Boost Capture Volume", MAX9867_LEFTMICGAIN,
170*4882a593Smuzhiyun MAX9867_RIGHTMICGAIN, 5, 3, 0, max9867_micboost_tlv),
171*4882a593Smuzhiyun SOC_SINGLE("Digital Sidetone Volume", MAX9867_SIDETONE, 0, 31, 1),
172*4882a593Smuzhiyun SOC_SINGLE_TLV("Digital Playback Volume", MAX9867_DACLEVEL, 0, 15, 1,
173*4882a593Smuzhiyun max9867_dac_tlv),
174*4882a593Smuzhiyun SOC_SINGLE_TLV("Digital Boost Playback Volume", MAX9867_DACLEVEL, 4, 3, 0,
175*4882a593Smuzhiyun max9867_dacboost_tlv),
176*4882a593Smuzhiyun SOC_DOUBLE_TLV("Digital Capture Volume", MAX9867_ADCLEVEL, 4, 0, 15, 1,
177*4882a593Smuzhiyun max9867_adc_tlv),
178*4882a593Smuzhiyun SOC_ENUM("Speaker Mode", max9867_spkmode),
179*4882a593Smuzhiyun SOC_SINGLE("Volume Smoothing Switch", MAX9867_MODECONFIG, 6, 1, 0),
180*4882a593Smuzhiyun SOC_SINGLE("Line ZC Switch", MAX9867_MODECONFIG, 5, 1, 0),
181*4882a593Smuzhiyun SOC_ENUM_EXT("DSP Filter", max9867_filter, max9867_filter_get, max9867_filter_set),
182*4882a593Smuzhiyun SOC_ENUM("ADC Filter", max9867_adc_filter),
183*4882a593Smuzhiyun SOC_ENUM("DAC Filter", max9867_dac_filter),
184*4882a593Smuzhiyun SOC_SINGLE("Mono Playback Switch", MAX9867_IFC1B, 3, 1, 0),
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /* Input mixer */
188*4882a593Smuzhiyun static const struct snd_kcontrol_new max9867_input_mixer_controls[] = {
189*4882a593Smuzhiyun SOC_DAPM_DOUBLE("Line Capture Switch", MAX9867_INPUTCONFIG, 7, 5, 1, 0),
190*4882a593Smuzhiyun SOC_DAPM_DOUBLE("Mic Capture Switch", MAX9867_INPUTCONFIG, 6, 4, 1, 0),
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /* Output mixer */
194*4882a593Smuzhiyun static const struct snd_kcontrol_new max9867_output_mixer_controls[] = {
195*4882a593Smuzhiyun SOC_DAPM_DOUBLE_R("Line Bypass Switch",
196*4882a593Smuzhiyun MAX9867_LEFTLINELVL, MAX9867_RIGHTLINELVL, 6, 1, 1),
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* Sidetone mixer */
200*4882a593Smuzhiyun static const struct snd_kcontrol_new max9867_sidetone_mixer_controls[] = {
201*4882a593Smuzhiyun SOC_DAPM_DOUBLE("Sidetone Switch", MAX9867_SIDETONE, 6, 7, 1, 0),
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* Line out switch */
205*4882a593Smuzhiyun static const struct snd_kcontrol_new max9867_line_out_control =
206*4882a593Smuzhiyun SOC_DAPM_DOUBLE_R("Switch",
207*4882a593Smuzhiyun MAX9867_LEFTVOL, MAX9867_RIGHTVOL, 6, 1, 1);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun /* DMIC mux */
210*4882a593Smuzhiyun static const char *const dmic_mux_text[] = {
211*4882a593Smuzhiyun "ADC", "DMIC"
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(left_dmic_mux_enum,
214*4882a593Smuzhiyun MAX9867_MICCONFIG, 5, dmic_mux_text);
215*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(right_dmic_mux_enum,
216*4882a593Smuzhiyun MAX9867_MICCONFIG, 4, dmic_mux_text);
217*4882a593Smuzhiyun static const struct snd_kcontrol_new max9867_left_dmic_mux =
218*4882a593Smuzhiyun SOC_DAPM_ENUM("DMICL Mux", left_dmic_mux_enum);
219*4882a593Smuzhiyun static const struct snd_kcontrol_new max9867_right_dmic_mux =
220*4882a593Smuzhiyun SOC_DAPM_ENUM("DMICR Mux", right_dmic_mux_enum);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun static const struct snd_soc_dapm_widget max9867_dapm_widgets[] = {
223*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MICL"),
224*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MICR"),
225*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICL"),
226*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICR"),
227*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("LINL"),
228*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("LINR"),
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Left Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
231*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Right Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
232*4882a593Smuzhiyun SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
233*4882a593Smuzhiyun max9867_input_mixer_controls,
234*4882a593Smuzhiyun ARRAY_SIZE(max9867_input_mixer_controls)),
235*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DMICL Mux", SND_SOC_NOPM, 0, 0,
236*4882a593Smuzhiyun &max9867_left_dmic_mux),
237*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DMICR Mux", SND_SOC_NOPM, 0, 0,
238*4882a593Smuzhiyun &max9867_right_dmic_mux),
239*4882a593Smuzhiyun SND_SOC_DAPM_ADC_E("ADCL", "HiFi Capture", SND_SOC_NOPM, 0, 0,
240*4882a593Smuzhiyun max9867_adc_dac_event,
241*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
242*4882a593Smuzhiyun SND_SOC_DAPM_ADC_E("ADCR", "HiFi Capture", SND_SOC_NOPM, 0, 0,
243*4882a593Smuzhiyun max9867_adc_dac_event,
244*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Digital", SND_SOC_NOPM, 0, 0,
247*4882a593Smuzhiyun max9867_sidetone_mixer_controls,
248*4882a593Smuzhiyun ARRAY_SIZE(max9867_sidetone_mixer_controls)),
249*4882a593Smuzhiyun SND_SOC_DAPM_MIXER_NAMED_CTL("Output Mixer", SND_SOC_NOPM, 0, 0,
250*4882a593Smuzhiyun max9867_output_mixer_controls,
251*4882a593Smuzhiyun ARRAY_SIZE(max9867_output_mixer_controls)),
252*4882a593Smuzhiyun SND_SOC_DAPM_DAC_E("DACL", "HiFi Playback", SND_SOC_NOPM, 0, 0,
253*4882a593Smuzhiyun max9867_adc_dac_event,
254*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
255*4882a593Smuzhiyun SND_SOC_DAPM_DAC_E("DACR", "HiFi Playback", SND_SOC_NOPM, 0, 0,
256*4882a593Smuzhiyun max9867_adc_dac_event,
257*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
258*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("Master Playback", SND_SOC_NOPM, 0, 0,
259*4882a593Smuzhiyun &max9867_line_out_control),
260*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LOUT"),
261*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("ROUT"),
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun static const struct snd_soc_dapm_route max9867_audio_map[] = {
265*4882a593Smuzhiyun {"Left Line Input", NULL, "LINL"},
266*4882a593Smuzhiyun {"Right Line Input", NULL, "LINR"},
267*4882a593Smuzhiyun {"Input Mixer", "Mic Capture Switch", "MICL"},
268*4882a593Smuzhiyun {"Input Mixer", "Mic Capture Switch", "MICR"},
269*4882a593Smuzhiyun {"Input Mixer", "Line Capture Switch", "Left Line Input"},
270*4882a593Smuzhiyun {"Input Mixer", "Line Capture Switch", "Right Line Input"},
271*4882a593Smuzhiyun {"DMICL Mux", "DMIC", "DMICL"},
272*4882a593Smuzhiyun {"DMICR Mux", "DMIC", "DMICR"},
273*4882a593Smuzhiyun {"DMICL Mux", "ADC", "Input Mixer"},
274*4882a593Smuzhiyun {"DMICR Mux", "ADC", "Input Mixer"},
275*4882a593Smuzhiyun {"ADCL", NULL, "DMICL Mux"},
276*4882a593Smuzhiyun {"ADCR", NULL, "DMICR Mux"},
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun {"Digital", "Sidetone Switch", "ADCL"},
279*4882a593Smuzhiyun {"Digital", "Sidetone Switch", "ADCR"},
280*4882a593Smuzhiyun {"DACL", NULL, "Digital"},
281*4882a593Smuzhiyun {"DACR", NULL, "Digital"},
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun {"Output Mixer", "Line Bypass Switch", "Left Line Input"},
284*4882a593Smuzhiyun {"Output Mixer", "Line Bypass Switch", "Right Line Input"},
285*4882a593Smuzhiyun {"Output Mixer", NULL, "DACL"},
286*4882a593Smuzhiyun {"Output Mixer", NULL, "DACR"},
287*4882a593Smuzhiyun {"Master Playback", "Switch", "Output Mixer"},
288*4882a593Smuzhiyun {"LOUT", NULL, "Master Playback"},
289*4882a593Smuzhiyun {"ROUT", NULL, "Master Playback"},
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun static const unsigned int max9867_rates_44k1[] = {
293*4882a593Smuzhiyun 11025, 22050, 44100,
294*4882a593Smuzhiyun };
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list max9867_constraints_44k1 = {
297*4882a593Smuzhiyun .list = max9867_rates_44k1,
298*4882a593Smuzhiyun .count = ARRAY_SIZE(max9867_rates_44k1),
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun static const unsigned int max9867_rates_48k[] = {
302*4882a593Smuzhiyun 8000, 16000, 32000, 48000,
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list max9867_constraints_48k = {
306*4882a593Smuzhiyun .list = max9867_rates_48k,
307*4882a593Smuzhiyun .count = ARRAY_SIZE(max9867_rates_48k),
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun
max9867_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)310*4882a593Smuzhiyun static int max9867_startup(struct snd_pcm_substream *substream,
311*4882a593Smuzhiyun struct snd_soc_dai *dai)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun struct max9867_priv *max9867 =
314*4882a593Smuzhiyun snd_soc_component_get_drvdata(dai->component);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun if (max9867->constraints)
317*4882a593Smuzhiyun snd_pcm_hw_constraint_list(substream->runtime, 0,
318*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE, max9867->constraints);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun return 0;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
max9867_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)323*4882a593Smuzhiyun static int max9867_dai_hw_params(struct snd_pcm_substream *substream,
324*4882a593Smuzhiyun struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun int value;
327*4882a593Smuzhiyun unsigned long int rate, ratio;
328*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
329*4882a593Smuzhiyun struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
330*4882a593Smuzhiyun unsigned int ni = DIV_ROUND_CLOSEST_ULL(96ULL * 0x10000 * params_rate(params),
331*4882a593Smuzhiyun max9867->pclk);
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun /* set up the ni value */
334*4882a593Smuzhiyun regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKHIGH,
335*4882a593Smuzhiyun MAX9867_NI_HIGH_MASK, (0xFF00 & ni) >> 8);
336*4882a593Smuzhiyun regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKLOW,
337*4882a593Smuzhiyun MAX9867_NI_LOW_MASK, 0x00FF & ni);
338*4882a593Smuzhiyun if (max9867->master) {
339*4882a593Smuzhiyun if (max9867->dsp_a) {
340*4882a593Smuzhiyun value = MAX9867_IFC1B_48X;
341*4882a593Smuzhiyun } else {
342*4882a593Smuzhiyun rate = params_rate(params) * 2 * params_width(params);
343*4882a593Smuzhiyun ratio = max9867->pclk / rate;
344*4882a593Smuzhiyun switch (params_width(params)) {
345*4882a593Smuzhiyun case 8:
346*4882a593Smuzhiyun case 16:
347*4882a593Smuzhiyun switch (ratio) {
348*4882a593Smuzhiyun case 2:
349*4882a593Smuzhiyun value = MAX9867_IFC1B_PCLK_2;
350*4882a593Smuzhiyun break;
351*4882a593Smuzhiyun case 4:
352*4882a593Smuzhiyun value = MAX9867_IFC1B_PCLK_4;
353*4882a593Smuzhiyun break;
354*4882a593Smuzhiyun case 8:
355*4882a593Smuzhiyun value = MAX9867_IFC1B_PCLK_8;
356*4882a593Smuzhiyun break;
357*4882a593Smuzhiyun case 16:
358*4882a593Smuzhiyun value = MAX9867_IFC1B_PCLK_16;
359*4882a593Smuzhiyun break;
360*4882a593Smuzhiyun default:
361*4882a593Smuzhiyun return -EINVAL;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun break;
364*4882a593Smuzhiyun case 24:
365*4882a593Smuzhiyun value = MAX9867_IFC1B_48X;
366*4882a593Smuzhiyun break;
367*4882a593Smuzhiyun case 32:
368*4882a593Smuzhiyun value = MAX9867_IFC1B_64X;
369*4882a593Smuzhiyun break;
370*4882a593Smuzhiyun default:
371*4882a593Smuzhiyun return -EINVAL;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun regmap_update_bits(max9867->regmap, MAX9867_IFC1B,
375*4882a593Smuzhiyun MAX9867_IFC1B_BCLK_MASK, value);
376*4882a593Smuzhiyun } else {
377*4882a593Smuzhiyun /*
378*4882a593Smuzhiyun * digital pll locks on to any externally supplied LRCLK signal
379*4882a593Smuzhiyun * and also enable rapid lock mode.
380*4882a593Smuzhiyun */
381*4882a593Smuzhiyun regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKLOW,
382*4882a593Smuzhiyun MAX9867_RAPID_LOCK, MAX9867_RAPID_LOCK);
383*4882a593Smuzhiyun regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKHIGH,
384*4882a593Smuzhiyun MAX9867_PLL, MAX9867_PLL);
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun return 0;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
max9867_mute(struct snd_soc_dai * dai,int mute,int direction)389*4882a593Smuzhiyun static int max9867_mute(struct snd_soc_dai *dai, int mute, int direction)
390*4882a593Smuzhiyun {
391*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
392*4882a593Smuzhiyun struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun return regmap_update_bits(max9867->regmap, MAX9867_DACLEVEL,
395*4882a593Smuzhiyun 1 << 6, !!mute << 6);
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
max9867_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)398*4882a593Smuzhiyun static int max9867_set_dai_sysclk(struct snd_soc_dai *codec_dai,
399*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
402*4882a593Smuzhiyun struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
403*4882a593Smuzhiyun int value = 0;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun /* Set the prescaler based on the master clock frequency*/
406*4882a593Smuzhiyun if (freq >= 10000000 && freq <= 20000000) {
407*4882a593Smuzhiyun value |= MAX9867_PSCLK_10_20;
408*4882a593Smuzhiyun max9867->pclk = freq;
409*4882a593Smuzhiyun } else if (freq >= 20000000 && freq <= 40000000) {
410*4882a593Smuzhiyun value |= MAX9867_PSCLK_20_40;
411*4882a593Smuzhiyun max9867->pclk = freq / 2;
412*4882a593Smuzhiyun } else if (freq >= 40000000 && freq <= 60000000) {
413*4882a593Smuzhiyun value |= MAX9867_PSCLK_40_60;
414*4882a593Smuzhiyun max9867->pclk = freq / 4;
415*4882a593Smuzhiyun } else {
416*4882a593Smuzhiyun dev_err(component->dev,
417*4882a593Smuzhiyun "Invalid clock frequency %uHz (required 10-60MHz)\n",
418*4882a593Smuzhiyun freq);
419*4882a593Smuzhiyun return -EINVAL;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun if (freq % 48000 == 0)
422*4882a593Smuzhiyun max9867->constraints = &max9867_constraints_48k;
423*4882a593Smuzhiyun else if (freq % 44100 == 0)
424*4882a593Smuzhiyun max9867->constraints = &max9867_constraints_44k1;
425*4882a593Smuzhiyun else
426*4882a593Smuzhiyun dev_warn(component->dev,
427*4882a593Smuzhiyun "Unable to set exact rate with %uHz clock frequency\n",
428*4882a593Smuzhiyun freq);
429*4882a593Smuzhiyun max9867->sysclk = freq;
430*4882a593Smuzhiyun value = value << MAX9867_PSCLK_SHIFT;
431*4882a593Smuzhiyun /* exact integer mode is not supported */
432*4882a593Smuzhiyun value &= ~MAX9867_FREQ_MASK;
433*4882a593Smuzhiyun regmap_update_bits(max9867->regmap, MAX9867_SYSCLK,
434*4882a593Smuzhiyun MAX9867_PSCLK_MASK, value);
435*4882a593Smuzhiyun return 0;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
max9867_dai_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)438*4882a593Smuzhiyun static int max9867_dai_set_fmt(struct snd_soc_dai *codec_dai,
439*4882a593Smuzhiyun unsigned int fmt)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
442*4882a593Smuzhiyun struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
443*4882a593Smuzhiyun u8 iface1A, iface1B;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
446*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
447*4882a593Smuzhiyun max9867->master = true;
448*4882a593Smuzhiyun iface1A = MAX9867_MASTER;
449*4882a593Smuzhiyun iface1B = MAX9867_IFC1B_48X;
450*4882a593Smuzhiyun break;
451*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
452*4882a593Smuzhiyun max9867->master = false;
453*4882a593Smuzhiyun iface1A = iface1B = 0;
454*4882a593Smuzhiyun break;
455*4882a593Smuzhiyun default:
456*4882a593Smuzhiyun return -EINVAL;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
460*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
461*4882a593Smuzhiyun max9867->dsp_a = false;
462*4882a593Smuzhiyun iface1A |= MAX9867_I2S_DLY;
463*4882a593Smuzhiyun break;
464*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
465*4882a593Smuzhiyun max9867->dsp_a = true;
466*4882a593Smuzhiyun iface1A |= MAX9867_TDM_MODE | MAX9867_SDOUT_HIZ;
467*4882a593Smuzhiyun break;
468*4882a593Smuzhiyun default:
469*4882a593Smuzhiyun return -EINVAL;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun /* Clock inversion bits, BCI and WCI */
473*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
474*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
475*4882a593Smuzhiyun break;
476*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
477*4882a593Smuzhiyun iface1A |= MAX9867_WCI_MODE | MAX9867_BCI_MODE;
478*4882a593Smuzhiyun break;
479*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
480*4882a593Smuzhiyun iface1A |= MAX9867_BCI_MODE;
481*4882a593Smuzhiyun break;
482*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
483*4882a593Smuzhiyun iface1A |= MAX9867_WCI_MODE;
484*4882a593Smuzhiyun break;
485*4882a593Smuzhiyun default:
486*4882a593Smuzhiyun return -EINVAL;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun regmap_write(max9867->regmap, MAX9867_IFC1A, iface1A);
490*4882a593Smuzhiyun regmap_update_bits(max9867->regmap, MAX9867_IFC1B,
491*4882a593Smuzhiyun MAX9867_IFC1B_BCLK_MASK, iface1B);
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun return 0;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun static const struct snd_soc_dai_ops max9867_dai_ops = {
497*4882a593Smuzhiyun .set_sysclk = max9867_set_dai_sysclk,
498*4882a593Smuzhiyun .set_fmt = max9867_dai_set_fmt,
499*4882a593Smuzhiyun .mute_stream = max9867_mute,
500*4882a593Smuzhiyun .startup = max9867_startup,
501*4882a593Smuzhiyun .hw_params = max9867_dai_hw_params,
502*4882a593Smuzhiyun .no_capture_mute = 1,
503*4882a593Smuzhiyun };
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun static struct snd_soc_dai_driver max9867_dai[] = {
506*4882a593Smuzhiyun {
507*4882a593Smuzhiyun .name = "max9867-aif1",
508*4882a593Smuzhiyun .playback = {
509*4882a593Smuzhiyun .stream_name = "HiFi Playback",
510*4882a593Smuzhiyun .channels_min = 2,
511*4882a593Smuzhiyun .channels_max = 2,
512*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_48000,
513*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S16_LE,
514*4882a593Smuzhiyun },
515*4882a593Smuzhiyun .capture = {
516*4882a593Smuzhiyun .stream_name = "HiFi Capture",
517*4882a593Smuzhiyun .channels_min = 2,
518*4882a593Smuzhiyun .channels_max = 2,
519*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_48000,
520*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S16_LE,
521*4882a593Smuzhiyun },
522*4882a593Smuzhiyun .ops = &max9867_dai_ops,
523*4882a593Smuzhiyun .symmetric_rates = 1,
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun };
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun #ifdef CONFIG_PM
max9867_suspend(struct snd_soc_component * component)528*4882a593Smuzhiyun static int max9867_suspend(struct snd_soc_component *component)
529*4882a593Smuzhiyun {
530*4882a593Smuzhiyun snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun return 0;
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun
max9867_resume(struct snd_soc_component * component)535*4882a593Smuzhiyun static int max9867_resume(struct snd_soc_component *component)
536*4882a593Smuzhiyun {
537*4882a593Smuzhiyun snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun return 0;
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun #else
542*4882a593Smuzhiyun #define max9867_suspend NULL
543*4882a593Smuzhiyun #define max9867_resume NULL
544*4882a593Smuzhiyun #endif
545*4882a593Smuzhiyun
max9867_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)546*4882a593Smuzhiyun static int max9867_set_bias_level(struct snd_soc_component *component,
547*4882a593Smuzhiyun enum snd_soc_bias_level level)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun int err;
550*4882a593Smuzhiyun struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun switch (level) {
553*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
554*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
555*4882a593Smuzhiyun err = regcache_sync(max9867->regmap);
556*4882a593Smuzhiyun if (err)
557*4882a593Smuzhiyun return err;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun err = regmap_write(max9867->regmap,
560*4882a593Smuzhiyun MAX9867_PWRMAN, 0xff);
561*4882a593Smuzhiyun if (err)
562*4882a593Smuzhiyun return err;
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun break;
565*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
566*4882a593Smuzhiyun err = regmap_write(max9867->regmap, MAX9867_PWRMAN, 0);
567*4882a593Smuzhiyun if (err)
568*4882a593Smuzhiyun return err;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun regcache_mark_dirty(max9867->regmap);
571*4882a593Smuzhiyun break;
572*4882a593Smuzhiyun default:
573*4882a593Smuzhiyun break;
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun return 0;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun static const struct snd_soc_component_driver max9867_component = {
580*4882a593Smuzhiyun .controls = max9867_snd_controls,
581*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(max9867_snd_controls),
582*4882a593Smuzhiyun .dapm_routes = max9867_audio_map,
583*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(max9867_audio_map),
584*4882a593Smuzhiyun .dapm_widgets = max9867_dapm_widgets,
585*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(max9867_dapm_widgets),
586*4882a593Smuzhiyun .suspend = max9867_suspend,
587*4882a593Smuzhiyun .resume = max9867_resume,
588*4882a593Smuzhiyun .set_bias_level = max9867_set_bias_level,
589*4882a593Smuzhiyun .idle_bias_on = 1,
590*4882a593Smuzhiyun .use_pmdown_time = 1,
591*4882a593Smuzhiyun .endianness = 1,
592*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
593*4882a593Smuzhiyun };
594*4882a593Smuzhiyun
max9867_volatile_register(struct device * dev,unsigned int reg)595*4882a593Smuzhiyun static bool max9867_volatile_register(struct device *dev, unsigned int reg)
596*4882a593Smuzhiyun {
597*4882a593Smuzhiyun switch (reg) {
598*4882a593Smuzhiyun case MAX9867_STATUS:
599*4882a593Smuzhiyun case MAX9867_JACKSTATUS:
600*4882a593Smuzhiyun case MAX9867_AUXHIGH:
601*4882a593Smuzhiyun case MAX9867_AUXLOW:
602*4882a593Smuzhiyun return true;
603*4882a593Smuzhiyun default:
604*4882a593Smuzhiyun return false;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun static const struct regmap_config max9867_regmap = {
609*4882a593Smuzhiyun .reg_bits = 8,
610*4882a593Smuzhiyun .val_bits = 8,
611*4882a593Smuzhiyun .max_register = MAX9867_REVISION,
612*4882a593Smuzhiyun .volatile_reg = max9867_volatile_register,
613*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
614*4882a593Smuzhiyun };
615*4882a593Smuzhiyun
max9867_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)616*4882a593Smuzhiyun static int max9867_i2c_probe(struct i2c_client *i2c,
617*4882a593Smuzhiyun const struct i2c_device_id *id)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun struct max9867_priv *max9867;
620*4882a593Smuzhiyun int ret, reg;
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun max9867 = devm_kzalloc(&i2c->dev, sizeof(*max9867), GFP_KERNEL);
623*4882a593Smuzhiyun if (!max9867)
624*4882a593Smuzhiyun return -ENOMEM;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun i2c_set_clientdata(i2c, max9867);
627*4882a593Smuzhiyun max9867->regmap = devm_regmap_init_i2c(i2c, &max9867_regmap);
628*4882a593Smuzhiyun if (IS_ERR(max9867->regmap)) {
629*4882a593Smuzhiyun ret = PTR_ERR(max9867->regmap);
630*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
631*4882a593Smuzhiyun return ret;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun ret = regmap_read(max9867->regmap, MAX9867_REVISION, ®);
634*4882a593Smuzhiyun if (ret < 0) {
635*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to read: %d\n", ret);
636*4882a593Smuzhiyun return ret;
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun dev_info(&i2c->dev, "device revision: %x\n", reg);
639*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev, &max9867_component,
640*4882a593Smuzhiyun max9867_dai, ARRAY_SIZE(max9867_dai));
641*4882a593Smuzhiyun if (ret < 0)
642*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
643*4882a593Smuzhiyun return ret;
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun static const struct i2c_device_id max9867_i2c_id[] = {
647*4882a593Smuzhiyun { "max9867", 0 },
648*4882a593Smuzhiyun { }
649*4882a593Smuzhiyun };
650*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, max9867_i2c_id);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun static const struct of_device_id max9867_of_match[] = {
653*4882a593Smuzhiyun { .compatible = "maxim,max9867", },
654*4882a593Smuzhiyun { }
655*4882a593Smuzhiyun };
656*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max9867_of_match);
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun static struct i2c_driver max9867_i2c_driver = {
659*4882a593Smuzhiyun .driver = {
660*4882a593Smuzhiyun .name = "max9867",
661*4882a593Smuzhiyun .of_match_table = of_match_ptr(max9867_of_match),
662*4882a593Smuzhiyun },
663*4882a593Smuzhiyun .probe = max9867_i2c_probe,
664*4882a593Smuzhiyun .id_table = max9867_i2c_id,
665*4882a593Smuzhiyun };
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun module_i2c_driver(max9867_i2c_driver);
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun MODULE_AUTHOR("Ladislav Michl <ladis@linux-mips.org>");
670*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC MAX9867 driver");
671*4882a593Smuzhiyun MODULE_LICENSE("GPL");
672