1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * max98371.c -- ALSA SoC Stereo MAX98371 driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2015-16 Maxim Integrated Products
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/i2c.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/regmap.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <sound/pcm.h>
13*4882a593Smuzhiyun #include <sound/pcm_params.h>
14*4882a593Smuzhiyun #include <sound/soc.h>
15*4882a593Smuzhiyun #include <sound/tlv.h>
16*4882a593Smuzhiyun #include "max98371.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static const char *const monomix_text[] = {
19*4882a593Smuzhiyun "Left", "Right", "LeftRightDiv2",
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static const char *const hpf_cutoff_txt[] = {
23*4882a593Smuzhiyun "Disable", "DC Block", "50Hz",
24*4882a593Smuzhiyun "100Hz", "200Hz", "400Hz", "800Hz",
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(max98371_monomix, MAX98371_MONOMIX_CFG, 0,
28*4882a593Smuzhiyun monomix_text);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(max98371_hpf_cutoff, MAX98371_HPF, 0,
31*4882a593Smuzhiyun hpf_cutoff_txt);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(max98371_dht_min_gain,
34*4882a593Smuzhiyun 0, 1, TLV_DB_SCALE_ITEM(537, 66, 0),
35*4882a593Smuzhiyun 2, 3, TLV_DB_SCALE_ITEM(677, 82, 0),
36*4882a593Smuzhiyun 4, 5, TLV_DB_SCALE_ITEM(852, 104, 0),
37*4882a593Smuzhiyun 6, 7, TLV_DB_SCALE_ITEM(1072, 131, 0),
38*4882a593Smuzhiyun 8, 9, TLV_DB_SCALE_ITEM(1350, 165, 0),
39*4882a593Smuzhiyun 10, 11, TLV_DB_SCALE_ITEM(1699, 101, 0),
40*4882a593Smuzhiyun );
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(max98371_dht_max_gain,
43*4882a593Smuzhiyun 0, 1, TLV_DB_SCALE_ITEM(537, 66, 0),
44*4882a593Smuzhiyun 2, 3, TLV_DB_SCALE_ITEM(677, 82, 0),
45*4882a593Smuzhiyun 4, 5, TLV_DB_SCALE_ITEM(852, 104, 0),
46*4882a593Smuzhiyun 6, 7, TLV_DB_SCALE_ITEM(1072, 131, 0),
47*4882a593Smuzhiyun 8, 9, TLV_DB_SCALE_ITEM(1350, 165, 0),
48*4882a593Smuzhiyun 10, 11, TLV_DB_SCALE_ITEM(1699, 208, 0),
49*4882a593Smuzhiyun );
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(max98371_dht_rot_gain,
52*4882a593Smuzhiyun 0, 1, TLV_DB_SCALE_ITEM(-50, -50, 0),
53*4882a593Smuzhiyun 2, 6, TLV_DB_SCALE_ITEM(-100, -100, 0),
54*4882a593Smuzhiyun 7, 8, TLV_DB_SCALE_ITEM(-800, -200, 0),
55*4882a593Smuzhiyun 9, 11, TLV_DB_SCALE_ITEM(-1200, -300, 0),
56*4882a593Smuzhiyun 12, 13, TLV_DB_SCALE_ITEM(-2000, -200, 0),
57*4882a593Smuzhiyun 14, 15, TLV_DB_SCALE_ITEM(-2500, -500, 0),
58*4882a593Smuzhiyun );
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static const struct reg_default max98371_reg[] = {
61*4882a593Smuzhiyun { 0x01, 0x00 },
62*4882a593Smuzhiyun { 0x02, 0x00 },
63*4882a593Smuzhiyun { 0x03, 0x00 },
64*4882a593Smuzhiyun { 0x04, 0x00 },
65*4882a593Smuzhiyun { 0x05, 0x00 },
66*4882a593Smuzhiyun { 0x06, 0x00 },
67*4882a593Smuzhiyun { 0x07, 0x00 },
68*4882a593Smuzhiyun { 0x08, 0x00 },
69*4882a593Smuzhiyun { 0x09, 0x00 },
70*4882a593Smuzhiyun { 0x0A, 0x00 },
71*4882a593Smuzhiyun { 0x10, 0x06 },
72*4882a593Smuzhiyun { 0x11, 0x08 },
73*4882a593Smuzhiyun { 0x14, 0x80 },
74*4882a593Smuzhiyun { 0x15, 0x00 },
75*4882a593Smuzhiyun { 0x16, 0x00 },
76*4882a593Smuzhiyun { 0x18, 0x00 },
77*4882a593Smuzhiyun { 0x19, 0x00 },
78*4882a593Smuzhiyun { 0x1C, 0x00 },
79*4882a593Smuzhiyun { 0x1D, 0x00 },
80*4882a593Smuzhiyun { 0x1E, 0x00 },
81*4882a593Smuzhiyun { 0x1F, 0x00 },
82*4882a593Smuzhiyun { 0x20, 0x00 },
83*4882a593Smuzhiyun { 0x21, 0x00 },
84*4882a593Smuzhiyun { 0x22, 0x00 },
85*4882a593Smuzhiyun { 0x23, 0x00 },
86*4882a593Smuzhiyun { 0x24, 0x00 },
87*4882a593Smuzhiyun { 0x25, 0x00 },
88*4882a593Smuzhiyun { 0x26, 0x00 },
89*4882a593Smuzhiyun { 0x27, 0x00 },
90*4882a593Smuzhiyun { 0x28, 0x00 },
91*4882a593Smuzhiyun { 0x29, 0x00 },
92*4882a593Smuzhiyun { 0x2A, 0x00 },
93*4882a593Smuzhiyun { 0x2B, 0x00 },
94*4882a593Smuzhiyun { 0x2C, 0x00 },
95*4882a593Smuzhiyun { 0x2D, 0x00 },
96*4882a593Smuzhiyun { 0x2E, 0x0B },
97*4882a593Smuzhiyun { 0x31, 0x00 },
98*4882a593Smuzhiyun { 0x32, 0x18 },
99*4882a593Smuzhiyun { 0x33, 0x00 },
100*4882a593Smuzhiyun { 0x34, 0x00 },
101*4882a593Smuzhiyun { 0x36, 0x00 },
102*4882a593Smuzhiyun { 0x37, 0x00 },
103*4882a593Smuzhiyun { 0x38, 0x00 },
104*4882a593Smuzhiyun { 0x39, 0x00 },
105*4882a593Smuzhiyun { 0x3A, 0x00 },
106*4882a593Smuzhiyun { 0x3B, 0x00 },
107*4882a593Smuzhiyun { 0x3C, 0x00 },
108*4882a593Smuzhiyun { 0x3D, 0x00 },
109*4882a593Smuzhiyun { 0x3E, 0x00 },
110*4882a593Smuzhiyun { 0x3F, 0x00 },
111*4882a593Smuzhiyun { 0x40, 0x00 },
112*4882a593Smuzhiyun { 0x41, 0x00 },
113*4882a593Smuzhiyun { 0x42, 0x00 },
114*4882a593Smuzhiyun { 0x43, 0x00 },
115*4882a593Smuzhiyun { 0x4A, 0x00 },
116*4882a593Smuzhiyun { 0x4B, 0x00 },
117*4882a593Smuzhiyun { 0x4C, 0x00 },
118*4882a593Smuzhiyun { 0x4D, 0x00 },
119*4882a593Smuzhiyun { 0x4E, 0x00 },
120*4882a593Smuzhiyun { 0x50, 0x00 },
121*4882a593Smuzhiyun { 0x51, 0x00 },
122*4882a593Smuzhiyun { 0x55, 0x00 },
123*4882a593Smuzhiyun { 0x58, 0x00 },
124*4882a593Smuzhiyun { 0x59, 0x00 },
125*4882a593Smuzhiyun { 0x5C, 0x00 },
126*4882a593Smuzhiyun { 0xFF, 0x43 },
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
max98371_volatile_register(struct device * dev,unsigned int reg)129*4882a593Smuzhiyun static bool max98371_volatile_register(struct device *dev, unsigned int reg)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun switch (reg) {
132*4882a593Smuzhiyun case MAX98371_IRQ_CLEAR1:
133*4882a593Smuzhiyun case MAX98371_IRQ_CLEAR2:
134*4882a593Smuzhiyun case MAX98371_IRQ_CLEAR3:
135*4882a593Smuzhiyun case MAX98371_VERSION:
136*4882a593Smuzhiyun return true;
137*4882a593Smuzhiyun default:
138*4882a593Smuzhiyun return false;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
max98371_readable_register(struct device * dev,unsigned int reg)142*4882a593Smuzhiyun static bool max98371_readable_register(struct device *dev, unsigned int reg)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun switch (reg) {
145*4882a593Smuzhiyun case MAX98371_SOFT_RESET:
146*4882a593Smuzhiyun return false;
147*4882a593Smuzhiyun default:
148*4882a593Smuzhiyun return true;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(max98371_gain_tlv,
153*4882a593Smuzhiyun 0, 7, TLV_DB_SCALE_ITEM(0, 50, 0),
154*4882a593Smuzhiyun 8, 10, TLV_DB_SCALE_ITEM(400, 100, 0)
155*4882a593Smuzhiyun );
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(digital_tlv, -6300, 50, 1);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static const struct snd_kcontrol_new max98371_snd_controls[] = {
160*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker Volume", MAX98371_GAIN,
161*4882a593Smuzhiyun MAX98371_GAIN_SHIFT, (1<<MAX98371_GAIN_WIDTH)-1, 0,
162*4882a593Smuzhiyun max98371_gain_tlv),
163*4882a593Smuzhiyun SOC_SINGLE_TLV("Digital Volume", MAX98371_DIGITAL_GAIN, 0,
164*4882a593Smuzhiyun (1<<MAX98371_DIGITAL_GAIN_WIDTH)-1, 1, digital_tlv),
165*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker DHT Max Volume", MAX98371_GAIN,
166*4882a593Smuzhiyun 0, (1<<MAX98371_DHT_MAX_WIDTH)-1, 0,
167*4882a593Smuzhiyun max98371_dht_max_gain),
168*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker DHT Min Volume", MAX98371_DHT_GAIN,
169*4882a593Smuzhiyun 0, (1<<MAX98371_DHT_GAIN_WIDTH)-1, 0,
170*4882a593Smuzhiyun max98371_dht_min_gain),
171*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker DHT Rotation Volume", MAX98371_DHT_GAIN,
172*4882a593Smuzhiyun 0, (1<<MAX98371_DHT_ROT_WIDTH)-1, 0,
173*4882a593Smuzhiyun max98371_dht_rot_gain),
174*4882a593Smuzhiyun SOC_SINGLE("DHT Attack Step", MAX98371_DHT, MAX98371_DHT_STEP, 3, 0),
175*4882a593Smuzhiyun SOC_SINGLE("DHT Attack Rate", MAX98371_DHT, 0, 7, 0),
176*4882a593Smuzhiyun SOC_ENUM("Monomix Select", max98371_monomix),
177*4882a593Smuzhiyun SOC_ENUM("HPF Cutoff", max98371_hpf_cutoff),
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
max98371_dai_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)180*4882a593Smuzhiyun static int max98371_dai_set_fmt(struct snd_soc_dai *codec_dai,
181*4882a593Smuzhiyun unsigned int fmt)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
184*4882a593Smuzhiyun struct max98371_priv *max98371 = snd_soc_component_get_drvdata(component);
185*4882a593Smuzhiyun unsigned int val = 0;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
188*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
189*4882a593Smuzhiyun break;
190*4882a593Smuzhiyun default:
191*4882a593Smuzhiyun dev_err(component->dev, "DAI clock mode unsupported");
192*4882a593Smuzhiyun return -EINVAL;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
196*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
197*4882a593Smuzhiyun val |= 0;
198*4882a593Smuzhiyun break;
199*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
200*4882a593Smuzhiyun val |= MAX98371_DAI_RIGHT;
201*4882a593Smuzhiyun break;
202*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
203*4882a593Smuzhiyun val |= MAX98371_DAI_LEFT;
204*4882a593Smuzhiyun break;
205*4882a593Smuzhiyun default:
206*4882a593Smuzhiyun dev_err(component->dev, "DAI wrong mode unsupported");
207*4882a593Smuzhiyun return -EINVAL;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun regmap_update_bits(max98371->regmap, MAX98371_FMT,
210*4882a593Smuzhiyun MAX98371_FMT_MODE_MASK, val);
211*4882a593Smuzhiyun return 0;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
max98371_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)214*4882a593Smuzhiyun static int max98371_dai_hw_params(struct snd_pcm_substream *substream,
215*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
216*4882a593Smuzhiyun struct snd_soc_dai *dai)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
219*4882a593Smuzhiyun struct max98371_priv *max98371 = snd_soc_component_get_drvdata(component);
220*4882a593Smuzhiyun int blr_clk_ratio, ch_size, channels = params_channels(params);
221*4882a593Smuzhiyun int rate = params_rate(params);
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun switch (params_format(params)) {
224*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S8:
225*4882a593Smuzhiyun regmap_update_bits(max98371->regmap, MAX98371_FMT,
226*4882a593Smuzhiyun MAX98371_FMT_MASK, MAX98371_DAI_CHANSZ_16);
227*4882a593Smuzhiyun ch_size = 8;
228*4882a593Smuzhiyun break;
229*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S16_LE:
230*4882a593Smuzhiyun regmap_update_bits(max98371->regmap, MAX98371_FMT,
231*4882a593Smuzhiyun MAX98371_FMT_MASK, MAX98371_DAI_CHANSZ_16);
232*4882a593Smuzhiyun ch_size = 16;
233*4882a593Smuzhiyun break;
234*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S24_LE:
235*4882a593Smuzhiyun regmap_update_bits(max98371->regmap, MAX98371_FMT,
236*4882a593Smuzhiyun MAX98371_FMT_MASK, MAX98371_DAI_CHANSZ_32);
237*4882a593Smuzhiyun ch_size = 24;
238*4882a593Smuzhiyun break;
239*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S32_LE:
240*4882a593Smuzhiyun regmap_update_bits(max98371->regmap, MAX98371_FMT,
241*4882a593Smuzhiyun MAX98371_FMT_MASK, MAX98371_DAI_CHANSZ_32);
242*4882a593Smuzhiyun ch_size = 32;
243*4882a593Smuzhiyun break;
244*4882a593Smuzhiyun default:
245*4882a593Smuzhiyun return -EINVAL;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* BCLK/LRCLK ratio calculation */
249*4882a593Smuzhiyun blr_clk_ratio = channels * ch_size;
250*4882a593Smuzhiyun switch (blr_clk_ratio) {
251*4882a593Smuzhiyun case 32:
252*4882a593Smuzhiyun regmap_update_bits(max98371->regmap,
253*4882a593Smuzhiyun MAX98371_DAI_CLK,
254*4882a593Smuzhiyun MAX98371_DAI_BSEL_MASK, MAX98371_DAI_BSEL_32);
255*4882a593Smuzhiyun break;
256*4882a593Smuzhiyun case 48:
257*4882a593Smuzhiyun regmap_update_bits(max98371->regmap,
258*4882a593Smuzhiyun MAX98371_DAI_CLK,
259*4882a593Smuzhiyun MAX98371_DAI_BSEL_MASK, MAX98371_DAI_BSEL_48);
260*4882a593Smuzhiyun break;
261*4882a593Smuzhiyun case 64:
262*4882a593Smuzhiyun regmap_update_bits(max98371->regmap,
263*4882a593Smuzhiyun MAX98371_DAI_CLK,
264*4882a593Smuzhiyun MAX98371_DAI_BSEL_MASK, MAX98371_DAI_BSEL_64);
265*4882a593Smuzhiyun break;
266*4882a593Smuzhiyun default:
267*4882a593Smuzhiyun return -EINVAL;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun switch (rate) {
271*4882a593Smuzhiyun case 32000:
272*4882a593Smuzhiyun regmap_update_bits(max98371->regmap,
273*4882a593Smuzhiyun MAX98371_SPK_SR,
274*4882a593Smuzhiyun MAX98371_SPK_SR_MASK, MAX98371_SPK_SR_32);
275*4882a593Smuzhiyun break;
276*4882a593Smuzhiyun case 44100:
277*4882a593Smuzhiyun regmap_update_bits(max98371->regmap,
278*4882a593Smuzhiyun MAX98371_SPK_SR,
279*4882a593Smuzhiyun MAX98371_SPK_SR_MASK, MAX98371_SPK_SR_44);
280*4882a593Smuzhiyun break;
281*4882a593Smuzhiyun case 48000:
282*4882a593Smuzhiyun regmap_update_bits(max98371->regmap,
283*4882a593Smuzhiyun MAX98371_SPK_SR,
284*4882a593Smuzhiyun MAX98371_SPK_SR_MASK, MAX98371_SPK_SR_48);
285*4882a593Smuzhiyun break;
286*4882a593Smuzhiyun case 88200:
287*4882a593Smuzhiyun regmap_update_bits(max98371->regmap,
288*4882a593Smuzhiyun MAX98371_SPK_SR,
289*4882a593Smuzhiyun MAX98371_SPK_SR_MASK, MAX98371_SPK_SR_88);
290*4882a593Smuzhiyun break;
291*4882a593Smuzhiyun case 96000:
292*4882a593Smuzhiyun regmap_update_bits(max98371->regmap,
293*4882a593Smuzhiyun MAX98371_SPK_SR,
294*4882a593Smuzhiyun MAX98371_SPK_SR_MASK, MAX98371_SPK_SR_96);
295*4882a593Smuzhiyun break;
296*4882a593Smuzhiyun default:
297*4882a593Smuzhiyun return -EINVAL;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun /* enabling both the RX channels*/
301*4882a593Smuzhiyun regmap_update_bits(max98371->regmap, MAX98371_MONOMIX_SRC,
302*4882a593Smuzhiyun MAX98371_MONOMIX_SRC_MASK, MONOMIX_RX_0_1);
303*4882a593Smuzhiyun regmap_update_bits(max98371->regmap, MAX98371_DAI_CHANNEL,
304*4882a593Smuzhiyun MAX98371_CHANNEL_MASK, MAX98371_CHANNEL_MASK);
305*4882a593Smuzhiyun return 0;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun static const struct snd_soc_dapm_widget max98371_dapm_widgets[] = {
309*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC", NULL, MAX98371_SPK_ENABLE, 0, 0),
310*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Global Enable", MAX98371_GLOBAL_ENABLE,
311*4882a593Smuzhiyun 0, 0, NULL, 0),
312*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPK_OUT"),
313*4882a593Smuzhiyun };
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun static const struct snd_soc_dapm_route max98371_audio_map[] = {
316*4882a593Smuzhiyun {"DAC", NULL, "HiFi Playback"},
317*4882a593Smuzhiyun {"SPK_OUT", NULL, "DAC"},
318*4882a593Smuzhiyun {"SPK_OUT", NULL, "Global Enable"},
319*4882a593Smuzhiyun };
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun #define MAX98371_RATES SNDRV_PCM_RATE_8000_48000
322*4882a593Smuzhiyun #define MAX98371_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
323*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE)
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun static const struct snd_soc_dai_ops max98371_dai_ops = {
326*4882a593Smuzhiyun .set_fmt = max98371_dai_set_fmt,
327*4882a593Smuzhiyun .hw_params = max98371_dai_hw_params,
328*4882a593Smuzhiyun };
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun static struct snd_soc_dai_driver max98371_dai[] = {
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun .name = "max98371-aif1",
333*4882a593Smuzhiyun .playback = {
334*4882a593Smuzhiyun .stream_name = "HiFi Playback",
335*4882a593Smuzhiyun .channels_min = 1,
336*4882a593Smuzhiyun .channels_max = 2,
337*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_48000,
338*4882a593Smuzhiyun .formats = MAX98371_FORMATS,
339*4882a593Smuzhiyun },
340*4882a593Smuzhiyun .ops = &max98371_dai_ops,
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun };
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun static const struct snd_soc_component_driver max98371_component = {
345*4882a593Smuzhiyun .controls = max98371_snd_controls,
346*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(max98371_snd_controls),
347*4882a593Smuzhiyun .dapm_routes = max98371_audio_map,
348*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(max98371_audio_map),
349*4882a593Smuzhiyun .dapm_widgets = max98371_dapm_widgets,
350*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(max98371_dapm_widgets),
351*4882a593Smuzhiyun .idle_bias_on = 1,
352*4882a593Smuzhiyun .use_pmdown_time = 1,
353*4882a593Smuzhiyun .endianness = 1,
354*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
355*4882a593Smuzhiyun };
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun static const struct regmap_config max98371_regmap = {
358*4882a593Smuzhiyun .reg_bits = 8,
359*4882a593Smuzhiyun .val_bits = 8,
360*4882a593Smuzhiyun .max_register = MAX98371_VERSION,
361*4882a593Smuzhiyun .reg_defaults = max98371_reg,
362*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(max98371_reg),
363*4882a593Smuzhiyun .volatile_reg = max98371_volatile_register,
364*4882a593Smuzhiyun .readable_reg = max98371_readable_register,
365*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
366*4882a593Smuzhiyun };
367*4882a593Smuzhiyun
max98371_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)368*4882a593Smuzhiyun static int max98371_i2c_probe(struct i2c_client *i2c,
369*4882a593Smuzhiyun const struct i2c_device_id *id)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun struct max98371_priv *max98371;
372*4882a593Smuzhiyun int ret, reg;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun max98371 = devm_kzalloc(&i2c->dev,
375*4882a593Smuzhiyun sizeof(*max98371), GFP_KERNEL);
376*4882a593Smuzhiyun if (!max98371)
377*4882a593Smuzhiyun return -ENOMEM;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun i2c_set_clientdata(i2c, max98371);
380*4882a593Smuzhiyun max98371->regmap = devm_regmap_init_i2c(i2c, &max98371_regmap);
381*4882a593Smuzhiyun if (IS_ERR(max98371->regmap)) {
382*4882a593Smuzhiyun ret = PTR_ERR(max98371->regmap);
383*4882a593Smuzhiyun dev_err(&i2c->dev,
384*4882a593Smuzhiyun "Failed to allocate regmap: %d\n", ret);
385*4882a593Smuzhiyun return ret;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun ret = regmap_read(max98371->regmap, MAX98371_VERSION, ®);
389*4882a593Smuzhiyun if (ret < 0) {
390*4882a593Smuzhiyun dev_info(&i2c->dev, "device error %d\n", ret);
391*4882a593Smuzhiyun return ret;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun dev_info(&i2c->dev, "device version %x\n", reg);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev, &max98371_component,
396*4882a593Smuzhiyun max98371_dai, ARRAY_SIZE(max98371_dai));
397*4882a593Smuzhiyun if (ret < 0) {
398*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
399*4882a593Smuzhiyun return ret;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun return ret;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun static const struct i2c_device_id max98371_i2c_id[] = {
405*4882a593Smuzhiyun { "max98371", 0 },
406*4882a593Smuzhiyun { }
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, max98371_i2c_id);
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun static const struct of_device_id max98371_of_match[] = {
412*4882a593Smuzhiyun { .compatible = "maxim,max98371", },
413*4882a593Smuzhiyun { }
414*4882a593Smuzhiyun };
415*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max98371_of_match);
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun static struct i2c_driver max98371_i2c_driver = {
418*4882a593Smuzhiyun .driver = {
419*4882a593Smuzhiyun .name = "max98371",
420*4882a593Smuzhiyun .pm = NULL,
421*4882a593Smuzhiyun .of_match_table = of_match_ptr(max98371_of_match),
422*4882a593Smuzhiyun },
423*4882a593Smuzhiyun .probe = max98371_i2c_probe,
424*4882a593Smuzhiyun .id_table = max98371_i2c_id,
425*4882a593Smuzhiyun };
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun module_i2c_driver(max98371_i2c_driver);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun MODULE_AUTHOR("anish kumar <yesanishhere@gmail.com>");
430*4882a593Smuzhiyun MODULE_DESCRIPTION("ALSA SoC MAX98371 driver");
431*4882a593Smuzhiyun MODULE_LICENSE("GPL");
432