1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * lm49453.h - LM49453 ALSA Soc Audio drive 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2012 Texas Instruments, Inc 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _LM49453_H 9*4882a593Smuzhiyun #define _LM49453_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/bitops.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* LM49453_P0 register space for page0 */ 14*4882a593Smuzhiyun #define LM49453_P0_PMC_SETUP_REG 0x00 15*4882a593Smuzhiyun #define LM49453_P0_PLL_CLK_SEL1_REG 0x01 16*4882a593Smuzhiyun #define LM49453_P0_PLL_CLK_SEL2_REG 0x02 17*4882a593Smuzhiyun #define LM49453_P0_PMC_CLK_DIV_REG 0x03 18*4882a593Smuzhiyun #define LM49453_P0_HSDET_CLK_DIV_REG 0x04 19*4882a593Smuzhiyun #define LM49453_P0_DMIC_CLK_DIV_REG 0x05 20*4882a593Smuzhiyun #define LM49453_P0_ADC_CLK_DIV_REG 0x06 21*4882a593Smuzhiyun #define LM49453_P0_DAC_OT_CLK_DIV_REG 0x07 22*4882a593Smuzhiyun #define LM49453_P0_PLL_HF_M_REG 0x08 23*4882a593Smuzhiyun #define LM49453_P0_PLL_LF_M_REG 0x09 24*4882a593Smuzhiyun #define LM49453_P0_PLL_NL_REG 0x0A 25*4882a593Smuzhiyun #define LM49453_P0_PLL_N_MODL_REG 0x0B 26*4882a593Smuzhiyun #define LM49453_P0_PLL_N_MODH_REG 0x0C 27*4882a593Smuzhiyun #define LM49453_P0_PLL_P1_REG 0x0D 28*4882a593Smuzhiyun #define LM49453_P0_PLL_P2_REG 0x0E 29*4882a593Smuzhiyun #define LM49453_P0_FLL_REF_FREQL_REG 0x0F 30*4882a593Smuzhiyun #define LM49453_P0_FLL_REF_FREQH_REG 0x10 31*4882a593Smuzhiyun #define LM49453_P0_VCO_TARGETLL_REG 0x11 32*4882a593Smuzhiyun #define LM49453_P0_VCO_TARGETLH_REG 0x12 33*4882a593Smuzhiyun #define LM49453_P0_VCO_TARGETHL_REG 0x13 34*4882a593Smuzhiyun #define LM49453_P0_VCO_TARGETHH_REG 0x14 35*4882a593Smuzhiyun #define LM49453_P0_PLL_CONFIG_REG 0x15 36*4882a593Smuzhiyun #define LM49453_P0_DAC_CLK_SEL_REG 0x16 37*4882a593Smuzhiyun #define LM49453_P0_DAC_HP_CLK_DIV_REG 0x17 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Analog Mixer Input Stages */ 40*4882a593Smuzhiyun #define LM49453_P0_MICL_REG 0x20 41*4882a593Smuzhiyun #define LM49453_P0_MICR_REG 0x21 42*4882a593Smuzhiyun #define LM49453_P0_EP_REG 0x24 43*4882a593Smuzhiyun #define LM49453_P0_DIS_PKVL_FB_REG 0x25 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Analog Mixer Output Stages */ 46*4882a593Smuzhiyun #define LM49453_P0_ANALOG_MIXER_ADC_REG 0x2E 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /*ADC or DAC */ 49*4882a593Smuzhiyun #define LM49453_P0_ADC_DSP_REG 0x30 50*4882a593Smuzhiyun #define LM49453_P0_DAC_DSP_REG 0x31 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* EFFECTS ENABLES */ 53*4882a593Smuzhiyun #define LM49453_P0_ADC_FX_ENABLES_REG 0x33 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* GPIO */ 56*4882a593Smuzhiyun #define LM49453_P0_GPIO1_REG 0x38 57*4882a593Smuzhiyun #define LM49453_P0_GPIO2_REG 0x39 58*4882a593Smuzhiyun #define LM49453_P0_GPIO3_REG 0x3A 59*4882a593Smuzhiyun #define LM49453_P0_HAP_CTL_REG 0x3B 60*4882a593Smuzhiyun #define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG 0x3C 61*4882a593Smuzhiyun #define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG 0x3D 62*4882a593Smuzhiyun #define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG 0x3E 63*4882a593Smuzhiyun #define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG 0x3F 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* DIGITAL MIXER */ 66*4882a593Smuzhiyun #define LM49453_P0_DMIX_CLK_SEL_REG 0x40 67*4882a593Smuzhiyun #define LM49453_P0_PORT1_RX_LVL1_REG 0x41 68*4882a593Smuzhiyun #define LM49453_P0_PORT1_RX_LVL2_REG 0x42 69*4882a593Smuzhiyun #define LM49453_P0_PORT2_RX_LVL_REG 0x43 70*4882a593Smuzhiyun #define LM49453_P0_PORT1_TX1_REG 0x44 71*4882a593Smuzhiyun #define LM49453_P0_PORT1_TX2_REG 0x45 72*4882a593Smuzhiyun #define LM49453_P0_PORT1_TX3_REG 0x46 73*4882a593Smuzhiyun #define LM49453_P0_PORT1_TX4_REG 0x47 74*4882a593Smuzhiyun #define LM49453_P0_PORT1_TX5_REG 0x48 75*4882a593Smuzhiyun #define LM49453_P0_PORT1_TX6_REG 0x49 76*4882a593Smuzhiyun #define LM49453_P0_PORT1_TX7_REG 0x4A 77*4882a593Smuzhiyun #define LM49453_P0_PORT1_TX8_REG 0x4B 78*4882a593Smuzhiyun #define LM49453_P0_PORT2_TX1_REG 0x4C 79*4882a593Smuzhiyun #define LM49453_P0_PORT2_TX2_REG 0x4D 80*4882a593Smuzhiyun #define LM49453_P0_STN_SEL_REG 0x4F 81*4882a593Smuzhiyun #define LM49453_P0_DACHPL1_REG 0x50 82*4882a593Smuzhiyun #define LM49453_P0_DACHPL2_REG 0x51 83*4882a593Smuzhiyun #define LM49453_P0_DACHPR1_REG 0x52 84*4882a593Smuzhiyun #define LM49453_P0_DACHPR2_REG 0x53 85*4882a593Smuzhiyun #define LM49453_P0_DACLOL1_REG 0x54 86*4882a593Smuzhiyun #define LM49453_P0_DACLOL2_REG 0x55 87*4882a593Smuzhiyun #define LM49453_P0_DACLOR1_REG 0x56 88*4882a593Smuzhiyun #define LM49453_P0_DACLOR2_REG 0x57 89*4882a593Smuzhiyun #define LM49453_P0_DACLSL1_REG 0x58 90*4882a593Smuzhiyun #define LM49453_P0_DACLSL2_REG 0x59 91*4882a593Smuzhiyun #define LM49453_P0_DACLSR1_REG 0x5A 92*4882a593Smuzhiyun #define LM49453_P0_DACLSR2_REG 0x5B 93*4882a593Smuzhiyun #define LM49453_P0_DACHAL1_REG 0x5C 94*4882a593Smuzhiyun #define LM49453_P0_DACHAL2_REG 0x5D 95*4882a593Smuzhiyun #define LM49453_P0_DACHAR1_REG 0x5E 96*4882a593Smuzhiyun #define LM49453_P0_DACHAR2_REG 0x5F 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* AUDIO PORT 1 (TDM) */ 99*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT1_BASIC_REG 0x60 100*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT1_CLK_GEN1_REG 0x61 101*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT1_CLK_GEN2_REG 0x62 102*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT1_CLK_GEN3_REG 0x63 103*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT1_SYNC_RATE_REG 0x64 104*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT1_SYNC_SDO_SETUP_REG 0x65 105*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT1_DATA_WIDTH_REG 0x66 106*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT1_RX_MSB_REG 0x67 107*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT1_TX_MSB_REG 0x68 108*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT1_TDM_CHANNELS_REG 0x69 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* AUDIO PORT 2 */ 111*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT2_BASIC_REG 0x6A 112*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT2_CLK_GEN1_REG 0x6B 113*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT2_CLK_GEN2_REG 0x6C 114*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT2_SYNC_GEN_REG 0x6D 115*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT2_DATA_WIDTH_REG 0x6E 116*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT2_RX_MODE_REG 0x6F 117*4882a593Smuzhiyun #define LM49453_P0_AUDIO_PORT2_TX_MODE_REG 0x70 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* SAMPLE RATE */ 120*4882a593Smuzhiyun #define LM49453_P0_PORT1_SR_LSB_REG 0x79 121*4882a593Smuzhiyun #define LM49453_P0_PORT1_SR_MSB_REG 0x7A 122*4882a593Smuzhiyun #define LM49453_P0_PORT2_SR_LSB_REG 0x7B 123*4882a593Smuzhiyun #define LM49453_P0_PORT2_SR_MSB_REG 0x7C 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* EFFECTS - HPFs */ 126*4882a593Smuzhiyun #define LM49453_P0_HPF_REG 0x80 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* EFFECTS ADC ALC */ 129*4882a593Smuzhiyun #define LM49453_P0_ADC_ALC1_REG 0x82 130*4882a593Smuzhiyun #define LM49453_P0_ADC_ALC2_REG 0x83 131*4882a593Smuzhiyun #define LM49453_P0_ADC_ALC3_REG 0x84 132*4882a593Smuzhiyun #define LM49453_P0_ADC_ALC4_REG 0x85 133*4882a593Smuzhiyun #define LM49453_P0_ADC_ALC5_REG 0x86 134*4882a593Smuzhiyun #define LM49453_P0_ADC_ALC6_REG 0x87 135*4882a593Smuzhiyun #define LM49453_P0_ADC_ALC7_REG 0x88 136*4882a593Smuzhiyun #define LM49453_P0_ADC_ALC8_REG 0x89 137*4882a593Smuzhiyun #define LM49453_P0_DMIC1_LEVELL_REG 0x8A 138*4882a593Smuzhiyun #define LM49453_P0_DMIC1_LEVELR_REG 0x8B 139*4882a593Smuzhiyun #define LM49453_P0_DMIC2_LEVELL_REG 0x8C 140*4882a593Smuzhiyun #define LM49453_P0_DMIC2_LEVELR_REG 0x8D 141*4882a593Smuzhiyun #define LM49453_P0_ADC_LEVELL_REG 0x8E 142*4882a593Smuzhiyun #define LM49453_P0_ADC_LEVELR_REG 0x8F 143*4882a593Smuzhiyun #define LM49453_P0_DAC_HP_LEVELL_REG 0x90 144*4882a593Smuzhiyun #define LM49453_P0_DAC_HP_LEVELR_REG 0x91 145*4882a593Smuzhiyun #define LM49453_P0_DAC_LO_LEVELL_REG 0x92 146*4882a593Smuzhiyun #define LM49453_P0_DAC_LO_LEVELR_REG 0x93 147*4882a593Smuzhiyun #define LM49453_P0_DAC_LS_LEVELL_REG 0x94 148*4882a593Smuzhiyun #define LM49453_P0_DAC_LS_LEVELR_REG 0x95 149*4882a593Smuzhiyun #define LM49453_P0_DAC_HA_LEVELL_REG 0x96 150*4882a593Smuzhiyun #define LM49453_P0_DAC_HA_LEVELR_REG 0x97 151*4882a593Smuzhiyun #define LM49453_P0_SOFT_MUTE_REG 0x98 152*4882a593Smuzhiyun #define LM49453_P0_DMIC_MUTE_CFG_REG 0x99 153*4882a593Smuzhiyun #define LM49453_P0_ADC_MUTE_CFG_REG 0x9A 154*4882a593Smuzhiyun #define LM49453_P0_DAC_MUTE_CFG_REG 0x9B 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /*DIGITAL MIC1 */ 157*4882a593Smuzhiyun #define LM49453_P0_DIGITAL_MIC1_CONFIG_REG 0xB0 158*4882a593Smuzhiyun #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYL_REG 0xB1 159*4882a593Smuzhiyun #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYR_REG 0xB2 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /*DIGITAL MIC2 */ 162*4882a593Smuzhiyun #define LM49453_P0_DIGITAL_MIC2_CONFIG_REG 0xB3 163*4882a593Smuzhiyun #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYL_REG 0xB4 164*4882a593Smuzhiyun #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYR_REG 0xB5 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* ADC DECIMATOR */ 167*4882a593Smuzhiyun #define LM49453_P0_ADC_DECIMATOR_REG 0xB6 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* DAC CONFIGURE */ 170*4882a593Smuzhiyun #define LM49453_P0_DAC_CONFIG_REG 0xB7 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* SIDETONE */ 173*4882a593Smuzhiyun #define LM49453_P0_STN_VOL_ADCL_REG 0xB8 174*4882a593Smuzhiyun #define LM49453_P0_STN_VOL_ADCR_REG 0xB9 175*4882a593Smuzhiyun #define LM49453_P0_STN_VOL_DMIC1L_REG 0xBA 176*4882a593Smuzhiyun #define LM49453_P0_STN_VOL_DMIC1R_REG 0xBB 177*4882a593Smuzhiyun #define LM49453_P0_STN_VOL_DMIC2L_REG 0xBC 178*4882a593Smuzhiyun #define LM49453_P0_STN_VOL_DMIC2R_REG 0xBD 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* ADC/DAC CLIPPING MONITORS (Read Only/Write to Clear) */ 181*4882a593Smuzhiyun #define LM49453_P0_ADC_DEC_CLIP_REG 0xC2 182*4882a593Smuzhiyun #define LM49453_P0_ADC_HPF_CLIP_REG 0xC3 183*4882a593Smuzhiyun #define LM49453_P0_ADC_LVL_CLIP_REG 0xC4 184*4882a593Smuzhiyun #define LM49453_P0_DAC_LVL_CLIP_REG 0xC5 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* ADC ALC EFFECT MONITORS (Read Only) */ 187*4882a593Smuzhiyun #define LM49453_P0_ADC_LVLMONL_REG 0xC8 188*4882a593Smuzhiyun #define LM49453_P0_ADC_LVLMONR_REG 0xC9 189*4882a593Smuzhiyun #define LM49453_P0_ADC_ALCMONL_REG 0xCA 190*4882a593Smuzhiyun #define LM49453_P0_ADC_ALCMONR_REG 0xCB 191*4882a593Smuzhiyun #define LM49453_P0_ADC_MUTED_REG 0xCC 192*4882a593Smuzhiyun #define LM49453_P0_DAC_MUTED_REG 0xCD 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* HEADSET DETECT */ 195*4882a593Smuzhiyun #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITL_REG 0xD0 196*4882a593Smuzhiyun #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITR_REG 0xD1 197*4882a593Smuzhiyun #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITL_REG 0xD2 198*4882a593Smuzhiyun #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITH_REG 0xD3 199*4882a593Smuzhiyun #define LM49453_P0_HSD_TIMEOUT1_REG 0xD4 200*4882a593Smuzhiyun #define LM49453_P0_HSD_TIMEOUT2_REG 0xD5 201*4882a593Smuzhiyun #define LM49453_P0_HSD_TIMEOUT3_REG 0xD6 202*4882a593Smuzhiyun #define LM49453_P0_HSD_PIN3_4_CFG_REG 0xD7 203*4882a593Smuzhiyun #define LM49453_P0_HSD_IRQ1_REG 0xD8 204*4882a593Smuzhiyun #define LM49453_P0_HSD_IRQ2_REG 0xD9 205*4882a593Smuzhiyun #define LM49453_P0_HSD_IRQ3_REG 0xDA 206*4882a593Smuzhiyun #define LM49453_P0_HSD_IRQ4_REG 0xDB 207*4882a593Smuzhiyun #define LM49453_P0_HSD_IRQ_MASK1_REG 0xDC 208*4882a593Smuzhiyun #define LM49453_P0_HSD_IRQ_MASK2_REG 0xDD 209*4882a593Smuzhiyun #define LM49453_P0_HSD_IRQ_MASK3_REG 0xDE 210*4882a593Smuzhiyun #define LM49453_P0_HSD_R_HPLL_REG 0xE0 211*4882a593Smuzhiyun #define LM49453_P0_HSD_R_HPLH_REG 0xE1 212*4882a593Smuzhiyun #define LM49453_P0_HSD_R_HPLU_REG 0xE2 213*4882a593Smuzhiyun #define LM49453_P0_HSD_R_HPRL_REG 0xE3 214*4882a593Smuzhiyun #define LM49453_P0_HSD_R_HPRH_REG 0xE4 215*4882a593Smuzhiyun #define LM49453_P0_HSD_R_HPRU_REG 0xE5 216*4882a593Smuzhiyun #define LM49453_P0_HSD_VEL_L_FINALL_REG 0xE6 217*4882a593Smuzhiyun #define LM49453_P0_HSD_VEL_L_FINALH_REG 0xE7 218*4882a593Smuzhiyun #define LM49453_P0_HSD_VEL_L_FINALU_REG 0xE8 219*4882a593Smuzhiyun #define LM49453_P0_HSD_RO_FINALL_REG 0xE9 220*4882a593Smuzhiyun #define LM49453_P0_HSD_RO_FINALH_REG 0xEA 221*4882a593Smuzhiyun #define LM49453_P0_HSD_RO_FINALU_REG 0xEB 222*4882a593Smuzhiyun #define LM49453_P0_HSD_VMIC_BIAS_FINALL_REG 0xEC 223*4882a593Smuzhiyun #define LM49453_P0_HSD_VMIC_BIAS_FINALH_REG 0xED 224*4882a593Smuzhiyun #define LM49453_P0_HSD_VMIC_BIAS_FINALU_REG 0xEE 225*4882a593Smuzhiyun #define LM49453_P0_HSD_PIN_CONFIG_REG 0xEF 226*4882a593Smuzhiyun #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS1_REG 0xF1 227*4882a593Smuzhiyun #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS2_REG 0xF2 228*4882a593Smuzhiyun #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS3_REG 0xF3 229*4882a593Smuzhiyun #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEL_REG 0xF4 230*4882a593Smuzhiyun #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEH_REG 0xF5 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun /* I/O PULLDOWN CONFIG */ 233*4882a593Smuzhiyun #define LM49453_P0_PULL_CONFIG1_REG 0xF8 234*4882a593Smuzhiyun #define LM49453_P0_PULL_CONFIG2_REG 0xF9 235*4882a593Smuzhiyun #define LM49453_P0_PULL_CONFIG3_REG 0xFA 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* RESET */ 238*4882a593Smuzhiyun #define LM49453_P0_RESET_REG 0xFE 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* PAGE */ 241*4882a593Smuzhiyun #define LM49453_PAGE_REG 0xFF 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun #define LM49453_MAX_REGISTER (0xFF+1) 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /* LM49453_P0_PMC_SETUP_REG (0x00h) */ 246*4882a593Smuzhiyun #define LM49453_PMC_SETUP_CHIP_EN (BIT(1)|BIT(0)) 247*4882a593Smuzhiyun #define LM49453_PMC_SETUP_PLL_EN BIT(2) 248*4882a593Smuzhiyun #define LM49453_PMC_SETUP_PLL_P2_EN BIT(3) 249*4882a593Smuzhiyun #define LM49453_PMC_SETUP_PLL_FLL BIT(4) 250*4882a593Smuzhiyun #define LM49453_PMC_SETUP_MCLK_OVER BIT(5) 251*4882a593Smuzhiyun #define LM49453_PMC_SETUP_RTC_CLK_OVER BIT(6) 252*4882a593Smuzhiyun #define LM49453_PMC_SETUP_CHIP_ACTIVE BIT(7) 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun /* Chip Enable bits */ 255*4882a593Smuzhiyun #define LM49453_CHIP_EN_SHUTDOWN 0x00 256*4882a593Smuzhiyun #define LM49453_CHIP_EN 0x01 257*4882a593Smuzhiyun #define LM49453_CHIP_EN_HSD_DETECT 0x02 258*4882a593Smuzhiyun #define LM49453_CHIP_EN_INVALID_HSD 0x03 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun /* LM49453_P0_PLL_CLK_SEL1_REG (0x01h) */ 261*4882a593Smuzhiyun #define LM49453_CLK_SEL1_MCLK_SEL 0x11 262*4882a593Smuzhiyun #define LM49453_CLK_SEL1_RTC_SEL 0x11 263*4882a593Smuzhiyun #define LM49453_CLK_SEL1_PORT1_SEL 0x10 264*4882a593Smuzhiyun #define LM49453_CLK_SEL1_PORT2_SEL 0x11 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /* LM49453_P0_PLL_CLK_SEL2_REG (0x02h) */ 267*4882a593Smuzhiyun #define LM49453_CLK_SEL2_ADC_CLK_SEL 0x38 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /* LM49453_P0_FLL_REF_FREQL_REG (0x0F) */ 270*4882a593Smuzhiyun #define LM49453_FLL_REF_FREQ_VAL 0x8ca0001 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun /* LM49453_P0_VCO_TARGETLL_REG (0x11) */ 273*4882a593Smuzhiyun #define LM49453_VCO_TARGET_VAL 0x8ca0001 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun /* LM49453_P0_ADC_DSP_REG (0x30h) */ 276*4882a593Smuzhiyun #define LM49453_ADC_DSP_ADC_MUTEL BIT(0) 277*4882a593Smuzhiyun #define LM49453_ADC_DSP_ADC_MUTER BIT(1) 278*4882a593Smuzhiyun #define LM49453_ADC_DSP_DMIC1_MUTEL BIT(2) 279*4882a593Smuzhiyun #define LM49453_ADC_DSP_DMIC1_MUTER BIT(3) 280*4882a593Smuzhiyun #define LM49453_ADC_DSP_DMIC2_MUTEL BIT(4) 281*4882a593Smuzhiyun #define LM49453_ADC_DSP_DMIC2_MUTER BIT(5) 282*4882a593Smuzhiyun #define LM49453_ADC_DSP_MUTE_ALL 0x3F 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun /* LM49453_P0_DAC_DSP_REG (0x31h) */ 285*4882a593Smuzhiyun #define LM49453_DAC_DSP_MUTE_ALL 0xFF 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* LM49453_P0_AUDIO_PORT1_BASIC_REG (0x60h) */ 288*4882a593Smuzhiyun #define LM49453_AUDIO_PORT1_BASIC_FMT_MASK (BIT(4)|BIT(3)) 289*4882a593Smuzhiyun #define LM49453_AUDIO_PORT1_BASIC_CLK_MS BIT(3) 290*4882a593Smuzhiyun #define LM49453_AUDIO_PORT1_BASIC_SYNC_MS BIT(4) 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun /* LM49453_P0_RESET_REG (0xFEh) */ 293*4882a593Smuzhiyun #define LM49453_RESET_REG_RST BIT(0) 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun /* Page select register bits (0xFF) */ 296*4882a593Smuzhiyun #define LM49453_PAGE0_SELECT 0x0 297*4882a593Smuzhiyun #define LM49453_PAGE1_SELECT 0x1 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun /* LM49453_P0_HSD_PIN3_4_CFG_REG (Jack Pin config - 0xD7) */ 300*4882a593Smuzhiyun #define LM49453_JACK_DISABLE 0x00 301*4882a593Smuzhiyun #define LM49453_JACK_CONFIG1 0x01 302*4882a593Smuzhiyun #define LM49453_JACK_CONFIG2 0x02 303*4882a593Smuzhiyun #define LM49453_JACK_CONFIG3 0x03 304*4882a593Smuzhiyun #define LM49453_JACK_CONFIG4 0x04 305*4882a593Smuzhiyun #define LM49453_JACK_CONFIG5 0x05 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* Page 1 REGISTERS */ 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun /* SIDETONE */ 310*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA0L_REG 0x80 311*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA0H_REG 0x81 312*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SAB0U_REG 0x82 313*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB0L_REG 0x83 314*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB0H_REG 0x84 315*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH0L_REG 0x85 316*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH0H_REG 0x86 317*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH0U_REG 0x87 318*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA1L_REG 0x88 319*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA1H_REG 0x89 320*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SAB1U_REG 0x8A 321*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB1L_REG 0x8B 322*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB1H_REG 0x8C 323*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH1L_REG 0x8D 324*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH1H_REG 0x8E 325*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH1U_REG 0x8F 326*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA2L_REG 0x90 327*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA2H_REG 0x91 328*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SAB2U_REG 0x92 329*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB2L_REG 0x93 330*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB2H_REG 0x94 331*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH2L_REG 0x95 332*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH2H_REG 0x96 333*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH2U_REG 0x97 334*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA3L_REG 0x98 335*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA3H_REG 0x99 336*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SAB3U_REG 0x9A 337*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB3L_REG 0x9B 338*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB3H_REG 0x9C 339*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH3L_REG 0x9D 340*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH3H_REG 0x9E 341*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH3U_REG 0x9F 342*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA4L_REG 0xA0 343*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA4H_REG 0xA1 344*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SAB4U_REG 0xA2 345*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB4L_REG 0xA3 346*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB4H_REG 0xA4 347*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH4L_REG 0xA5 348*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH4H_REG 0xA6 349*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH4U_REG 0xA7 350*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA5L_REG 0xA8 351*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SA5H_REG 0xA9 352*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SAB5U_REG 0xAA 353*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB5L_REG 0xAB 354*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SB5H_REG 0xAC 355*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH5L_REG 0xAD 356*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH5H_REG 0xAE 357*4882a593Smuzhiyun #define LM49453_P1_SIDETONE_SH5U_REG 0xAF 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun /* CHARGE PUMP CONFIG */ 360*4882a593Smuzhiyun #define LM49453_P1_CP_CONFIG1_REG 0xB0 361*4882a593Smuzhiyun #define LM49453_P1_CP_CONFIG2_REG 0xB1 362*4882a593Smuzhiyun #define LM49453_P1_CP_CONFIG3_REG 0xB2 363*4882a593Smuzhiyun #define LM49453_P1_CP_CONFIG4_REG 0xB3 364*4882a593Smuzhiyun #define LM49453_P1_CP_LA_VTH1L_REG 0xB4 365*4882a593Smuzhiyun #define LM49453_P1_CP_LA_VTH1M_REG 0xB5 366*4882a593Smuzhiyun #define LM49453_P1_CP_LA_VTH2L_REG 0xB6 367*4882a593Smuzhiyun #define LM49453_P1_CP_LA_VTH2M_REG 0xB7 368*4882a593Smuzhiyun #define LM49453_P1_CP_LA_VTH3L_REG 0xB8 369*4882a593Smuzhiyun #define LM49453_P1_CP_LA_VTH3H_REG 0xB9 370*4882a593Smuzhiyun #define LM49453_P1_CP_CLK_DIV_REG 0xBA 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun /* DAC */ 373*4882a593Smuzhiyun #define LM49453_P1_DAC_CHOP_REG 0xC0 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun #define LM49453_CLK_SRC_MCLK 1 376*4882a593Smuzhiyun #endif 377