1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * da7218.c - DA7218 ALSA SoC Codec Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015 Dialog Semiconductor
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/pm.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
19*4882a593Smuzhiyun #include <sound/pcm.h>
20*4882a593Smuzhiyun #include <sound/pcm_params.h>
21*4882a593Smuzhiyun #include <sound/soc.h>
22*4882a593Smuzhiyun #include <sound/soc-dapm.h>
23*4882a593Smuzhiyun #include <sound/jack.h>
24*4882a593Smuzhiyun #include <sound/initval.h>
25*4882a593Smuzhiyun #include <sound/tlv.h>
26*4882a593Smuzhiyun #include <asm/div64.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <sound/da7218.h>
29*4882a593Smuzhiyun #include "da7218.h"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * TLVs and Enums
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Input TLVs */
37*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_mic_gain_tlv, -600, 600, 0);
38*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_mixin_gain_tlv, -450, 150, 0);
39*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_in_dig_gain_tlv, -8325, 75, 0);
40*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_ags_trigger_tlv, -9000, 600, 0);
41*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_ags_att_max_tlv, 0, 600, 0);
42*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_alc_threshold_tlv, -9450, 150, 0);
43*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_alc_gain_tlv, 0, 600, 0);
44*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_alc_ana_gain_tlv, 0, 600, 0);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Input/Output TLVs */
47*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_dmix_gain_tlv, -4200, 150, 0);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Output TLVs */
50*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_dgs_trigger_tlv, -9450, 150, 0);
51*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_dgs_anticlip_tlv, -4200, 600, 0);
52*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_dgs_signal_tlv, -9000, 600, 0);
53*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_out_eq_band_tlv, -1050, 150, 0);
54*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_out_dig_gain_tlv, -8325, 75, 0);
55*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_dac_ng_threshold_tlv, -10200, 600, 0);
56*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_mixout_gain_tlv, -100, 50, 0);
57*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7218_hp_gain_tlv, -5700, 150, 0);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Input Enums */
60*4882a593Smuzhiyun static const char * const da7218_alc_attack_rate_txt[] = {
61*4882a593Smuzhiyun "7.33/fs", "14.66/fs", "29.32/fs", "58.64/fs", "117.3/fs", "234.6/fs",
62*4882a593Smuzhiyun "469.1/fs", "938.2/fs", "1876/fs", "3753/fs", "7506/fs", "15012/fs",
63*4882a593Smuzhiyun "30024/fs",
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static const struct soc_enum da7218_alc_attack_rate =
67*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_ALC_CTRL2, DA7218_ALC_ATTACK_SHIFT,
68*4882a593Smuzhiyun DA7218_ALC_ATTACK_MAX, da7218_alc_attack_rate_txt);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static const char * const da7218_alc_release_rate_txt[] = {
71*4882a593Smuzhiyun "28.66/fs", "57.33/fs", "114.6/fs", "229.3/fs", "458.6/fs", "917.1/fs",
72*4882a593Smuzhiyun "1834/fs", "3668/fs", "7337/fs", "14674/fs", "29348/fs",
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static const struct soc_enum da7218_alc_release_rate =
76*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_ALC_CTRL2, DA7218_ALC_RELEASE_SHIFT,
77*4882a593Smuzhiyun DA7218_ALC_RELEASE_MAX, da7218_alc_release_rate_txt);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const char * const da7218_alc_hold_time_txt[] = {
80*4882a593Smuzhiyun "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
81*4882a593Smuzhiyun "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
82*4882a593Smuzhiyun "253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static const struct soc_enum da7218_alc_hold_time =
86*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_ALC_CTRL3, DA7218_ALC_HOLD_SHIFT,
87*4882a593Smuzhiyun DA7218_ALC_HOLD_MAX, da7218_alc_hold_time_txt);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static const char * const da7218_alc_anticlip_step_txt[] = {
90*4882a593Smuzhiyun "0.034dB/fs", "0.068dB/fs", "0.136dB/fs", "0.272dB/fs",
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static const struct soc_enum da7218_alc_anticlip_step =
94*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_ALC_ANTICLIP_CTRL,
95*4882a593Smuzhiyun DA7218_ALC_ANTICLIP_STEP_SHIFT,
96*4882a593Smuzhiyun DA7218_ALC_ANTICLIP_STEP_MAX,
97*4882a593Smuzhiyun da7218_alc_anticlip_step_txt);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const char * const da7218_integ_rate_txt[] = {
100*4882a593Smuzhiyun "1/4", "1/16", "1/256", "1/65536"
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const struct soc_enum da7218_integ_attack_rate =
104*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_ENV_TRACK_CTRL, DA7218_INTEG_ATTACK_SHIFT,
105*4882a593Smuzhiyun DA7218_INTEG_MAX, da7218_integ_rate_txt);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static const struct soc_enum da7218_integ_release_rate =
108*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_ENV_TRACK_CTRL, DA7218_INTEG_RELEASE_SHIFT,
109*4882a593Smuzhiyun DA7218_INTEG_MAX, da7218_integ_rate_txt);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Input/Output Enums */
112*4882a593Smuzhiyun static const char * const da7218_gain_ramp_rate_txt[] = {
113*4882a593Smuzhiyun "Nominal Rate * 8", "Nominal Rate", "Nominal Rate / 8",
114*4882a593Smuzhiyun "Nominal Rate / 16",
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun static const struct soc_enum da7218_gain_ramp_rate =
118*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_GAIN_RAMP_CTRL, DA7218_GAIN_RAMP_RATE_SHIFT,
119*4882a593Smuzhiyun DA7218_GAIN_RAMP_RATE_MAX, da7218_gain_ramp_rate_txt);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static const char * const da7218_hpf_mode_txt[] = {
122*4882a593Smuzhiyun "Disabled", "Audio", "Voice",
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun static const unsigned int da7218_hpf_mode_val[] = {
126*4882a593Smuzhiyun DA7218_HPF_DISABLED, DA7218_HPF_AUDIO_EN, DA7218_HPF_VOICE_EN,
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static const struct soc_enum da7218_in1_hpf_mode =
130*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(DA7218_IN_1_HPF_FILTER_CTRL,
131*4882a593Smuzhiyun DA7218_HPF_MODE_SHIFT, DA7218_HPF_MODE_MASK,
132*4882a593Smuzhiyun DA7218_HPF_MODE_MAX, da7218_hpf_mode_txt,
133*4882a593Smuzhiyun da7218_hpf_mode_val);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun static const struct soc_enum da7218_in2_hpf_mode =
136*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(DA7218_IN_2_HPF_FILTER_CTRL,
137*4882a593Smuzhiyun DA7218_HPF_MODE_SHIFT, DA7218_HPF_MODE_MASK,
138*4882a593Smuzhiyun DA7218_HPF_MODE_MAX, da7218_hpf_mode_txt,
139*4882a593Smuzhiyun da7218_hpf_mode_val);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun static const struct soc_enum da7218_out1_hpf_mode =
142*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(DA7218_OUT_1_HPF_FILTER_CTRL,
143*4882a593Smuzhiyun DA7218_HPF_MODE_SHIFT, DA7218_HPF_MODE_MASK,
144*4882a593Smuzhiyun DA7218_HPF_MODE_MAX, da7218_hpf_mode_txt,
145*4882a593Smuzhiyun da7218_hpf_mode_val);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static const char * const da7218_audio_hpf_corner_txt[] = {
148*4882a593Smuzhiyun "2Hz", "4Hz", "8Hz", "16Hz",
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const struct soc_enum da7218_in1_audio_hpf_corner =
152*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_IN_1_HPF_FILTER_CTRL,
153*4882a593Smuzhiyun DA7218_IN_1_AUDIO_HPF_CORNER_SHIFT,
154*4882a593Smuzhiyun DA7218_AUDIO_HPF_CORNER_MAX,
155*4882a593Smuzhiyun da7218_audio_hpf_corner_txt);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun static const struct soc_enum da7218_in2_audio_hpf_corner =
158*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_IN_2_HPF_FILTER_CTRL,
159*4882a593Smuzhiyun DA7218_IN_2_AUDIO_HPF_CORNER_SHIFT,
160*4882a593Smuzhiyun DA7218_AUDIO_HPF_CORNER_MAX,
161*4882a593Smuzhiyun da7218_audio_hpf_corner_txt);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun static const struct soc_enum da7218_out1_audio_hpf_corner =
164*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_OUT_1_HPF_FILTER_CTRL,
165*4882a593Smuzhiyun DA7218_OUT_1_AUDIO_HPF_CORNER_SHIFT,
166*4882a593Smuzhiyun DA7218_AUDIO_HPF_CORNER_MAX,
167*4882a593Smuzhiyun da7218_audio_hpf_corner_txt);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun static const char * const da7218_voice_hpf_corner_txt[] = {
170*4882a593Smuzhiyun "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz",
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun static const struct soc_enum da7218_in1_voice_hpf_corner =
174*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_IN_1_HPF_FILTER_CTRL,
175*4882a593Smuzhiyun DA7218_IN_1_VOICE_HPF_CORNER_SHIFT,
176*4882a593Smuzhiyun DA7218_VOICE_HPF_CORNER_MAX,
177*4882a593Smuzhiyun da7218_voice_hpf_corner_txt);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun static const struct soc_enum da7218_in2_voice_hpf_corner =
180*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_IN_2_HPF_FILTER_CTRL,
181*4882a593Smuzhiyun DA7218_IN_2_VOICE_HPF_CORNER_SHIFT,
182*4882a593Smuzhiyun DA7218_VOICE_HPF_CORNER_MAX,
183*4882a593Smuzhiyun da7218_voice_hpf_corner_txt);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun static const struct soc_enum da7218_out1_voice_hpf_corner =
186*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_OUT_1_HPF_FILTER_CTRL,
187*4882a593Smuzhiyun DA7218_OUT_1_VOICE_HPF_CORNER_SHIFT,
188*4882a593Smuzhiyun DA7218_VOICE_HPF_CORNER_MAX,
189*4882a593Smuzhiyun da7218_voice_hpf_corner_txt);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun static const char * const da7218_tonegen_dtmf_key_txt[] = {
192*4882a593Smuzhiyun "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "A", "B", "C", "D",
193*4882a593Smuzhiyun "*", "#"
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun static const struct soc_enum da7218_tonegen_dtmf_key =
197*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_TONE_GEN_CFG1, DA7218_DTMF_REG_SHIFT,
198*4882a593Smuzhiyun DA7218_DTMF_REG_MAX, da7218_tonegen_dtmf_key_txt);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun static const char * const da7218_tonegen_swg_sel_txt[] = {
201*4882a593Smuzhiyun "Sum", "SWG1", "SWG2", "SWG1_1-Cos"
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun static const struct soc_enum da7218_tonegen_swg_sel =
205*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_TONE_GEN_CFG2, DA7218_SWG_SEL_SHIFT,
206*4882a593Smuzhiyun DA7218_SWG_SEL_MAX, da7218_tonegen_swg_sel_txt);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /* Output Enums */
209*4882a593Smuzhiyun static const char * const da7218_dgs_rise_coeff_txt[] = {
210*4882a593Smuzhiyun "1/1", "1/16", "1/64", "1/256", "1/1024", "1/4096", "1/16384",
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun static const struct soc_enum da7218_dgs_rise_coeff =
214*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_DGS_RISE_FALL, DA7218_DGS_RISE_COEFF_SHIFT,
215*4882a593Smuzhiyun DA7218_DGS_RISE_COEFF_MAX, da7218_dgs_rise_coeff_txt);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun static const char * const da7218_dgs_fall_coeff_txt[] = {
218*4882a593Smuzhiyun "1/4", "1/16", "1/64", "1/256", "1/1024", "1/4096", "1/16384", "1/65536",
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun static const struct soc_enum da7218_dgs_fall_coeff =
222*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_DGS_RISE_FALL, DA7218_DGS_FALL_COEFF_SHIFT,
223*4882a593Smuzhiyun DA7218_DGS_FALL_COEFF_MAX, da7218_dgs_fall_coeff_txt);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun static const char * const da7218_dac_ng_setup_time_txt[] = {
226*4882a593Smuzhiyun "256 Samples", "512 Samples", "1024 Samples", "2048 Samples"
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun static const struct soc_enum da7218_dac_ng_setup_time =
230*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_DAC_NG_SETUP_TIME,
231*4882a593Smuzhiyun DA7218_DAC_NG_SETUP_TIME_SHIFT,
232*4882a593Smuzhiyun DA7218_DAC_NG_SETUP_TIME_MAX,
233*4882a593Smuzhiyun da7218_dac_ng_setup_time_txt);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun static const char * const da7218_dac_ng_rampup_txt[] = {
236*4882a593Smuzhiyun "0.22ms/dB", "0.0138ms/dB"
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun static const struct soc_enum da7218_dac_ng_rampup_rate =
240*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_DAC_NG_SETUP_TIME,
241*4882a593Smuzhiyun DA7218_DAC_NG_RAMPUP_RATE_SHIFT,
242*4882a593Smuzhiyun DA7218_DAC_NG_RAMPUP_RATE_MAX,
243*4882a593Smuzhiyun da7218_dac_ng_rampup_txt);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun static const char * const da7218_dac_ng_rampdown_txt[] = {
246*4882a593Smuzhiyun "0.88ms/dB", "14.08ms/dB"
247*4882a593Smuzhiyun };
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun static const struct soc_enum da7218_dac_ng_rampdown_rate =
250*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_DAC_NG_SETUP_TIME,
251*4882a593Smuzhiyun DA7218_DAC_NG_RAMPDN_RATE_SHIFT,
252*4882a593Smuzhiyun DA7218_DAC_NG_RAMPDN_RATE_MAX,
253*4882a593Smuzhiyun da7218_dac_ng_rampdown_txt);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun static const char * const da7218_cp_mchange_txt[] = {
256*4882a593Smuzhiyun "Largest Volume", "DAC Volume", "Signal Magnitude"
257*4882a593Smuzhiyun };
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun static const unsigned int da7218_cp_mchange_val[] = {
260*4882a593Smuzhiyun DA7218_CP_MCHANGE_LARGEST_VOL, DA7218_CP_MCHANGE_DAC_VOL,
261*4882a593Smuzhiyun DA7218_CP_MCHANGE_SIG_MAG
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun static const struct soc_enum da7218_cp_mchange =
265*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(DA7218_CP_CTRL, DA7218_CP_MCHANGE_SHIFT,
266*4882a593Smuzhiyun DA7218_CP_MCHANGE_REL_MASK, DA7218_CP_MCHANGE_MAX,
267*4882a593Smuzhiyun da7218_cp_mchange_txt, da7218_cp_mchange_val);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun static const char * const da7218_cp_fcontrol_txt[] = {
270*4882a593Smuzhiyun "1MHz", "500KHz", "250KHz", "125KHz", "63KHz", "0KHz"
271*4882a593Smuzhiyun };
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun static const struct soc_enum da7218_cp_fcontrol =
274*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_CP_DELAY, DA7218_CP_FCONTROL_SHIFT,
275*4882a593Smuzhiyun DA7218_CP_FCONTROL_MAX, da7218_cp_fcontrol_txt);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun static const char * const da7218_cp_tau_delay_txt[] = {
278*4882a593Smuzhiyun "0ms", "2ms", "4ms", "16ms", "64ms", "128ms", "256ms", "512ms"
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun static const struct soc_enum da7218_cp_tau_delay =
282*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_CP_DELAY, DA7218_CP_TAU_DELAY_SHIFT,
283*4882a593Smuzhiyun DA7218_CP_TAU_DELAY_MAX, da7218_cp_tau_delay_txt);
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /*
286*4882a593Smuzhiyun * Control Functions
287*4882a593Smuzhiyun */
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun /* ALC */
da7218_alc_calib(struct snd_soc_component * component)290*4882a593Smuzhiyun static void da7218_alc_calib(struct snd_soc_component *component)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun u8 mic_1_ctrl, mic_2_ctrl;
293*4882a593Smuzhiyun u8 mixin_1_ctrl, mixin_2_ctrl;
294*4882a593Smuzhiyun u8 in_1l_filt_ctrl, in_1r_filt_ctrl, in_2l_filt_ctrl, in_2r_filt_ctrl;
295*4882a593Smuzhiyun u8 in_1_hpf_ctrl, in_2_hpf_ctrl;
296*4882a593Smuzhiyun u8 calib_ctrl;
297*4882a593Smuzhiyun int i = 0;
298*4882a593Smuzhiyun bool calibrated = false;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun /* Save current state of MIC control registers */
301*4882a593Smuzhiyun mic_1_ctrl = snd_soc_component_read(component, DA7218_MIC_1_CTRL);
302*4882a593Smuzhiyun mic_2_ctrl = snd_soc_component_read(component, DA7218_MIC_2_CTRL);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /* Save current state of input mixer control registers */
305*4882a593Smuzhiyun mixin_1_ctrl = snd_soc_component_read(component, DA7218_MIXIN_1_CTRL);
306*4882a593Smuzhiyun mixin_2_ctrl = snd_soc_component_read(component, DA7218_MIXIN_2_CTRL);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /* Save current state of input filter control registers */
309*4882a593Smuzhiyun in_1l_filt_ctrl = snd_soc_component_read(component, DA7218_IN_1L_FILTER_CTRL);
310*4882a593Smuzhiyun in_1r_filt_ctrl = snd_soc_component_read(component, DA7218_IN_1R_FILTER_CTRL);
311*4882a593Smuzhiyun in_2l_filt_ctrl = snd_soc_component_read(component, DA7218_IN_2L_FILTER_CTRL);
312*4882a593Smuzhiyun in_2r_filt_ctrl = snd_soc_component_read(component, DA7218_IN_2R_FILTER_CTRL);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun /* Save current state of input HPF control registers */
315*4882a593Smuzhiyun in_1_hpf_ctrl = snd_soc_component_read(component, DA7218_IN_1_HPF_FILTER_CTRL);
316*4882a593Smuzhiyun in_2_hpf_ctrl = snd_soc_component_read(component, DA7218_IN_2_HPF_FILTER_CTRL);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun /* Enable then Mute MIC PGAs */
319*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_MIC_1_CTRL, DA7218_MIC_1_AMP_EN_MASK,
320*4882a593Smuzhiyun DA7218_MIC_1_AMP_EN_MASK);
321*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_MIC_2_CTRL, DA7218_MIC_2_AMP_EN_MASK,
322*4882a593Smuzhiyun DA7218_MIC_2_AMP_EN_MASK);
323*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_MIC_1_CTRL,
324*4882a593Smuzhiyun DA7218_MIC_1_AMP_MUTE_EN_MASK,
325*4882a593Smuzhiyun DA7218_MIC_1_AMP_MUTE_EN_MASK);
326*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_MIC_2_CTRL,
327*4882a593Smuzhiyun DA7218_MIC_2_AMP_MUTE_EN_MASK,
328*4882a593Smuzhiyun DA7218_MIC_2_AMP_MUTE_EN_MASK);
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun /* Enable input mixers unmuted */
331*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_MIXIN_1_CTRL,
332*4882a593Smuzhiyun DA7218_MIXIN_1_AMP_EN_MASK |
333*4882a593Smuzhiyun DA7218_MIXIN_1_AMP_MUTE_EN_MASK,
334*4882a593Smuzhiyun DA7218_MIXIN_1_AMP_EN_MASK);
335*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_MIXIN_2_CTRL,
336*4882a593Smuzhiyun DA7218_MIXIN_2_AMP_EN_MASK |
337*4882a593Smuzhiyun DA7218_MIXIN_2_AMP_MUTE_EN_MASK,
338*4882a593Smuzhiyun DA7218_MIXIN_2_AMP_EN_MASK);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun /* Enable input filters unmuted */
341*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_IN_1L_FILTER_CTRL,
342*4882a593Smuzhiyun DA7218_IN_1L_FILTER_EN_MASK |
343*4882a593Smuzhiyun DA7218_IN_1L_MUTE_EN_MASK,
344*4882a593Smuzhiyun DA7218_IN_1L_FILTER_EN_MASK);
345*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_IN_1R_FILTER_CTRL,
346*4882a593Smuzhiyun DA7218_IN_1R_FILTER_EN_MASK |
347*4882a593Smuzhiyun DA7218_IN_1R_MUTE_EN_MASK,
348*4882a593Smuzhiyun DA7218_IN_1R_FILTER_EN_MASK);
349*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_IN_2L_FILTER_CTRL,
350*4882a593Smuzhiyun DA7218_IN_2L_FILTER_EN_MASK |
351*4882a593Smuzhiyun DA7218_IN_2L_MUTE_EN_MASK,
352*4882a593Smuzhiyun DA7218_IN_2L_FILTER_EN_MASK);
353*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_IN_2R_FILTER_CTRL,
354*4882a593Smuzhiyun DA7218_IN_2R_FILTER_EN_MASK |
355*4882a593Smuzhiyun DA7218_IN_2R_MUTE_EN_MASK,
356*4882a593Smuzhiyun DA7218_IN_2R_FILTER_EN_MASK);
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun /*
359*4882a593Smuzhiyun * Make sure input HPFs voice mode is disabled, otherwise for sampling
360*4882a593Smuzhiyun * rates above 32KHz the ADC signals will be stopped and will cause
361*4882a593Smuzhiyun * calibration to lock up.
362*4882a593Smuzhiyun */
363*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_IN_1_HPF_FILTER_CTRL,
364*4882a593Smuzhiyun DA7218_IN_1_VOICE_EN_MASK, 0);
365*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_IN_2_HPF_FILTER_CTRL,
366*4882a593Smuzhiyun DA7218_IN_2_VOICE_EN_MASK, 0);
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun /* Perform auto calibration */
369*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_CALIB_CTRL, DA7218_CALIB_AUTO_EN_MASK,
370*4882a593Smuzhiyun DA7218_CALIB_AUTO_EN_MASK);
371*4882a593Smuzhiyun do {
372*4882a593Smuzhiyun calib_ctrl = snd_soc_component_read(component, DA7218_CALIB_CTRL);
373*4882a593Smuzhiyun if (calib_ctrl & DA7218_CALIB_AUTO_EN_MASK) {
374*4882a593Smuzhiyun ++i;
375*4882a593Smuzhiyun usleep_range(DA7218_ALC_CALIB_DELAY_MIN,
376*4882a593Smuzhiyun DA7218_ALC_CALIB_DELAY_MAX);
377*4882a593Smuzhiyun } else {
378*4882a593Smuzhiyun calibrated = true;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun } while ((i < DA7218_ALC_CALIB_MAX_TRIES) && (!calibrated));
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun /* If auto calibration fails, disable DC offset, hybrid ALC */
384*4882a593Smuzhiyun if ((!calibrated) || (calib_ctrl & DA7218_CALIB_OVERFLOW_MASK)) {
385*4882a593Smuzhiyun dev_warn(component->dev,
386*4882a593Smuzhiyun "ALC auto calibration failed - %s\n",
387*4882a593Smuzhiyun (calibrated) ? "overflow" : "timeout");
388*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_CALIB_CTRL,
389*4882a593Smuzhiyun DA7218_CALIB_OFFSET_EN_MASK, 0);
390*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_ALC_CTRL1,
391*4882a593Smuzhiyun DA7218_ALC_SYNC_MODE_MASK, 0);
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun } else {
394*4882a593Smuzhiyun /* Enable DC offset cancellation */
395*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_CALIB_CTRL,
396*4882a593Smuzhiyun DA7218_CALIB_OFFSET_EN_MASK,
397*4882a593Smuzhiyun DA7218_CALIB_OFFSET_EN_MASK);
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun /* Enable ALC hybrid mode */
400*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_ALC_CTRL1,
401*4882a593Smuzhiyun DA7218_ALC_SYNC_MODE_MASK,
402*4882a593Smuzhiyun DA7218_ALC_SYNC_MODE_CH1 |
403*4882a593Smuzhiyun DA7218_ALC_SYNC_MODE_CH2);
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun /* Restore input HPF control registers to original states */
407*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_IN_1_HPF_FILTER_CTRL, in_1_hpf_ctrl);
408*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_IN_2_HPF_FILTER_CTRL, in_2_hpf_ctrl);
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun /* Restore input filter control registers to original states */
411*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_IN_1L_FILTER_CTRL, in_1l_filt_ctrl);
412*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_IN_1R_FILTER_CTRL, in_1r_filt_ctrl);
413*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_IN_2L_FILTER_CTRL, in_2l_filt_ctrl);
414*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_IN_2R_FILTER_CTRL, in_2r_filt_ctrl);
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun /* Restore input mixer control registers to original state */
417*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_MIXIN_1_CTRL, mixin_1_ctrl);
418*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_MIXIN_2_CTRL, mixin_2_ctrl);
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun /* Restore MIC control registers to original states */
421*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_MIC_1_CTRL, mic_1_ctrl);
422*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_MIC_2_CTRL, mic_2_ctrl);
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
da7218_mixin_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)425*4882a593Smuzhiyun static int da7218_mixin_gain_put(struct snd_kcontrol *kcontrol,
426*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
427*4882a593Smuzhiyun {
428*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
429*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
430*4882a593Smuzhiyun int ret;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun ret = snd_soc_put_volsw(kcontrol, ucontrol);
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun /*
435*4882a593Smuzhiyun * If ALC in operation and value of control has been updated,
436*4882a593Smuzhiyun * make sure calibrated offsets are updated.
437*4882a593Smuzhiyun */
438*4882a593Smuzhiyun if ((ret == 1) && (da7218->alc_en))
439*4882a593Smuzhiyun da7218_alc_calib(component);
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun return ret;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
da7218_alc_sw_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)444*4882a593Smuzhiyun static int da7218_alc_sw_put(struct snd_kcontrol *kcontrol,
445*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
446*4882a593Smuzhiyun {
447*4882a593Smuzhiyun struct soc_mixer_control *mc =
448*4882a593Smuzhiyun (struct soc_mixer_control *) kcontrol->private_value;
449*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
450*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
451*4882a593Smuzhiyun unsigned int lvalue = ucontrol->value.integer.value[0];
452*4882a593Smuzhiyun unsigned int rvalue = ucontrol->value.integer.value[1];
453*4882a593Smuzhiyun unsigned int lshift = mc->shift;
454*4882a593Smuzhiyun unsigned int rshift = mc->rshift;
455*4882a593Smuzhiyun unsigned int mask = (mc->max << lshift) | (mc->max << rshift);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun /* Force ALC offset calibration if enabling ALC */
458*4882a593Smuzhiyun if ((lvalue || rvalue) && (!da7218->alc_en))
459*4882a593Smuzhiyun da7218_alc_calib(component);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun /* Update bits to detail which channels are enabled/disabled */
462*4882a593Smuzhiyun da7218->alc_en &= ~mask;
463*4882a593Smuzhiyun da7218->alc_en |= (lvalue << lshift) | (rvalue << rshift);
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun return snd_soc_put_volsw(kcontrol, ucontrol);
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun /* ToneGen */
da7218_tonegen_freq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)469*4882a593Smuzhiyun static int da7218_tonegen_freq_get(struct snd_kcontrol *kcontrol,
470*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
473*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
474*4882a593Smuzhiyun struct soc_mixer_control *mixer_ctrl =
475*4882a593Smuzhiyun (struct soc_mixer_control *) kcontrol->private_value;
476*4882a593Smuzhiyun unsigned int reg = mixer_ctrl->reg;
477*4882a593Smuzhiyun u16 val;
478*4882a593Smuzhiyun int ret;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun /*
481*4882a593Smuzhiyun * Frequency value spans two 8-bit registers, lower then upper byte.
482*4882a593Smuzhiyun * Therefore we need to convert to host endianness here.
483*4882a593Smuzhiyun */
484*4882a593Smuzhiyun ret = regmap_raw_read(da7218->regmap, reg, &val, 2);
485*4882a593Smuzhiyun if (ret)
486*4882a593Smuzhiyun return ret;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun ucontrol->value.integer.value[0] = le16_to_cpu(val);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun return 0;
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun
da7218_tonegen_freq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)493*4882a593Smuzhiyun static int da7218_tonegen_freq_put(struct snd_kcontrol *kcontrol,
494*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
497*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
498*4882a593Smuzhiyun struct soc_mixer_control *mixer_ctrl =
499*4882a593Smuzhiyun (struct soc_mixer_control *) kcontrol->private_value;
500*4882a593Smuzhiyun unsigned int reg = mixer_ctrl->reg;
501*4882a593Smuzhiyun u16 val;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun /*
504*4882a593Smuzhiyun * Frequency value spans two 8-bit registers, lower then upper byte.
505*4882a593Smuzhiyun * Therefore we need to convert to little endian here to align with
506*4882a593Smuzhiyun * HW registers.
507*4882a593Smuzhiyun */
508*4882a593Smuzhiyun val = cpu_to_le16(ucontrol->value.integer.value[0]);
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun return regmap_raw_write(da7218->regmap, reg, &val, 2);
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun
da7218_mic_lvl_det_sw_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)513*4882a593Smuzhiyun static int da7218_mic_lvl_det_sw_put(struct snd_kcontrol *kcontrol,
514*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
517*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
518*4882a593Smuzhiyun struct soc_mixer_control *mixer_ctrl =
519*4882a593Smuzhiyun (struct soc_mixer_control *) kcontrol->private_value;
520*4882a593Smuzhiyun unsigned int lvalue = ucontrol->value.integer.value[0];
521*4882a593Smuzhiyun unsigned int rvalue = ucontrol->value.integer.value[1];
522*4882a593Smuzhiyun unsigned int lshift = mixer_ctrl->shift;
523*4882a593Smuzhiyun unsigned int rshift = mixer_ctrl->rshift;
524*4882a593Smuzhiyun unsigned int mask = (mixer_ctrl->max << lshift) |
525*4882a593Smuzhiyun (mixer_ctrl->max << rshift);
526*4882a593Smuzhiyun da7218->mic_lvl_det_en &= ~mask;
527*4882a593Smuzhiyun da7218->mic_lvl_det_en |= (lvalue << lshift) | (rvalue << rshift);
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun /*
530*4882a593Smuzhiyun * Here we only enable the feature on paths which are already
531*4882a593Smuzhiyun * powered. If a channel is enabled here for level detect, but that path
532*4882a593Smuzhiyun * isn't powered, then the channel will actually be enabled when we do
533*4882a593Smuzhiyun * power the path (IN_FILTER widget events). This handling avoids
534*4882a593Smuzhiyun * unwanted level detect events.
535*4882a593Smuzhiyun */
536*4882a593Smuzhiyun return snd_soc_component_write(component, mixer_ctrl->reg,
537*4882a593Smuzhiyun (da7218->in_filt_en & da7218->mic_lvl_det_en));
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun
da7218_mic_lvl_det_sw_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)540*4882a593Smuzhiyun static int da7218_mic_lvl_det_sw_get(struct snd_kcontrol *kcontrol,
541*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
544*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
545*4882a593Smuzhiyun struct soc_mixer_control *mixer_ctrl =
546*4882a593Smuzhiyun (struct soc_mixer_control *) kcontrol->private_value;
547*4882a593Smuzhiyun unsigned int lshift = mixer_ctrl->shift;
548*4882a593Smuzhiyun unsigned int rshift = mixer_ctrl->rshift;
549*4882a593Smuzhiyun unsigned int lmask = (mixer_ctrl->max << lshift);
550*4882a593Smuzhiyun unsigned int rmask = (mixer_ctrl->max << rshift);
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun ucontrol->value.integer.value[0] =
553*4882a593Smuzhiyun (da7218->mic_lvl_det_en & lmask) >> lshift;
554*4882a593Smuzhiyun ucontrol->value.integer.value[1] =
555*4882a593Smuzhiyun (da7218->mic_lvl_det_en & rmask) >> rshift;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun return 0;
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun
da7218_biquad_coeff_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)560*4882a593Smuzhiyun static int da7218_biquad_coeff_get(struct snd_kcontrol *kcontrol,
561*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
562*4882a593Smuzhiyun {
563*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
564*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
565*4882a593Smuzhiyun struct soc_bytes_ext *bytes_ext =
566*4882a593Smuzhiyun (struct soc_bytes_ext *) kcontrol->private_value;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun /* Determine which BiQuads we're setting based on size of config data */
569*4882a593Smuzhiyun switch (bytes_ext->max) {
570*4882a593Smuzhiyun case DA7218_OUT_1_BIQ_5STAGE_CFG_SIZE:
571*4882a593Smuzhiyun memcpy(ucontrol->value.bytes.data, da7218->biq_5stage_coeff,
572*4882a593Smuzhiyun bytes_ext->max);
573*4882a593Smuzhiyun break;
574*4882a593Smuzhiyun case DA7218_SIDETONE_BIQ_3STAGE_CFG_SIZE:
575*4882a593Smuzhiyun memcpy(ucontrol->value.bytes.data, da7218->stbiq_3stage_coeff,
576*4882a593Smuzhiyun bytes_ext->max);
577*4882a593Smuzhiyun break;
578*4882a593Smuzhiyun default:
579*4882a593Smuzhiyun return -EINVAL;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun return 0;
583*4882a593Smuzhiyun }
584*4882a593Smuzhiyun
da7218_biquad_coeff_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)585*4882a593Smuzhiyun static int da7218_biquad_coeff_put(struct snd_kcontrol *kcontrol,
586*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
587*4882a593Smuzhiyun {
588*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
589*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
590*4882a593Smuzhiyun struct soc_bytes_ext *bytes_ext =
591*4882a593Smuzhiyun (struct soc_bytes_ext *) kcontrol->private_value;
592*4882a593Smuzhiyun u8 reg, out_filt1l;
593*4882a593Smuzhiyun u8 cfg[DA7218_BIQ_CFG_SIZE];
594*4882a593Smuzhiyun int i;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun /*
597*4882a593Smuzhiyun * Determine which BiQuads we're setting based on size of config data,
598*4882a593Smuzhiyun * and stored the data for use by get function.
599*4882a593Smuzhiyun */
600*4882a593Smuzhiyun switch (bytes_ext->max) {
601*4882a593Smuzhiyun case DA7218_OUT_1_BIQ_5STAGE_CFG_SIZE:
602*4882a593Smuzhiyun reg = DA7218_OUT_1_BIQ_5STAGE_DATA;
603*4882a593Smuzhiyun memcpy(da7218->biq_5stage_coeff, ucontrol->value.bytes.data,
604*4882a593Smuzhiyun bytes_ext->max);
605*4882a593Smuzhiyun break;
606*4882a593Smuzhiyun case DA7218_SIDETONE_BIQ_3STAGE_CFG_SIZE:
607*4882a593Smuzhiyun reg = DA7218_SIDETONE_BIQ_3STAGE_DATA;
608*4882a593Smuzhiyun memcpy(da7218->stbiq_3stage_coeff, ucontrol->value.bytes.data,
609*4882a593Smuzhiyun bytes_ext->max);
610*4882a593Smuzhiyun break;
611*4882a593Smuzhiyun default:
612*4882a593Smuzhiyun return -EINVAL;
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun /* Make sure at least out filter1 enabled to allow programming */
616*4882a593Smuzhiyun out_filt1l = snd_soc_component_read(component, DA7218_OUT_1L_FILTER_CTRL);
617*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_OUT_1L_FILTER_CTRL,
618*4882a593Smuzhiyun out_filt1l | DA7218_OUT_1L_FILTER_EN_MASK);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun for (i = 0; i < bytes_ext->max; ++i) {
621*4882a593Smuzhiyun cfg[DA7218_BIQ_CFG_DATA] = ucontrol->value.bytes.data[i];
622*4882a593Smuzhiyun cfg[DA7218_BIQ_CFG_ADDR] = i;
623*4882a593Smuzhiyun regmap_raw_write(da7218->regmap, reg, cfg, DA7218_BIQ_CFG_SIZE);
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun /* Restore filter to previous setting */
627*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_OUT_1L_FILTER_CTRL, out_filt1l);
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun return 0;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun /*
634*4882a593Smuzhiyun * KControls
635*4882a593Smuzhiyun */
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_snd_controls[] = {
638*4882a593Smuzhiyun /* Mics */
639*4882a593Smuzhiyun SOC_SINGLE_TLV("Mic1 Volume", DA7218_MIC_1_GAIN,
640*4882a593Smuzhiyun DA7218_MIC_1_AMP_GAIN_SHIFT, DA7218_MIC_AMP_GAIN_MAX,
641*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_mic_gain_tlv),
642*4882a593Smuzhiyun SOC_SINGLE("Mic1 Switch", DA7218_MIC_1_CTRL,
643*4882a593Smuzhiyun DA7218_MIC_1_AMP_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
644*4882a593Smuzhiyun DA7218_INVERT),
645*4882a593Smuzhiyun SOC_SINGLE_TLV("Mic2 Volume", DA7218_MIC_2_GAIN,
646*4882a593Smuzhiyun DA7218_MIC_2_AMP_GAIN_SHIFT, DA7218_MIC_AMP_GAIN_MAX,
647*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_mic_gain_tlv),
648*4882a593Smuzhiyun SOC_SINGLE("Mic2 Switch", DA7218_MIC_2_CTRL,
649*4882a593Smuzhiyun DA7218_MIC_2_AMP_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
650*4882a593Smuzhiyun DA7218_INVERT),
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun /* Mixer Input */
653*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("Mixin1 Volume", DA7218_MIXIN_1_GAIN,
654*4882a593Smuzhiyun DA7218_MIXIN_1_AMP_GAIN_SHIFT,
655*4882a593Smuzhiyun DA7218_MIXIN_AMP_GAIN_MAX, DA7218_NO_INVERT,
656*4882a593Smuzhiyun snd_soc_get_volsw, da7218_mixin_gain_put,
657*4882a593Smuzhiyun da7218_mixin_gain_tlv),
658*4882a593Smuzhiyun SOC_SINGLE("Mixin1 Switch", DA7218_MIXIN_1_CTRL,
659*4882a593Smuzhiyun DA7218_MIXIN_1_AMP_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
660*4882a593Smuzhiyun DA7218_INVERT),
661*4882a593Smuzhiyun SOC_SINGLE("Mixin1 Gain Ramp Switch", DA7218_MIXIN_1_CTRL,
662*4882a593Smuzhiyun DA7218_MIXIN_1_AMP_RAMP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
663*4882a593Smuzhiyun DA7218_NO_INVERT),
664*4882a593Smuzhiyun SOC_SINGLE("Mixin1 ZC Gain Switch", DA7218_MIXIN_1_CTRL,
665*4882a593Smuzhiyun DA7218_MIXIN_1_AMP_ZC_EN_SHIFT, DA7218_SWITCH_EN_MAX,
666*4882a593Smuzhiyun DA7218_NO_INVERT),
667*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("Mixin2 Volume", DA7218_MIXIN_2_GAIN,
668*4882a593Smuzhiyun DA7218_MIXIN_2_AMP_GAIN_SHIFT,
669*4882a593Smuzhiyun DA7218_MIXIN_AMP_GAIN_MAX, DA7218_NO_INVERT,
670*4882a593Smuzhiyun snd_soc_get_volsw, da7218_mixin_gain_put,
671*4882a593Smuzhiyun da7218_mixin_gain_tlv),
672*4882a593Smuzhiyun SOC_SINGLE("Mixin2 Switch", DA7218_MIXIN_2_CTRL,
673*4882a593Smuzhiyun DA7218_MIXIN_2_AMP_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
674*4882a593Smuzhiyun DA7218_INVERT),
675*4882a593Smuzhiyun SOC_SINGLE("Mixin2 Gain Ramp Switch", DA7218_MIXIN_2_CTRL,
676*4882a593Smuzhiyun DA7218_MIXIN_2_AMP_RAMP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
677*4882a593Smuzhiyun DA7218_NO_INVERT),
678*4882a593Smuzhiyun SOC_SINGLE("Mixin2 ZC Gain Switch", DA7218_MIXIN_2_CTRL,
679*4882a593Smuzhiyun DA7218_MIXIN_2_AMP_ZC_EN_SHIFT, DA7218_SWITCH_EN_MAX,
680*4882a593Smuzhiyun DA7218_NO_INVERT),
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun /* ADCs */
683*4882a593Smuzhiyun SOC_SINGLE("ADC1 AAF Switch", DA7218_ADC_1_CTRL,
684*4882a593Smuzhiyun DA7218_ADC_1_AAF_EN_SHIFT, DA7218_SWITCH_EN_MAX,
685*4882a593Smuzhiyun DA7218_NO_INVERT),
686*4882a593Smuzhiyun SOC_SINGLE("ADC2 AAF Switch", DA7218_ADC_2_CTRL,
687*4882a593Smuzhiyun DA7218_ADC_2_AAF_EN_SHIFT, DA7218_SWITCH_EN_MAX,
688*4882a593Smuzhiyun DA7218_NO_INVERT),
689*4882a593Smuzhiyun SOC_SINGLE("ADC LP Mode Switch", DA7218_ADC_MODE,
690*4882a593Smuzhiyun DA7218_ADC_LP_MODE_SHIFT, DA7218_SWITCH_EN_MAX,
691*4882a593Smuzhiyun DA7218_NO_INVERT),
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun /* Input Filters */
694*4882a593Smuzhiyun SOC_SINGLE_TLV("In Filter1L Volume", DA7218_IN_1L_GAIN,
695*4882a593Smuzhiyun DA7218_IN_1L_DIGITAL_GAIN_SHIFT,
696*4882a593Smuzhiyun DA7218_IN_DIGITAL_GAIN_MAX, DA7218_NO_INVERT,
697*4882a593Smuzhiyun da7218_in_dig_gain_tlv),
698*4882a593Smuzhiyun SOC_SINGLE("In Filter1L Switch", DA7218_IN_1L_FILTER_CTRL,
699*4882a593Smuzhiyun DA7218_IN_1L_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
700*4882a593Smuzhiyun DA7218_INVERT),
701*4882a593Smuzhiyun SOC_SINGLE("In Filter1L Gain Ramp Switch", DA7218_IN_1L_FILTER_CTRL,
702*4882a593Smuzhiyun DA7218_IN_1L_RAMP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
703*4882a593Smuzhiyun DA7218_NO_INVERT),
704*4882a593Smuzhiyun SOC_SINGLE_TLV("In Filter1R Volume", DA7218_IN_1R_GAIN,
705*4882a593Smuzhiyun DA7218_IN_1R_DIGITAL_GAIN_SHIFT,
706*4882a593Smuzhiyun DA7218_IN_DIGITAL_GAIN_MAX, DA7218_NO_INVERT,
707*4882a593Smuzhiyun da7218_in_dig_gain_tlv),
708*4882a593Smuzhiyun SOC_SINGLE("In Filter1R Switch", DA7218_IN_1R_FILTER_CTRL,
709*4882a593Smuzhiyun DA7218_IN_1R_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
710*4882a593Smuzhiyun DA7218_INVERT),
711*4882a593Smuzhiyun SOC_SINGLE("In Filter1R Gain Ramp Switch",
712*4882a593Smuzhiyun DA7218_IN_1R_FILTER_CTRL, DA7218_IN_1R_RAMP_EN_SHIFT,
713*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
714*4882a593Smuzhiyun SOC_SINGLE_TLV("In Filter2L Volume", DA7218_IN_2L_GAIN,
715*4882a593Smuzhiyun DA7218_IN_2L_DIGITAL_GAIN_SHIFT,
716*4882a593Smuzhiyun DA7218_IN_DIGITAL_GAIN_MAX, DA7218_NO_INVERT,
717*4882a593Smuzhiyun da7218_in_dig_gain_tlv),
718*4882a593Smuzhiyun SOC_SINGLE("In Filter2L Switch", DA7218_IN_2L_FILTER_CTRL,
719*4882a593Smuzhiyun DA7218_IN_2L_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
720*4882a593Smuzhiyun DA7218_INVERT),
721*4882a593Smuzhiyun SOC_SINGLE("In Filter2L Gain Ramp Switch", DA7218_IN_2L_FILTER_CTRL,
722*4882a593Smuzhiyun DA7218_IN_2L_RAMP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
723*4882a593Smuzhiyun DA7218_NO_INVERT),
724*4882a593Smuzhiyun SOC_SINGLE_TLV("In Filter2R Volume", DA7218_IN_2R_GAIN,
725*4882a593Smuzhiyun DA7218_IN_2R_DIGITAL_GAIN_SHIFT,
726*4882a593Smuzhiyun DA7218_IN_DIGITAL_GAIN_MAX, DA7218_NO_INVERT,
727*4882a593Smuzhiyun da7218_in_dig_gain_tlv),
728*4882a593Smuzhiyun SOC_SINGLE("In Filter2R Switch", DA7218_IN_2R_FILTER_CTRL,
729*4882a593Smuzhiyun DA7218_IN_2R_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
730*4882a593Smuzhiyun DA7218_INVERT),
731*4882a593Smuzhiyun SOC_SINGLE("In Filter2R Gain Ramp Switch",
732*4882a593Smuzhiyun DA7218_IN_2R_FILTER_CTRL, DA7218_IN_2R_RAMP_EN_SHIFT,
733*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun /* AGS */
736*4882a593Smuzhiyun SOC_SINGLE_TLV("AGS Trigger", DA7218_AGS_TRIGGER,
737*4882a593Smuzhiyun DA7218_AGS_TRIGGER_SHIFT, DA7218_AGS_TRIGGER_MAX,
738*4882a593Smuzhiyun DA7218_INVERT, da7218_ags_trigger_tlv),
739*4882a593Smuzhiyun SOC_SINGLE_TLV("AGS Max Attenuation", DA7218_AGS_ATT_MAX,
740*4882a593Smuzhiyun DA7218_AGS_ATT_MAX_SHIFT, DA7218_AGS_ATT_MAX_MAX,
741*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_ags_att_max_tlv),
742*4882a593Smuzhiyun SOC_SINGLE("AGS Anticlip Switch", DA7218_AGS_ANTICLIP_CTRL,
743*4882a593Smuzhiyun DA7218_AGS_ANTICLIP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
744*4882a593Smuzhiyun DA7218_NO_INVERT),
745*4882a593Smuzhiyun SOC_SINGLE("AGS Channel1 Switch", DA7218_AGS_ENABLE,
746*4882a593Smuzhiyun DA7218_AGS_ENABLE_CHAN1_SHIFT, DA7218_SWITCH_EN_MAX,
747*4882a593Smuzhiyun DA7218_NO_INVERT),
748*4882a593Smuzhiyun SOC_SINGLE("AGS Channel2 Switch", DA7218_AGS_ENABLE,
749*4882a593Smuzhiyun DA7218_AGS_ENABLE_CHAN2_SHIFT, DA7218_SWITCH_EN_MAX,
750*4882a593Smuzhiyun DA7218_NO_INVERT),
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun /* ALC */
753*4882a593Smuzhiyun SOC_ENUM("ALC Attack Rate", da7218_alc_attack_rate),
754*4882a593Smuzhiyun SOC_ENUM("ALC Release Rate", da7218_alc_release_rate),
755*4882a593Smuzhiyun SOC_ENUM("ALC Hold Time", da7218_alc_hold_time),
756*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Noise Threshold", DA7218_ALC_NOISE,
757*4882a593Smuzhiyun DA7218_ALC_NOISE_SHIFT, DA7218_ALC_THRESHOLD_MAX,
758*4882a593Smuzhiyun DA7218_INVERT, da7218_alc_threshold_tlv),
759*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Min Threshold", DA7218_ALC_TARGET_MIN,
760*4882a593Smuzhiyun DA7218_ALC_THRESHOLD_MIN_SHIFT, DA7218_ALC_THRESHOLD_MAX,
761*4882a593Smuzhiyun DA7218_INVERT, da7218_alc_threshold_tlv),
762*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Max Threshold", DA7218_ALC_TARGET_MAX,
763*4882a593Smuzhiyun DA7218_ALC_THRESHOLD_MAX_SHIFT, DA7218_ALC_THRESHOLD_MAX,
764*4882a593Smuzhiyun DA7218_INVERT, da7218_alc_threshold_tlv),
765*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Max Attenuation", DA7218_ALC_GAIN_LIMITS,
766*4882a593Smuzhiyun DA7218_ALC_ATTEN_MAX_SHIFT, DA7218_ALC_ATTEN_GAIN_MAX,
767*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_alc_gain_tlv),
768*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Max Gain", DA7218_ALC_GAIN_LIMITS,
769*4882a593Smuzhiyun DA7218_ALC_GAIN_MAX_SHIFT, DA7218_ALC_ATTEN_GAIN_MAX,
770*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_alc_gain_tlv),
771*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("ALC Min Analog Gain", DA7218_ALC_ANA_GAIN_LIMITS,
772*4882a593Smuzhiyun DA7218_ALC_ANA_GAIN_MIN_SHIFT,
773*4882a593Smuzhiyun DA7218_ALC_ANA_GAIN_MIN, DA7218_ALC_ANA_GAIN_MAX,
774*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_alc_ana_gain_tlv),
775*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("ALC Max Analog Gain", DA7218_ALC_ANA_GAIN_LIMITS,
776*4882a593Smuzhiyun DA7218_ALC_ANA_GAIN_MAX_SHIFT,
777*4882a593Smuzhiyun DA7218_ALC_ANA_GAIN_MIN, DA7218_ALC_ANA_GAIN_MAX,
778*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_alc_ana_gain_tlv),
779*4882a593Smuzhiyun SOC_ENUM("ALC Anticlip Step", da7218_alc_anticlip_step),
780*4882a593Smuzhiyun SOC_SINGLE("ALC Anticlip Switch", DA7218_ALC_ANTICLIP_CTRL,
781*4882a593Smuzhiyun DA7218_ALC_ANTICLIP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
782*4882a593Smuzhiyun DA7218_NO_INVERT),
783*4882a593Smuzhiyun SOC_DOUBLE_EXT("ALC Channel1 Switch", DA7218_ALC_CTRL1,
784*4882a593Smuzhiyun DA7218_ALC_CHAN1_L_EN_SHIFT, DA7218_ALC_CHAN1_R_EN_SHIFT,
785*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT,
786*4882a593Smuzhiyun snd_soc_get_volsw, da7218_alc_sw_put),
787*4882a593Smuzhiyun SOC_DOUBLE_EXT("ALC Channel2 Switch", DA7218_ALC_CTRL1,
788*4882a593Smuzhiyun DA7218_ALC_CHAN2_L_EN_SHIFT, DA7218_ALC_CHAN2_R_EN_SHIFT,
789*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT,
790*4882a593Smuzhiyun snd_soc_get_volsw, da7218_alc_sw_put),
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun /* Envelope Tracking */
793*4882a593Smuzhiyun SOC_ENUM("Envelope Tracking Attack Rate", da7218_integ_attack_rate),
794*4882a593Smuzhiyun SOC_ENUM("Envelope Tracking Release Rate", da7218_integ_release_rate),
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun /* Input High-Pass Filters */
797*4882a593Smuzhiyun SOC_ENUM("In Filter1 HPF Mode", da7218_in1_hpf_mode),
798*4882a593Smuzhiyun SOC_ENUM("In Filter1 HPF Corner Audio", da7218_in1_audio_hpf_corner),
799*4882a593Smuzhiyun SOC_ENUM("In Filter1 HPF Corner Voice", da7218_in1_voice_hpf_corner),
800*4882a593Smuzhiyun SOC_ENUM("In Filter2 HPF Mode", da7218_in2_hpf_mode),
801*4882a593Smuzhiyun SOC_ENUM("In Filter2 HPF Corner Audio", da7218_in2_audio_hpf_corner),
802*4882a593Smuzhiyun SOC_ENUM("In Filter2 HPF Corner Voice", da7218_in2_voice_hpf_corner),
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun /* Mic Level Detect */
805*4882a593Smuzhiyun SOC_DOUBLE_EXT("Mic Level Detect Channel1 Switch", DA7218_LVL_DET_CTRL,
806*4882a593Smuzhiyun DA7218_LVL_DET_EN_CHAN1L_SHIFT,
807*4882a593Smuzhiyun DA7218_LVL_DET_EN_CHAN1R_SHIFT, DA7218_SWITCH_EN_MAX,
808*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_mic_lvl_det_sw_get,
809*4882a593Smuzhiyun da7218_mic_lvl_det_sw_put),
810*4882a593Smuzhiyun SOC_DOUBLE_EXT("Mic Level Detect Channel2 Switch", DA7218_LVL_DET_CTRL,
811*4882a593Smuzhiyun DA7218_LVL_DET_EN_CHAN2L_SHIFT,
812*4882a593Smuzhiyun DA7218_LVL_DET_EN_CHAN2R_SHIFT, DA7218_SWITCH_EN_MAX,
813*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_mic_lvl_det_sw_get,
814*4882a593Smuzhiyun da7218_mic_lvl_det_sw_put),
815*4882a593Smuzhiyun SOC_SINGLE("Mic Level Detect Level", DA7218_LVL_DET_LEVEL,
816*4882a593Smuzhiyun DA7218_LVL_DET_LEVEL_SHIFT, DA7218_LVL_DET_LEVEL_MAX,
817*4882a593Smuzhiyun DA7218_NO_INVERT),
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun /* Digital Mixer (Input) */
820*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1L Out1 DAIL Volume",
821*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1L_INFILT_1L_GAIN,
822*4882a593Smuzhiyun DA7218_OUTDAI_1L_INFILT_1L_GAIN_SHIFT,
823*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
824*4882a593Smuzhiyun da7218_dmix_gain_tlv),
825*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1L Out1 DAIR Volume",
826*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1R_INFILT_1L_GAIN,
827*4882a593Smuzhiyun DA7218_OUTDAI_1R_INFILT_1L_GAIN_SHIFT,
828*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
829*4882a593Smuzhiyun da7218_dmix_gain_tlv),
830*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1L Out2 DAIL Volume",
831*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2L_INFILT_1L_GAIN,
832*4882a593Smuzhiyun DA7218_OUTDAI_2L_INFILT_1L_GAIN_SHIFT,
833*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
834*4882a593Smuzhiyun da7218_dmix_gain_tlv),
835*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1L Out2 DAIR Volume",
836*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2R_INFILT_1L_GAIN,
837*4882a593Smuzhiyun DA7218_OUTDAI_2R_INFILT_1L_GAIN_SHIFT,
838*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
839*4882a593Smuzhiyun da7218_dmix_gain_tlv),
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1R Out1 DAIL Volume",
842*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1L_INFILT_1R_GAIN,
843*4882a593Smuzhiyun DA7218_OUTDAI_1L_INFILT_1R_GAIN_SHIFT,
844*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
845*4882a593Smuzhiyun da7218_dmix_gain_tlv),
846*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1R Out1 DAIR Volume",
847*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1R_INFILT_1R_GAIN,
848*4882a593Smuzhiyun DA7218_OUTDAI_1R_INFILT_1R_GAIN_SHIFT,
849*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
850*4882a593Smuzhiyun da7218_dmix_gain_tlv),
851*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1R Out2 DAIL Volume",
852*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2L_INFILT_1R_GAIN,
853*4882a593Smuzhiyun DA7218_OUTDAI_2L_INFILT_1R_GAIN_SHIFT,
854*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
855*4882a593Smuzhiyun da7218_dmix_gain_tlv),
856*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1R Out2 DAIR Volume",
857*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2R_INFILT_1R_GAIN,
858*4882a593Smuzhiyun DA7218_OUTDAI_2R_INFILT_1R_GAIN_SHIFT,
859*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
860*4882a593Smuzhiyun da7218_dmix_gain_tlv),
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2L Out1 DAIL Volume",
863*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1L_INFILT_2L_GAIN,
864*4882a593Smuzhiyun DA7218_OUTDAI_1L_INFILT_2L_GAIN_SHIFT,
865*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
866*4882a593Smuzhiyun da7218_dmix_gain_tlv),
867*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2L Out1 DAIR Volume",
868*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1R_INFILT_2L_GAIN,
869*4882a593Smuzhiyun DA7218_OUTDAI_1R_INFILT_2L_GAIN_SHIFT,
870*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
871*4882a593Smuzhiyun da7218_dmix_gain_tlv),
872*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2L Out2 DAIL Volume",
873*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2L_INFILT_2L_GAIN,
874*4882a593Smuzhiyun DA7218_OUTDAI_2L_INFILT_2L_GAIN_SHIFT,
875*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
876*4882a593Smuzhiyun da7218_dmix_gain_tlv),
877*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2L Out2 DAIR Volume",
878*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2R_INFILT_2L_GAIN,
879*4882a593Smuzhiyun DA7218_OUTDAI_2R_INFILT_2L_GAIN_SHIFT,
880*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
881*4882a593Smuzhiyun da7218_dmix_gain_tlv),
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2R Out1 DAIL Volume",
884*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1L_INFILT_2R_GAIN,
885*4882a593Smuzhiyun DA7218_OUTDAI_1L_INFILT_2R_GAIN_SHIFT,
886*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
887*4882a593Smuzhiyun da7218_dmix_gain_tlv),
888*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2R Out1 DAIR Volume",
889*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1R_INFILT_2R_GAIN,
890*4882a593Smuzhiyun DA7218_OUTDAI_1R_INFILT_2R_GAIN_SHIFT,
891*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
892*4882a593Smuzhiyun da7218_dmix_gain_tlv),
893*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2R Out2 DAIL Volume",
894*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2L_INFILT_2R_GAIN,
895*4882a593Smuzhiyun DA7218_OUTDAI_2L_INFILT_2R_GAIN_SHIFT,
896*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
897*4882a593Smuzhiyun da7218_dmix_gain_tlv),
898*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2R Out2 DAIR Volume",
899*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2R_INFILT_2R_GAIN,
900*4882a593Smuzhiyun DA7218_OUTDAI_2R_INFILT_2R_GAIN_SHIFT,
901*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
902*4882a593Smuzhiyun da7218_dmix_gain_tlv),
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix ToneGen Out1 DAIL Volume",
905*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1L_TONEGEN_GAIN,
906*4882a593Smuzhiyun DA7218_OUTDAI_1L_TONEGEN_GAIN_SHIFT,
907*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
908*4882a593Smuzhiyun da7218_dmix_gain_tlv),
909*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix ToneGen Out1 DAIR Volume",
910*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1R_TONEGEN_GAIN,
911*4882a593Smuzhiyun DA7218_OUTDAI_1R_TONEGEN_GAIN_SHIFT,
912*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
913*4882a593Smuzhiyun da7218_dmix_gain_tlv),
914*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix ToneGen Out2 DAIL Volume",
915*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2L_TONEGEN_GAIN,
916*4882a593Smuzhiyun DA7218_OUTDAI_2L_TONEGEN_GAIN_SHIFT,
917*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
918*4882a593Smuzhiyun da7218_dmix_gain_tlv),
919*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix ToneGen Out2 DAIR Volume",
920*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2R_TONEGEN_GAIN,
921*4882a593Smuzhiyun DA7218_OUTDAI_2R_TONEGEN_GAIN_SHIFT,
922*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
923*4882a593Smuzhiyun da7218_dmix_gain_tlv),
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIL Out1 DAIL Volume",
926*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1L_INDAI_1L_GAIN,
927*4882a593Smuzhiyun DA7218_OUTDAI_1L_INDAI_1L_GAIN_SHIFT,
928*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
929*4882a593Smuzhiyun da7218_dmix_gain_tlv),
930*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIL Out1 DAIR Volume",
931*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1R_INDAI_1L_GAIN,
932*4882a593Smuzhiyun DA7218_OUTDAI_1R_INDAI_1L_GAIN_SHIFT,
933*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
934*4882a593Smuzhiyun da7218_dmix_gain_tlv),
935*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIL Out2 DAIL Volume",
936*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2L_INDAI_1L_GAIN,
937*4882a593Smuzhiyun DA7218_OUTDAI_2L_INDAI_1L_GAIN_SHIFT,
938*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
939*4882a593Smuzhiyun da7218_dmix_gain_tlv),
940*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIL Out2 DAIR Volume",
941*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2R_INDAI_1L_GAIN,
942*4882a593Smuzhiyun DA7218_OUTDAI_2R_INDAI_1L_GAIN_SHIFT,
943*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
944*4882a593Smuzhiyun da7218_dmix_gain_tlv),
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIR Out1 DAIL Volume",
947*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1L_INDAI_1R_GAIN,
948*4882a593Smuzhiyun DA7218_OUTDAI_1L_INDAI_1R_GAIN_SHIFT,
949*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
950*4882a593Smuzhiyun da7218_dmix_gain_tlv),
951*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIR Out1 DAIR Volume",
952*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_1R_INDAI_1R_GAIN,
953*4882a593Smuzhiyun DA7218_OUTDAI_1R_INDAI_1R_GAIN_SHIFT,
954*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
955*4882a593Smuzhiyun da7218_dmix_gain_tlv),
956*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIR Out2 DAIL Volume",
957*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2L_INDAI_1R_GAIN,
958*4882a593Smuzhiyun DA7218_OUTDAI_2L_INDAI_1R_GAIN_SHIFT,
959*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
960*4882a593Smuzhiyun da7218_dmix_gain_tlv),
961*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIR Out2 DAIR Volume",
962*4882a593Smuzhiyun DA7218_DMIX_OUTDAI_2R_INDAI_1R_GAIN,
963*4882a593Smuzhiyun DA7218_OUTDAI_2R_INDAI_1R_GAIN_SHIFT,
964*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
965*4882a593Smuzhiyun da7218_dmix_gain_tlv),
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun /* Digital Mixer (Output) */
968*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1L Out FilterL Volume",
969*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1L_INFILT_1L_GAIN,
970*4882a593Smuzhiyun DA7218_OUTFILT_1L_INFILT_1L_GAIN_SHIFT,
971*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
972*4882a593Smuzhiyun da7218_dmix_gain_tlv),
973*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1L Out FilterR Volume",
974*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1R_INFILT_1L_GAIN,
975*4882a593Smuzhiyun DA7218_OUTFILT_1R_INFILT_1L_GAIN_SHIFT,
976*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
977*4882a593Smuzhiyun da7218_dmix_gain_tlv),
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1R Out FilterL Volume",
980*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1L_INFILT_1R_GAIN,
981*4882a593Smuzhiyun DA7218_OUTFILT_1L_INFILT_1R_GAIN_SHIFT,
982*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
983*4882a593Smuzhiyun da7218_dmix_gain_tlv),
984*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter1R Out FilterR Volume",
985*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1R_INFILT_1R_GAIN,
986*4882a593Smuzhiyun DA7218_OUTFILT_1R_INFILT_1R_GAIN_SHIFT,
987*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
988*4882a593Smuzhiyun da7218_dmix_gain_tlv),
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2L Out FilterL Volume",
991*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1L_INFILT_2L_GAIN,
992*4882a593Smuzhiyun DA7218_OUTFILT_1L_INFILT_2L_GAIN_SHIFT,
993*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
994*4882a593Smuzhiyun da7218_dmix_gain_tlv),
995*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2L Out FilterR Volume",
996*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1R_INFILT_2L_GAIN,
997*4882a593Smuzhiyun DA7218_OUTFILT_1R_INFILT_2L_GAIN_SHIFT,
998*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
999*4882a593Smuzhiyun da7218_dmix_gain_tlv),
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2R Out FilterL Volume",
1002*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1L_INFILT_2R_GAIN,
1003*4882a593Smuzhiyun DA7218_OUTFILT_1L_INFILT_2R_GAIN_SHIFT,
1004*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
1005*4882a593Smuzhiyun da7218_dmix_gain_tlv),
1006*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In Filter2R Out FilterR Volume",
1007*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1R_INFILT_2R_GAIN,
1008*4882a593Smuzhiyun DA7218_OUTFILT_1R_INFILT_2R_GAIN_SHIFT,
1009*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
1010*4882a593Smuzhiyun da7218_dmix_gain_tlv),
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix ToneGen Out FilterL Volume",
1013*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1L_TONEGEN_GAIN,
1014*4882a593Smuzhiyun DA7218_OUTFILT_1L_TONEGEN_GAIN_SHIFT,
1015*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
1016*4882a593Smuzhiyun da7218_dmix_gain_tlv),
1017*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix ToneGen Out FilterR Volume",
1018*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1R_TONEGEN_GAIN,
1019*4882a593Smuzhiyun DA7218_OUTFILT_1R_TONEGEN_GAIN_SHIFT,
1020*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
1021*4882a593Smuzhiyun da7218_dmix_gain_tlv),
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIL Out FilterL Volume",
1024*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1L_INDAI_1L_GAIN,
1025*4882a593Smuzhiyun DA7218_OUTFILT_1L_INDAI_1L_GAIN_SHIFT,
1026*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
1027*4882a593Smuzhiyun da7218_dmix_gain_tlv),
1028*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIL Out FilterR Volume",
1029*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1R_INDAI_1L_GAIN,
1030*4882a593Smuzhiyun DA7218_OUTFILT_1R_INDAI_1L_GAIN_SHIFT,
1031*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
1032*4882a593Smuzhiyun da7218_dmix_gain_tlv),
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIR Out FilterL Volume",
1035*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1L_INDAI_1R_GAIN,
1036*4882a593Smuzhiyun DA7218_OUTFILT_1L_INDAI_1R_GAIN_SHIFT,
1037*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
1038*4882a593Smuzhiyun da7218_dmix_gain_tlv),
1039*4882a593Smuzhiyun SOC_SINGLE_TLV("DMix In DAIR Out FilterR Volume",
1040*4882a593Smuzhiyun DA7218_DMIX_OUTFILT_1R_INDAI_1R_GAIN,
1041*4882a593Smuzhiyun DA7218_OUTFILT_1R_INDAI_1R_GAIN_SHIFT,
1042*4882a593Smuzhiyun DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
1043*4882a593Smuzhiyun da7218_dmix_gain_tlv),
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun /* Sidetone Filter */
1046*4882a593Smuzhiyun SND_SOC_BYTES_EXT("Sidetone BiQuad Coefficients",
1047*4882a593Smuzhiyun DA7218_SIDETONE_BIQ_3STAGE_CFG_SIZE,
1048*4882a593Smuzhiyun da7218_biquad_coeff_get, da7218_biquad_coeff_put),
1049*4882a593Smuzhiyun SOC_SINGLE_TLV("Sidetone Volume", DA7218_SIDETONE_GAIN,
1050*4882a593Smuzhiyun DA7218_SIDETONE_GAIN_SHIFT, DA7218_DMIX_GAIN_MAX,
1051*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_dmix_gain_tlv),
1052*4882a593Smuzhiyun SOC_SINGLE("Sidetone Switch", DA7218_SIDETONE_CTRL,
1053*4882a593Smuzhiyun DA7218_SIDETONE_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
1054*4882a593Smuzhiyun DA7218_INVERT),
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun /* Tone Generator */
1057*4882a593Smuzhiyun SOC_ENUM("ToneGen DTMF Key", da7218_tonegen_dtmf_key),
1058*4882a593Smuzhiyun SOC_SINGLE("ToneGen DTMF Switch", DA7218_TONE_GEN_CFG1,
1059*4882a593Smuzhiyun DA7218_DTMF_EN_SHIFT, DA7218_SWITCH_EN_MAX,
1060*4882a593Smuzhiyun DA7218_NO_INVERT),
1061*4882a593Smuzhiyun SOC_ENUM("ToneGen Sinewave Gen Type", da7218_tonegen_swg_sel),
1062*4882a593Smuzhiyun SOC_SINGLE_EXT("ToneGen Sinewave1 Freq", DA7218_TONE_GEN_FREQ1_L,
1063*4882a593Smuzhiyun DA7218_FREQ1_L_SHIFT, DA7218_FREQ_MAX, DA7218_NO_INVERT,
1064*4882a593Smuzhiyun da7218_tonegen_freq_get, da7218_tonegen_freq_put),
1065*4882a593Smuzhiyun SOC_SINGLE_EXT("ToneGen Sinewave2 Freq", DA7218_TONE_GEN_FREQ2_L,
1066*4882a593Smuzhiyun DA7218_FREQ2_L_SHIFT, DA7218_FREQ_MAX, DA7218_NO_INVERT,
1067*4882a593Smuzhiyun da7218_tonegen_freq_get, da7218_tonegen_freq_put),
1068*4882a593Smuzhiyun SOC_SINGLE("ToneGen On Time", DA7218_TONE_GEN_ON_PER,
1069*4882a593Smuzhiyun DA7218_BEEP_ON_PER_SHIFT, DA7218_BEEP_ON_OFF_MAX,
1070*4882a593Smuzhiyun DA7218_NO_INVERT),
1071*4882a593Smuzhiyun SOC_SINGLE("ToneGen Off Time", DA7218_TONE_GEN_OFF_PER,
1072*4882a593Smuzhiyun DA7218_BEEP_OFF_PER_SHIFT, DA7218_BEEP_ON_OFF_MAX,
1073*4882a593Smuzhiyun DA7218_NO_INVERT),
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun /* Gain ramping */
1076*4882a593Smuzhiyun SOC_ENUM("Gain Ramp Rate", da7218_gain_ramp_rate),
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun /* DGS */
1079*4882a593Smuzhiyun SOC_SINGLE_TLV("DGS Trigger", DA7218_DGS_TRIGGER,
1080*4882a593Smuzhiyun DA7218_DGS_TRIGGER_LVL_SHIFT, DA7218_DGS_TRIGGER_MAX,
1081*4882a593Smuzhiyun DA7218_INVERT, da7218_dgs_trigger_tlv),
1082*4882a593Smuzhiyun SOC_ENUM("DGS Rise Coefficient", da7218_dgs_rise_coeff),
1083*4882a593Smuzhiyun SOC_ENUM("DGS Fall Coefficient", da7218_dgs_fall_coeff),
1084*4882a593Smuzhiyun SOC_SINGLE("DGS Sync Delay", DA7218_DGS_SYNC_DELAY,
1085*4882a593Smuzhiyun DA7218_DGS_SYNC_DELAY_SHIFT, DA7218_DGS_SYNC_DELAY_MAX,
1086*4882a593Smuzhiyun DA7218_NO_INVERT),
1087*4882a593Smuzhiyun SOC_SINGLE("DGS Fast SR Sync Delay", DA7218_DGS_SYNC_DELAY2,
1088*4882a593Smuzhiyun DA7218_DGS_SYNC_DELAY2_SHIFT, DA7218_DGS_SYNC_DELAY_MAX,
1089*4882a593Smuzhiyun DA7218_NO_INVERT),
1090*4882a593Smuzhiyun SOC_SINGLE("DGS Voice Filter Sync Delay", DA7218_DGS_SYNC_DELAY3,
1091*4882a593Smuzhiyun DA7218_DGS_SYNC_DELAY3_SHIFT, DA7218_DGS_SYNC_DELAY3_MAX,
1092*4882a593Smuzhiyun DA7218_NO_INVERT),
1093*4882a593Smuzhiyun SOC_SINGLE_TLV("DGS Anticlip Level", DA7218_DGS_LEVELS,
1094*4882a593Smuzhiyun DA7218_DGS_ANTICLIP_LVL_SHIFT,
1095*4882a593Smuzhiyun DA7218_DGS_ANTICLIP_LVL_MAX, DA7218_INVERT,
1096*4882a593Smuzhiyun da7218_dgs_anticlip_tlv),
1097*4882a593Smuzhiyun SOC_SINGLE_TLV("DGS Signal Level", DA7218_DGS_LEVELS,
1098*4882a593Smuzhiyun DA7218_DGS_SIGNAL_LVL_SHIFT, DA7218_DGS_SIGNAL_LVL_MAX,
1099*4882a593Smuzhiyun DA7218_INVERT, da7218_dgs_signal_tlv),
1100*4882a593Smuzhiyun SOC_SINGLE("DGS Gain Subrange Switch", DA7218_DGS_GAIN_CTRL,
1101*4882a593Smuzhiyun DA7218_DGS_SUBR_EN_SHIFT, DA7218_SWITCH_EN_MAX,
1102*4882a593Smuzhiyun DA7218_NO_INVERT),
1103*4882a593Smuzhiyun SOC_SINGLE("DGS Gain Ramp Switch", DA7218_DGS_GAIN_CTRL,
1104*4882a593Smuzhiyun DA7218_DGS_RAMP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
1105*4882a593Smuzhiyun DA7218_NO_INVERT),
1106*4882a593Smuzhiyun SOC_SINGLE("DGS Gain Steps", DA7218_DGS_GAIN_CTRL,
1107*4882a593Smuzhiyun DA7218_DGS_STEPS_SHIFT, DA7218_DGS_STEPS_MAX,
1108*4882a593Smuzhiyun DA7218_NO_INVERT),
1109*4882a593Smuzhiyun SOC_DOUBLE("DGS Switch", DA7218_DGS_ENABLE, DA7218_DGS_ENABLE_L_SHIFT,
1110*4882a593Smuzhiyun DA7218_DGS_ENABLE_R_SHIFT, DA7218_SWITCH_EN_MAX,
1111*4882a593Smuzhiyun DA7218_NO_INVERT),
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun /* Output High-Pass Filter */
1114*4882a593Smuzhiyun SOC_ENUM("Out Filter HPF Mode", da7218_out1_hpf_mode),
1115*4882a593Smuzhiyun SOC_ENUM("Out Filter HPF Corner Audio", da7218_out1_audio_hpf_corner),
1116*4882a593Smuzhiyun SOC_ENUM("Out Filter HPF Corner Voice", da7218_out1_voice_hpf_corner),
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun /* 5-Band Equaliser */
1119*4882a593Smuzhiyun SOC_SINGLE_TLV("Out EQ Band1 Volume", DA7218_OUT_1_EQ_12_FILTER_CTRL,
1120*4882a593Smuzhiyun DA7218_OUT_1_EQ_BAND1_SHIFT, DA7218_OUT_EQ_BAND_MAX,
1121*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_out_eq_band_tlv),
1122*4882a593Smuzhiyun SOC_SINGLE_TLV("Out EQ Band2 Volume", DA7218_OUT_1_EQ_12_FILTER_CTRL,
1123*4882a593Smuzhiyun DA7218_OUT_1_EQ_BAND2_SHIFT, DA7218_OUT_EQ_BAND_MAX,
1124*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_out_eq_band_tlv),
1125*4882a593Smuzhiyun SOC_SINGLE_TLV("Out EQ Band3 Volume", DA7218_OUT_1_EQ_34_FILTER_CTRL,
1126*4882a593Smuzhiyun DA7218_OUT_1_EQ_BAND3_SHIFT, DA7218_OUT_EQ_BAND_MAX,
1127*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_out_eq_band_tlv),
1128*4882a593Smuzhiyun SOC_SINGLE_TLV("Out EQ Band4 Volume", DA7218_OUT_1_EQ_34_FILTER_CTRL,
1129*4882a593Smuzhiyun DA7218_OUT_1_EQ_BAND4_SHIFT, DA7218_OUT_EQ_BAND_MAX,
1130*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_out_eq_band_tlv),
1131*4882a593Smuzhiyun SOC_SINGLE_TLV("Out EQ Band5 Volume", DA7218_OUT_1_EQ_5_FILTER_CTRL,
1132*4882a593Smuzhiyun DA7218_OUT_1_EQ_BAND5_SHIFT, DA7218_OUT_EQ_BAND_MAX,
1133*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_out_eq_band_tlv),
1134*4882a593Smuzhiyun SOC_SINGLE("Out EQ Switch", DA7218_OUT_1_EQ_5_FILTER_CTRL,
1135*4882a593Smuzhiyun DA7218_OUT_1_EQ_EN_SHIFT, DA7218_SWITCH_EN_MAX,
1136*4882a593Smuzhiyun DA7218_NO_INVERT),
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun /* BiQuad Filters */
1139*4882a593Smuzhiyun SND_SOC_BYTES_EXT("BiQuad Coefficients",
1140*4882a593Smuzhiyun DA7218_OUT_1_BIQ_5STAGE_CFG_SIZE,
1141*4882a593Smuzhiyun da7218_biquad_coeff_get, da7218_biquad_coeff_put),
1142*4882a593Smuzhiyun SOC_SINGLE("BiQuad Filter Switch", DA7218_OUT_1_BIQ_5STAGE_CTRL,
1143*4882a593Smuzhiyun DA7218_OUT_1_BIQ_5STAGE_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
1144*4882a593Smuzhiyun DA7218_INVERT),
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun /* Output Filters */
1147*4882a593Smuzhiyun SOC_DOUBLE_R_RANGE_TLV("Out Filter Volume", DA7218_OUT_1L_GAIN,
1148*4882a593Smuzhiyun DA7218_OUT_1R_GAIN,
1149*4882a593Smuzhiyun DA7218_OUT_1L_DIGITAL_GAIN_SHIFT,
1150*4882a593Smuzhiyun DA7218_OUT_DIGITAL_GAIN_MIN,
1151*4882a593Smuzhiyun DA7218_OUT_DIGITAL_GAIN_MAX, DA7218_NO_INVERT,
1152*4882a593Smuzhiyun da7218_out_dig_gain_tlv),
1153*4882a593Smuzhiyun SOC_DOUBLE_R("Out Filter Switch", DA7218_OUT_1L_FILTER_CTRL,
1154*4882a593Smuzhiyun DA7218_OUT_1R_FILTER_CTRL, DA7218_OUT_1L_MUTE_EN_SHIFT,
1155*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_INVERT),
1156*4882a593Smuzhiyun SOC_DOUBLE_R("Out Filter Gain Subrange Switch",
1157*4882a593Smuzhiyun DA7218_OUT_1L_FILTER_CTRL, DA7218_OUT_1R_FILTER_CTRL,
1158*4882a593Smuzhiyun DA7218_OUT_1L_SUBRANGE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
1159*4882a593Smuzhiyun DA7218_NO_INVERT),
1160*4882a593Smuzhiyun SOC_DOUBLE_R("Out Filter Gain Ramp Switch", DA7218_OUT_1L_FILTER_CTRL,
1161*4882a593Smuzhiyun DA7218_OUT_1R_FILTER_CTRL, DA7218_OUT_1L_RAMP_EN_SHIFT,
1162*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun /* Mixer Output */
1165*4882a593Smuzhiyun SOC_DOUBLE_R_RANGE_TLV("Mixout Volume", DA7218_MIXOUT_L_GAIN,
1166*4882a593Smuzhiyun DA7218_MIXOUT_R_GAIN,
1167*4882a593Smuzhiyun DA7218_MIXOUT_L_AMP_GAIN_SHIFT,
1168*4882a593Smuzhiyun DA7218_MIXOUT_AMP_GAIN_MIN,
1169*4882a593Smuzhiyun DA7218_MIXOUT_AMP_GAIN_MAX, DA7218_NO_INVERT,
1170*4882a593Smuzhiyun da7218_mixout_gain_tlv),
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun /* DAC Noise Gate */
1173*4882a593Smuzhiyun SOC_ENUM("DAC NG Setup Time", da7218_dac_ng_setup_time),
1174*4882a593Smuzhiyun SOC_ENUM("DAC NG Rampup Rate", da7218_dac_ng_rampup_rate),
1175*4882a593Smuzhiyun SOC_ENUM("DAC NG Rampdown Rate", da7218_dac_ng_rampdown_rate),
1176*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC NG Off Threshold", DA7218_DAC_NG_OFF_THRESH,
1177*4882a593Smuzhiyun DA7218_DAC_NG_OFF_THRESHOLD_SHIFT,
1178*4882a593Smuzhiyun DA7218_DAC_NG_THRESHOLD_MAX, DA7218_NO_INVERT,
1179*4882a593Smuzhiyun da7218_dac_ng_threshold_tlv),
1180*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC NG On Threshold", DA7218_DAC_NG_ON_THRESH,
1181*4882a593Smuzhiyun DA7218_DAC_NG_ON_THRESHOLD_SHIFT,
1182*4882a593Smuzhiyun DA7218_DAC_NG_THRESHOLD_MAX, DA7218_NO_INVERT,
1183*4882a593Smuzhiyun da7218_dac_ng_threshold_tlv),
1184*4882a593Smuzhiyun SOC_SINGLE("DAC NG Switch", DA7218_DAC_NG_CTRL, DA7218_DAC_NG_EN_SHIFT,
1185*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun /* CP */
1188*4882a593Smuzhiyun SOC_ENUM("Charge Pump Track Mode", da7218_cp_mchange),
1189*4882a593Smuzhiyun SOC_ENUM("Charge Pump Frequency", da7218_cp_fcontrol),
1190*4882a593Smuzhiyun SOC_ENUM("Charge Pump Decay Rate", da7218_cp_tau_delay),
1191*4882a593Smuzhiyun SOC_SINGLE("Charge Pump Threshold", DA7218_CP_VOL_THRESHOLD1,
1192*4882a593Smuzhiyun DA7218_CP_THRESH_VDD2_SHIFT, DA7218_CP_THRESH_VDD2_MAX,
1193*4882a593Smuzhiyun DA7218_NO_INVERT),
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun /* Headphones */
1196*4882a593Smuzhiyun SOC_DOUBLE_R_RANGE_TLV("Headphone Volume", DA7218_HP_L_GAIN,
1197*4882a593Smuzhiyun DA7218_HP_R_GAIN, DA7218_HP_L_AMP_GAIN_SHIFT,
1198*4882a593Smuzhiyun DA7218_HP_AMP_GAIN_MIN, DA7218_HP_AMP_GAIN_MAX,
1199*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_hp_gain_tlv),
1200*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone Switch", DA7218_HP_L_CTRL, DA7218_HP_R_CTRL,
1201*4882a593Smuzhiyun DA7218_HP_L_AMP_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
1202*4882a593Smuzhiyun DA7218_INVERT),
1203*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone Gain Ramp Switch", DA7218_HP_L_CTRL,
1204*4882a593Smuzhiyun DA7218_HP_R_CTRL, DA7218_HP_L_AMP_RAMP_EN_SHIFT,
1205*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
1206*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone ZC Gain Switch", DA7218_HP_L_CTRL,
1207*4882a593Smuzhiyun DA7218_HP_R_CTRL, DA7218_HP_L_AMP_ZC_EN_SHIFT,
1208*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
1209*4882a593Smuzhiyun };
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun
1212*4882a593Smuzhiyun /*
1213*4882a593Smuzhiyun * DAPM Mux Controls
1214*4882a593Smuzhiyun */
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun static const char * const da7218_mic_sel_text[] = { "Analog", "Digital" };
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun static const struct soc_enum da7218_mic1_sel =
1219*4882a593Smuzhiyun SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(da7218_mic_sel_text),
1220*4882a593Smuzhiyun da7218_mic_sel_text);
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_mic1_sel_mux =
1223*4882a593Smuzhiyun SOC_DAPM_ENUM("Mic1 Mux", da7218_mic1_sel);
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun static const struct soc_enum da7218_mic2_sel =
1226*4882a593Smuzhiyun SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(da7218_mic_sel_text),
1227*4882a593Smuzhiyun da7218_mic_sel_text);
1228*4882a593Smuzhiyun
1229*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_mic2_sel_mux =
1230*4882a593Smuzhiyun SOC_DAPM_ENUM("Mic2 Mux", da7218_mic2_sel);
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun static const char * const da7218_sidetone_in_sel_txt[] = {
1233*4882a593Smuzhiyun "In Filter1L", "In Filter1R", "In Filter2L", "In Filter2R"
1234*4882a593Smuzhiyun };
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun static const struct soc_enum da7218_sidetone_in_sel =
1237*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_SIDETONE_IN_SELECT,
1238*4882a593Smuzhiyun DA7218_SIDETONE_IN_SELECT_SHIFT,
1239*4882a593Smuzhiyun DA7218_SIDETONE_IN_SELECT_MAX,
1240*4882a593Smuzhiyun da7218_sidetone_in_sel_txt);
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_sidetone_in_sel_mux =
1243*4882a593Smuzhiyun SOC_DAPM_ENUM("Sidetone Mux", da7218_sidetone_in_sel);
1244*4882a593Smuzhiyun
1245*4882a593Smuzhiyun static const char * const da7218_out_filt_biq_sel_txt[] = {
1246*4882a593Smuzhiyun "Bypass", "Enabled"
1247*4882a593Smuzhiyun };
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun static const struct soc_enum da7218_out_filtl_biq_sel =
1250*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_OUT_1L_FILTER_CTRL,
1251*4882a593Smuzhiyun DA7218_OUT_1L_BIQ_5STAGE_SEL_SHIFT,
1252*4882a593Smuzhiyun DA7218_OUT_BIQ_5STAGE_SEL_MAX,
1253*4882a593Smuzhiyun da7218_out_filt_biq_sel_txt);
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_out_filtl_biq_sel_mux =
1256*4882a593Smuzhiyun SOC_DAPM_ENUM("Out FilterL BiQuad Mux", da7218_out_filtl_biq_sel);
1257*4882a593Smuzhiyun
1258*4882a593Smuzhiyun static const struct soc_enum da7218_out_filtr_biq_sel =
1259*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7218_OUT_1R_FILTER_CTRL,
1260*4882a593Smuzhiyun DA7218_OUT_1R_BIQ_5STAGE_SEL_SHIFT,
1261*4882a593Smuzhiyun DA7218_OUT_BIQ_5STAGE_SEL_MAX,
1262*4882a593Smuzhiyun da7218_out_filt_biq_sel_txt);
1263*4882a593Smuzhiyun
1264*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_out_filtr_biq_sel_mux =
1265*4882a593Smuzhiyun SOC_DAPM_ENUM("Out FilterR BiQuad Mux", da7218_out_filtr_biq_sel);
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun
1268*4882a593Smuzhiyun /*
1269*4882a593Smuzhiyun * DAPM Mixer Controls
1270*4882a593Smuzhiyun */
1271*4882a593Smuzhiyun
1272*4882a593Smuzhiyun #define DA7218_DMIX_CTRLS(reg) \
1273*4882a593Smuzhiyun SOC_DAPM_SINGLE("In Filter1L Switch", reg, \
1274*4882a593Smuzhiyun DA7218_DMIX_SRC_INFILT1L, \
1275*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
1276*4882a593Smuzhiyun SOC_DAPM_SINGLE("In Filter1R Switch", reg, \
1277*4882a593Smuzhiyun DA7218_DMIX_SRC_INFILT1R, \
1278*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
1279*4882a593Smuzhiyun SOC_DAPM_SINGLE("In Filter2L Switch", reg, \
1280*4882a593Smuzhiyun DA7218_DMIX_SRC_INFILT2L, \
1281*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
1282*4882a593Smuzhiyun SOC_DAPM_SINGLE("In Filter2R Switch", reg, \
1283*4882a593Smuzhiyun DA7218_DMIX_SRC_INFILT2R, \
1284*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
1285*4882a593Smuzhiyun SOC_DAPM_SINGLE("ToneGen Switch", reg, \
1286*4882a593Smuzhiyun DA7218_DMIX_SRC_TONEGEN, \
1287*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
1288*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAIL Switch", reg, DA7218_DMIX_SRC_DAIL, \
1289*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
1290*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAIR Switch", reg, DA7218_DMIX_SRC_DAIR, \
1291*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT)
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_out_dai1l_mix_controls[] = {
1294*4882a593Smuzhiyun DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTDAI_1L),
1295*4882a593Smuzhiyun };
1296*4882a593Smuzhiyun
1297*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_out_dai1r_mix_controls[] = {
1298*4882a593Smuzhiyun DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTDAI_1R),
1299*4882a593Smuzhiyun };
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_out_dai2l_mix_controls[] = {
1302*4882a593Smuzhiyun DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTDAI_2L),
1303*4882a593Smuzhiyun };
1304*4882a593Smuzhiyun
1305*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_out_dai2r_mix_controls[] = {
1306*4882a593Smuzhiyun DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTDAI_2R),
1307*4882a593Smuzhiyun };
1308*4882a593Smuzhiyun
1309*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_out_filtl_mix_controls[] = {
1310*4882a593Smuzhiyun DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTFILT_1L),
1311*4882a593Smuzhiyun };
1312*4882a593Smuzhiyun
1313*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_out_filtr_mix_controls[] = {
1314*4882a593Smuzhiyun DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTFILT_1R),
1315*4882a593Smuzhiyun };
1316*4882a593Smuzhiyun
1317*4882a593Smuzhiyun #define DA7218_DMIX_ST_CTRLS(reg) \
1318*4882a593Smuzhiyun SOC_DAPM_SINGLE("Out FilterL Switch", reg, \
1319*4882a593Smuzhiyun DA7218_DMIX_ST_SRC_OUTFILT1L, \
1320*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
1321*4882a593Smuzhiyun SOC_DAPM_SINGLE("Out FilterR Switch", reg, \
1322*4882a593Smuzhiyun DA7218_DMIX_ST_SRC_OUTFILT1R, \
1323*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
1324*4882a593Smuzhiyun SOC_DAPM_SINGLE("Sidetone Switch", reg, \
1325*4882a593Smuzhiyun DA7218_DMIX_ST_SRC_SIDETONE, \
1326*4882a593Smuzhiyun DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT) \
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_st_out_filtl_mix_controls[] = {
1329*4882a593Smuzhiyun DA7218_DMIX_ST_CTRLS(DA7218_DROUTING_ST_OUTFILT_1L),
1330*4882a593Smuzhiyun };
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun static const struct snd_kcontrol_new da7218_st_out_filtr_mix_controls[] = {
1333*4882a593Smuzhiyun DA7218_DMIX_ST_CTRLS(DA7218_DROUTING_ST_OUTFILT_1R),
1334*4882a593Smuzhiyun };
1335*4882a593Smuzhiyun
1336*4882a593Smuzhiyun
1337*4882a593Smuzhiyun /*
1338*4882a593Smuzhiyun * DAPM Events
1339*4882a593Smuzhiyun */
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun /*
1342*4882a593Smuzhiyun * We keep track of which input filters are enabled. This is used in the logic
1343*4882a593Smuzhiyun * for controlling the mic level detect feature.
1344*4882a593Smuzhiyun */
da7218_in_filter_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1345*4882a593Smuzhiyun static int da7218_in_filter_event(struct snd_soc_dapm_widget *w,
1346*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
1347*4882a593Smuzhiyun {
1348*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1349*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
1350*4882a593Smuzhiyun u8 mask;
1351*4882a593Smuzhiyun
1352*4882a593Smuzhiyun switch (w->reg) {
1353*4882a593Smuzhiyun case DA7218_IN_1L_FILTER_CTRL:
1354*4882a593Smuzhiyun mask = (1 << DA7218_LVL_DET_EN_CHAN1L_SHIFT);
1355*4882a593Smuzhiyun break;
1356*4882a593Smuzhiyun case DA7218_IN_1R_FILTER_CTRL:
1357*4882a593Smuzhiyun mask = (1 << DA7218_LVL_DET_EN_CHAN1R_SHIFT);
1358*4882a593Smuzhiyun break;
1359*4882a593Smuzhiyun case DA7218_IN_2L_FILTER_CTRL:
1360*4882a593Smuzhiyun mask = (1 << DA7218_LVL_DET_EN_CHAN2L_SHIFT);
1361*4882a593Smuzhiyun break;
1362*4882a593Smuzhiyun case DA7218_IN_2R_FILTER_CTRL:
1363*4882a593Smuzhiyun mask = (1 << DA7218_LVL_DET_EN_CHAN2R_SHIFT);
1364*4882a593Smuzhiyun break;
1365*4882a593Smuzhiyun default:
1366*4882a593Smuzhiyun return -EINVAL;
1367*4882a593Smuzhiyun }
1368*4882a593Smuzhiyun
1369*4882a593Smuzhiyun switch (event) {
1370*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
1371*4882a593Smuzhiyun da7218->in_filt_en |= mask;
1372*4882a593Smuzhiyun /*
1373*4882a593Smuzhiyun * If we're enabling path for mic level detect, wait for path
1374*4882a593Smuzhiyun * to settle before enabling feature to avoid incorrect and
1375*4882a593Smuzhiyun * unwanted detect events.
1376*4882a593Smuzhiyun */
1377*4882a593Smuzhiyun if (mask & da7218->mic_lvl_det_en)
1378*4882a593Smuzhiyun msleep(DA7218_MIC_LVL_DET_DELAY);
1379*4882a593Smuzhiyun break;
1380*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
1381*4882a593Smuzhiyun da7218->in_filt_en &= ~mask;
1382*4882a593Smuzhiyun break;
1383*4882a593Smuzhiyun default:
1384*4882a593Smuzhiyun return -EINVAL;
1385*4882a593Smuzhiyun }
1386*4882a593Smuzhiyun
1387*4882a593Smuzhiyun /* Enable configured level detection paths */
1388*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_LVL_DET_CTRL,
1389*4882a593Smuzhiyun (da7218->in_filt_en & da7218->mic_lvl_det_en));
1390*4882a593Smuzhiyun
1391*4882a593Smuzhiyun return 0;
1392*4882a593Smuzhiyun }
1393*4882a593Smuzhiyun
da7218_dai_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1394*4882a593Smuzhiyun static int da7218_dai_event(struct snd_soc_dapm_widget *w,
1395*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
1396*4882a593Smuzhiyun {
1397*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1398*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
1399*4882a593Smuzhiyun u8 pll_ctrl, pll_status, refosc_cal;
1400*4882a593Smuzhiyun int i;
1401*4882a593Smuzhiyun bool success;
1402*4882a593Smuzhiyun
1403*4882a593Smuzhiyun switch (event) {
1404*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
1405*4882a593Smuzhiyun if (da7218->master)
1406*4882a593Smuzhiyun /* Enable DAI clks for master mode */
1407*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DAI_CLK_MODE,
1408*4882a593Smuzhiyun DA7218_DAI_CLK_EN_MASK,
1409*4882a593Smuzhiyun DA7218_DAI_CLK_EN_MASK);
1410*4882a593Smuzhiyun
1411*4882a593Smuzhiyun /* Tune reference oscillator */
1412*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_PLL_REFOSC_CAL,
1413*4882a593Smuzhiyun DA7218_PLL_REFOSC_CAL_START_MASK);
1414*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_PLL_REFOSC_CAL,
1415*4882a593Smuzhiyun DA7218_PLL_REFOSC_CAL_START_MASK |
1416*4882a593Smuzhiyun DA7218_PLL_REFOSC_CAL_EN_MASK);
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun /* Check tuning complete */
1419*4882a593Smuzhiyun i = 0;
1420*4882a593Smuzhiyun success = false;
1421*4882a593Smuzhiyun do {
1422*4882a593Smuzhiyun refosc_cal = snd_soc_component_read(component, DA7218_PLL_REFOSC_CAL);
1423*4882a593Smuzhiyun if (!(refosc_cal & DA7218_PLL_REFOSC_CAL_START_MASK)) {
1424*4882a593Smuzhiyun success = true;
1425*4882a593Smuzhiyun } else {
1426*4882a593Smuzhiyun ++i;
1427*4882a593Smuzhiyun usleep_range(DA7218_REF_OSC_CHECK_DELAY_MIN,
1428*4882a593Smuzhiyun DA7218_REF_OSC_CHECK_DELAY_MAX);
1429*4882a593Smuzhiyun }
1430*4882a593Smuzhiyun } while ((i < DA7218_REF_OSC_CHECK_TRIES) && (!success));
1431*4882a593Smuzhiyun
1432*4882a593Smuzhiyun if (!success)
1433*4882a593Smuzhiyun dev_warn(component->dev,
1434*4882a593Smuzhiyun "Reference oscillator failed calibration\n");
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun /* PC synchronised to DAI */
1437*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_PC_COUNT,
1438*4882a593Smuzhiyun DA7218_PC_RESYNC_AUTO_MASK);
1439*4882a593Smuzhiyun
1440*4882a593Smuzhiyun /* If SRM not enabled, we don't need to check status */
1441*4882a593Smuzhiyun pll_ctrl = snd_soc_component_read(component, DA7218_PLL_CTRL);
1442*4882a593Smuzhiyun if ((pll_ctrl & DA7218_PLL_MODE_MASK) != DA7218_PLL_MODE_SRM)
1443*4882a593Smuzhiyun return 0;
1444*4882a593Smuzhiyun
1445*4882a593Smuzhiyun /* Check SRM has locked */
1446*4882a593Smuzhiyun i = 0;
1447*4882a593Smuzhiyun success = false;
1448*4882a593Smuzhiyun do {
1449*4882a593Smuzhiyun pll_status = snd_soc_component_read(component, DA7218_PLL_STATUS);
1450*4882a593Smuzhiyun if (pll_status & DA7218_PLL_SRM_STATUS_SRM_LOCK) {
1451*4882a593Smuzhiyun success = true;
1452*4882a593Smuzhiyun } else {
1453*4882a593Smuzhiyun ++i;
1454*4882a593Smuzhiyun msleep(DA7218_SRM_CHECK_DELAY);
1455*4882a593Smuzhiyun }
1456*4882a593Smuzhiyun } while ((i < DA7218_SRM_CHECK_TRIES) && (!success));
1457*4882a593Smuzhiyun
1458*4882a593Smuzhiyun if (!success)
1459*4882a593Smuzhiyun dev_warn(component->dev, "SRM failed to lock\n");
1460*4882a593Smuzhiyun
1461*4882a593Smuzhiyun return 0;
1462*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
1463*4882a593Smuzhiyun /* PC free-running */
1464*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_PC_COUNT, DA7218_PC_FREERUN_MASK);
1465*4882a593Smuzhiyun
1466*4882a593Smuzhiyun if (da7218->master)
1467*4882a593Smuzhiyun /* Disable DAI clks for master mode */
1468*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DAI_CLK_MODE,
1469*4882a593Smuzhiyun DA7218_DAI_CLK_EN_MASK, 0);
1470*4882a593Smuzhiyun
1471*4882a593Smuzhiyun return 0;
1472*4882a593Smuzhiyun default:
1473*4882a593Smuzhiyun return -EINVAL;
1474*4882a593Smuzhiyun }
1475*4882a593Smuzhiyun }
1476*4882a593Smuzhiyun
da7218_cp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1477*4882a593Smuzhiyun static int da7218_cp_event(struct snd_soc_dapm_widget *w,
1478*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
1479*4882a593Smuzhiyun {
1480*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1481*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
1482*4882a593Smuzhiyun
1483*4882a593Smuzhiyun /*
1484*4882a593Smuzhiyun * If this is DA7217 and we're using single supply for differential
1485*4882a593Smuzhiyun * output, we really don't want to touch the charge pump.
1486*4882a593Smuzhiyun */
1487*4882a593Smuzhiyun if (da7218->hp_single_supply)
1488*4882a593Smuzhiyun return 0;
1489*4882a593Smuzhiyun
1490*4882a593Smuzhiyun switch (event) {
1491*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
1492*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_CP_CTRL, DA7218_CP_EN_MASK,
1493*4882a593Smuzhiyun DA7218_CP_EN_MASK);
1494*4882a593Smuzhiyun return 0;
1495*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
1496*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_CP_CTRL, DA7218_CP_EN_MASK,
1497*4882a593Smuzhiyun 0);
1498*4882a593Smuzhiyun return 0;
1499*4882a593Smuzhiyun default:
1500*4882a593Smuzhiyun return -EINVAL;
1501*4882a593Smuzhiyun }
1502*4882a593Smuzhiyun }
1503*4882a593Smuzhiyun
da7218_hp_pga_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1504*4882a593Smuzhiyun static int da7218_hp_pga_event(struct snd_soc_dapm_widget *w,
1505*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
1506*4882a593Smuzhiyun {
1507*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun switch (event) {
1510*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
1511*4882a593Smuzhiyun /* Enable headphone output */
1512*4882a593Smuzhiyun snd_soc_component_update_bits(component, w->reg, DA7218_HP_AMP_OE_MASK,
1513*4882a593Smuzhiyun DA7218_HP_AMP_OE_MASK);
1514*4882a593Smuzhiyun return 0;
1515*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
1516*4882a593Smuzhiyun /* Headphone output high impedance */
1517*4882a593Smuzhiyun snd_soc_component_update_bits(component, w->reg, DA7218_HP_AMP_OE_MASK, 0);
1518*4882a593Smuzhiyun return 0;
1519*4882a593Smuzhiyun default:
1520*4882a593Smuzhiyun return -EINVAL;
1521*4882a593Smuzhiyun }
1522*4882a593Smuzhiyun }
1523*4882a593Smuzhiyun
1524*4882a593Smuzhiyun
1525*4882a593Smuzhiyun /*
1526*4882a593Smuzhiyun * DAPM Widgets
1527*4882a593Smuzhiyun */
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun static const struct snd_soc_dapm_widget da7218_dapm_widgets[] = {
1530*4882a593Smuzhiyun /* Input Supplies */
1531*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mic Bias1", DA7218_MICBIAS_EN,
1532*4882a593Smuzhiyun DA7218_MICBIAS_1_EN_SHIFT, DA7218_NO_INVERT,
1533*4882a593Smuzhiyun NULL, 0),
1534*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mic Bias2", DA7218_MICBIAS_EN,
1535*4882a593Smuzhiyun DA7218_MICBIAS_2_EN_SHIFT, DA7218_NO_INVERT,
1536*4882a593Smuzhiyun NULL, 0),
1537*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMic1 Left", DA7218_DMIC_1_CTRL,
1538*4882a593Smuzhiyun DA7218_DMIC_1L_EN_SHIFT, DA7218_NO_INVERT,
1539*4882a593Smuzhiyun NULL, 0),
1540*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMic1 Right", DA7218_DMIC_1_CTRL,
1541*4882a593Smuzhiyun DA7218_DMIC_1R_EN_SHIFT, DA7218_NO_INVERT,
1542*4882a593Smuzhiyun NULL, 0),
1543*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMic2 Left", DA7218_DMIC_2_CTRL,
1544*4882a593Smuzhiyun DA7218_DMIC_2L_EN_SHIFT, DA7218_NO_INVERT,
1545*4882a593Smuzhiyun NULL, 0),
1546*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DMic2 Right", DA7218_DMIC_2_CTRL,
1547*4882a593Smuzhiyun DA7218_DMIC_2R_EN_SHIFT, DA7218_NO_INVERT,
1548*4882a593Smuzhiyun NULL, 0),
1549*4882a593Smuzhiyun
1550*4882a593Smuzhiyun /* Inputs */
1551*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MIC1"),
1552*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MIC2"),
1553*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC1L"),
1554*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC1R"),
1555*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC2L"),
1556*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMIC2R"),
1557*4882a593Smuzhiyun
1558*4882a593Smuzhiyun /* Input Mixer Supplies */
1559*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mixin1 Supply", DA7218_MIXIN_1_CTRL,
1560*4882a593Smuzhiyun DA7218_MIXIN_1_MIX_SEL_SHIFT, DA7218_NO_INVERT,
1561*4882a593Smuzhiyun NULL, 0),
1562*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mixin2 Supply", DA7218_MIXIN_2_CTRL,
1563*4882a593Smuzhiyun DA7218_MIXIN_2_MIX_SEL_SHIFT, DA7218_NO_INVERT,
1564*4882a593Smuzhiyun NULL, 0),
1565*4882a593Smuzhiyun
1566*4882a593Smuzhiyun /* Input PGAs */
1567*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mic1 PGA", DA7218_MIC_1_CTRL,
1568*4882a593Smuzhiyun DA7218_MIC_1_AMP_EN_SHIFT, DA7218_NO_INVERT,
1569*4882a593Smuzhiyun NULL, 0),
1570*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mic2 PGA", DA7218_MIC_2_CTRL,
1571*4882a593Smuzhiyun DA7218_MIC_2_AMP_EN_SHIFT, DA7218_NO_INVERT,
1572*4882a593Smuzhiyun NULL, 0),
1573*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mixin1 PGA", DA7218_MIXIN_1_CTRL,
1574*4882a593Smuzhiyun DA7218_MIXIN_1_AMP_EN_SHIFT, DA7218_NO_INVERT,
1575*4882a593Smuzhiyun NULL, 0),
1576*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mixin2 PGA", DA7218_MIXIN_2_CTRL,
1577*4882a593Smuzhiyun DA7218_MIXIN_2_AMP_EN_SHIFT, DA7218_NO_INVERT,
1578*4882a593Smuzhiyun NULL, 0),
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun /* Mic/DMic Muxes */
1581*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Mic1 Mux", SND_SOC_NOPM, 0, 0, &da7218_mic1_sel_mux),
1582*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Mic2 Mux", SND_SOC_NOPM, 0, 0, &da7218_mic2_sel_mux),
1583*4882a593Smuzhiyun
1584*4882a593Smuzhiyun /* Input Filters */
1585*4882a593Smuzhiyun SND_SOC_DAPM_ADC_E("In Filter1L", NULL, DA7218_IN_1L_FILTER_CTRL,
1586*4882a593Smuzhiyun DA7218_IN_1L_FILTER_EN_SHIFT, DA7218_NO_INVERT,
1587*4882a593Smuzhiyun da7218_in_filter_event,
1588*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1589*4882a593Smuzhiyun SND_SOC_DAPM_ADC_E("In Filter1R", NULL, DA7218_IN_1R_FILTER_CTRL,
1590*4882a593Smuzhiyun DA7218_IN_1R_FILTER_EN_SHIFT, DA7218_NO_INVERT,
1591*4882a593Smuzhiyun da7218_in_filter_event,
1592*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1593*4882a593Smuzhiyun SND_SOC_DAPM_ADC_E("In Filter2L", NULL, DA7218_IN_2L_FILTER_CTRL,
1594*4882a593Smuzhiyun DA7218_IN_2L_FILTER_EN_SHIFT, DA7218_NO_INVERT,
1595*4882a593Smuzhiyun da7218_in_filter_event,
1596*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1597*4882a593Smuzhiyun SND_SOC_DAPM_ADC_E("In Filter2R", NULL, DA7218_IN_2R_FILTER_CTRL,
1598*4882a593Smuzhiyun DA7218_IN_2R_FILTER_EN_SHIFT, DA7218_NO_INVERT,
1599*4882a593Smuzhiyun da7218_in_filter_event,
1600*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1601*4882a593Smuzhiyun
1602*4882a593Smuzhiyun /* Tone Generator */
1603*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("TONE"),
1604*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator", DA7218_TONE_GEN_CFG1,
1605*4882a593Smuzhiyun DA7218_START_STOPN_SHIFT, DA7218_NO_INVERT, NULL, 0),
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun /* Sidetone Input */
1608*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
1609*4882a593Smuzhiyun &da7218_sidetone_in_sel_mux),
1610*4882a593Smuzhiyun SND_SOC_DAPM_ADC("Sidetone Filter", NULL, DA7218_SIDETONE_CTRL,
1611*4882a593Smuzhiyun DA7218_SIDETONE_FILTER_EN_SHIFT, DA7218_NO_INVERT),
1612*4882a593Smuzhiyun
1613*4882a593Smuzhiyun /* Input Mixers */
1614*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixer DAI1L", SND_SOC_NOPM, 0, 0,
1615*4882a593Smuzhiyun da7218_out_dai1l_mix_controls,
1616*4882a593Smuzhiyun ARRAY_SIZE(da7218_out_dai1l_mix_controls)),
1617*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixer DAI1R", SND_SOC_NOPM, 0, 0,
1618*4882a593Smuzhiyun da7218_out_dai1r_mix_controls,
1619*4882a593Smuzhiyun ARRAY_SIZE(da7218_out_dai1r_mix_controls)),
1620*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixer DAI2L", SND_SOC_NOPM, 0, 0,
1621*4882a593Smuzhiyun da7218_out_dai2l_mix_controls,
1622*4882a593Smuzhiyun ARRAY_SIZE(da7218_out_dai2l_mix_controls)),
1623*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixer DAI2R", SND_SOC_NOPM, 0, 0,
1624*4882a593Smuzhiyun da7218_out_dai2r_mix_controls,
1625*4882a593Smuzhiyun ARRAY_SIZE(da7218_out_dai2r_mix_controls)),
1626*4882a593Smuzhiyun
1627*4882a593Smuzhiyun /* DAI Supply */
1628*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DAI", DA7218_DAI_CTRL, DA7218_DAI_EN_SHIFT,
1629*4882a593Smuzhiyun DA7218_NO_INVERT, da7218_dai_event,
1630*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1631*4882a593Smuzhiyun
1632*4882a593Smuzhiyun /* DAI */
1633*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("DAIOUT", "Capture", 0, DA7218_DAI_TDM_CTRL,
1634*4882a593Smuzhiyun DA7218_DAI_OE_SHIFT, DA7218_NO_INVERT),
1635*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("DAIIN", "Playback", 0, SND_SOC_NOPM, 0, 0),
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun /* Output Mixers */
1638*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixer Out FilterL", SND_SOC_NOPM, 0, 0,
1639*4882a593Smuzhiyun da7218_out_filtl_mix_controls,
1640*4882a593Smuzhiyun ARRAY_SIZE(da7218_out_filtl_mix_controls)),
1641*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixer Out FilterR", SND_SOC_NOPM, 0, 0,
1642*4882a593Smuzhiyun da7218_out_filtr_mix_controls,
1643*4882a593Smuzhiyun ARRAY_SIZE(da7218_out_filtr_mix_controls)),
1644*4882a593Smuzhiyun
1645*4882a593Smuzhiyun /* BiQuad Filters */
1646*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Out FilterL BiQuad Mux", SND_SOC_NOPM, 0, 0,
1647*4882a593Smuzhiyun &da7218_out_filtl_biq_sel_mux),
1648*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Out FilterR BiQuad Mux", SND_SOC_NOPM, 0, 0,
1649*4882a593Smuzhiyun &da7218_out_filtr_biq_sel_mux),
1650*4882a593Smuzhiyun SND_SOC_DAPM_DAC("BiQuad Filter", NULL, DA7218_OUT_1_BIQ_5STAGE_CTRL,
1651*4882a593Smuzhiyun DA7218_OUT_1_BIQ_5STAGE_FILTER_EN_SHIFT,
1652*4882a593Smuzhiyun DA7218_NO_INVERT),
1653*4882a593Smuzhiyun
1654*4882a593Smuzhiyun /* Sidetone Mixers */
1655*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("ST Mixer Out FilterL", SND_SOC_NOPM, 0, 0,
1656*4882a593Smuzhiyun da7218_st_out_filtl_mix_controls,
1657*4882a593Smuzhiyun ARRAY_SIZE(da7218_st_out_filtl_mix_controls)),
1658*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("ST Mixer Out FilterR", SND_SOC_NOPM, 0, 0,
1659*4882a593Smuzhiyun da7218_st_out_filtr_mix_controls,
1660*4882a593Smuzhiyun ARRAY_SIZE(da7218_st_out_filtr_mix_controls)),
1661*4882a593Smuzhiyun
1662*4882a593Smuzhiyun /* Output Filters */
1663*4882a593Smuzhiyun SND_SOC_DAPM_DAC("Out FilterL", NULL, DA7218_OUT_1L_FILTER_CTRL,
1664*4882a593Smuzhiyun DA7218_OUT_1L_FILTER_EN_SHIFT, DA7218_NO_INVERT),
1665*4882a593Smuzhiyun SND_SOC_DAPM_DAC("Out FilterR", NULL, DA7218_OUT_1R_FILTER_CTRL,
1666*4882a593Smuzhiyun DA7218_IN_1R_FILTER_EN_SHIFT, DA7218_NO_INVERT),
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun /* Output PGAs */
1669*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mixout Left PGA", DA7218_MIXOUT_L_CTRL,
1670*4882a593Smuzhiyun DA7218_MIXOUT_L_AMP_EN_SHIFT, DA7218_NO_INVERT,
1671*4882a593Smuzhiyun NULL, 0),
1672*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mixout Right PGA", DA7218_MIXOUT_R_CTRL,
1673*4882a593Smuzhiyun DA7218_MIXOUT_R_AMP_EN_SHIFT, DA7218_NO_INVERT,
1674*4882a593Smuzhiyun NULL, 0),
1675*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("Headphone Left PGA", DA7218_HP_L_CTRL,
1676*4882a593Smuzhiyun DA7218_HP_L_AMP_EN_SHIFT, DA7218_NO_INVERT, NULL, 0,
1677*4882a593Smuzhiyun da7218_hp_pga_event,
1678*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1679*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("Headphone Right PGA", DA7218_HP_R_CTRL,
1680*4882a593Smuzhiyun DA7218_HP_R_AMP_EN_SHIFT, DA7218_NO_INVERT, NULL, 0,
1681*4882a593Smuzhiyun da7218_hp_pga_event,
1682*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1683*4882a593Smuzhiyun
1684*4882a593Smuzhiyun /* Output Supplies */
1685*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0, da7218_cp_event,
1686*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1687*4882a593Smuzhiyun
1688*4882a593Smuzhiyun /* Outputs */
1689*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPL"),
1690*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPR"),
1691*4882a593Smuzhiyun };
1692*4882a593Smuzhiyun
1693*4882a593Smuzhiyun
1694*4882a593Smuzhiyun /*
1695*4882a593Smuzhiyun * DAPM Mixer Routes
1696*4882a593Smuzhiyun */
1697*4882a593Smuzhiyun
1698*4882a593Smuzhiyun #define DA7218_DMIX_ROUTES(name) \
1699*4882a593Smuzhiyun {name, "In Filter1L Switch", "In Filter1L"}, \
1700*4882a593Smuzhiyun {name, "In Filter1R Switch", "In Filter1R"}, \
1701*4882a593Smuzhiyun {name, "In Filter2L Switch", "In Filter2L"}, \
1702*4882a593Smuzhiyun {name, "In Filter2R Switch", "In Filter2R"}, \
1703*4882a593Smuzhiyun {name, "ToneGen Switch", "Tone Generator"}, \
1704*4882a593Smuzhiyun {name, "DAIL Switch", "DAIIN"}, \
1705*4882a593Smuzhiyun {name, "DAIR Switch", "DAIIN"}
1706*4882a593Smuzhiyun
1707*4882a593Smuzhiyun #define DA7218_DMIX_ST_ROUTES(name) \
1708*4882a593Smuzhiyun {name, "Out FilterL Switch", "Out FilterL BiQuad Mux"}, \
1709*4882a593Smuzhiyun {name, "Out FilterR Switch", "Out FilterR BiQuad Mux"}, \
1710*4882a593Smuzhiyun {name, "Sidetone Switch", "Sidetone Filter"}
1711*4882a593Smuzhiyun
1712*4882a593Smuzhiyun
1713*4882a593Smuzhiyun /*
1714*4882a593Smuzhiyun * DAPM audio route definition
1715*4882a593Smuzhiyun */
1716*4882a593Smuzhiyun
1717*4882a593Smuzhiyun static const struct snd_soc_dapm_route da7218_audio_map[] = {
1718*4882a593Smuzhiyun /* Input paths */
1719*4882a593Smuzhiyun {"MIC1", NULL, "Mic Bias1"},
1720*4882a593Smuzhiyun {"MIC2", NULL, "Mic Bias2"},
1721*4882a593Smuzhiyun {"DMIC1L", NULL, "Mic Bias1"},
1722*4882a593Smuzhiyun {"DMIC1L", NULL, "DMic1 Left"},
1723*4882a593Smuzhiyun {"DMIC1R", NULL, "Mic Bias1"},
1724*4882a593Smuzhiyun {"DMIC1R", NULL, "DMic1 Right"},
1725*4882a593Smuzhiyun {"DMIC2L", NULL, "Mic Bias2"},
1726*4882a593Smuzhiyun {"DMIC2L", NULL, "DMic2 Left"},
1727*4882a593Smuzhiyun {"DMIC2R", NULL, "Mic Bias2"},
1728*4882a593Smuzhiyun {"DMIC2R", NULL, "DMic2 Right"},
1729*4882a593Smuzhiyun
1730*4882a593Smuzhiyun {"Mic1 PGA", NULL, "MIC1"},
1731*4882a593Smuzhiyun {"Mic2 PGA", NULL, "MIC2"},
1732*4882a593Smuzhiyun
1733*4882a593Smuzhiyun {"Mixin1 PGA", NULL, "Mixin1 Supply"},
1734*4882a593Smuzhiyun {"Mixin2 PGA", NULL, "Mixin2 Supply"},
1735*4882a593Smuzhiyun
1736*4882a593Smuzhiyun {"Mixin1 PGA", NULL, "Mic1 PGA"},
1737*4882a593Smuzhiyun {"Mixin2 PGA", NULL, "Mic2 PGA"},
1738*4882a593Smuzhiyun
1739*4882a593Smuzhiyun {"Mic1 Mux", "Analog", "Mixin1 PGA"},
1740*4882a593Smuzhiyun {"Mic1 Mux", "Digital", "DMIC1L"},
1741*4882a593Smuzhiyun {"Mic1 Mux", "Digital", "DMIC1R"},
1742*4882a593Smuzhiyun {"Mic2 Mux", "Analog", "Mixin2 PGA"},
1743*4882a593Smuzhiyun {"Mic2 Mux", "Digital", "DMIC2L"},
1744*4882a593Smuzhiyun {"Mic2 Mux", "Digital", "DMIC2R"},
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun {"In Filter1L", NULL, "Mic1 Mux"},
1747*4882a593Smuzhiyun {"In Filter1R", NULL, "Mic1 Mux"},
1748*4882a593Smuzhiyun {"In Filter2L", NULL, "Mic2 Mux"},
1749*4882a593Smuzhiyun {"In Filter2R", NULL, "Mic2 Mux"},
1750*4882a593Smuzhiyun
1751*4882a593Smuzhiyun {"Tone Generator", NULL, "TONE"},
1752*4882a593Smuzhiyun
1753*4882a593Smuzhiyun {"Sidetone Mux", "In Filter1L", "In Filter1L"},
1754*4882a593Smuzhiyun {"Sidetone Mux", "In Filter1R", "In Filter1R"},
1755*4882a593Smuzhiyun {"Sidetone Mux", "In Filter2L", "In Filter2L"},
1756*4882a593Smuzhiyun {"Sidetone Mux", "In Filter2R", "In Filter2R"},
1757*4882a593Smuzhiyun {"Sidetone Filter", NULL, "Sidetone Mux"},
1758*4882a593Smuzhiyun
1759*4882a593Smuzhiyun DA7218_DMIX_ROUTES("Mixer DAI1L"),
1760*4882a593Smuzhiyun DA7218_DMIX_ROUTES("Mixer DAI1R"),
1761*4882a593Smuzhiyun DA7218_DMIX_ROUTES("Mixer DAI2L"),
1762*4882a593Smuzhiyun DA7218_DMIX_ROUTES("Mixer DAI2R"),
1763*4882a593Smuzhiyun
1764*4882a593Smuzhiyun {"DAIOUT", NULL, "Mixer DAI1L"},
1765*4882a593Smuzhiyun {"DAIOUT", NULL, "Mixer DAI1R"},
1766*4882a593Smuzhiyun {"DAIOUT", NULL, "Mixer DAI2L"},
1767*4882a593Smuzhiyun {"DAIOUT", NULL, "Mixer DAI2R"},
1768*4882a593Smuzhiyun
1769*4882a593Smuzhiyun {"DAIOUT", NULL, "DAI"},
1770*4882a593Smuzhiyun
1771*4882a593Smuzhiyun /* Output paths */
1772*4882a593Smuzhiyun {"DAIIN", NULL, "DAI"},
1773*4882a593Smuzhiyun
1774*4882a593Smuzhiyun DA7218_DMIX_ROUTES("Mixer Out FilterL"),
1775*4882a593Smuzhiyun DA7218_DMIX_ROUTES("Mixer Out FilterR"),
1776*4882a593Smuzhiyun
1777*4882a593Smuzhiyun {"BiQuad Filter", NULL, "Mixer Out FilterL"},
1778*4882a593Smuzhiyun {"BiQuad Filter", NULL, "Mixer Out FilterR"},
1779*4882a593Smuzhiyun
1780*4882a593Smuzhiyun {"Out FilterL BiQuad Mux", "Bypass", "Mixer Out FilterL"},
1781*4882a593Smuzhiyun {"Out FilterL BiQuad Mux", "Enabled", "BiQuad Filter"},
1782*4882a593Smuzhiyun {"Out FilterR BiQuad Mux", "Bypass", "Mixer Out FilterR"},
1783*4882a593Smuzhiyun {"Out FilterR BiQuad Mux", "Enabled", "BiQuad Filter"},
1784*4882a593Smuzhiyun
1785*4882a593Smuzhiyun DA7218_DMIX_ST_ROUTES("ST Mixer Out FilterL"),
1786*4882a593Smuzhiyun DA7218_DMIX_ST_ROUTES("ST Mixer Out FilterR"),
1787*4882a593Smuzhiyun
1788*4882a593Smuzhiyun {"Out FilterL", NULL, "ST Mixer Out FilterL"},
1789*4882a593Smuzhiyun {"Out FilterR", NULL, "ST Mixer Out FilterR"},
1790*4882a593Smuzhiyun
1791*4882a593Smuzhiyun {"Mixout Left PGA", NULL, "Out FilterL"},
1792*4882a593Smuzhiyun {"Mixout Right PGA", NULL, "Out FilterR"},
1793*4882a593Smuzhiyun
1794*4882a593Smuzhiyun {"Headphone Left PGA", NULL, "Mixout Left PGA"},
1795*4882a593Smuzhiyun {"Headphone Right PGA", NULL, "Mixout Right PGA"},
1796*4882a593Smuzhiyun
1797*4882a593Smuzhiyun {"HPL", NULL, "Headphone Left PGA"},
1798*4882a593Smuzhiyun {"HPR", NULL, "Headphone Right PGA"},
1799*4882a593Smuzhiyun
1800*4882a593Smuzhiyun {"HPL", NULL, "Charge Pump"},
1801*4882a593Smuzhiyun {"HPR", NULL, "Charge Pump"},
1802*4882a593Smuzhiyun };
1803*4882a593Smuzhiyun
1804*4882a593Smuzhiyun
1805*4882a593Smuzhiyun /*
1806*4882a593Smuzhiyun * DAI operations
1807*4882a593Smuzhiyun */
1808*4882a593Smuzhiyun
da7218_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)1809*4882a593Smuzhiyun static int da7218_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1810*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
1811*4882a593Smuzhiyun {
1812*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
1813*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
1814*4882a593Smuzhiyun int ret;
1815*4882a593Smuzhiyun
1816*4882a593Smuzhiyun if (da7218->mclk_rate == freq)
1817*4882a593Smuzhiyun return 0;
1818*4882a593Smuzhiyun
1819*4882a593Smuzhiyun if ((freq < 2000000) || (freq > 54000000)) {
1820*4882a593Smuzhiyun dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
1821*4882a593Smuzhiyun freq);
1822*4882a593Smuzhiyun return -EINVAL;
1823*4882a593Smuzhiyun }
1824*4882a593Smuzhiyun
1825*4882a593Smuzhiyun switch (clk_id) {
1826*4882a593Smuzhiyun case DA7218_CLKSRC_MCLK_SQR:
1827*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_PLL_CTRL,
1828*4882a593Smuzhiyun DA7218_PLL_MCLK_SQR_EN_MASK,
1829*4882a593Smuzhiyun DA7218_PLL_MCLK_SQR_EN_MASK);
1830*4882a593Smuzhiyun break;
1831*4882a593Smuzhiyun case DA7218_CLKSRC_MCLK:
1832*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_PLL_CTRL,
1833*4882a593Smuzhiyun DA7218_PLL_MCLK_SQR_EN_MASK, 0);
1834*4882a593Smuzhiyun break;
1835*4882a593Smuzhiyun default:
1836*4882a593Smuzhiyun dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
1837*4882a593Smuzhiyun return -EINVAL;
1838*4882a593Smuzhiyun }
1839*4882a593Smuzhiyun
1840*4882a593Smuzhiyun if (da7218->mclk) {
1841*4882a593Smuzhiyun freq = clk_round_rate(da7218->mclk, freq);
1842*4882a593Smuzhiyun ret = clk_set_rate(da7218->mclk, freq);
1843*4882a593Smuzhiyun if (ret) {
1844*4882a593Smuzhiyun dev_err(codec_dai->dev, "Failed to set clock rate %d\n",
1845*4882a593Smuzhiyun freq);
1846*4882a593Smuzhiyun return ret;
1847*4882a593Smuzhiyun }
1848*4882a593Smuzhiyun }
1849*4882a593Smuzhiyun
1850*4882a593Smuzhiyun da7218->mclk_rate = freq;
1851*4882a593Smuzhiyun
1852*4882a593Smuzhiyun return 0;
1853*4882a593Smuzhiyun }
1854*4882a593Smuzhiyun
da7218_set_dai_pll(struct snd_soc_dai * codec_dai,int pll_id,int source,unsigned int fref,unsigned int fout)1855*4882a593Smuzhiyun static int da7218_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1856*4882a593Smuzhiyun int source, unsigned int fref, unsigned int fout)
1857*4882a593Smuzhiyun {
1858*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
1859*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
1860*4882a593Smuzhiyun
1861*4882a593Smuzhiyun u8 pll_ctrl, indiv_bits, indiv;
1862*4882a593Smuzhiyun u8 pll_frac_top, pll_frac_bot, pll_integer;
1863*4882a593Smuzhiyun u32 freq_ref;
1864*4882a593Smuzhiyun u64 frac_div;
1865*4882a593Smuzhiyun
1866*4882a593Smuzhiyun /* Verify 2MHz - 54MHz MCLK provided, and set input divider */
1867*4882a593Smuzhiyun if (da7218->mclk_rate < 2000000) {
1868*4882a593Smuzhiyun dev_err(component->dev, "PLL input clock %d below valid range\n",
1869*4882a593Smuzhiyun da7218->mclk_rate);
1870*4882a593Smuzhiyun return -EINVAL;
1871*4882a593Smuzhiyun } else if (da7218->mclk_rate <= 4500000) {
1872*4882a593Smuzhiyun indiv_bits = DA7218_PLL_INDIV_2_TO_4_5_MHZ;
1873*4882a593Smuzhiyun indiv = DA7218_PLL_INDIV_2_TO_4_5_MHZ_VAL;
1874*4882a593Smuzhiyun } else if (da7218->mclk_rate <= 9000000) {
1875*4882a593Smuzhiyun indiv_bits = DA7218_PLL_INDIV_4_5_TO_9_MHZ;
1876*4882a593Smuzhiyun indiv = DA7218_PLL_INDIV_4_5_TO_9_MHZ_VAL;
1877*4882a593Smuzhiyun } else if (da7218->mclk_rate <= 18000000) {
1878*4882a593Smuzhiyun indiv_bits = DA7218_PLL_INDIV_9_TO_18_MHZ;
1879*4882a593Smuzhiyun indiv = DA7218_PLL_INDIV_9_TO_18_MHZ_VAL;
1880*4882a593Smuzhiyun } else if (da7218->mclk_rate <= 36000000) {
1881*4882a593Smuzhiyun indiv_bits = DA7218_PLL_INDIV_18_TO_36_MHZ;
1882*4882a593Smuzhiyun indiv = DA7218_PLL_INDIV_18_TO_36_MHZ_VAL;
1883*4882a593Smuzhiyun } else if (da7218->mclk_rate <= 54000000) {
1884*4882a593Smuzhiyun indiv_bits = DA7218_PLL_INDIV_36_TO_54_MHZ;
1885*4882a593Smuzhiyun indiv = DA7218_PLL_INDIV_36_TO_54_MHZ_VAL;
1886*4882a593Smuzhiyun } else {
1887*4882a593Smuzhiyun dev_err(component->dev, "PLL input clock %d above valid range\n",
1888*4882a593Smuzhiyun da7218->mclk_rate);
1889*4882a593Smuzhiyun return -EINVAL;
1890*4882a593Smuzhiyun }
1891*4882a593Smuzhiyun freq_ref = (da7218->mclk_rate / indiv);
1892*4882a593Smuzhiyun pll_ctrl = indiv_bits;
1893*4882a593Smuzhiyun
1894*4882a593Smuzhiyun /* Configure PLL */
1895*4882a593Smuzhiyun switch (source) {
1896*4882a593Smuzhiyun case DA7218_SYSCLK_MCLK:
1897*4882a593Smuzhiyun pll_ctrl |= DA7218_PLL_MODE_BYPASS;
1898*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_PLL_CTRL,
1899*4882a593Smuzhiyun DA7218_PLL_INDIV_MASK |
1900*4882a593Smuzhiyun DA7218_PLL_MODE_MASK, pll_ctrl);
1901*4882a593Smuzhiyun return 0;
1902*4882a593Smuzhiyun case DA7218_SYSCLK_PLL:
1903*4882a593Smuzhiyun pll_ctrl |= DA7218_PLL_MODE_NORMAL;
1904*4882a593Smuzhiyun break;
1905*4882a593Smuzhiyun case DA7218_SYSCLK_PLL_SRM:
1906*4882a593Smuzhiyun pll_ctrl |= DA7218_PLL_MODE_SRM;
1907*4882a593Smuzhiyun break;
1908*4882a593Smuzhiyun default:
1909*4882a593Smuzhiyun dev_err(component->dev, "Invalid PLL config\n");
1910*4882a593Smuzhiyun return -EINVAL;
1911*4882a593Smuzhiyun }
1912*4882a593Smuzhiyun
1913*4882a593Smuzhiyun /* Calculate dividers for PLL */
1914*4882a593Smuzhiyun pll_integer = fout / freq_ref;
1915*4882a593Smuzhiyun frac_div = (u64)(fout % freq_ref) * 8192ULL;
1916*4882a593Smuzhiyun do_div(frac_div, freq_ref);
1917*4882a593Smuzhiyun pll_frac_top = (frac_div >> DA7218_BYTE_SHIFT) & DA7218_BYTE_MASK;
1918*4882a593Smuzhiyun pll_frac_bot = (frac_div) & DA7218_BYTE_MASK;
1919*4882a593Smuzhiyun
1920*4882a593Smuzhiyun /* Write PLL config & dividers */
1921*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_PLL_FRAC_TOP, pll_frac_top);
1922*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_PLL_FRAC_BOT, pll_frac_bot);
1923*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_PLL_INTEGER, pll_integer);
1924*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_PLL_CTRL,
1925*4882a593Smuzhiyun DA7218_PLL_MODE_MASK | DA7218_PLL_INDIV_MASK,
1926*4882a593Smuzhiyun pll_ctrl);
1927*4882a593Smuzhiyun
1928*4882a593Smuzhiyun return 0;
1929*4882a593Smuzhiyun }
1930*4882a593Smuzhiyun
da7218_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1931*4882a593Smuzhiyun static int da7218_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1932*4882a593Smuzhiyun {
1933*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
1934*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
1935*4882a593Smuzhiyun u8 dai_clk_mode = 0, dai_ctrl = 0;
1936*4882a593Smuzhiyun
1937*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1938*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
1939*4882a593Smuzhiyun da7218->master = true;
1940*4882a593Smuzhiyun break;
1941*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
1942*4882a593Smuzhiyun da7218->master = false;
1943*4882a593Smuzhiyun break;
1944*4882a593Smuzhiyun default:
1945*4882a593Smuzhiyun return -EINVAL;
1946*4882a593Smuzhiyun }
1947*4882a593Smuzhiyun
1948*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1949*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
1950*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
1951*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
1952*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1953*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
1954*4882a593Smuzhiyun break;
1955*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
1956*4882a593Smuzhiyun dai_clk_mode |= DA7218_DAI_WCLK_POL_INV;
1957*4882a593Smuzhiyun break;
1958*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
1959*4882a593Smuzhiyun dai_clk_mode |= DA7218_DAI_CLK_POL_INV;
1960*4882a593Smuzhiyun break;
1961*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
1962*4882a593Smuzhiyun dai_clk_mode |= DA7218_DAI_WCLK_POL_INV |
1963*4882a593Smuzhiyun DA7218_DAI_CLK_POL_INV;
1964*4882a593Smuzhiyun break;
1965*4882a593Smuzhiyun default:
1966*4882a593Smuzhiyun return -EINVAL;
1967*4882a593Smuzhiyun }
1968*4882a593Smuzhiyun break;
1969*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
1970*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1971*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
1972*4882a593Smuzhiyun dai_clk_mode |= DA7218_DAI_CLK_POL_INV;
1973*4882a593Smuzhiyun break;
1974*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
1975*4882a593Smuzhiyun dai_clk_mode |= DA7218_DAI_WCLK_POL_INV |
1976*4882a593Smuzhiyun DA7218_DAI_CLK_POL_INV;
1977*4882a593Smuzhiyun break;
1978*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
1979*4882a593Smuzhiyun break;
1980*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
1981*4882a593Smuzhiyun dai_clk_mode |= DA7218_DAI_WCLK_POL_INV;
1982*4882a593Smuzhiyun break;
1983*4882a593Smuzhiyun default:
1984*4882a593Smuzhiyun return -EINVAL;
1985*4882a593Smuzhiyun }
1986*4882a593Smuzhiyun break;
1987*4882a593Smuzhiyun default:
1988*4882a593Smuzhiyun return -EINVAL;
1989*4882a593Smuzhiyun }
1990*4882a593Smuzhiyun
1991*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1992*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
1993*4882a593Smuzhiyun dai_ctrl |= DA7218_DAI_FORMAT_I2S;
1994*4882a593Smuzhiyun break;
1995*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
1996*4882a593Smuzhiyun dai_ctrl |= DA7218_DAI_FORMAT_LEFT_J;
1997*4882a593Smuzhiyun break;
1998*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
1999*4882a593Smuzhiyun dai_ctrl |= DA7218_DAI_FORMAT_RIGHT_J;
2000*4882a593Smuzhiyun break;
2001*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
2002*4882a593Smuzhiyun dai_ctrl |= DA7218_DAI_FORMAT_DSP;
2003*4882a593Smuzhiyun break;
2004*4882a593Smuzhiyun default:
2005*4882a593Smuzhiyun return -EINVAL;
2006*4882a593Smuzhiyun }
2007*4882a593Smuzhiyun
2008*4882a593Smuzhiyun /* By default 64 BCLKs per WCLK is supported */
2009*4882a593Smuzhiyun dai_clk_mode |= DA7218_DAI_BCLKS_PER_WCLK_64;
2010*4882a593Smuzhiyun
2011*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_DAI_CLK_MODE, dai_clk_mode);
2012*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DAI_CTRL, DA7218_DAI_FORMAT_MASK,
2013*4882a593Smuzhiyun dai_ctrl);
2014*4882a593Smuzhiyun
2015*4882a593Smuzhiyun return 0;
2016*4882a593Smuzhiyun }
2017*4882a593Smuzhiyun
da7218_set_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)2018*4882a593Smuzhiyun static int da7218_set_dai_tdm_slot(struct snd_soc_dai *dai,
2019*4882a593Smuzhiyun unsigned int tx_mask, unsigned int rx_mask,
2020*4882a593Smuzhiyun int slots, int slot_width)
2021*4882a593Smuzhiyun {
2022*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
2023*4882a593Smuzhiyun u8 dai_bclks_per_wclk;
2024*4882a593Smuzhiyun u32 frame_size;
2025*4882a593Smuzhiyun
2026*4882a593Smuzhiyun /* No channels enabled so disable TDM, revert to 64-bit frames */
2027*4882a593Smuzhiyun if (!tx_mask) {
2028*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DAI_TDM_CTRL,
2029*4882a593Smuzhiyun DA7218_DAI_TDM_CH_EN_MASK |
2030*4882a593Smuzhiyun DA7218_DAI_TDM_MODE_EN_MASK, 0);
2031*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DAI_CLK_MODE,
2032*4882a593Smuzhiyun DA7218_DAI_BCLKS_PER_WCLK_MASK,
2033*4882a593Smuzhiyun DA7218_DAI_BCLKS_PER_WCLK_64);
2034*4882a593Smuzhiyun return 0;
2035*4882a593Smuzhiyun }
2036*4882a593Smuzhiyun
2037*4882a593Smuzhiyun /* Check we have valid slots */
2038*4882a593Smuzhiyun if (fls(tx_mask) > DA7218_DAI_TDM_MAX_SLOTS) {
2039*4882a593Smuzhiyun dev_err(component->dev, "Invalid number of slots, max = %d\n",
2040*4882a593Smuzhiyun DA7218_DAI_TDM_MAX_SLOTS);
2041*4882a593Smuzhiyun return -EINVAL;
2042*4882a593Smuzhiyun }
2043*4882a593Smuzhiyun
2044*4882a593Smuzhiyun /* Check we have a valid offset given (first 2 bytes of rx_mask) */
2045*4882a593Smuzhiyun if (rx_mask >> DA7218_2BYTE_SHIFT) {
2046*4882a593Smuzhiyun dev_err(component->dev, "Invalid slot offset, max = %d\n",
2047*4882a593Smuzhiyun DA7218_2BYTE_MASK);
2048*4882a593Smuzhiyun return -EINVAL;
2049*4882a593Smuzhiyun }
2050*4882a593Smuzhiyun
2051*4882a593Smuzhiyun /* Calculate & validate frame size based on slot info provided. */
2052*4882a593Smuzhiyun frame_size = slots * slot_width;
2053*4882a593Smuzhiyun switch (frame_size) {
2054*4882a593Smuzhiyun case 32:
2055*4882a593Smuzhiyun dai_bclks_per_wclk = DA7218_DAI_BCLKS_PER_WCLK_32;
2056*4882a593Smuzhiyun break;
2057*4882a593Smuzhiyun case 64:
2058*4882a593Smuzhiyun dai_bclks_per_wclk = DA7218_DAI_BCLKS_PER_WCLK_64;
2059*4882a593Smuzhiyun break;
2060*4882a593Smuzhiyun case 128:
2061*4882a593Smuzhiyun dai_bclks_per_wclk = DA7218_DAI_BCLKS_PER_WCLK_128;
2062*4882a593Smuzhiyun break;
2063*4882a593Smuzhiyun case 256:
2064*4882a593Smuzhiyun dai_bclks_per_wclk = DA7218_DAI_BCLKS_PER_WCLK_256;
2065*4882a593Smuzhiyun break;
2066*4882a593Smuzhiyun default:
2067*4882a593Smuzhiyun dev_err(component->dev, "Invalid frame size\n");
2068*4882a593Smuzhiyun return -EINVAL;
2069*4882a593Smuzhiyun }
2070*4882a593Smuzhiyun
2071*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DAI_CLK_MODE,
2072*4882a593Smuzhiyun DA7218_DAI_BCLKS_PER_WCLK_MASK,
2073*4882a593Smuzhiyun dai_bclks_per_wclk);
2074*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_DAI_OFFSET_LOWER,
2075*4882a593Smuzhiyun (rx_mask & DA7218_BYTE_MASK));
2076*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_DAI_OFFSET_UPPER,
2077*4882a593Smuzhiyun ((rx_mask >> DA7218_BYTE_SHIFT) & DA7218_BYTE_MASK));
2078*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DAI_TDM_CTRL,
2079*4882a593Smuzhiyun DA7218_DAI_TDM_CH_EN_MASK |
2080*4882a593Smuzhiyun DA7218_DAI_TDM_MODE_EN_MASK,
2081*4882a593Smuzhiyun (tx_mask << DA7218_DAI_TDM_CH_EN_SHIFT) |
2082*4882a593Smuzhiyun DA7218_DAI_TDM_MODE_EN_MASK);
2083*4882a593Smuzhiyun
2084*4882a593Smuzhiyun return 0;
2085*4882a593Smuzhiyun }
2086*4882a593Smuzhiyun
da7218_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2087*4882a593Smuzhiyun static int da7218_hw_params(struct snd_pcm_substream *substream,
2088*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
2089*4882a593Smuzhiyun struct snd_soc_dai *dai)
2090*4882a593Smuzhiyun {
2091*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
2092*4882a593Smuzhiyun u8 dai_ctrl = 0, fs;
2093*4882a593Smuzhiyun unsigned int channels;
2094*4882a593Smuzhiyun
2095*4882a593Smuzhiyun switch (params_width(params)) {
2096*4882a593Smuzhiyun case 16:
2097*4882a593Smuzhiyun dai_ctrl |= DA7218_DAI_WORD_LENGTH_S16_LE;
2098*4882a593Smuzhiyun break;
2099*4882a593Smuzhiyun case 20:
2100*4882a593Smuzhiyun dai_ctrl |= DA7218_DAI_WORD_LENGTH_S20_LE;
2101*4882a593Smuzhiyun break;
2102*4882a593Smuzhiyun case 24:
2103*4882a593Smuzhiyun dai_ctrl |= DA7218_DAI_WORD_LENGTH_S24_LE;
2104*4882a593Smuzhiyun break;
2105*4882a593Smuzhiyun case 32:
2106*4882a593Smuzhiyun dai_ctrl |= DA7218_DAI_WORD_LENGTH_S32_LE;
2107*4882a593Smuzhiyun break;
2108*4882a593Smuzhiyun default:
2109*4882a593Smuzhiyun return -EINVAL;
2110*4882a593Smuzhiyun }
2111*4882a593Smuzhiyun
2112*4882a593Smuzhiyun channels = params_channels(params);
2113*4882a593Smuzhiyun if ((channels < 1) || (channels > DA7218_DAI_CH_NUM_MAX)) {
2114*4882a593Smuzhiyun dev_err(component->dev,
2115*4882a593Smuzhiyun "Invalid number of channels, only 1 to %d supported\n",
2116*4882a593Smuzhiyun DA7218_DAI_CH_NUM_MAX);
2117*4882a593Smuzhiyun return -EINVAL;
2118*4882a593Smuzhiyun }
2119*4882a593Smuzhiyun dai_ctrl |= channels << DA7218_DAI_CH_NUM_SHIFT;
2120*4882a593Smuzhiyun
2121*4882a593Smuzhiyun switch (params_rate(params)) {
2122*4882a593Smuzhiyun case 8000:
2123*4882a593Smuzhiyun fs = DA7218_SR_8000;
2124*4882a593Smuzhiyun break;
2125*4882a593Smuzhiyun case 11025:
2126*4882a593Smuzhiyun fs = DA7218_SR_11025;
2127*4882a593Smuzhiyun break;
2128*4882a593Smuzhiyun case 12000:
2129*4882a593Smuzhiyun fs = DA7218_SR_12000;
2130*4882a593Smuzhiyun break;
2131*4882a593Smuzhiyun case 16000:
2132*4882a593Smuzhiyun fs = DA7218_SR_16000;
2133*4882a593Smuzhiyun break;
2134*4882a593Smuzhiyun case 22050:
2135*4882a593Smuzhiyun fs = DA7218_SR_22050;
2136*4882a593Smuzhiyun break;
2137*4882a593Smuzhiyun case 24000:
2138*4882a593Smuzhiyun fs = DA7218_SR_24000;
2139*4882a593Smuzhiyun break;
2140*4882a593Smuzhiyun case 32000:
2141*4882a593Smuzhiyun fs = DA7218_SR_32000;
2142*4882a593Smuzhiyun break;
2143*4882a593Smuzhiyun case 44100:
2144*4882a593Smuzhiyun fs = DA7218_SR_44100;
2145*4882a593Smuzhiyun break;
2146*4882a593Smuzhiyun case 48000:
2147*4882a593Smuzhiyun fs = DA7218_SR_48000;
2148*4882a593Smuzhiyun break;
2149*4882a593Smuzhiyun case 88200:
2150*4882a593Smuzhiyun fs = DA7218_SR_88200;
2151*4882a593Smuzhiyun break;
2152*4882a593Smuzhiyun case 96000:
2153*4882a593Smuzhiyun fs = DA7218_SR_96000;
2154*4882a593Smuzhiyun break;
2155*4882a593Smuzhiyun default:
2156*4882a593Smuzhiyun return -EINVAL;
2157*4882a593Smuzhiyun }
2158*4882a593Smuzhiyun
2159*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DAI_CTRL,
2160*4882a593Smuzhiyun DA7218_DAI_WORD_LENGTH_MASK | DA7218_DAI_CH_NUM_MASK,
2161*4882a593Smuzhiyun dai_ctrl);
2162*4882a593Smuzhiyun /* SRs tied for ADCs and DACs. */
2163*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_SR,
2164*4882a593Smuzhiyun (fs << DA7218_SR_DAC_SHIFT) | (fs << DA7218_SR_ADC_SHIFT));
2165*4882a593Smuzhiyun
2166*4882a593Smuzhiyun return 0;
2167*4882a593Smuzhiyun }
2168*4882a593Smuzhiyun
2169*4882a593Smuzhiyun static const struct snd_soc_dai_ops da7218_dai_ops = {
2170*4882a593Smuzhiyun .hw_params = da7218_hw_params,
2171*4882a593Smuzhiyun .set_sysclk = da7218_set_dai_sysclk,
2172*4882a593Smuzhiyun .set_pll = da7218_set_dai_pll,
2173*4882a593Smuzhiyun .set_fmt = da7218_set_dai_fmt,
2174*4882a593Smuzhiyun .set_tdm_slot = da7218_set_dai_tdm_slot,
2175*4882a593Smuzhiyun };
2176*4882a593Smuzhiyun
2177*4882a593Smuzhiyun #define DA7218_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2178*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2179*4882a593Smuzhiyun
2180*4882a593Smuzhiyun static struct snd_soc_dai_driver da7218_dai = {
2181*4882a593Smuzhiyun .name = "da7218-hifi",
2182*4882a593Smuzhiyun .playback = {
2183*4882a593Smuzhiyun .stream_name = "Playback",
2184*4882a593Smuzhiyun .channels_min = 1,
2185*4882a593Smuzhiyun .channels_max = 4, /* Only 2 channels of data */
2186*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_96000,
2187*4882a593Smuzhiyun .formats = DA7218_FORMATS,
2188*4882a593Smuzhiyun },
2189*4882a593Smuzhiyun .capture = {
2190*4882a593Smuzhiyun .stream_name = "Capture",
2191*4882a593Smuzhiyun .channels_min = 1,
2192*4882a593Smuzhiyun .channels_max = 4,
2193*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_96000,
2194*4882a593Smuzhiyun .formats = DA7218_FORMATS,
2195*4882a593Smuzhiyun },
2196*4882a593Smuzhiyun .ops = &da7218_dai_ops,
2197*4882a593Smuzhiyun .symmetric_rates = 1,
2198*4882a593Smuzhiyun .symmetric_channels = 1,
2199*4882a593Smuzhiyun .symmetric_samplebits = 1,
2200*4882a593Smuzhiyun };
2201*4882a593Smuzhiyun
2202*4882a593Smuzhiyun
2203*4882a593Smuzhiyun /*
2204*4882a593Smuzhiyun * HP Detect
2205*4882a593Smuzhiyun */
2206*4882a593Smuzhiyun
da7218_hpldet(struct snd_soc_component * component,struct snd_soc_jack * jack)2207*4882a593Smuzhiyun int da7218_hpldet(struct snd_soc_component *component, struct snd_soc_jack *jack)
2208*4882a593Smuzhiyun {
2209*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
2210*4882a593Smuzhiyun
2211*4882a593Smuzhiyun if (da7218->dev_id == DA7217_DEV_ID)
2212*4882a593Smuzhiyun return -EINVAL;
2213*4882a593Smuzhiyun
2214*4882a593Smuzhiyun da7218->jack = jack;
2215*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_HPLDET_JACK,
2216*4882a593Smuzhiyun DA7218_HPLDET_JACK_EN_MASK,
2217*4882a593Smuzhiyun jack ? DA7218_HPLDET_JACK_EN_MASK : 0);
2218*4882a593Smuzhiyun
2219*4882a593Smuzhiyun return 0;
2220*4882a593Smuzhiyun }
2221*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(da7218_hpldet);
2222*4882a593Smuzhiyun
da7218_micldet_irq(struct snd_soc_component * component)2223*4882a593Smuzhiyun static void da7218_micldet_irq(struct snd_soc_component *component)
2224*4882a593Smuzhiyun {
2225*4882a593Smuzhiyun char *envp[] = {
2226*4882a593Smuzhiyun "EVENT=MIC_LEVEL_DETECT",
2227*4882a593Smuzhiyun NULL,
2228*4882a593Smuzhiyun };
2229*4882a593Smuzhiyun
2230*4882a593Smuzhiyun kobject_uevent_env(&component->dev->kobj, KOBJ_CHANGE, envp);
2231*4882a593Smuzhiyun }
2232*4882a593Smuzhiyun
da7218_hpldet_irq(struct snd_soc_component * component)2233*4882a593Smuzhiyun static void da7218_hpldet_irq(struct snd_soc_component *component)
2234*4882a593Smuzhiyun {
2235*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
2236*4882a593Smuzhiyun u8 jack_status;
2237*4882a593Smuzhiyun int report;
2238*4882a593Smuzhiyun
2239*4882a593Smuzhiyun jack_status = snd_soc_component_read(component, DA7218_EVENT_STATUS);
2240*4882a593Smuzhiyun
2241*4882a593Smuzhiyun if (jack_status & DA7218_HPLDET_JACK_STS_MASK)
2242*4882a593Smuzhiyun report = SND_JACK_HEADPHONE;
2243*4882a593Smuzhiyun else
2244*4882a593Smuzhiyun report = 0;
2245*4882a593Smuzhiyun
2246*4882a593Smuzhiyun snd_soc_jack_report(da7218->jack, report, SND_JACK_HEADPHONE);
2247*4882a593Smuzhiyun }
2248*4882a593Smuzhiyun
2249*4882a593Smuzhiyun /*
2250*4882a593Smuzhiyun * IRQ
2251*4882a593Smuzhiyun */
2252*4882a593Smuzhiyun
da7218_irq_thread(int irq,void * data)2253*4882a593Smuzhiyun static irqreturn_t da7218_irq_thread(int irq, void *data)
2254*4882a593Smuzhiyun {
2255*4882a593Smuzhiyun struct snd_soc_component *component = data;
2256*4882a593Smuzhiyun u8 status;
2257*4882a593Smuzhiyun
2258*4882a593Smuzhiyun /* Read IRQ status reg */
2259*4882a593Smuzhiyun status = snd_soc_component_read(component, DA7218_EVENT);
2260*4882a593Smuzhiyun if (!status)
2261*4882a593Smuzhiyun return IRQ_NONE;
2262*4882a593Smuzhiyun
2263*4882a593Smuzhiyun /* Mic level detect */
2264*4882a593Smuzhiyun if (status & DA7218_LVL_DET_EVENT_MASK)
2265*4882a593Smuzhiyun da7218_micldet_irq(component);
2266*4882a593Smuzhiyun
2267*4882a593Smuzhiyun /* HP detect */
2268*4882a593Smuzhiyun if (status & DA7218_HPLDET_JACK_EVENT_MASK)
2269*4882a593Smuzhiyun da7218_hpldet_irq(component);
2270*4882a593Smuzhiyun
2271*4882a593Smuzhiyun /* Clear interrupts */
2272*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_EVENT, status);
2273*4882a593Smuzhiyun
2274*4882a593Smuzhiyun return IRQ_HANDLED;
2275*4882a593Smuzhiyun }
2276*4882a593Smuzhiyun
2277*4882a593Smuzhiyun /*
2278*4882a593Smuzhiyun * DT
2279*4882a593Smuzhiyun */
2280*4882a593Smuzhiyun
2281*4882a593Smuzhiyun static const struct of_device_id da7218_of_match[] = {
2282*4882a593Smuzhiyun { .compatible = "dlg,da7217", .data = (void *) DA7217_DEV_ID },
2283*4882a593Smuzhiyun { .compatible = "dlg,da7218", .data = (void *) DA7218_DEV_ID },
2284*4882a593Smuzhiyun { }
2285*4882a593Smuzhiyun };
2286*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, da7218_of_match);
2287*4882a593Smuzhiyun
da7218_of_get_id(struct device * dev)2288*4882a593Smuzhiyun static inline int da7218_of_get_id(struct device *dev)
2289*4882a593Smuzhiyun {
2290*4882a593Smuzhiyun const struct of_device_id *id = of_match_device(da7218_of_match, dev);
2291*4882a593Smuzhiyun
2292*4882a593Smuzhiyun if (id)
2293*4882a593Smuzhiyun return (uintptr_t)id->data;
2294*4882a593Smuzhiyun else
2295*4882a593Smuzhiyun return -EINVAL;
2296*4882a593Smuzhiyun }
2297*4882a593Smuzhiyun
2298*4882a593Smuzhiyun static enum da7218_micbias_voltage
da7218_of_micbias_lvl(struct snd_soc_component * component,u32 val)2299*4882a593Smuzhiyun da7218_of_micbias_lvl(struct snd_soc_component *component, u32 val)
2300*4882a593Smuzhiyun {
2301*4882a593Smuzhiyun switch (val) {
2302*4882a593Smuzhiyun case 1200:
2303*4882a593Smuzhiyun return DA7218_MICBIAS_1_2V;
2304*4882a593Smuzhiyun case 1600:
2305*4882a593Smuzhiyun return DA7218_MICBIAS_1_6V;
2306*4882a593Smuzhiyun case 1800:
2307*4882a593Smuzhiyun return DA7218_MICBIAS_1_8V;
2308*4882a593Smuzhiyun case 2000:
2309*4882a593Smuzhiyun return DA7218_MICBIAS_2_0V;
2310*4882a593Smuzhiyun case 2200:
2311*4882a593Smuzhiyun return DA7218_MICBIAS_2_2V;
2312*4882a593Smuzhiyun case 2400:
2313*4882a593Smuzhiyun return DA7218_MICBIAS_2_4V;
2314*4882a593Smuzhiyun case 2600:
2315*4882a593Smuzhiyun return DA7218_MICBIAS_2_6V;
2316*4882a593Smuzhiyun case 2800:
2317*4882a593Smuzhiyun return DA7218_MICBIAS_2_8V;
2318*4882a593Smuzhiyun case 3000:
2319*4882a593Smuzhiyun return DA7218_MICBIAS_3_0V;
2320*4882a593Smuzhiyun default:
2321*4882a593Smuzhiyun dev_warn(component->dev, "Invalid micbias level");
2322*4882a593Smuzhiyun return DA7218_MICBIAS_1_6V;
2323*4882a593Smuzhiyun }
2324*4882a593Smuzhiyun }
2325*4882a593Smuzhiyun
2326*4882a593Smuzhiyun static enum da7218_mic_amp_in_sel
da7218_of_mic_amp_in_sel(struct snd_soc_component * component,const char * str)2327*4882a593Smuzhiyun da7218_of_mic_amp_in_sel(struct snd_soc_component *component, const char *str)
2328*4882a593Smuzhiyun {
2329*4882a593Smuzhiyun if (!strcmp(str, "diff")) {
2330*4882a593Smuzhiyun return DA7218_MIC_AMP_IN_SEL_DIFF;
2331*4882a593Smuzhiyun } else if (!strcmp(str, "se_p")) {
2332*4882a593Smuzhiyun return DA7218_MIC_AMP_IN_SEL_SE_P;
2333*4882a593Smuzhiyun } else if (!strcmp(str, "se_n")) {
2334*4882a593Smuzhiyun return DA7218_MIC_AMP_IN_SEL_SE_N;
2335*4882a593Smuzhiyun } else {
2336*4882a593Smuzhiyun dev_warn(component->dev, "Invalid mic input type selection");
2337*4882a593Smuzhiyun return DA7218_MIC_AMP_IN_SEL_DIFF;
2338*4882a593Smuzhiyun }
2339*4882a593Smuzhiyun }
2340*4882a593Smuzhiyun
2341*4882a593Smuzhiyun static enum da7218_dmic_data_sel
da7218_of_dmic_data_sel(struct snd_soc_component * component,const char * str)2342*4882a593Smuzhiyun da7218_of_dmic_data_sel(struct snd_soc_component *component, const char *str)
2343*4882a593Smuzhiyun {
2344*4882a593Smuzhiyun if (!strcmp(str, "lrise_rfall")) {
2345*4882a593Smuzhiyun return DA7218_DMIC_DATA_LRISE_RFALL;
2346*4882a593Smuzhiyun } else if (!strcmp(str, "lfall_rrise")) {
2347*4882a593Smuzhiyun return DA7218_DMIC_DATA_LFALL_RRISE;
2348*4882a593Smuzhiyun } else {
2349*4882a593Smuzhiyun dev_warn(component->dev, "Invalid DMIC data type selection");
2350*4882a593Smuzhiyun return DA7218_DMIC_DATA_LRISE_RFALL;
2351*4882a593Smuzhiyun }
2352*4882a593Smuzhiyun }
2353*4882a593Smuzhiyun
2354*4882a593Smuzhiyun static enum da7218_dmic_samplephase
da7218_of_dmic_samplephase(struct snd_soc_component * component,const char * str)2355*4882a593Smuzhiyun da7218_of_dmic_samplephase(struct snd_soc_component *component, const char *str)
2356*4882a593Smuzhiyun {
2357*4882a593Smuzhiyun if (!strcmp(str, "on_clkedge")) {
2358*4882a593Smuzhiyun return DA7218_DMIC_SAMPLE_ON_CLKEDGE;
2359*4882a593Smuzhiyun } else if (!strcmp(str, "between_clkedge")) {
2360*4882a593Smuzhiyun return DA7218_DMIC_SAMPLE_BETWEEN_CLKEDGE;
2361*4882a593Smuzhiyun } else {
2362*4882a593Smuzhiyun dev_warn(component->dev, "Invalid DMIC sample phase");
2363*4882a593Smuzhiyun return DA7218_DMIC_SAMPLE_ON_CLKEDGE;
2364*4882a593Smuzhiyun }
2365*4882a593Smuzhiyun }
2366*4882a593Smuzhiyun
2367*4882a593Smuzhiyun static enum da7218_dmic_clk_rate
da7218_of_dmic_clkrate(struct snd_soc_component * component,u32 val)2368*4882a593Smuzhiyun da7218_of_dmic_clkrate(struct snd_soc_component *component, u32 val)
2369*4882a593Smuzhiyun {
2370*4882a593Smuzhiyun switch (val) {
2371*4882a593Smuzhiyun case 1500000:
2372*4882a593Smuzhiyun return DA7218_DMIC_CLK_1_5MHZ;
2373*4882a593Smuzhiyun case 3000000:
2374*4882a593Smuzhiyun return DA7218_DMIC_CLK_3_0MHZ;
2375*4882a593Smuzhiyun default:
2376*4882a593Smuzhiyun dev_warn(component->dev, "Invalid DMIC clock rate");
2377*4882a593Smuzhiyun return DA7218_DMIC_CLK_3_0MHZ;
2378*4882a593Smuzhiyun }
2379*4882a593Smuzhiyun }
2380*4882a593Smuzhiyun
2381*4882a593Smuzhiyun static enum da7218_hpldet_jack_rate
da7218_of_jack_rate(struct snd_soc_component * component,u32 val)2382*4882a593Smuzhiyun da7218_of_jack_rate(struct snd_soc_component *component, u32 val)
2383*4882a593Smuzhiyun {
2384*4882a593Smuzhiyun switch (val) {
2385*4882a593Smuzhiyun case 5:
2386*4882a593Smuzhiyun return DA7218_HPLDET_JACK_RATE_5US;
2387*4882a593Smuzhiyun case 10:
2388*4882a593Smuzhiyun return DA7218_HPLDET_JACK_RATE_10US;
2389*4882a593Smuzhiyun case 20:
2390*4882a593Smuzhiyun return DA7218_HPLDET_JACK_RATE_20US;
2391*4882a593Smuzhiyun case 40:
2392*4882a593Smuzhiyun return DA7218_HPLDET_JACK_RATE_40US;
2393*4882a593Smuzhiyun case 80:
2394*4882a593Smuzhiyun return DA7218_HPLDET_JACK_RATE_80US;
2395*4882a593Smuzhiyun case 160:
2396*4882a593Smuzhiyun return DA7218_HPLDET_JACK_RATE_160US;
2397*4882a593Smuzhiyun case 320:
2398*4882a593Smuzhiyun return DA7218_HPLDET_JACK_RATE_320US;
2399*4882a593Smuzhiyun case 640:
2400*4882a593Smuzhiyun return DA7218_HPLDET_JACK_RATE_640US;
2401*4882a593Smuzhiyun default:
2402*4882a593Smuzhiyun dev_warn(component->dev, "Invalid jack detect rate");
2403*4882a593Smuzhiyun return DA7218_HPLDET_JACK_RATE_40US;
2404*4882a593Smuzhiyun }
2405*4882a593Smuzhiyun }
2406*4882a593Smuzhiyun
2407*4882a593Smuzhiyun static enum da7218_hpldet_jack_debounce
da7218_of_jack_debounce(struct snd_soc_component * component,u32 val)2408*4882a593Smuzhiyun da7218_of_jack_debounce(struct snd_soc_component *component, u32 val)
2409*4882a593Smuzhiyun {
2410*4882a593Smuzhiyun switch (val) {
2411*4882a593Smuzhiyun case 0:
2412*4882a593Smuzhiyun return DA7218_HPLDET_JACK_DEBOUNCE_OFF;
2413*4882a593Smuzhiyun case 2:
2414*4882a593Smuzhiyun return DA7218_HPLDET_JACK_DEBOUNCE_2;
2415*4882a593Smuzhiyun case 3:
2416*4882a593Smuzhiyun return DA7218_HPLDET_JACK_DEBOUNCE_3;
2417*4882a593Smuzhiyun case 4:
2418*4882a593Smuzhiyun return DA7218_HPLDET_JACK_DEBOUNCE_4;
2419*4882a593Smuzhiyun default:
2420*4882a593Smuzhiyun dev_warn(component->dev, "Invalid jack debounce");
2421*4882a593Smuzhiyun return DA7218_HPLDET_JACK_DEBOUNCE_2;
2422*4882a593Smuzhiyun }
2423*4882a593Smuzhiyun }
2424*4882a593Smuzhiyun
2425*4882a593Smuzhiyun static enum da7218_hpldet_jack_thr
da7218_of_jack_thr(struct snd_soc_component * component,u32 val)2426*4882a593Smuzhiyun da7218_of_jack_thr(struct snd_soc_component *component, u32 val)
2427*4882a593Smuzhiyun {
2428*4882a593Smuzhiyun switch (val) {
2429*4882a593Smuzhiyun case 84:
2430*4882a593Smuzhiyun return DA7218_HPLDET_JACK_THR_84PCT;
2431*4882a593Smuzhiyun case 88:
2432*4882a593Smuzhiyun return DA7218_HPLDET_JACK_THR_88PCT;
2433*4882a593Smuzhiyun case 92:
2434*4882a593Smuzhiyun return DA7218_HPLDET_JACK_THR_92PCT;
2435*4882a593Smuzhiyun case 96:
2436*4882a593Smuzhiyun return DA7218_HPLDET_JACK_THR_96PCT;
2437*4882a593Smuzhiyun default:
2438*4882a593Smuzhiyun dev_warn(component->dev, "Invalid jack threshold level");
2439*4882a593Smuzhiyun return DA7218_HPLDET_JACK_THR_84PCT;
2440*4882a593Smuzhiyun }
2441*4882a593Smuzhiyun }
2442*4882a593Smuzhiyun
da7218_of_to_pdata(struct snd_soc_component * component)2443*4882a593Smuzhiyun static struct da7218_pdata *da7218_of_to_pdata(struct snd_soc_component *component)
2444*4882a593Smuzhiyun {
2445*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
2446*4882a593Smuzhiyun struct device_node *np = component->dev->of_node;
2447*4882a593Smuzhiyun struct device_node *hpldet_np;
2448*4882a593Smuzhiyun struct da7218_pdata *pdata;
2449*4882a593Smuzhiyun struct da7218_hpldet_pdata *hpldet_pdata;
2450*4882a593Smuzhiyun const char *of_str;
2451*4882a593Smuzhiyun u32 of_val32;
2452*4882a593Smuzhiyun
2453*4882a593Smuzhiyun pdata = devm_kzalloc(component->dev, sizeof(*pdata), GFP_KERNEL);
2454*4882a593Smuzhiyun if (!pdata)
2455*4882a593Smuzhiyun return NULL;
2456*4882a593Smuzhiyun
2457*4882a593Smuzhiyun if (of_property_read_u32(np, "dlg,micbias1-lvl-millivolt", &of_val32) >= 0)
2458*4882a593Smuzhiyun pdata->micbias1_lvl = da7218_of_micbias_lvl(component, of_val32);
2459*4882a593Smuzhiyun else
2460*4882a593Smuzhiyun pdata->micbias1_lvl = DA7218_MICBIAS_1_6V;
2461*4882a593Smuzhiyun
2462*4882a593Smuzhiyun if (of_property_read_u32(np, "dlg,micbias2-lvl-millivolt", &of_val32) >= 0)
2463*4882a593Smuzhiyun pdata->micbias2_lvl = da7218_of_micbias_lvl(component, of_val32);
2464*4882a593Smuzhiyun else
2465*4882a593Smuzhiyun pdata->micbias2_lvl = DA7218_MICBIAS_1_6V;
2466*4882a593Smuzhiyun
2467*4882a593Smuzhiyun if (!of_property_read_string(np, "dlg,mic1-amp-in-sel", &of_str))
2468*4882a593Smuzhiyun pdata->mic1_amp_in_sel =
2469*4882a593Smuzhiyun da7218_of_mic_amp_in_sel(component, of_str);
2470*4882a593Smuzhiyun else
2471*4882a593Smuzhiyun pdata->mic1_amp_in_sel = DA7218_MIC_AMP_IN_SEL_DIFF;
2472*4882a593Smuzhiyun
2473*4882a593Smuzhiyun if (!of_property_read_string(np, "dlg,mic2-amp-in-sel", &of_str))
2474*4882a593Smuzhiyun pdata->mic2_amp_in_sel =
2475*4882a593Smuzhiyun da7218_of_mic_amp_in_sel(component, of_str);
2476*4882a593Smuzhiyun else
2477*4882a593Smuzhiyun pdata->mic2_amp_in_sel = DA7218_MIC_AMP_IN_SEL_DIFF;
2478*4882a593Smuzhiyun
2479*4882a593Smuzhiyun if (!of_property_read_string(np, "dlg,dmic1-data-sel", &of_str))
2480*4882a593Smuzhiyun pdata->dmic1_data_sel = da7218_of_dmic_data_sel(component, of_str);
2481*4882a593Smuzhiyun else
2482*4882a593Smuzhiyun pdata->dmic1_data_sel = DA7218_DMIC_DATA_LRISE_RFALL;
2483*4882a593Smuzhiyun
2484*4882a593Smuzhiyun if (!of_property_read_string(np, "dlg,dmic1-samplephase", &of_str))
2485*4882a593Smuzhiyun pdata->dmic1_samplephase =
2486*4882a593Smuzhiyun da7218_of_dmic_samplephase(component, of_str);
2487*4882a593Smuzhiyun else
2488*4882a593Smuzhiyun pdata->dmic1_samplephase = DA7218_DMIC_SAMPLE_ON_CLKEDGE;
2489*4882a593Smuzhiyun
2490*4882a593Smuzhiyun if (of_property_read_u32(np, "dlg,dmic1-clkrate-hz", &of_val32) >= 0)
2491*4882a593Smuzhiyun pdata->dmic1_clk_rate = da7218_of_dmic_clkrate(component, of_val32);
2492*4882a593Smuzhiyun else
2493*4882a593Smuzhiyun pdata->dmic1_clk_rate = DA7218_DMIC_CLK_3_0MHZ;
2494*4882a593Smuzhiyun
2495*4882a593Smuzhiyun if (!of_property_read_string(np, "dlg,dmic2-data-sel", &of_str))
2496*4882a593Smuzhiyun pdata->dmic2_data_sel = da7218_of_dmic_data_sel(component, of_str);
2497*4882a593Smuzhiyun else
2498*4882a593Smuzhiyun pdata->dmic2_data_sel = DA7218_DMIC_DATA_LRISE_RFALL;
2499*4882a593Smuzhiyun
2500*4882a593Smuzhiyun if (!of_property_read_string(np, "dlg,dmic2-samplephase", &of_str))
2501*4882a593Smuzhiyun pdata->dmic2_samplephase =
2502*4882a593Smuzhiyun da7218_of_dmic_samplephase(component, of_str);
2503*4882a593Smuzhiyun else
2504*4882a593Smuzhiyun pdata->dmic2_samplephase = DA7218_DMIC_SAMPLE_ON_CLKEDGE;
2505*4882a593Smuzhiyun
2506*4882a593Smuzhiyun if (of_property_read_u32(np, "dlg,dmic2-clkrate-hz", &of_val32) >= 0)
2507*4882a593Smuzhiyun pdata->dmic2_clk_rate = da7218_of_dmic_clkrate(component, of_val32);
2508*4882a593Smuzhiyun else
2509*4882a593Smuzhiyun pdata->dmic2_clk_rate = DA7218_DMIC_CLK_3_0MHZ;
2510*4882a593Smuzhiyun
2511*4882a593Smuzhiyun if (da7218->dev_id == DA7217_DEV_ID) {
2512*4882a593Smuzhiyun if (of_property_read_bool(np, "dlg,hp-diff-single-supply"))
2513*4882a593Smuzhiyun pdata->hp_diff_single_supply = true;
2514*4882a593Smuzhiyun }
2515*4882a593Smuzhiyun
2516*4882a593Smuzhiyun if (da7218->dev_id == DA7218_DEV_ID) {
2517*4882a593Smuzhiyun hpldet_np = of_get_child_by_name(np, "da7218_hpldet");
2518*4882a593Smuzhiyun if (!hpldet_np)
2519*4882a593Smuzhiyun return pdata;
2520*4882a593Smuzhiyun
2521*4882a593Smuzhiyun hpldet_pdata = devm_kzalloc(component->dev, sizeof(*hpldet_pdata),
2522*4882a593Smuzhiyun GFP_KERNEL);
2523*4882a593Smuzhiyun if (!hpldet_pdata) {
2524*4882a593Smuzhiyun of_node_put(hpldet_np);
2525*4882a593Smuzhiyun return pdata;
2526*4882a593Smuzhiyun }
2527*4882a593Smuzhiyun pdata->hpldet_pdata = hpldet_pdata;
2528*4882a593Smuzhiyun
2529*4882a593Smuzhiyun if (of_property_read_u32(hpldet_np, "dlg,jack-rate-us",
2530*4882a593Smuzhiyun &of_val32) >= 0)
2531*4882a593Smuzhiyun hpldet_pdata->jack_rate =
2532*4882a593Smuzhiyun da7218_of_jack_rate(component, of_val32);
2533*4882a593Smuzhiyun else
2534*4882a593Smuzhiyun hpldet_pdata->jack_rate = DA7218_HPLDET_JACK_RATE_40US;
2535*4882a593Smuzhiyun
2536*4882a593Smuzhiyun if (of_property_read_u32(hpldet_np, "dlg,jack-debounce",
2537*4882a593Smuzhiyun &of_val32) >= 0)
2538*4882a593Smuzhiyun hpldet_pdata->jack_debounce =
2539*4882a593Smuzhiyun da7218_of_jack_debounce(component, of_val32);
2540*4882a593Smuzhiyun else
2541*4882a593Smuzhiyun hpldet_pdata->jack_debounce =
2542*4882a593Smuzhiyun DA7218_HPLDET_JACK_DEBOUNCE_2;
2543*4882a593Smuzhiyun
2544*4882a593Smuzhiyun if (of_property_read_u32(hpldet_np, "dlg,jack-threshold-pct",
2545*4882a593Smuzhiyun &of_val32) >= 0)
2546*4882a593Smuzhiyun hpldet_pdata->jack_thr =
2547*4882a593Smuzhiyun da7218_of_jack_thr(component, of_val32);
2548*4882a593Smuzhiyun else
2549*4882a593Smuzhiyun hpldet_pdata->jack_thr = DA7218_HPLDET_JACK_THR_84PCT;
2550*4882a593Smuzhiyun
2551*4882a593Smuzhiyun if (of_property_read_bool(hpldet_np, "dlg,comp-inv"))
2552*4882a593Smuzhiyun hpldet_pdata->comp_inv = true;
2553*4882a593Smuzhiyun
2554*4882a593Smuzhiyun if (of_property_read_bool(hpldet_np, "dlg,hyst"))
2555*4882a593Smuzhiyun hpldet_pdata->hyst = true;
2556*4882a593Smuzhiyun
2557*4882a593Smuzhiyun if (of_property_read_bool(hpldet_np, "dlg,discharge"))
2558*4882a593Smuzhiyun hpldet_pdata->discharge = true;
2559*4882a593Smuzhiyun
2560*4882a593Smuzhiyun of_node_put(hpldet_np);
2561*4882a593Smuzhiyun }
2562*4882a593Smuzhiyun
2563*4882a593Smuzhiyun return pdata;
2564*4882a593Smuzhiyun }
2565*4882a593Smuzhiyun
2566*4882a593Smuzhiyun
2567*4882a593Smuzhiyun /*
2568*4882a593Smuzhiyun * Codec driver functions
2569*4882a593Smuzhiyun */
2570*4882a593Smuzhiyun
da7218_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2571*4882a593Smuzhiyun static int da7218_set_bias_level(struct snd_soc_component *component,
2572*4882a593Smuzhiyun enum snd_soc_bias_level level)
2573*4882a593Smuzhiyun {
2574*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
2575*4882a593Smuzhiyun int ret;
2576*4882a593Smuzhiyun
2577*4882a593Smuzhiyun switch (level) {
2578*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
2579*4882a593Smuzhiyun break;
2580*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
2581*4882a593Smuzhiyun /* Enable MCLK for transition to ON state */
2582*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
2583*4882a593Smuzhiyun if (da7218->mclk) {
2584*4882a593Smuzhiyun ret = clk_prepare_enable(da7218->mclk);
2585*4882a593Smuzhiyun if (ret) {
2586*4882a593Smuzhiyun dev_err(component->dev, "Failed to enable mclk\n");
2587*4882a593Smuzhiyun return ret;
2588*4882a593Smuzhiyun }
2589*4882a593Smuzhiyun }
2590*4882a593Smuzhiyun }
2591*4882a593Smuzhiyun
2592*4882a593Smuzhiyun break;
2593*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
2594*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
2595*4882a593Smuzhiyun /* Master bias */
2596*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_REFERENCES,
2597*4882a593Smuzhiyun DA7218_BIAS_EN_MASK,
2598*4882a593Smuzhiyun DA7218_BIAS_EN_MASK);
2599*4882a593Smuzhiyun
2600*4882a593Smuzhiyun /* Internal LDO */
2601*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_LDO_CTRL,
2602*4882a593Smuzhiyun DA7218_LDO_EN_MASK,
2603*4882a593Smuzhiyun DA7218_LDO_EN_MASK);
2604*4882a593Smuzhiyun } else {
2605*4882a593Smuzhiyun /* Remove MCLK */
2606*4882a593Smuzhiyun if (da7218->mclk)
2607*4882a593Smuzhiyun clk_disable_unprepare(da7218->mclk);
2608*4882a593Smuzhiyun }
2609*4882a593Smuzhiyun break;
2610*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
2611*4882a593Smuzhiyun /* Only disable if jack detection disabled */
2612*4882a593Smuzhiyun if (!da7218->jack) {
2613*4882a593Smuzhiyun /* Internal LDO */
2614*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_LDO_CTRL,
2615*4882a593Smuzhiyun DA7218_LDO_EN_MASK, 0);
2616*4882a593Smuzhiyun
2617*4882a593Smuzhiyun /* Master bias */
2618*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_REFERENCES,
2619*4882a593Smuzhiyun DA7218_BIAS_EN_MASK, 0);
2620*4882a593Smuzhiyun }
2621*4882a593Smuzhiyun break;
2622*4882a593Smuzhiyun }
2623*4882a593Smuzhiyun
2624*4882a593Smuzhiyun return 0;
2625*4882a593Smuzhiyun }
2626*4882a593Smuzhiyun
2627*4882a593Smuzhiyun static const char *da7218_supply_names[DA7218_NUM_SUPPLIES] = {
2628*4882a593Smuzhiyun [DA7218_SUPPLY_VDD] = "VDD",
2629*4882a593Smuzhiyun [DA7218_SUPPLY_VDDMIC] = "VDDMIC",
2630*4882a593Smuzhiyun [DA7218_SUPPLY_VDDIO] = "VDDIO",
2631*4882a593Smuzhiyun };
2632*4882a593Smuzhiyun
da7218_handle_supplies(struct snd_soc_component * component)2633*4882a593Smuzhiyun static int da7218_handle_supplies(struct snd_soc_component *component)
2634*4882a593Smuzhiyun {
2635*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
2636*4882a593Smuzhiyun struct regulator *vddio;
2637*4882a593Smuzhiyun u8 io_voltage_lvl = DA7218_IO_VOLTAGE_LEVEL_2_5V_3_6V;
2638*4882a593Smuzhiyun int i, ret;
2639*4882a593Smuzhiyun
2640*4882a593Smuzhiyun /* Get required supplies */
2641*4882a593Smuzhiyun for (i = 0; i < DA7218_NUM_SUPPLIES; ++i)
2642*4882a593Smuzhiyun da7218->supplies[i].supply = da7218_supply_names[i];
2643*4882a593Smuzhiyun
2644*4882a593Smuzhiyun ret = devm_regulator_bulk_get(component->dev, DA7218_NUM_SUPPLIES,
2645*4882a593Smuzhiyun da7218->supplies);
2646*4882a593Smuzhiyun if (ret) {
2647*4882a593Smuzhiyun dev_err(component->dev, "Failed to get supplies\n");
2648*4882a593Smuzhiyun return ret;
2649*4882a593Smuzhiyun }
2650*4882a593Smuzhiyun
2651*4882a593Smuzhiyun /* Determine VDDIO voltage provided */
2652*4882a593Smuzhiyun vddio = da7218->supplies[DA7218_SUPPLY_VDDIO].consumer;
2653*4882a593Smuzhiyun ret = regulator_get_voltage(vddio);
2654*4882a593Smuzhiyun if (ret < 1500000)
2655*4882a593Smuzhiyun dev_warn(component->dev, "Invalid VDDIO voltage\n");
2656*4882a593Smuzhiyun else if (ret < 2500000)
2657*4882a593Smuzhiyun io_voltage_lvl = DA7218_IO_VOLTAGE_LEVEL_1_5V_2_5V;
2658*4882a593Smuzhiyun
2659*4882a593Smuzhiyun /* Enable main supplies */
2660*4882a593Smuzhiyun ret = regulator_bulk_enable(DA7218_NUM_SUPPLIES, da7218->supplies);
2661*4882a593Smuzhiyun if (ret) {
2662*4882a593Smuzhiyun dev_err(component->dev, "Failed to enable supplies\n");
2663*4882a593Smuzhiyun return ret;
2664*4882a593Smuzhiyun }
2665*4882a593Smuzhiyun
2666*4882a593Smuzhiyun /* Ensure device in active mode */
2667*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_SYSTEM_ACTIVE, DA7218_SYSTEM_ACTIVE_MASK);
2668*4882a593Smuzhiyun
2669*4882a593Smuzhiyun /* Update IO voltage level range */
2670*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_IO_CTRL, io_voltage_lvl);
2671*4882a593Smuzhiyun
2672*4882a593Smuzhiyun return 0;
2673*4882a593Smuzhiyun }
2674*4882a593Smuzhiyun
da7218_handle_pdata(struct snd_soc_component * component)2675*4882a593Smuzhiyun static void da7218_handle_pdata(struct snd_soc_component *component)
2676*4882a593Smuzhiyun {
2677*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
2678*4882a593Smuzhiyun struct da7218_pdata *pdata = da7218->pdata;
2679*4882a593Smuzhiyun
2680*4882a593Smuzhiyun if (pdata) {
2681*4882a593Smuzhiyun u8 micbias_lvl = 0, dmic_cfg = 0;
2682*4882a593Smuzhiyun
2683*4882a593Smuzhiyun /* Mic Bias voltages */
2684*4882a593Smuzhiyun switch (pdata->micbias1_lvl) {
2685*4882a593Smuzhiyun case DA7218_MICBIAS_1_2V:
2686*4882a593Smuzhiyun micbias_lvl |= DA7218_MICBIAS_1_LP_MODE_MASK;
2687*4882a593Smuzhiyun break;
2688*4882a593Smuzhiyun case DA7218_MICBIAS_1_6V:
2689*4882a593Smuzhiyun case DA7218_MICBIAS_1_8V:
2690*4882a593Smuzhiyun case DA7218_MICBIAS_2_0V:
2691*4882a593Smuzhiyun case DA7218_MICBIAS_2_2V:
2692*4882a593Smuzhiyun case DA7218_MICBIAS_2_4V:
2693*4882a593Smuzhiyun case DA7218_MICBIAS_2_6V:
2694*4882a593Smuzhiyun case DA7218_MICBIAS_2_8V:
2695*4882a593Smuzhiyun case DA7218_MICBIAS_3_0V:
2696*4882a593Smuzhiyun micbias_lvl |= (pdata->micbias1_lvl <<
2697*4882a593Smuzhiyun DA7218_MICBIAS_1_LEVEL_SHIFT);
2698*4882a593Smuzhiyun break;
2699*4882a593Smuzhiyun }
2700*4882a593Smuzhiyun
2701*4882a593Smuzhiyun switch (pdata->micbias2_lvl) {
2702*4882a593Smuzhiyun case DA7218_MICBIAS_1_2V:
2703*4882a593Smuzhiyun micbias_lvl |= DA7218_MICBIAS_2_LP_MODE_MASK;
2704*4882a593Smuzhiyun break;
2705*4882a593Smuzhiyun case DA7218_MICBIAS_1_6V:
2706*4882a593Smuzhiyun case DA7218_MICBIAS_1_8V:
2707*4882a593Smuzhiyun case DA7218_MICBIAS_2_0V:
2708*4882a593Smuzhiyun case DA7218_MICBIAS_2_2V:
2709*4882a593Smuzhiyun case DA7218_MICBIAS_2_4V:
2710*4882a593Smuzhiyun case DA7218_MICBIAS_2_6V:
2711*4882a593Smuzhiyun case DA7218_MICBIAS_2_8V:
2712*4882a593Smuzhiyun case DA7218_MICBIAS_3_0V:
2713*4882a593Smuzhiyun micbias_lvl |= (pdata->micbias2_lvl <<
2714*4882a593Smuzhiyun DA7218_MICBIAS_2_LEVEL_SHIFT);
2715*4882a593Smuzhiyun break;
2716*4882a593Smuzhiyun }
2717*4882a593Smuzhiyun
2718*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_MICBIAS_CTRL, micbias_lvl);
2719*4882a593Smuzhiyun
2720*4882a593Smuzhiyun /* Mic */
2721*4882a593Smuzhiyun switch (pdata->mic1_amp_in_sel) {
2722*4882a593Smuzhiyun case DA7218_MIC_AMP_IN_SEL_DIFF:
2723*4882a593Smuzhiyun case DA7218_MIC_AMP_IN_SEL_SE_P:
2724*4882a593Smuzhiyun case DA7218_MIC_AMP_IN_SEL_SE_N:
2725*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_MIC_1_SELECT,
2726*4882a593Smuzhiyun pdata->mic1_amp_in_sel);
2727*4882a593Smuzhiyun break;
2728*4882a593Smuzhiyun }
2729*4882a593Smuzhiyun
2730*4882a593Smuzhiyun switch (pdata->mic2_amp_in_sel) {
2731*4882a593Smuzhiyun case DA7218_MIC_AMP_IN_SEL_DIFF:
2732*4882a593Smuzhiyun case DA7218_MIC_AMP_IN_SEL_SE_P:
2733*4882a593Smuzhiyun case DA7218_MIC_AMP_IN_SEL_SE_N:
2734*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_MIC_2_SELECT,
2735*4882a593Smuzhiyun pdata->mic2_amp_in_sel);
2736*4882a593Smuzhiyun break;
2737*4882a593Smuzhiyun }
2738*4882a593Smuzhiyun
2739*4882a593Smuzhiyun /* DMic */
2740*4882a593Smuzhiyun switch (pdata->dmic1_data_sel) {
2741*4882a593Smuzhiyun case DA7218_DMIC_DATA_LFALL_RRISE:
2742*4882a593Smuzhiyun case DA7218_DMIC_DATA_LRISE_RFALL:
2743*4882a593Smuzhiyun dmic_cfg |= (pdata->dmic1_data_sel <<
2744*4882a593Smuzhiyun DA7218_DMIC_1_DATA_SEL_SHIFT);
2745*4882a593Smuzhiyun break;
2746*4882a593Smuzhiyun }
2747*4882a593Smuzhiyun
2748*4882a593Smuzhiyun switch (pdata->dmic1_samplephase) {
2749*4882a593Smuzhiyun case DA7218_DMIC_SAMPLE_ON_CLKEDGE:
2750*4882a593Smuzhiyun case DA7218_DMIC_SAMPLE_BETWEEN_CLKEDGE:
2751*4882a593Smuzhiyun dmic_cfg |= (pdata->dmic1_samplephase <<
2752*4882a593Smuzhiyun DA7218_DMIC_1_SAMPLEPHASE_SHIFT);
2753*4882a593Smuzhiyun break;
2754*4882a593Smuzhiyun }
2755*4882a593Smuzhiyun
2756*4882a593Smuzhiyun switch (pdata->dmic1_clk_rate) {
2757*4882a593Smuzhiyun case DA7218_DMIC_CLK_3_0MHZ:
2758*4882a593Smuzhiyun case DA7218_DMIC_CLK_1_5MHZ:
2759*4882a593Smuzhiyun dmic_cfg |= (pdata->dmic1_clk_rate <<
2760*4882a593Smuzhiyun DA7218_DMIC_1_CLK_RATE_SHIFT);
2761*4882a593Smuzhiyun break;
2762*4882a593Smuzhiyun }
2763*4882a593Smuzhiyun
2764*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DMIC_1_CTRL,
2765*4882a593Smuzhiyun DA7218_DMIC_1_DATA_SEL_MASK |
2766*4882a593Smuzhiyun DA7218_DMIC_1_SAMPLEPHASE_MASK |
2767*4882a593Smuzhiyun DA7218_DMIC_1_CLK_RATE_MASK, dmic_cfg);
2768*4882a593Smuzhiyun
2769*4882a593Smuzhiyun dmic_cfg = 0;
2770*4882a593Smuzhiyun switch (pdata->dmic2_data_sel) {
2771*4882a593Smuzhiyun case DA7218_DMIC_DATA_LFALL_RRISE:
2772*4882a593Smuzhiyun case DA7218_DMIC_DATA_LRISE_RFALL:
2773*4882a593Smuzhiyun dmic_cfg |= (pdata->dmic2_data_sel <<
2774*4882a593Smuzhiyun DA7218_DMIC_2_DATA_SEL_SHIFT);
2775*4882a593Smuzhiyun break;
2776*4882a593Smuzhiyun }
2777*4882a593Smuzhiyun
2778*4882a593Smuzhiyun switch (pdata->dmic2_samplephase) {
2779*4882a593Smuzhiyun case DA7218_DMIC_SAMPLE_ON_CLKEDGE:
2780*4882a593Smuzhiyun case DA7218_DMIC_SAMPLE_BETWEEN_CLKEDGE:
2781*4882a593Smuzhiyun dmic_cfg |= (pdata->dmic2_samplephase <<
2782*4882a593Smuzhiyun DA7218_DMIC_2_SAMPLEPHASE_SHIFT);
2783*4882a593Smuzhiyun break;
2784*4882a593Smuzhiyun }
2785*4882a593Smuzhiyun
2786*4882a593Smuzhiyun switch (pdata->dmic2_clk_rate) {
2787*4882a593Smuzhiyun case DA7218_DMIC_CLK_3_0MHZ:
2788*4882a593Smuzhiyun case DA7218_DMIC_CLK_1_5MHZ:
2789*4882a593Smuzhiyun dmic_cfg |= (pdata->dmic2_clk_rate <<
2790*4882a593Smuzhiyun DA7218_DMIC_2_CLK_RATE_SHIFT);
2791*4882a593Smuzhiyun break;
2792*4882a593Smuzhiyun }
2793*4882a593Smuzhiyun
2794*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DMIC_2_CTRL,
2795*4882a593Smuzhiyun DA7218_DMIC_2_DATA_SEL_MASK |
2796*4882a593Smuzhiyun DA7218_DMIC_2_SAMPLEPHASE_MASK |
2797*4882a593Smuzhiyun DA7218_DMIC_2_CLK_RATE_MASK, dmic_cfg);
2798*4882a593Smuzhiyun
2799*4882a593Smuzhiyun /* DA7217 Specific */
2800*4882a593Smuzhiyun if (da7218->dev_id == DA7217_DEV_ID) {
2801*4882a593Smuzhiyun da7218->hp_single_supply =
2802*4882a593Smuzhiyun pdata->hp_diff_single_supply;
2803*4882a593Smuzhiyun
2804*4882a593Smuzhiyun if (da7218->hp_single_supply) {
2805*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_HP_DIFF_UNLOCK,
2806*4882a593Smuzhiyun DA7218_HP_DIFF_UNLOCK_VAL);
2807*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_HP_DIFF_CTRL,
2808*4882a593Smuzhiyun DA7218_HP_AMP_SINGLE_SUPPLY_EN_MASK,
2809*4882a593Smuzhiyun DA7218_HP_AMP_SINGLE_SUPPLY_EN_MASK);
2810*4882a593Smuzhiyun }
2811*4882a593Smuzhiyun }
2812*4882a593Smuzhiyun
2813*4882a593Smuzhiyun /* DA7218 Specific */
2814*4882a593Smuzhiyun if ((da7218->dev_id == DA7218_DEV_ID) &&
2815*4882a593Smuzhiyun (pdata->hpldet_pdata)) {
2816*4882a593Smuzhiyun struct da7218_hpldet_pdata *hpldet_pdata =
2817*4882a593Smuzhiyun pdata->hpldet_pdata;
2818*4882a593Smuzhiyun u8 hpldet_cfg = 0;
2819*4882a593Smuzhiyun
2820*4882a593Smuzhiyun switch (hpldet_pdata->jack_rate) {
2821*4882a593Smuzhiyun case DA7218_HPLDET_JACK_RATE_5US:
2822*4882a593Smuzhiyun case DA7218_HPLDET_JACK_RATE_10US:
2823*4882a593Smuzhiyun case DA7218_HPLDET_JACK_RATE_20US:
2824*4882a593Smuzhiyun case DA7218_HPLDET_JACK_RATE_40US:
2825*4882a593Smuzhiyun case DA7218_HPLDET_JACK_RATE_80US:
2826*4882a593Smuzhiyun case DA7218_HPLDET_JACK_RATE_160US:
2827*4882a593Smuzhiyun case DA7218_HPLDET_JACK_RATE_320US:
2828*4882a593Smuzhiyun case DA7218_HPLDET_JACK_RATE_640US:
2829*4882a593Smuzhiyun hpldet_cfg |=
2830*4882a593Smuzhiyun (hpldet_pdata->jack_rate <<
2831*4882a593Smuzhiyun DA7218_HPLDET_JACK_RATE_SHIFT);
2832*4882a593Smuzhiyun break;
2833*4882a593Smuzhiyun }
2834*4882a593Smuzhiyun
2835*4882a593Smuzhiyun switch (hpldet_pdata->jack_debounce) {
2836*4882a593Smuzhiyun case DA7218_HPLDET_JACK_DEBOUNCE_OFF:
2837*4882a593Smuzhiyun case DA7218_HPLDET_JACK_DEBOUNCE_2:
2838*4882a593Smuzhiyun case DA7218_HPLDET_JACK_DEBOUNCE_3:
2839*4882a593Smuzhiyun case DA7218_HPLDET_JACK_DEBOUNCE_4:
2840*4882a593Smuzhiyun hpldet_cfg |=
2841*4882a593Smuzhiyun (hpldet_pdata->jack_debounce <<
2842*4882a593Smuzhiyun DA7218_HPLDET_JACK_DEBOUNCE_SHIFT);
2843*4882a593Smuzhiyun break;
2844*4882a593Smuzhiyun }
2845*4882a593Smuzhiyun
2846*4882a593Smuzhiyun switch (hpldet_pdata->jack_thr) {
2847*4882a593Smuzhiyun case DA7218_HPLDET_JACK_THR_84PCT:
2848*4882a593Smuzhiyun case DA7218_HPLDET_JACK_THR_88PCT:
2849*4882a593Smuzhiyun case DA7218_HPLDET_JACK_THR_92PCT:
2850*4882a593Smuzhiyun case DA7218_HPLDET_JACK_THR_96PCT:
2851*4882a593Smuzhiyun hpldet_cfg |=
2852*4882a593Smuzhiyun (hpldet_pdata->jack_thr <<
2853*4882a593Smuzhiyun DA7218_HPLDET_JACK_THR_SHIFT);
2854*4882a593Smuzhiyun break;
2855*4882a593Smuzhiyun }
2856*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_HPLDET_JACK,
2857*4882a593Smuzhiyun DA7218_HPLDET_JACK_RATE_MASK |
2858*4882a593Smuzhiyun DA7218_HPLDET_JACK_DEBOUNCE_MASK |
2859*4882a593Smuzhiyun DA7218_HPLDET_JACK_THR_MASK,
2860*4882a593Smuzhiyun hpldet_cfg);
2861*4882a593Smuzhiyun
2862*4882a593Smuzhiyun hpldet_cfg = 0;
2863*4882a593Smuzhiyun if (hpldet_pdata->comp_inv)
2864*4882a593Smuzhiyun hpldet_cfg |= DA7218_HPLDET_COMP_INV_MASK;
2865*4882a593Smuzhiyun
2866*4882a593Smuzhiyun if (hpldet_pdata->hyst)
2867*4882a593Smuzhiyun hpldet_cfg |= DA7218_HPLDET_HYST_EN_MASK;
2868*4882a593Smuzhiyun
2869*4882a593Smuzhiyun if (hpldet_pdata->discharge)
2870*4882a593Smuzhiyun hpldet_cfg |= DA7218_HPLDET_DISCHARGE_EN_MASK;
2871*4882a593Smuzhiyun
2872*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_HPLDET_CTRL, hpldet_cfg);
2873*4882a593Smuzhiyun }
2874*4882a593Smuzhiyun }
2875*4882a593Smuzhiyun }
2876*4882a593Smuzhiyun
da7218_probe(struct snd_soc_component * component)2877*4882a593Smuzhiyun static int da7218_probe(struct snd_soc_component *component)
2878*4882a593Smuzhiyun {
2879*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
2880*4882a593Smuzhiyun int ret;
2881*4882a593Smuzhiyun
2882*4882a593Smuzhiyun /* Regulator configuration */
2883*4882a593Smuzhiyun ret = da7218_handle_supplies(component);
2884*4882a593Smuzhiyun if (ret)
2885*4882a593Smuzhiyun return ret;
2886*4882a593Smuzhiyun
2887*4882a593Smuzhiyun /* Handle DT/Platform data */
2888*4882a593Smuzhiyun if (component->dev->of_node)
2889*4882a593Smuzhiyun da7218->pdata = da7218_of_to_pdata(component);
2890*4882a593Smuzhiyun else
2891*4882a593Smuzhiyun da7218->pdata = dev_get_platdata(component->dev);
2892*4882a593Smuzhiyun
2893*4882a593Smuzhiyun da7218_handle_pdata(component);
2894*4882a593Smuzhiyun
2895*4882a593Smuzhiyun /* Check if MCLK provided, if not the clock is NULL */
2896*4882a593Smuzhiyun da7218->mclk = devm_clk_get(component->dev, "mclk");
2897*4882a593Smuzhiyun if (IS_ERR(da7218->mclk)) {
2898*4882a593Smuzhiyun if (PTR_ERR(da7218->mclk) != -ENOENT) {
2899*4882a593Smuzhiyun ret = PTR_ERR(da7218->mclk);
2900*4882a593Smuzhiyun goto err_disable_reg;
2901*4882a593Smuzhiyun } else {
2902*4882a593Smuzhiyun da7218->mclk = NULL;
2903*4882a593Smuzhiyun }
2904*4882a593Smuzhiyun }
2905*4882a593Smuzhiyun
2906*4882a593Smuzhiyun /* Default PC to free-running */
2907*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_PC_COUNT, DA7218_PC_FREERUN_MASK);
2908*4882a593Smuzhiyun
2909*4882a593Smuzhiyun /*
2910*4882a593Smuzhiyun * Default Output Filter mixers to off otherwise DAPM will power
2911*4882a593Smuzhiyun * Mic to HP passthrough paths by default at startup.
2912*4882a593Smuzhiyun */
2913*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_DROUTING_OUTFILT_1L, 0);
2914*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_DROUTING_OUTFILT_1R, 0);
2915*4882a593Smuzhiyun
2916*4882a593Smuzhiyun /* Default CP to normal load, power mode */
2917*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_CP_CTRL,
2918*4882a593Smuzhiyun DA7218_CP_SMALL_SWITCH_FREQ_EN_MASK, 0);
2919*4882a593Smuzhiyun
2920*4882a593Smuzhiyun /* Default gain ramping */
2921*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_MIXIN_1_CTRL,
2922*4882a593Smuzhiyun DA7218_MIXIN_1_AMP_RAMP_EN_MASK,
2923*4882a593Smuzhiyun DA7218_MIXIN_1_AMP_RAMP_EN_MASK);
2924*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_MIXIN_2_CTRL,
2925*4882a593Smuzhiyun DA7218_MIXIN_2_AMP_RAMP_EN_MASK,
2926*4882a593Smuzhiyun DA7218_MIXIN_2_AMP_RAMP_EN_MASK);
2927*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_IN_1L_FILTER_CTRL,
2928*4882a593Smuzhiyun DA7218_IN_1L_RAMP_EN_MASK,
2929*4882a593Smuzhiyun DA7218_IN_1L_RAMP_EN_MASK);
2930*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_IN_1R_FILTER_CTRL,
2931*4882a593Smuzhiyun DA7218_IN_1R_RAMP_EN_MASK,
2932*4882a593Smuzhiyun DA7218_IN_1R_RAMP_EN_MASK);
2933*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_IN_2L_FILTER_CTRL,
2934*4882a593Smuzhiyun DA7218_IN_2L_RAMP_EN_MASK,
2935*4882a593Smuzhiyun DA7218_IN_2L_RAMP_EN_MASK);
2936*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_IN_2R_FILTER_CTRL,
2937*4882a593Smuzhiyun DA7218_IN_2R_RAMP_EN_MASK,
2938*4882a593Smuzhiyun DA7218_IN_2R_RAMP_EN_MASK);
2939*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_DGS_GAIN_CTRL,
2940*4882a593Smuzhiyun DA7218_DGS_RAMP_EN_MASK, DA7218_DGS_RAMP_EN_MASK);
2941*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_OUT_1L_FILTER_CTRL,
2942*4882a593Smuzhiyun DA7218_OUT_1L_RAMP_EN_MASK,
2943*4882a593Smuzhiyun DA7218_OUT_1L_RAMP_EN_MASK);
2944*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_OUT_1R_FILTER_CTRL,
2945*4882a593Smuzhiyun DA7218_OUT_1R_RAMP_EN_MASK,
2946*4882a593Smuzhiyun DA7218_OUT_1R_RAMP_EN_MASK);
2947*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_HP_L_CTRL,
2948*4882a593Smuzhiyun DA7218_HP_L_AMP_RAMP_EN_MASK,
2949*4882a593Smuzhiyun DA7218_HP_L_AMP_RAMP_EN_MASK);
2950*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_HP_R_CTRL,
2951*4882a593Smuzhiyun DA7218_HP_R_AMP_RAMP_EN_MASK,
2952*4882a593Smuzhiyun DA7218_HP_R_AMP_RAMP_EN_MASK);
2953*4882a593Smuzhiyun
2954*4882a593Smuzhiyun /* Default infinite tone gen, start/stop by Kcontrol */
2955*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_TONE_GEN_CYCLES, DA7218_BEEP_CYCLES_MASK);
2956*4882a593Smuzhiyun
2957*4882a593Smuzhiyun /* DA7217 specific config */
2958*4882a593Smuzhiyun if (da7218->dev_id == DA7217_DEV_ID) {
2959*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7218_HP_DIFF_CTRL,
2960*4882a593Smuzhiyun DA7218_HP_AMP_DIFF_MODE_EN_MASK,
2961*4882a593Smuzhiyun DA7218_HP_AMP_DIFF_MODE_EN_MASK);
2962*4882a593Smuzhiyun
2963*4882a593Smuzhiyun /* Only DA7218 supports HP detect, mask off for DA7217 */
2964*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_EVENT_MASK,
2965*4882a593Smuzhiyun DA7218_HPLDET_JACK_EVENT_IRQ_MSK_MASK);
2966*4882a593Smuzhiyun }
2967*4882a593Smuzhiyun
2968*4882a593Smuzhiyun if (da7218->irq) {
2969*4882a593Smuzhiyun ret = devm_request_threaded_irq(component->dev, da7218->irq, NULL,
2970*4882a593Smuzhiyun da7218_irq_thread,
2971*4882a593Smuzhiyun IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2972*4882a593Smuzhiyun "da7218", component);
2973*4882a593Smuzhiyun if (ret != 0) {
2974*4882a593Smuzhiyun dev_err(component->dev, "Failed to request IRQ %d: %d\n",
2975*4882a593Smuzhiyun da7218->irq, ret);
2976*4882a593Smuzhiyun goto err_disable_reg;
2977*4882a593Smuzhiyun }
2978*4882a593Smuzhiyun
2979*4882a593Smuzhiyun }
2980*4882a593Smuzhiyun
2981*4882a593Smuzhiyun return 0;
2982*4882a593Smuzhiyun
2983*4882a593Smuzhiyun err_disable_reg:
2984*4882a593Smuzhiyun regulator_bulk_disable(DA7218_NUM_SUPPLIES, da7218->supplies);
2985*4882a593Smuzhiyun
2986*4882a593Smuzhiyun return ret;
2987*4882a593Smuzhiyun }
2988*4882a593Smuzhiyun
da7218_remove(struct snd_soc_component * component)2989*4882a593Smuzhiyun static void da7218_remove(struct snd_soc_component *component)
2990*4882a593Smuzhiyun {
2991*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
2992*4882a593Smuzhiyun
2993*4882a593Smuzhiyun regulator_bulk_disable(DA7218_NUM_SUPPLIES, da7218->supplies);
2994*4882a593Smuzhiyun }
2995*4882a593Smuzhiyun
2996*4882a593Smuzhiyun #ifdef CONFIG_PM
da7218_suspend(struct snd_soc_component * component)2997*4882a593Smuzhiyun static int da7218_suspend(struct snd_soc_component *component)
2998*4882a593Smuzhiyun {
2999*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
3000*4882a593Smuzhiyun
3001*4882a593Smuzhiyun da7218_set_bias_level(component, SND_SOC_BIAS_OFF);
3002*4882a593Smuzhiyun
3003*4882a593Smuzhiyun /* Put device into standby mode if jack detection disabled */
3004*4882a593Smuzhiyun if (!da7218->jack)
3005*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_SYSTEM_ACTIVE, 0);
3006*4882a593Smuzhiyun
3007*4882a593Smuzhiyun return 0;
3008*4882a593Smuzhiyun }
3009*4882a593Smuzhiyun
da7218_resume(struct snd_soc_component * component)3010*4882a593Smuzhiyun static int da7218_resume(struct snd_soc_component *component)
3011*4882a593Smuzhiyun {
3012*4882a593Smuzhiyun struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
3013*4882a593Smuzhiyun
3014*4882a593Smuzhiyun /* Put device into active mode if previously moved to standby */
3015*4882a593Smuzhiyun if (!da7218->jack)
3016*4882a593Smuzhiyun snd_soc_component_write(component, DA7218_SYSTEM_ACTIVE,
3017*4882a593Smuzhiyun DA7218_SYSTEM_ACTIVE_MASK);
3018*4882a593Smuzhiyun
3019*4882a593Smuzhiyun da7218_set_bias_level(component, SND_SOC_BIAS_STANDBY);
3020*4882a593Smuzhiyun
3021*4882a593Smuzhiyun return 0;
3022*4882a593Smuzhiyun }
3023*4882a593Smuzhiyun #else
3024*4882a593Smuzhiyun #define da7218_suspend NULL
3025*4882a593Smuzhiyun #define da7218_resume NULL
3026*4882a593Smuzhiyun #endif
3027*4882a593Smuzhiyun
3028*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_da7218 = {
3029*4882a593Smuzhiyun .probe = da7218_probe,
3030*4882a593Smuzhiyun .remove = da7218_remove,
3031*4882a593Smuzhiyun .suspend = da7218_suspend,
3032*4882a593Smuzhiyun .resume = da7218_resume,
3033*4882a593Smuzhiyun .set_bias_level = da7218_set_bias_level,
3034*4882a593Smuzhiyun .controls = da7218_snd_controls,
3035*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(da7218_snd_controls),
3036*4882a593Smuzhiyun .dapm_widgets = da7218_dapm_widgets,
3037*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(da7218_dapm_widgets),
3038*4882a593Smuzhiyun .dapm_routes = da7218_audio_map,
3039*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(da7218_audio_map),
3040*4882a593Smuzhiyun .idle_bias_on = 1,
3041*4882a593Smuzhiyun .use_pmdown_time = 1,
3042*4882a593Smuzhiyun .endianness = 1,
3043*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
3044*4882a593Smuzhiyun };
3045*4882a593Smuzhiyun
3046*4882a593Smuzhiyun
3047*4882a593Smuzhiyun /*
3048*4882a593Smuzhiyun * Regmap configs
3049*4882a593Smuzhiyun */
3050*4882a593Smuzhiyun
3051*4882a593Smuzhiyun static struct reg_default da7218_reg_defaults[] = {
3052*4882a593Smuzhiyun { DA7218_SYSTEM_ACTIVE, 0x00 },
3053*4882a593Smuzhiyun { DA7218_CIF_CTRL, 0x00 },
3054*4882a593Smuzhiyun { DA7218_SPARE1, 0x00 },
3055*4882a593Smuzhiyun { DA7218_SR, 0xAA },
3056*4882a593Smuzhiyun { DA7218_PC_COUNT, 0x02 },
3057*4882a593Smuzhiyun { DA7218_GAIN_RAMP_CTRL, 0x00 },
3058*4882a593Smuzhiyun { DA7218_CIF_TIMEOUT_CTRL, 0x01 },
3059*4882a593Smuzhiyun { DA7218_SYSTEM_MODES_INPUT, 0x00 },
3060*4882a593Smuzhiyun { DA7218_SYSTEM_MODES_OUTPUT, 0x00 },
3061*4882a593Smuzhiyun { DA7218_IN_1L_FILTER_CTRL, 0x00 },
3062*4882a593Smuzhiyun { DA7218_IN_1R_FILTER_CTRL, 0x00 },
3063*4882a593Smuzhiyun { DA7218_IN_2L_FILTER_CTRL, 0x00 },
3064*4882a593Smuzhiyun { DA7218_IN_2R_FILTER_CTRL, 0x00 },
3065*4882a593Smuzhiyun { DA7218_OUT_1L_FILTER_CTRL, 0x40 },
3066*4882a593Smuzhiyun { DA7218_OUT_1R_FILTER_CTRL, 0x40 },
3067*4882a593Smuzhiyun { DA7218_OUT_1_HPF_FILTER_CTRL, 0x80 },
3068*4882a593Smuzhiyun { DA7218_OUT_1_EQ_12_FILTER_CTRL, 0x77 },
3069*4882a593Smuzhiyun { DA7218_OUT_1_EQ_34_FILTER_CTRL, 0x77 },
3070*4882a593Smuzhiyun { DA7218_OUT_1_EQ_5_FILTER_CTRL, 0x07 },
3071*4882a593Smuzhiyun { DA7218_OUT_1_BIQ_5STAGE_CTRL, 0x40 },
3072*4882a593Smuzhiyun { DA7218_OUT_1_BIQ_5STAGE_DATA, 0x00 },
3073*4882a593Smuzhiyun { DA7218_OUT_1_BIQ_5STAGE_ADDR, 0x00 },
3074*4882a593Smuzhiyun { DA7218_MIXIN_1_CTRL, 0x48 },
3075*4882a593Smuzhiyun { DA7218_MIXIN_1_GAIN, 0x03 },
3076*4882a593Smuzhiyun { DA7218_MIXIN_2_CTRL, 0x48 },
3077*4882a593Smuzhiyun { DA7218_MIXIN_2_GAIN, 0x03 },
3078*4882a593Smuzhiyun { DA7218_ALC_CTRL1, 0x00 },
3079*4882a593Smuzhiyun { DA7218_ALC_CTRL2, 0x00 },
3080*4882a593Smuzhiyun { DA7218_ALC_CTRL3, 0x00 },
3081*4882a593Smuzhiyun { DA7218_ALC_NOISE, 0x3F },
3082*4882a593Smuzhiyun { DA7218_ALC_TARGET_MIN, 0x3F },
3083*4882a593Smuzhiyun { DA7218_ALC_TARGET_MAX, 0x00 },
3084*4882a593Smuzhiyun { DA7218_ALC_GAIN_LIMITS, 0xFF },
3085*4882a593Smuzhiyun { DA7218_ALC_ANA_GAIN_LIMITS, 0x71 },
3086*4882a593Smuzhiyun { DA7218_ALC_ANTICLIP_CTRL, 0x00 },
3087*4882a593Smuzhiyun { DA7218_AGS_ENABLE, 0x00 },
3088*4882a593Smuzhiyun { DA7218_AGS_TRIGGER, 0x09 },
3089*4882a593Smuzhiyun { DA7218_AGS_ATT_MAX, 0x00 },
3090*4882a593Smuzhiyun { DA7218_AGS_TIMEOUT, 0x00 },
3091*4882a593Smuzhiyun { DA7218_AGS_ANTICLIP_CTRL, 0x00 },
3092*4882a593Smuzhiyun { DA7218_ENV_TRACK_CTRL, 0x00 },
3093*4882a593Smuzhiyun { DA7218_LVL_DET_CTRL, 0x00 },
3094*4882a593Smuzhiyun { DA7218_LVL_DET_LEVEL, 0x7F },
3095*4882a593Smuzhiyun { DA7218_DGS_TRIGGER, 0x24 },
3096*4882a593Smuzhiyun { DA7218_DGS_ENABLE, 0x00 },
3097*4882a593Smuzhiyun { DA7218_DGS_RISE_FALL, 0x50 },
3098*4882a593Smuzhiyun { DA7218_DGS_SYNC_DELAY, 0xA3 },
3099*4882a593Smuzhiyun { DA7218_DGS_SYNC_DELAY2, 0x31 },
3100*4882a593Smuzhiyun { DA7218_DGS_SYNC_DELAY3, 0x11 },
3101*4882a593Smuzhiyun { DA7218_DGS_LEVELS, 0x01 },
3102*4882a593Smuzhiyun { DA7218_DGS_GAIN_CTRL, 0x74 },
3103*4882a593Smuzhiyun { DA7218_DROUTING_OUTDAI_1L, 0x01 },
3104*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1L_INFILT_1L_GAIN, 0x1C },
3105*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1L_INFILT_1R_GAIN, 0x1C },
3106*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1L_INFILT_2L_GAIN, 0x1C },
3107*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1L_INFILT_2R_GAIN, 0x1C },
3108*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1L_TONEGEN_GAIN, 0x1C },
3109*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1L_INDAI_1L_GAIN, 0x1C },
3110*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1L_INDAI_1R_GAIN, 0x1C },
3111*4882a593Smuzhiyun { DA7218_DROUTING_OUTDAI_1R, 0x04 },
3112*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1R_INFILT_1L_GAIN, 0x1C },
3113*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1R_INFILT_1R_GAIN, 0x1C },
3114*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1R_INFILT_2L_GAIN, 0x1C },
3115*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1R_INFILT_2R_GAIN, 0x1C },
3116*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1R_TONEGEN_GAIN, 0x1C },
3117*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1R_INDAI_1L_GAIN, 0x1C },
3118*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_1R_INDAI_1R_GAIN, 0x1C },
3119*4882a593Smuzhiyun { DA7218_DROUTING_OUTFILT_1L, 0x01 },
3120*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1L_INFILT_1L_GAIN, 0x1C },
3121*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1L_INFILT_1R_GAIN, 0x1C },
3122*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1L_INFILT_2L_GAIN, 0x1C },
3123*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1L_INFILT_2R_GAIN, 0x1C },
3124*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1L_TONEGEN_GAIN, 0x1C },
3125*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1L_INDAI_1L_GAIN, 0x1C },
3126*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1L_INDAI_1R_GAIN, 0x1C },
3127*4882a593Smuzhiyun { DA7218_DROUTING_OUTFILT_1R, 0x04 },
3128*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1R_INFILT_1L_GAIN, 0x1C },
3129*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1R_INFILT_1R_GAIN, 0x1C },
3130*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1R_INFILT_2L_GAIN, 0x1C },
3131*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1R_INFILT_2R_GAIN, 0x1C },
3132*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1R_TONEGEN_GAIN, 0x1C },
3133*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1R_INDAI_1L_GAIN, 0x1C },
3134*4882a593Smuzhiyun { DA7218_DMIX_OUTFILT_1R_INDAI_1R_GAIN, 0x1C },
3135*4882a593Smuzhiyun { DA7218_DROUTING_OUTDAI_2L, 0x04 },
3136*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2L_INFILT_1L_GAIN, 0x1C },
3137*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2L_INFILT_1R_GAIN, 0x1C },
3138*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2L_INFILT_2L_GAIN, 0x1C },
3139*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2L_INFILT_2R_GAIN, 0x1C },
3140*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2L_TONEGEN_GAIN, 0x1C },
3141*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2L_INDAI_1L_GAIN, 0x1C },
3142*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2L_INDAI_1R_GAIN, 0x1C },
3143*4882a593Smuzhiyun { DA7218_DROUTING_OUTDAI_2R, 0x08 },
3144*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2R_INFILT_1L_GAIN, 0x1C },
3145*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2R_INFILT_1R_GAIN, 0x1C },
3146*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2R_INFILT_2L_GAIN, 0x1C },
3147*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2R_INFILT_2R_GAIN, 0x1C },
3148*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2R_TONEGEN_GAIN, 0x1C },
3149*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2R_INDAI_1L_GAIN, 0x1C },
3150*4882a593Smuzhiyun { DA7218_DMIX_OUTDAI_2R_INDAI_1R_GAIN, 0x1C },
3151*4882a593Smuzhiyun { DA7218_DAI_CTRL, 0x28 },
3152*4882a593Smuzhiyun { DA7218_DAI_TDM_CTRL, 0x40 },
3153*4882a593Smuzhiyun { DA7218_DAI_OFFSET_LOWER, 0x00 },
3154*4882a593Smuzhiyun { DA7218_DAI_OFFSET_UPPER, 0x00 },
3155*4882a593Smuzhiyun { DA7218_DAI_CLK_MODE, 0x01 },
3156*4882a593Smuzhiyun { DA7218_PLL_CTRL, 0x04 },
3157*4882a593Smuzhiyun { DA7218_PLL_FRAC_TOP, 0x00 },
3158*4882a593Smuzhiyun { DA7218_PLL_FRAC_BOT, 0x00 },
3159*4882a593Smuzhiyun { DA7218_PLL_INTEGER, 0x20 },
3160*4882a593Smuzhiyun { DA7218_DAC_NG_CTRL, 0x00 },
3161*4882a593Smuzhiyun { DA7218_DAC_NG_SETUP_TIME, 0x00 },
3162*4882a593Smuzhiyun { DA7218_DAC_NG_OFF_THRESH, 0x00 },
3163*4882a593Smuzhiyun { DA7218_DAC_NG_ON_THRESH, 0x00 },
3164*4882a593Smuzhiyun { DA7218_TONE_GEN_CFG2, 0x00 },
3165*4882a593Smuzhiyun { DA7218_TONE_GEN_FREQ1_L, 0x55 },
3166*4882a593Smuzhiyun { DA7218_TONE_GEN_FREQ1_U, 0x15 },
3167*4882a593Smuzhiyun { DA7218_TONE_GEN_FREQ2_L, 0x00 },
3168*4882a593Smuzhiyun { DA7218_TONE_GEN_FREQ2_U, 0x40 },
3169*4882a593Smuzhiyun { DA7218_TONE_GEN_CYCLES, 0x00 },
3170*4882a593Smuzhiyun { DA7218_TONE_GEN_ON_PER, 0x02 },
3171*4882a593Smuzhiyun { DA7218_TONE_GEN_OFF_PER, 0x01 },
3172*4882a593Smuzhiyun { DA7218_CP_CTRL, 0x60 },
3173*4882a593Smuzhiyun { DA7218_CP_DELAY, 0x11 },
3174*4882a593Smuzhiyun { DA7218_CP_VOL_THRESHOLD1, 0x0E },
3175*4882a593Smuzhiyun { DA7218_MIC_1_CTRL, 0x40 },
3176*4882a593Smuzhiyun { DA7218_MIC_1_GAIN, 0x01 },
3177*4882a593Smuzhiyun { DA7218_MIC_1_SELECT, 0x00 },
3178*4882a593Smuzhiyun { DA7218_MIC_2_CTRL, 0x40 },
3179*4882a593Smuzhiyun { DA7218_MIC_2_GAIN, 0x01 },
3180*4882a593Smuzhiyun { DA7218_MIC_2_SELECT, 0x00 },
3181*4882a593Smuzhiyun { DA7218_IN_1_HPF_FILTER_CTRL, 0x80 },
3182*4882a593Smuzhiyun { DA7218_IN_2_HPF_FILTER_CTRL, 0x80 },
3183*4882a593Smuzhiyun { DA7218_ADC_1_CTRL, 0x07 },
3184*4882a593Smuzhiyun { DA7218_ADC_2_CTRL, 0x07 },
3185*4882a593Smuzhiyun { DA7218_MIXOUT_L_CTRL, 0x00 },
3186*4882a593Smuzhiyun { DA7218_MIXOUT_L_GAIN, 0x03 },
3187*4882a593Smuzhiyun { DA7218_MIXOUT_R_CTRL, 0x00 },
3188*4882a593Smuzhiyun { DA7218_MIXOUT_R_GAIN, 0x03 },
3189*4882a593Smuzhiyun { DA7218_HP_L_CTRL, 0x40 },
3190*4882a593Smuzhiyun { DA7218_HP_L_GAIN, 0x3B },
3191*4882a593Smuzhiyun { DA7218_HP_R_CTRL, 0x40 },
3192*4882a593Smuzhiyun { DA7218_HP_R_GAIN, 0x3B },
3193*4882a593Smuzhiyun { DA7218_HP_DIFF_CTRL, 0x00 },
3194*4882a593Smuzhiyun { DA7218_HP_DIFF_UNLOCK, 0xC3 },
3195*4882a593Smuzhiyun { DA7218_HPLDET_JACK, 0x0B },
3196*4882a593Smuzhiyun { DA7218_HPLDET_CTRL, 0x00 },
3197*4882a593Smuzhiyun { DA7218_REFERENCES, 0x08 },
3198*4882a593Smuzhiyun { DA7218_IO_CTRL, 0x00 },
3199*4882a593Smuzhiyun { DA7218_LDO_CTRL, 0x00 },
3200*4882a593Smuzhiyun { DA7218_SIDETONE_CTRL, 0x40 },
3201*4882a593Smuzhiyun { DA7218_SIDETONE_IN_SELECT, 0x00 },
3202*4882a593Smuzhiyun { DA7218_SIDETONE_GAIN, 0x1C },
3203*4882a593Smuzhiyun { DA7218_DROUTING_ST_OUTFILT_1L, 0x01 },
3204*4882a593Smuzhiyun { DA7218_DROUTING_ST_OUTFILT_1R, 0x02 },
3205*4882a593Smuzhiyun { DA7218_SIDETONE_BIQ_3STAGE_DATA, 0x00 },
3206*4882a593Smuzhiyun { DA7218_SIDETONE_BIQ_3STAGE_ADDR, 0x00 },
3207*4882a593Smuzhiyun { DA7218_EVENT_MASK, 0x00 },
3208*4882a593Smuzhiyun { DA7218_DMIC_1_CTRL, 0x00 },
3209*4882a593Smuzhiyun { DA7218_DMIC_2_CTRL, 0x00 },
3210*4882a593Smuzhiyun { DA7218_IN_1L_GAIN, 0x6F },
3211*4882a593Smuzhiyun { DA7218_IN_1R_GAIN, 0x6F },
3212*4882a593Smuzhiyun { DA7218_IN_2L_GAIN, 0x6F },
3213*4882a593Smuzhiyun { DA7218_IN_2R_GAIN, 0x6F },
3214*4882a593Smuzhiyun { DA7218_OUT_1L_GAIN, 0x6F },
3215*4882a593Smuzhiyun { DA7218_OUT_1R_GAIN, 0x6F },
3216*4882a593Smuzhiyun { DA7218_MICBIAS_CTRL, 0x00 },
3217*4882a593Smuzhiyun { DA7218_MICBIAS_EN, 0x00 },
3218*4882a593Smuzhiyun };
3219*4882a593Smuzhiyun
da7218_volatile_register(struct device * dev,unsigned int reg)3220*4882a593Smuzhiyun static bool da7218_volatile_register(struct device *dev, unsigned int reg)
3221*4882a593Smuzhiyun {
3222*4882a593Smuzhiyun switch (reg) {
3223*4882a593Smuzhiyun case DA7218_STATUS1:
3224*4882a593Smuzhiyun case DA7218_SOFT_RESET:
3225*4882a593Smuzhiyun case DA7218_SYSTEM_STATUS:
3226*4882a593Smuzhiyun case DA7218_CALIB_CTRL:
3227*4882a593Smuzhiyun case DA7218_CALIB_OFFSET_AUTO_M_1:
3228*4882a593Smuzhiyun case DA7218_CALIB_OFFSET_AUTO_U_1:
3229*4882a593Smuzhiyun case DA7218_CALIB_OFFSET_AUTO_M_2:
3230*4882a593Smuzhiyun case DA7218_CALIB_OFFSET_AUTO_U_2:
3231*4882a593Smuzhiyun case DA7218_PLL_STATUS:
3232*4882a593Smuzhiyun case DA7218_PLL_REFOSC_CAL:
3233*4882a593Smuzhiyun case DA7218_TONE_GEN_CFG1:
3234*4882a593Smuzhiyun case DA7218_ADC_MODE:
3235*4882a593Smuzhiyun case DA7218_HP_SNGL_CTRL:
3236*4882a593Smuzhiyun case DA7218_HPLDET_TEST:
3237*4882a593Smuzhiyun case DA7218_EVENT_STATUS:
3238*4882a593Smuzhiyun case DA7218_EVENT:
3239*4882a593Smuzhiyun return true;
3240*4882a593Smuzhiyun default:
3241*4882a593Smuzhiyun return false;
3242*4882a593Smuzhiyun }
3243*4882a593Smuzhiyun }
3244*4882a593Smuzhiyun
3245*4882a593Smuzhiyun static const struct regmap_config da7218_regmap_config = {
3246*4882a593Smuzhiyun .reg_bits = 8,
3247*4882a593Smuzhiyun .val_bits = 8,
3248*4882a593Smuzhiyun
3249*4882a593Smuzhiyun .max_register = DA7218_MICBIAS_EN,
3250*4882a593Smuzhiyun .reg_defaults = da7218_reg_defaults,
3251*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(da7218_reg_defaults),
3252*4882a593Smuzhiyun .volatile_reg = da7218_volatile_register,
3253*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
3254*4882a593Smuzhiyun };
3255*4882a593Smuzhiyun
3256*4882a593Smuzhiyun
3257*4882a593Smuzhiyun /*
3258*4882a593Smuzhiyun * I2C layer
3259*4882a593Smuzhiyun */
3260*4882a593Smuzhiyun
da7218_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)3261*4882a593Smuzhiyun static int da7218_i2c_probe(struct i2c_client *i2c,
3262*4882a593Smuzhiyun const struct i2c_device_id *id)
3263*4882a593Smuzhiyun {
3264*4882a593Smuzhiyun struct da7218_priv *da7218;
3265*4882a593Smuzhiyun int ret;
3266*4882a593Smuzhiyun
3267*4882a593Smuzhiyun da7218 = devm_kzalloc(&i2c->dev, sizeof(*da7218), GFP_KERNEL);
3268*4882a593Smuzhiyun if (!da7218)
3269*4882a593Smuzhiyun return -ENOMEM;
3270*4882a593Smuzhiyun
3271*4882a593Smuzhiyun i2c_set_clientdata(i2c, da7218);
3272*4882a593Smuzhiyun
3273*4882a593Smuzhiyun if (i2c->dev.of_node)
3274*4882a593Smuzhiyun da7218->dev_id = da7218_of_get_id(&i2c->dev);
3275*4882a593Smuzhiyun else
3276*4882a593Smuzhiyun da7218->dev_id = id->driver_data;
3277*4882a593Smuzhiyun
3278*4882a593Smuzhiyun if ((da7218->dev_id != DA7217_DEV_ID) &&
3279*4882a593Smuzhiyun (da7218->dev_id != DA7218_DEV_ID)) {
3280*4882a593Smuzhiyun dev_err(&i2c->dev, "Invalid device Id\n");
3281*4882a593Smuzhiyun return -EINVAL;
3282*4882a593Smuzhiyun }
3283*4882a593Smuzhiyun
3284*4882a593Smuzhiyun da7218->irq = i2c->irq;
3285*4882a593Smuzhiyun
3286*4882a593Smuzhiyun da7218->regmap = devm_regmap_init_i2c(i2c, &da7218_regmap_config);
3287*4882a593Smuzhiyun if (IS_ERR(da7218->regmap)) {
3288*4882a593Smuzhiyun ret = PTR_ERR(da7218->regmap);
3289*4882a593Smuzhiyun dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
3290*4882a593Smuzhiyun return ret;
3291*4882a593Smuzhiyun }
3292*4882a593Smuzhiyun
3293*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev,
3294*4882a593Smuzhiyun &soc_component_dev_da7218, &da7218_dai, 1);
3295*4882a593Smuzhiyun if (ret < 0) {
3296*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to register da7218 component: %d\n",
3297*4882a593Smuzhiyun ret);
3298*4882a593Smuzhiyun }
3299*4882a593Smuzhiyun return ret;
3300*4882a593Smuzhiyun }
3301*4882a593Smuzhiyun
3302*4882a593Smuzhiyun static const struct i2c_device_id da7218_i2c_id[] = {
3303*4882a593Smuzhiyun { "da7217", DA7217_DEV_ID },
3304*4882a593Smuzhiyun { "da7218", DA7218_DEV_ID },
3305*4882a593Smuzhiyun { }
3306*4882a593Smuzhiyun };
3307*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, da7218_i2c_id);
3308*4882a593Smuzhiyun
3309*4882a593Smuzhiyun static struct i2c_driver da7218_i2c_driver = {
3310*4882a593Smuzhiyun .driver = {
3311*4882a593Smuzhiyun .name = "da7218",
3312*4882a593Smuzhiyun .of_match_table = of_match_ptr(da7218_of_match),
3313*4882a593Smuzhiyun },
3314*4882a593Smuzhiyun .probe = da7218_i2c_probe,
3315*4882a593Smuzhiyun .id_table = da7218_i2c_id,
3316*4882a593Smuzhiyun };
3317*4882a593Smuzhiyun
3318*4882a593Smuzhiyun module_i2c_driver(da7218_i2c_driver);
3319*4882a593Smuzhiyun
3320*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC DA7218 Codec driver");
3321*4882a593Smuzhiyun MODULE_AUTHOR("Adam Thomson <Adam.Thomson.Opensource@diasemi.com>");
3322*4882a593Smuzhiyun MODULE_LICENSE("GPL");
3323