1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * DA7213 ALSA SoC Codec Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2013 Dialog Semiconductor
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
8*4882a593Smuzhiyun * Based on DA9055 ALSA SoC codec driver.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/acpi.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/property.h>
14*4882a593Smuzhiyun #include <linux/clk.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <sound/pcm.h>
21*4882a593Smuzhiyun #include <sound/pcm_params.h>
22*4882a593Smuzhiyun #include <linux/pm_runtime.h>
23*4882a593Smuzhiyun #include <sound/soc.h>
24*4882a593Smuzhiyun #include <sound/initval.h>
25*4882a593Smuzhiyun #include <sound/tlv.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <sound/da7213.h>
28*4882a593Smuzhiyun #include "da7213.h"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Gain and Volume */
32*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(aux_vol_tlv,
33*4882a593Smuzhiyun /* -54dB */
34*4882a593Smuzhiyun 0x0, 0x11, TLV_DB_SCALE_ITEM(-5400, 0, 0),
35*4882a593Smuzhiyun /* -52.5dB to 15dB */
36*4882a593Smuzhiyun 0x12, 0x3f, TLV_DB_SCALE_ITEM(-5250, 150, 0)
37*4882a593Smuzhiyun );
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(digital_gain_tlv,
40*4882a593Smuzhiyun 0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
41*4882a593Smuzhiyun /* -78dB to 12dB */
42*4882a593Smuzhiyun 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
43*4882a593Smuzhiyun );
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(alc_analog_gain_tlv,
46*4882a593Smuzhiyun 0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
47*4882a593Smuzhiyun /* 0dB to 36dB */
48*4882a593Smuzhiyun 0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0)
49*4882a593Smuzhiyun );
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
52*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
53*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
54*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
55*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
56*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
57*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* ADC and DAC voice mode (8kHz) high pass cutoff value */
60*4882a593Smuzhiyun static const char * const da7213_voice_hpf_corner_txt[] = {
61*4882a593Smuzhiyun "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_dac_voice_hpf_corner,
65*4882a593Smuzhiyun DA7213_DAC_FILTERS1,
66*4882a593Smuzhiyun DA7213_VOICE_HPF_CORNER_SHIFT,
67*4882a593Smuzhiyun da7213_voice_hpf_corner_txt);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_adc_voice_hpf_corner,
70*4882a593Smuzhiyun DA7213_ADC_FILTERS1,
71*4882a593Smuzhiyun DA7213_VOICE_HPF_CORNER_SHIFT,
72*4882a593Smuzhiyun da7213_voice_hpf_corner_txt);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* ADC and DAC high pass filter cutoff value */
75*4882a593Smuzhiyun static const char * const da7213_audio_hpf_corner_txt[] = {
76*4882a593Smuzhiyun "Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000"
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_dac_audio_hpf_corner,
80*4882a593Smuzhiyun DA7213_DAC_FILTERS1
81*4882a593Smuzhiyun , DA7213_AUDIO_HPF_CORNER_SHIFT,
82*4882a593Smuzhiyun da7213_audio_hpf_corner_txt);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_adc_audio_hpf_corner,
85*4882a593Smuzhiyun DA7213_ADC_FILTERS1,
86*4882a593Smuzhiyun DA7213_AUDIO_HPF_CORNER_SHIFT,
87*4882a593Smuzhiyun da7213_audio_hpf_corner_txt);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Gain ramping rate value */
90*4882a593Smuzhiyun static const char * const da7213_gain_ramp_rate_txt[] = {
91*4882a593Smuzhiyun "nominal rate * 8", "nominal rate * 16", "nominal rate / 16",
92*4882a593Smuzhiyun "nominal rate / 32"
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_gain_ramp_rate,
96*4882a593Smuzhiyun DA7213_GAIN_RAMP_CTRL,
97*4882a593Smuzhiyun DA7213_GAIN_RAMP_RATE_SHIFT,
98*4882a593Smuzhiyun da7213_gain_ramp_rate_txt);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* DAC noise gate setup time value */
101*4882a593Smuzhiyun static const char * const da7213_dac_ng_setup_time_txt[] = {
102*4882a593Smuzhiyun "256 samples", "512 samples", "1024 samples", "2048 samples"
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_dac_ng_setup_time,
106*4882a593Smuzhiyun DA7213_DAC_NG_SETUP_TIME,
107*4882a593Smuzhiyun DA7213_DAC_NG_SETUP_TIME_SHIFT,
108*4882a593Smuzhiyun da7213_dac_ng_setup_time_txt);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* DAC noise gate rampup rate value */
111*4882a593Smuzhiyun static const char * const da7213_dac_ng_rampup_txt[] = {
112*4882a593Smuzhiyun "0.02 ms/dB", "0.16 ms/dB"
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_dac_ng_rampup_rate,
116*4882a593Smuzhiyun DA7213_DAC_NG_SETUP_TIME,
117*4882a593Smuzhiyun DA7213_DAC_NG_RAMPUP_RATE_SHIFT,
118*4882a593Smuzhiyun da7213_dac_ng_rampup_txt);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* DAC noise gate rampdown rate value */
121*4882a593Smuzhiyun static const char * const da7213_dac_ng_rampdown_txt[] = {
122*4882a593Smuzhiyun "0.64 ms/dB", "20.48 ms/dB"
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_dac_ng_rampdown_rate,
126*4882a593Smuzhiyun DA7213_DAC_NG_SETUP_TIME,
127*4882a593Smuzhiyun DA7213_DAC_NG_RAMPDN_RATE_SHIFT,
128*4882a593Smuzhiyun da7213_dac_ng_rampdown_txt);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* DAC soft mute rate value */
131*4882a593Smuzhiyun static const char * const da7213_dac_soft_mute_rate_txt[] = {
132*4882a593Smuzhiyun "1", "2", "4", "8", "16", "32", "64"
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_dac_soft_mute_rate,
136*4882a593Smuzhiyun DA7213_DAC_FILTERS5,
137*4882a593Smuzhiyun DA7213_DAC_SOFTMUTE_RATE_SHIFT,
138*4882a593Smuzhiyun da7213_dac_soft_mute_rate_txt);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* ALC Attack Rate select */
141*4882a593Smuzhiyun static const char * const da7213_alc_attack_rate_txt[] = {
142*4882a593Smuzhiyun "44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs",
143*4882a593Smuzhiyun "5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_alc_attack_rate,
147*4882a593Smuzhiyun DA7213_ALC_CTRL2,
148*4882a593Smuzhiyun DA7213_ALC_ATTACK_SHIFT,
149*4882a593Smuzhiyun da7213_alc_attack_rate_txt);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /* ALC Release Rate select */
152*4882a593Smuzhiyun static const char * const da7213_alc_release_rate_txt[] = {
153*4882a593Smuzhiyun "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs",
154*4882a593Smuzhiyun "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_alc_release_rate,
158*4882a593Smuzhiyun DA7213_ALC_CTRL2,
159*4882a593Smuzhiyun DA7213_ALC_RELEASE_SHIFT,
160*4882a593Smuzhiyun da7213_alc_release_rate_txt);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* ALC Hold Time select */
163*4882a593Smuzhiyun static const char * const da7213_alc_hold_time_txt[] = {
164*4882a593Smuzhiyun "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
165*4882a593Smuzhiyun "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
166*4882a593Smuzhiyun "253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_alc_hold_time,
170*4882a593Smuzhiyun DA7213_ALC_CTRL3,
171*4882a593Smuzhiyun DA7213_ALC_HOLD_SHIFT,
172*4882a593Smuzhiyun da7213_alc_hold_time_txt);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /* ALC Input Signal Tracking rate select */
175*4882a593Smuzhiyun static const char * const da7213_alc_integ_rate_txt[] = {
176*4882a593Smuzhiyun "1/4", "1/16", "1/256", "1/65536"
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_alc_integ_attack_rate,
180*4882a593Smuzhiyun DA7213_ALC_CTRL3,
181*4882a593Smuzhiyun DA7213_ALC_INTEG_ATTACK_SHIFT,
182*4882a593Smuzhiyun da7213_alc_integ_rate_txt);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_alc_integ_release_rate,
185*4882a593Smuzhiyun DA7213_ALC_CTRL3,
186*4882a593Smuzhiyun DA7213_ALC_INTEG_RELEASE_SHIFT,
187*4882a593Smuzhiyun da7213_alc_integ_rate_txt);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /*
191*4882a593Smuzhiyun * Control Functions
192*4882a593Smuzhiyun */
193*4882a593Smuzhiyun
da7213_get_alc_data(struct snd_soc_component * component,u8 reg_val)194*4882a593Smuzhiyun static int da7213_get_alc_data(struct snd_soc_component *component, u8 reg_val)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun int mid_data, top_data;
197*4882a593Smuzhiyun int sum = 0;
198*4882a593Smuzhiyun u8 iteration;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun for (iteration = 0; iteration < DA7213_ALC_AVG_ITERATIONS;
201*4882a593Smuzhiyun iteration++) {
202*4882a593Smuzhiyun /* Select the left or right channel and capture data */
203*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_ALC_CIC_OP_LVL_CTRL, reg_val);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun /* Select middle 8 bits for read back from data register */
206*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_ALC_CIC_OP_LVL_CTRL,
207*4882a593Smuzhiyun reg_val | DA7213_ALC_DATA_MIDDLE);
208*4882a593Smuzhiyun mid_data = snd_soc_component_read(component, DA7213_ALC_CIC_OP_LVL_DATA);
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /* Select top 8 bits for read back from data register */
211*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_ALC_CIC_OP_LVL_CTRL,
212*4882a593Smuzhiyun reg_val | DA7213_ALC_DATA_TOP);
213*4882a593Smuzhiyun top_data = snd_soc_component_read(component, DA7213_ALC_CIC_OP_LVL_DATA);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun sum += ((mid_data << 8) | (top_data << 16));
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun return sum / DA7213_ALC_AVG_ITERATIONS;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
da7213_alc_calib_man(struct snd_soc_component * component)221*4882a593Smuzhiyun static void da7213_alc_calib_man(struct snd_soc_component *component)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun u8 reg_val;
224*4882a593Smuzhiyun int avg_left_data, avg_right_data, offset_l, offset_r;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* Calculate average for Left and Right data */
227*4882a593Smuzhiyun /* Left Data */
228*4882a593Smuzhiyun avg_left_data = da7213_get_alc_data(component,
229*4882a593Smuzhiyun DA7213_ALC_CIC_OP_CHANNEL_LEFT);
230*4882a593Smuzhiyun /* Right Data */
231*4882a593Smuzhiyun avg_right_data = da7213_get_alc_data(component,
232*4882a593Smuzhiyun DA7213_ALC_CIC_OP_CHANNEL_RIGHT);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* Calculate DC offset */
235*4882a593Smuzhiyun offset_l = -avg_left_data;
236*4882a593Smuzhiyun offset_r = -avg_right_data;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun reg_val = (offset_l & DA7213_ALC_OFFSET_15_8) >> 8;
239*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_M_L, reg_val);
240*4882a593Smuzhiyun reg_val = (offset_l & DA7213_ALC_OFFSET_19_16) >> 16;
241*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_U_L, reg_val);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun reg_val = (offset_r & DA7213_ALC_OFFSET_15_8) >> 8;
244*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_M_R, reg_val);
245*4882a593Smuzhiyun reg_val = (offset_r & DA7213_ALC_OFFSET_19_16) >> 16;
246*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_U_R, reg_val);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* Enable analog/digital gain mode & offset cancellation */
249*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_ALC_CTRL1,
250*4882a593Smuzhiyun DA7213_ALC_OFFSET_EN | DA7213_ALC_SYNC_MODE,
251*4882a593Smuzhiyun DA7213_ALC_OFFSET_EN | DA7213_ALC_SYNC_MODE);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
da7213_alc_calib_auto(struct snd_soc_component * component)254*4882a593Smuzhiyun static void da7213_alc_calib_auto(struct snd_soc_component *component)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun u8 alc_ctrl1;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /* Begin auto calibration and wait for completion */
259*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_ALC_CTRL1, DA7213_ALC_AUTO_CALIB_EN,
260*4882a593Smuzhiyun DA7213_ALC_AUTO_CALIB_EN);
261*4882a593Smuzhiyun do {
262*4882a593Smuzhiyun alc_ctrl1 = snd_soc_component_read(component, DA7213_ALC_CTRL1);
263*4882a593Smuzhiyun } while (alc_ctrl1 & DA7213_ALC_AUTO_CALIB_EN);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun /* If auto calibration fails, fall back to digital gain only mode */
266*4882a593Smuzhiyun if (alc_ctrl1 & DA7213_ALC_CALIB_OVERFLOW) {
267*4882a593Smuzhiyun dev_warn(component->dev,
268*4882a593Smuzhiyun "ALC auto calibration failed with overflow\n");
269*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_ALC_CTRL1,
270*4882a593Smuzhiyun DA7213_ALC_OFFSET_EN | DA7213_ALC_SYNC_MODE,
271*4882a593Smuzhiyun 0);
272*4882a593Smuzhiyun } else {
273*4882a593Smuzhiyun /* Enable analog/digital gain mode & offset cancellation */
274*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_ALC_CTRL1,
275*4882a593Smuzhiyun DA7213_ALC_OFFSET_EN | DA7213_ALC_SYNC_MODE,
276*4882a593Smuzhiyun DA7213_ALC_OFFSET_EN | DA7213_ALC_SYNC_MODE);
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
da7213_alc_calib(struct snd_soc_component * component)281*4882a593Smuzhiyun static void da7213_alc_calib(struct snd_soc_component *component)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
284*4882a593Smuzhiyun u8 adc_l_ctrl, adc_r_ctrl;
285*4882a593Smuzhiyun u8 mixin_l_sel, mixin_r_sel;
286*4882a593Smuzhiyun u8 mic_1_ctrl, mic_2_ctrl;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /* Save current values from ADC control registers */
289*4882a593Smuzhiyun adc_l_ctrl = snd_soc_component_read(component, DA7213_ADC_L_CTRL);
290*4882a593Smuzhiyun adc_r_ctrl = snd_soc_component_read(component, DA7213_ADC_R_CTRL);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun /* Save current values from MIXIN_L/R_SELECT registers */
293*4882a593Smuzhiyun mixin_l_sel = snd_soc_component_read(component, DA7213_MIXIN_L_SELECT);
294*4882a593Smuzhiyun mixin_r_sel = snd_soc_component_read(component, DA7213_MIXIN_R_SELECT);
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun /* Save current values from MIC control registers */
297*4882a593Smuzhiyun mic_1_ctrl = snd_soc_component_read(component, DA7213_MIC_1_CTRL);
298*4882a593Smuzhiyun mic_2_ctrl = snd_soc_component_read(component, DA7213_MIC_2_CTRL);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun /* Enable ADC Left and Right */
301*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_ADC_L_CTRL, DA7213_ADC_EN,
302*4882a593Smuzhiyun DA7213_ADC_EN);
303*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_ADC_R_CTRL, DA7213_ADC_EN,
304*4882a593Smuzhiyun DA7213_ADC_EN);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun /* Enable MIC paths */
307*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIXIN_L_SELECT,
308*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MIC_1 |
309*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MIC_2,
310*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MIC_1 |
311*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MIC_2);
312*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIXIN_R_SELECT,
313*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MIC_2 |
314*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MIC_1,
315*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MIC_2 |
316*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MIC_1);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun /* Mute MIC PGAs */
319*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIC_1_CTRL, DA7213_MUTE_EN,
320*4882a593Smuzhiyun DA7213_MUTE_EN);
321*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIC_2_CTRL, DA7213_MUTE_EN,
322*4882a593Smuzhiyun DA7213_MUTE_EN);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /* Perform calibration */
325*4882a593Smuzhiyun if (da7213->alc_calib_auto)
326*4882a593Smuzhiyun da7213_alc_calib_auto(component);
327*4882a593Smuzhiyun else
328*4882a593Smuzhiyun da7213_alc_calib_man(component);
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun /* Restore MIXIN_L/R_SELECT registers to their original states */
331*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_MIXIN_L_SELECT, mixin_l_sel);
332*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_MIXIN_R_SELECT, mixin_r_sel);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* Restore ADC control registers to their original states */
335*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_ADC_L_CTRL, adc_l_ctrl);
336*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_ADC_R_CTRL, adc_r_ctrl);
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun /* Restore original values of MIC control registers */
339*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_MIC_1_CTRL, mic_1_ctrl);
340*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_MIC_2_CTRL, mic_2_ctrl);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
da7213_put_mixin_gain(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)343*4882a593Smuzhiyun static int da7213_put_mixin_gain(struct snd_kcontrol *kcontrol,
344*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
347*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
348*4882a593Smuzhiyun int ret;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun /* If ALC in operation, make sure calibrated offsets are updated */
353*4882a593Smuzhiyun if ((!ret) && (da7213->alc_en))
354*4882a593Smuzhiyun da7213_alc_calib(component);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun return ret;
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun
da7213_put_alc_sw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)359*4882a593Smuzhiyun static int da7213_put_alc_sw(struct snd_kcontrol *kcontrol,
360*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
363*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun /* Force ALC offset calibration if enabling ALC */
366*4882a593Smuzhiyun if (ucontrol->value.integer.value[0] ||
367*4882a593Smuzhiyun ucontrol->value.integer.value[1]) {
368*4882a593Smuzhiyun if (!da7213->alc_en) {
369*4882a593Smuzhiyun da7213_alc_calib(component);
370*4882a593Smuzhiyun da7213->alc_en = true;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun } else {
373*4882a593Smuzhiyun da7213->alc_en = false;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun return snd_soc_put_volsw(kcontrol, ucontrol);
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun /*
381*4882a593Smuzhiyun * KControls
382*4882a593Smuzhiyun */
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_snd_controls[] = {
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun /* Volume controls */
387*4882a593Smuzhiyun SOC_SINGLE_TLV("Mic 1 Volume", DA7213_MIC_1_GAIN,
388*4882a593Smuzhiyun DA7213_MIC_AMP_GAIN_SHIFT, DA7213_MIC_AMP_GAIN_MAX,
389*4882a593Smuzhiyun DA7213_NO_INVERT, mic_vol_tlv),
390*4882a593Smuzhiyun SOC_SINGLE_TLV("Mic 2 Volume", DA7213_MIC_2_GAIN,
391*4882a593Smuzhiyun DA7213_MIC_AMP_GAIN_SHIFT, DA7213_MIC_AMP_GAIN_MAX,
392*4882a593Smuzhiyun DA7213_NO_INVERT, mic_vol_tlv),
393*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Aux Volume", DA7213_AUX_L_GAIN, DA7213_AUX_R_GAIN,
394*4882a593Smuzhiyun DA7213_AUX_AMP_GAIN_SHIFT, DA7213_AUX_AMP_GAIN_MAX,
395*4882a593Smuzhiyun DA7213_NO_INVERT, aux_vol_tlv),
396*4882a593Smuzhiyun SOC_DOUBLE_R_EXT_TLV("Mixin PGA Volume", DA7213_MIXIN_L_GAIN,
397*4882a593Smuzhiyun DA7213_MIXIN_R_GAIN, DA7213_MIXIN_AMP_GAIN_SHIFT,
398*4882a593Smuzhiyun DA7213_MIXIN_AMP_GAIN_MAX, DA7213_NO_INVERT,
399*4882a593Smuzhiyun snd_soc_get_volsw_2r, da7213_put_mixin_gain,
400*4882a593Smuzhiyun mixin_gain_tlv),
401*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("ADC Volume", DA7213_ADC_L_GAIN, DA7213_ADC_R_GAIN,
402*4882a593Smuzhiyun DA7213_ADC_AMP_GAIN_SHIFT, DA7213_ADC_AMP_GAIN_MAX,
403*4882a593Smuzhiyun DA7213_NO_INVERT, digital_gain_tlv),
404*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("DAC Volume", DA7213_DAC_L_GAIN, DA7213_DAC_R_GAIN,
405*4882a593Smuzhiyun DA7213_DAC_AMP_GAIN_SHIFT, DA7213_DAC_AMP_GAIN_MAX,
406*4882a593Smuzhiyun DA7213_NO_INVERT, digital_gain_tlv),
407*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Headphone Volume", DA7213_HP_L_GAIN, DA7213_HP_R_GAIN,
408*4882a593Smuzhiyun DA7213_HP_AMP_GAIN_SHIFT, DA7213_HP_AMP_GAIN_MAX,
409*4882a593Smuzhiyun DA7213_NO_INVERT, hp_vol_tlv),
410*4882a593Smuzhiyun SOC_SINGLE_TLV("Lineout Volume", DA7213_LINE_GAIN,
411*4882a593Smuzhiyun DA7213_LINE_AMP_GAIN_SHIFT, DA7213_LINE_AMP_GAIN_MAX,
412*4882a593Smuzhiyun DA7213_NO_INVERT, lineout_vol_tlv),
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun /* DAC Equalizer controls */
415*4882a593Smuzhiyun SOC_SINGLE("DAC EQ Switch", DA7213_DAC_FILTERS4, DA7213_DAC_EQ_EN_SHIFT,
416*4882a593Smuzhiyun DA7213_DAC_EQ_EN_MAX, DA7213_NO_INVERT),
417*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC EQ1 Volume", DA7213_DAC_FILTERS2,
418*4882a593Smuzhiyun DA7213_DAC_EQ_BAND1_SHIFT, DA7213_DAC_EQ_BAND_MAX,
419*4882a593Smuzhiyun DA7213_NO_INVERT, eq_gain_tlv),
420*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC EQ2 Volume", DA7213_DAC_FILTERS2,
421*4882a593Smuzhiyun DA7213_DAC_EQ_BAND2_SHIFT, DA7213_DAC_EQ_BAND_MAX,
422*4882a593Smuzhiyun DA7213_NO_INVERT, eq_gain_tlv),
423*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC EQ3 Volume", DA7213_DAC_FILTERS3,
424*4882a593Smuzhiyun DA7213_DAC_EQ_BAND3_SHIFT, DA7213_DAC_EQ_BAND_MAX,
425*4882a593Smuzhiyun DA7213_NO_INVERT, eq_gain_tlv),
426*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC EQ4 Volume", DA7213_DAC_FILTERS3,
427*4882a593Smuzhiyun DA7213_DAC_EQ_BAND4_SHIFT, DA7213_DAC_EQ_BAND_MAX,
428*4882a593Smuzhiyun DA7213_NO_INVERT, eq_gain_tlv),
429*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC EQ5 Volume", DA7213_DAC_FILTERS4,
430*4882a593Smuzhiyun DA7213_DAC_EQ_BAND5_SHIFT, DA7213_DAC_EQ_BAND_MAX,
431*4882a593Smuzhiyun DA7213_NO_INVERT, eq_gain_tlv),
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun /* High Pass Filter and Voice Mode controls */
434*4882a593Smuzhiyun SOC_SINGLE("ADC HPF Switch", DA7213_ADC_FILTERS1, DA7213_HPF_EN_SHIFT,
435*4882a593Smuzhiyun DA7213_HPF_EN_MAX, DA7213_NO_INVERT),
436*4882a593Smuzhiyun SOC_ENUM("ADC HPF Cutoff", da7213_adc_audio_hpf_corner),
437*4882a593Smuzhiyun SOC_SINGLE("ADC Voice Mode Switch", DA7213_ADC_FILTERS1,
438*4882a593Smuzhiyun DA7213_VOICE_EN_SHIFT, DA7213_VOICE_EN_MAX,
439*4882a593Smuzhiyun DA7213_NO_INVERT),
440*4882a593Smuzhiyun SOC_ENUM("ADC Voice Cutoff", da7213_adc_voice_hpf_corner),
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun SOC_SINGLE("DAC HPF Switch", DA7213_DAC_FILTERS1, DA7213_HPF_EN_SHIFT,
443*4882a593Smuzhiyun DA7213_HPF_EN_MAX, DA7213_NO_INVERT),
444*4882a593Smuzhiyun SOC_ENUM("DAC HPF Cutoff", da7213_dac_audio_hpf_corner),
445*4882a593Smuzhiyun SOC_SINGLE("DAC Voice Mode Switch", DA7213_DAC_FILTERS1,
446*4882a593Smuzhiyun DA7213_VOICE_EN_SHIFT, DA7213_VOICE_EN_MAX,
447*4882a593Smuzhiyun DA7213_NO_INVERT),
448*4882a593Smuzhiyun SOC_ENUM("DAC Voice Cutoff", da7213_dac_voice_hpf_corner),
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun /* Mute controls */
451*4882a593Smuzhiyun SOC_SINGLE("Mic 1 Switch", DA7213_MIC_1_CTRL, DA7213_MUTE_EN_SHIFT,
452*4882a593Smuzhiyun DA7213_MUTE_EN_MAX, DA7213_INVERT),
453*4882a593Smuzhiyun SOC_SINGLE("Mic 2 Switch", DA7213_MIC_2_CTRL, DA7213_MUTE_EN_SHIFT,
454*4882a593Smuzhiyun DA7213_MUTE_EN_MAX, DA7213_INVERT),
455*4882a593Smuzhiyun SOC_DOUBLE_R("Aux Switch", DA7213_AUX_L_CTRL, DA7213_AUX_R_CTRL,
456*4882a593Smuzhiyun DA7213_MUTE_EN_SHIFT, DA7213_MUTE_EN_MAX, DA7213_INVERT),
457*4882a593Smuzhiyun SOC_DOUBLE_R("Mixin PGA Switch", DA7213_MIXIN_L_CTRL,
458*4882a593Smuzhiyun DA7213_MIXIN_R_CTRL, DA7213_MUTE_EN_SHIFT,
459*4882a593Smuzhiyun DA7213_MUTE_EN_MAX, DA7213_INVERT),
460*4882a593Smuzhiyun SOC_DOUBLE_R("ADC Switch", DA7213_ADC_L_CTRL, DA7213_ADC_R_CTRL,
461*4882a593Smuzhiyun DA7213_MUTE_EN_SHIFT, DA7213_MUTE_EN_MAX, DA7213_INVERT),
462*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone Switch", DA7213_HP_L_CTRL, DA7213_HP_R_CTRL,
463*4882a593Smuzhiyun DA7213_MUTE_EN_SHIFT, DA7213_MUTE_EN_MAX, DA7213_INVERT),
464*4882a593Smuzhiyun SOC_SINGLE("Lineout Switch", DA7213_LINE_CTRL, DA7213_MUTE_EN_SHIFT,
465*4882a593Smuzhiyun DA7213_MUTE_EN_MAX, DA7213_INVERT),
466*4882a593Smuzhiyun SOC_SINGLE("DAC Soft Mute Switch", DA7213_DAC_FILTERS5,
467*4882a593Smuzhiyun DA7213_DAC_SOFTMUTE_EN_SHIFT, DA7213_DAC_SOFTMUTE_EN_MAX,
468*4882a593Smuzhiyun DA7213_NO_INVERT),
469*4882a593Smuzhiyun SOC_ENUM("DAC Soft Mute Rate", da7213_dac_soft_mute_rate),
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun /* Zero Cross controls */
472*4882a593Smuzhiyun SOC_DOUBLE_R("Aux ZC Switch", DA7213_AUX_L_CTRL, DA7213_AUX_R_CTRL,
473*4882a593Smuzhiyun DA7213_ZC_EN_SHIFT, DA7213_ZC_EN_MAX, DA7213_NO_INVERT),
474*4882a593Smuzhiyun SOC_DOUBLE_R("Mixin PGA ZC Switch", DA7213_MIXIN_L_CTRL,
475*4882a593Smuzhiyun DA7213_MIXIN_R_CTRL, DA7213_ZC_EN_SHIFT, DA7213_ZC_EN_MAX,
476*4882a593Smuzhiyun DA7213_NO_INVERT),
477*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone ZC Switch", DA7213_HP_L_CTRL, DA7213_HP_R_CTRL,
478*4882a593Smuzhiyun DA7213_ZC_EN_SHIFT, DA7213_ZC_EN_MAX, DA7213_NO_INVERT),
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun /* Gain Ramping controls */
481*4882a593Smuzhiyun SOC_DOUBLE_R("Aux Gain Ramping Switch", DA7213_AUX_L_CTRL,
482*4882a593Smuzhiyun DA7213_AUX_R_CTRL, DA7213_GAIN_RAMP_EN_SHIFT,
483*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN_MAX, DA7213_NO_INVERT),
484*4882a593Smuzhiyun SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA7213_MIXIN_L_CTRL,
485*4882a593Smuzhiyun DA7213_MIXIN_R_CTRL, DA7213_GAIN_RAMP_EN_SHIFT,
486*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN_MAX, DA7213_NO_INVERT),
487*4882a593Smuzhiyun SOC_DOUBLE_R("ADC Gain Ramping Switch", DA7213_ADC_L_CTRL,
488*4882a593Smuzhiyun DA7213_ADC_R_CTRL, DA7213_GAIN_RAMP_EN_SHIFT,
489*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN_MAX, DA7213_NO_INVERT),
490*4882a593Smuzhiyun SOC_DOUBLE_R("DAC Gain Ramping Switch", DA7213_DAC_L_CTRL,
491*4882a593Smuzhiyun DA7213_DAC_R_CTRL, DA7213_GAIN_RAMP_EN_SHIFT,
492*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN_MAX, DA7213_NO_INVERT),
493*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA7213_HP_L_CTRL,
494*4882a593Smuzhiyun DA7213_HP_R_CTRL, DA7213_GAIN_RAMP_EN_SHIFT,
495*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN_MAX, DA7213_NO_INVERT),
496*4882a593Smuzhiyun SOC_SINGLE("Lineout Gain Ramping Switch", DA7213_LINE_CTRL,
497*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN_SHIFT, DA7213_GAIN_RAMP_EN_MAX,
498*4882a593Smuzhiyun DA7213_NO_INVERT),
499*4882a593Smuzhiyun SOC_ENUM("Gain Ramping Rate", da7213_gain_ramp_rate),
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun /* DAC Noise Gate controls */
502*4882a593Smuzhiyun SOC_SINGLE("DAC NG Switch", DA7213_DAC_NG_CTRL, DA7213_DAC_NG_EN_SHIFT,
503*4882a593Smuzhiyun DA7213_DAC_NG_EN_MAX, DA7213_NO_INVERT),
504*4882a593Smuzhiyun SOC_ENUM("DAC NG Setup Time", da7213_dac_ng_setup_time),
505*4882a593Smuzhiyun SOC_ENUM("DAC NG Rampup Rate", da7213_dac_ng_rampup_rate),
506*4882a593Smuzhiyun SOC_ENUM("DAC NG Rampdown Rate", da7213_dac_ng_rampdown_rate),
507*4882a593Smuzhiyun SOC_SINGLE("DAC NG OFF Threshold", DA7213_DAC_NG_OFF_THRESHOLD,
508*4882a593Smuzhiyun DA7213_DAC_NG_THRESHOLD_SHIFT, DA7213_DAC_NG_THRESHOLD_MAX,
509*4882a593Smuzhiyun DA7213_NO_INVERT),
510*4882a593Smuzhiyun SOC_SINGLE("DAC NG ON Threshold", DA7213_DAC_NG_ON_THRESHOLD,
511*4882a593Smuzhiyun DA7213_DAC_NG_THRESHOLD_SHIFT, DA7213_DAC_NG_THRESHOLD_MAX,
512*4882a593Smuzhiyun DA7213_NO_INVERT),
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun /* DAC Routing & Inversion */
515*4882a593Smuzhiyun SOC_DOUBLE("DAC Mono Switch", DA7213_DIG_ROUTING_DAC,
516*4882a593Smuzhiyun DA7213_DAC_L_MONO_SHIFT, DA7213_DAC_R_MONO_SHIFT,
517*4882a593Smuzhiyun DA7213_DAC_MONO_MAX, DA7213_NO_INVERT),
518*4882a593Smuzhiyun SOC_DOUBLE("DAC Invert Switch", DA7213_DIG_CTRL, DA7213_DAC_L_INV_SHIFT,
519*4882a593Smuzhiyun DA7213_DAC_R_INV_SHIFT, DA7213_DAC_INV_MAX,
520*4882a593Smuzhiyun DA7213_NO_INVERT),
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun /* DMIC controls */
523*4882a593Smuzhiyun SOC_DOUBLE_R("DMIC Switch", DA7213_MIXIN_L_SELECT,
524*4882a593Smuzhiyun DA7213_MIXIN_R_SELECT, DA7213_DMIC_EN_SHIFT,
525*4882a593Smuzhiyun DA7213_DMIC_EN_MAX, DA7213_NO_INVERT),
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun /* ALC Controls */
528*4882a593Smuzhiyun SOC_DOUBLE_EXT("ALC Switch", DA7213_ALC_CTRL1, DA7213_ALC_L_EN_SHIFT,
529*4882a593Smuzhiyun DA7213_ALC_R_EN_SHIFT, DA7213_ALC_EN_MAX,
530*4882a593Smuzhiyun DA7213_NO_INVERT, snd_soc_get_volsw, da7213_put_alc_sw),
531*4882a593Smuzhiyun SOC_ENUM("ALC Attack Rate", da7213_alc_attack_rate),
532*4882a593Smuzhiyun SOC_ENUM("ALC Release Rate", da7213_alc_release_rate),
533*4882a593Smuzhiyun SOC_ENUM("ALC Hold Time", da7213_alc_hold_time),
534*4882a593Smuzhiyun /*
535*4882a593Smuzhiyun * Rate at which input signal envelope is tracked as the signal gets
536*4882a593Smuzhiyun * larger
537*4882a593Smuzhiyun */
538*4882a593Smuzhiyun SOC_ENUM("ALC Integ Attack Rate", da7213_alc_integ_attack_rate),
539*4882a593Smuzhiyun /*
540*4882a593Smuzhiyun * Rate at which input signal envelope is tracked as the signal gets
541*4882a593Smuzhiyun * smaller
542*4882a593Smuzhiyun */
543*4882a593Smuzhiyun SOC_ENUM("ALC Integ Release Rate", da7213_alc_integ_release_rate),
544*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA7213_ALC_NOISE,
545*4882a593Smuzhiyun DA7213_ALC_THRESHOLD_SHIFT, DA7213_ALC_THRESHOLD_MAX,
546*4882a593Smuzhiyun DA7213_INVERT, alc_threshold_tlv),
547*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Min Threshold Volume", DA7213_ALC_TARGET_MIN,
548*4882a593Smuzhiyun DA7213_ALC_THRESHOLD_SHIFT, DA7213_ALC_THRESHOLD_MAX,
549*4882a593Smuzhiyun DA7213_INVERT, alc_threshold_tlv),
550*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Max Threshold Volume", DA7213_ALC_TARGET_MAX,
551*4882a593Smuzhiyun DA7213_ALC_THRESHOLD_SHIFT, DA7213_ALC_THRESHOLD_MAX,
552*4882a593Smuzhiyun DA7213_INVERT, alc_threshold_tlv),
553*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA7213_ALC_GAIN_LIMITS,
554*4882a593Smuzhiyun DA7213_ALC_ATTEN_MAX_SHIFT,
555*4882a593Smuzhiyun DA7213_ALC_ATTEN_GAIN_MAX_MAX, DA7213_NO_INVERT,
556*4882a593Smuzhiyun alc_gain_tlv),
557*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Max Gain Volume", DA7213_ALC_GAIN_LIMITS,
558*4882a593Smuzhiyun DA7213_ALC_GAIN_MAX_SHIFT, DA7213_ALC_ATTEN_GAIN_MAX_MAX,
559*4882a593Smuzhiyun DA7213_NO_INVERT, alc_gain_tlv),
560*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Min Analog Gain Volume", DA7213_ALC_ANA_GAIN_LIMITS,
561*4882a593Smuzhiyun DA7213_ALC_ANA_GAIN_MIN_SHIFT, DA7213_ALC_ANA_GAIN_MAX,
562*4882a593Smuzhiyun DA7213_NO_INVERT, alc_analog_gain_tlv),
563*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Max Analog Gain Volume", DA7213_ALC_ANA_GAIN_LIMITS,
564*4882a593Smuzhiyun DA7213_ALC_ANA_GAIN_MAX_SHIFT, DA7213_ALC_ANA_GAIN_MAX,
565*4882a593Smuzhiyun DA7213_NO_INVERT, alc_analog_gain_tlv),
566*4882a593Smuzhiyun SOC_SINGLE("ALC Anticlip Mode Switch", DA7213_ALC_ANTICLIP_CTRL,
567*4882a593Smuzhiyun DA7213_ALC_ANTICLIP_EN_SHIFT, DA7213_ALC_ANTICLIP_EN_MAX,
568*4882a593Smuzhiyun DA7213_NO_INVERT),
569*4882a593Smuzhiyun SOC_SINGLE("ALC Anticlip Level", DA7213_ALC_ANTICLIP_LEVEL,
570*4882a593Smuzhiyun DA7213_ALC_ANTICLIP_LEVEL_SHIFT,
571*4882a593Smuzhiyun DA7213_ALC_ANTICLIP_LEVEL_MAX, DA7213_NO_INVERT),
572*4882a593Smuzhiyun };
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun /*
576*4882a593Smuzhiyun * DAPM
577*4882a593Smuzhiyun */
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun /*
580*4882a593Smuzhiyun * Enums
581*4882a593Smuzhiyun */
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun /* MIC PGA source select */
584*4882a593Smuzhiyun static const char * const da7213_mic_amp_in_sel_txt[] = {
585*4882a593Smuzhiyun "Differential", "MIC_P", "MIC_N"
586*4882a593Smuzhiyun };
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_mic_1_amp_in_sel,
589*4882a593Smuzhiyun DA7213_MIC_1_CTRL,
590*4882a593Smuzhiyun DA7213_MIC_AMP_IN_SEL_SHIFT,
591*4882a593Smuzhiyun da7213_mic_amp_in_sel_txt);
592*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_mic_1_amp_in_sel_mux =
593*4882a593Smuzhiyun SOC_DAPM_ENUM("Mic 1 Amp Source MUX", da7213_mic_1_amp_in_sel);
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_mic_2_amp_in_sel,
596*4882a593Smuzhiyun DA7213_MIC_2_CTRL,
597*4882a593Smuzhiyun DA7213_MIC_AMP_IN_SEL_SHIFT,
598*4882a593Smuzhiyun da7213_mic_amp_in_sel_txt);
599*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_mic_2_amp_in_sel_mux =
600*4882a593Smuzhiyun SOC_DAPM_ENUM("Mic 2 Amp Source MUX", da7213_mic_2_amp_in_sel);
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun /* DAI routing select */
603*4882a593Smuzhiyun static const char * const da7213_dai_src_txt[] = {
604*4882a593Smuzhiyun "ADC Left", "ADC Right", "DAI Input Left", "DAI Input Right"
605*4882a593Smuzhiyun };
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_dai_l_src,
608*4882a593Smuzhiyun DA7213_DIG_ROUTING_DAI,
609*4882a593Smuzhiyun DA7213_DAI_L_SRC_SHIFT,
610*4882a593Smuzhiyun da7213_dai_src_txt);
611*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_dai_l_src_mux =
612*4882a593Smuzhiyun SOC_DAPM_ENUM("DAI Left Source MUX", da7213_dai_l_src);
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_dai_r_src,
615*4882a593Smuzhiyun DA7213_DIG_ROUTING_DAI,
616*4882a593Smuzhiyun DA7213_DAI_R_SRC_SHIFT,
617*4882a593Smuzhiyun da7213_dai_src_txt);
618*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_dai_r_src_mux =
619*4882a593Smuzhiyun SOC_DAPM_ENUM("DAI Right Source MUX", da7213_dai_r_src);
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun /* DAC routing select */
622*4882a593Smuzhiyun static const char * const da7213_dac_src_txt[] = {
623*4882a593Smuzhiyun "ADC Output Left", "ADC Output Right", "DAI Input Left",
624*4882a593Smuzhiyun "DAI Input Right"
625*4882a593Smuzhiyun };
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_dac_l_src,
628*4882a593Smuzhiyun DA7213_DIG_ROUTING_DAC,
629*4882a593Smuzhiyun DA7213_DAC_L_SRC_SHIFT,
630*4882a593Smuzhiyun da7213_dac_src_txt);
631*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_dac_l_src_mux =
632*4882a593Smuzhiyun SOC_DAPM_ENUM("DAC Left Source MUX", da7213_dac_l_src);
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7213_dac_r_src,
635*4882a593Smuzhiyun DA7213_DIG_ROUTING_DAC,
636*4882a593Smuzhiyun DA7213_DAC_R_SRC_SHIFT,
637*4882a593Smuzhiyun da7213_dac_src_txt);
638*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_dac_r_src_mux =
639*4882a593Smuzhiyun SOC_DAPM_ENUM("DAC Right Source MUX", da7213_dac_r_src);
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun /*
642*4882a593Smuzhiyun * Mixer Controls
643*4882a593Smuzhiyun */
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun /* Mixin Left */
646*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_dapm_mixinl_controls[] = {
647*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Left Switch", DA7213_MIXIN_L_SELECT,
648*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_AUX_L_SHIFT,
649*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
650*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mic 1 Switch", DA7213_MIXIN_L_SELECT,
651*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MIC_1_SHIFT,
652*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
653*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mic 2 Switch", DA7213_MIXIN_L_SELECT,
654*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MIC_2_SHIFT,
655*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
656*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixin Right Switch", DA7213_MIXIN_L_SELECT,
657*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MIXIN_R_SHIFT,
658*4882a593Smuzhiyun DA7213_MIXIN_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
659*4882a593Smuzhiyun };
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun /* Mixin Right */
662*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_dapm_mixinr_controls[] = {
663*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Right Switch", DA7213_MIXIN_R_SELECT,
664*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_AUX_R_SHIFT,
665*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
666*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mic 2 Switch", DA7213_MIXIN_R_SELECT,
667*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MIC_2_SHIFT,
668*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
669*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mic 1 Switch", DA7213_MIXIN_R_SELECT,
670*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MIC_1_SHIFT,
671*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
672*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixin Left Switch", DA7213_MIXIN_R_SELECT,
673*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MIXIN_L_SHIFT,
674*4882a593Smuzhiyun DA7213_MIXIN_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
675*4882a593Smuzhiyun };
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun /* Mixout Left */
678*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_dapm_mixoutl_controls[] = {
679*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Left Switch", DA7213_MIXOUT_L_SELECT,
680*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_AUX_L_SHIFT,
681*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
682*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixin Left Switch", DA7213_MIXOUT_L_SELECT,
683*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MIXIN_L_SHIFT,
684*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
685*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixin Right Switch", DA7213_MIXOUT_L_SELECT,
686*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MIXIN_R_SHIFT,
687*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
688*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC Left Switch", DA7213_MIXOUT_L_SELECT,
689*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_DAC_L_SHIFT,
690*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
691*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Left Invert Switch", DA7213_MIXOUT_L_SELECT,
692*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_AUX_L_INVERTED_SHIFT,
693*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
694*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA7213_MIXOUT_L_SELECT,
695*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MIXIN_L_INVERTED_SHIFT,
696*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
697*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA7213_MIXOUT_L_SELECT,
698*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MIXIN_R_INVERTED_SHIFT,
699*4882a593Smuzhiyun DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
700*4882a593Smuzhiyun };
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun /* Mixout Right */
703*4882a593Smuzhiyun static const struct snd_kcontrol_new da7213_dapm_mixoutr_controls[] = {
704*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Right Switch", DA7213_MIXOUT_R_SELECT,
705*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_AUX_R_SHIFT,
706*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
707*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixin Right Switch", DA7213_MIXOUT_R_SELECT,
708*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MIXIN_R_SHIFT,
709*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
710*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixin Left Switch", DA7213_MIXOUT_R_SELECT,
711*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MIXIN_L_SHIFT,
712*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
713*4882a593Smuzhiyun SOC_DAPM_SINGLE("DAC Right Switch", DA7213_MIXOUT_R_SELECT,
714*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_DAC_R_SHIFT,
715*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
716*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Right Invert Switch", DA7213_MIXOUT_R_SELECT,
717*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_AUX_R_INVERTED_SHIFT,
718*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
719*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA7213_MIXOUT_R_SELECT,
720*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MIXIN_R_INVERTED_SHIFT,
721*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
722*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA7213_MIXOUT_R_SELECT,
723*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MIXIN_L_INVERTED_SHIFT,
724*4882a593Smuzhiyun DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
725*4882a593Smuzhiyun };
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun /*
729*4882a593Smuzhiyun * DAPM Events
730*4882a593Smuzhiyun */
731*4882a593Smuzhiyun
da7213_dai_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)732*4882a593Smuzhiyun static int da7213_dai_event(struct snd_soc_dapm_widget *w,
733*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
734*4882a593Smuzhiyun {
735*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
736*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
737*4882a593Smuzhiyun u8 pll_ctrl, pll_status;
738*4882a593Smuzhiyun int i = 0;
739*4882a593Smuzhiyun bool srm_lock = false;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun switch (event) {
742*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
743*4882a593Smuzhiyun /* Enable DAI clks for master mode */
744*4882a593Smuzhiyun if (da7213->master)
745*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAI_CLK_MODE,
746*4882a593Smuzhiyun DA7213_DAI_CLK_EN_MASK,
747*4882a593Smuzhiyun DA7213_DAI_CLK_EN_MASK);
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun /* PC synchronised to DAI */
750*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_PC_COUNT,
751*4882a593Smuzhiyun DA7213_PC_FREERUN_MASK, 0);
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun /* If SRM not enabled then nothing more to do */
754*4882a593Smuzhiyun pll_ctrl = snd_soc_component_read(component, DA7213_PLL_CTRL);
755*4882a593Smuzhiyun if (!(pll_ctrl & DA7213_PLL_SRM_EN))
756*4882a593Smuzhiyun return 0;
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun /* Assist 32KHz mode PLL lock */
759*4882a593Smuzhiyun if (pll_ctrl & DA7213_PLL_32K_MODE) {
760*4882a593Smuzhiyun snd_soc_component_write(component, 0xF0, 0x8B);
761*4882a593Smuzhiyun snd_soc_component_write(component, 0xF2, 0x03);
762*4882a593Smuzhiyun snd_soc_component_write(component, 0xF0, 0x00);
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun /* Check SRM has locked */
766*4882a593Smuzhiyun do {
767*4882a593Smuzhiyun pll_status = snd_soc_component_read(component, DA7213_PLL_STATUS);
768*4882a593Smuzhiyun if (pll_status & DA7219_PLL_SRM_LOCK) {
769*4882a593Smuzhiyun srm_lock = true;
770*4882a593Smuzhiyun } else {
771*4882a593Smuzhiyun ++i;
772*4882a593Smuzhiyun msleep(50);
773*4882a593Smuzhiyun }
774*4882a593Smuzhiyun } while ((i < DA7213_SRM_CHECK_RETRIES) && (!srm_lock));
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun if (!srm_lock)
777*4882a593Smuzhiyun dev_warn(component->dev, "SRM failed to lock\n");
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun return 0;
780*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
781*4882a593Smuzhiyun /* Revert 32KHz PLL lock udpates if applied previously */
782*4882a593Smuzhiyun pll_ctrl = snd_soc_component_read(component, DA7213_PLL_CTRL);
783*4882a593Smuzhiyun if (pll_ctrl & DA7213_PLL_32K_MODE) {
784*4882a593Smuzhiyun snd_soc_component_write(component, 0xF0, 0x8B);
785*4882a593Smuzhiyun snd_soc_component_write(component, 0xF2, 0x01);
786*4882a593Smuzhiyun snd_soc_component_write(component, 0xF0, 0x00);
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun /* PC free-running */
790*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_PC_COUNT,
791*4882a593Smuzhiyun DA7213_PC_FREERUN_MASK,
792*4882a593Smuzhiyun DA7213_PC_FREERUN_MASK);
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun /* Disable DAI clks if in master mode */
795*4882a593Smuzhiyun if (da7213->master)
796*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAI_CLK_MODE,
797*4882a593Smuzhiyun DA7213_DAI_CLK_EN_MASK, 0);
798*4882a593Smuzhiyun return 0;
799*4882a593Smuzhiyun default:
800*4882a593Smuzhiyun return -EINVAL;
801*4882a593Smuzhiyun }
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun /*
806*4882a593Smuzhiyun * DAPM widgets
807*4882a593Smuzhiyun */
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun static const struct snd_soc_dapm_widget da7213_dapm_widgets[] = {
810*4882a593Smuzhiyun /*
811*4882a593Smuzhiyun * Power Supply
812*4882a593Smuzhiyun */
813*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("VDDMIC", 0, 0),
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun /*
816*4882a593Smuzhiyun * Input & Output
817*4882a593Smuzhiyun */
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun /* Use a supply here as this controls both input & output DAIs */
820*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DAI", DA7213_DAI_CTRL, DA7213_DAI_EN_SHIFT,
821*4882a593Smuzhiyun DA7213_NO_INVERT, da7213_dai_event,
822*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun /*
825*4882a593Smuzhiyun * Input
826*4882a593Smuzhiyun */
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun /* Input Lines */
829*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MIC1"),
830*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MIC2"),
831*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("AUXL"),
832*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("AUXR"),
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun /* MUXs for Mic PGA source selection */
835*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Mic 1 Amp Source MUX", SND_SOC_NOPM, 0, 0,
836*4882a593Smuzhiyun &da7213_mic_1_amp_in_sel_mux),
837*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Mic 2 Amp Source MUX", SND_SOC_NOPM, 0, 0,
838*4882a593Smuzhiyun &da7213_mic_2_amp_in_sel_mux),
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun /* Input PGAs */
841*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mic 1 PGA", DA7213_MIC_1_CTRL, DA7213_AMP_EN_SHIFT,
842*4882a593Smuzhiyun DA7213_NO_INVERT, NULL, 0),
843*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mic 2 PGA", DA7213_MIC_2_CTRL, DA7213_AMP_EN_SHIFT,
844*4882a593Smuzhiyun DA7213_NO_INVERT, NULL, 0),
845*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Aux Left PGA", DA7213_AUX_L_CTRL, DA7213_AMP_EN_SHIFT,
846*4882a593Smuzhiyun DA7213_NO_INVERT, NULL, 0),
847*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Aux Right PGA", DA7213_AUX_R_CTRL,
848*4882a593Smuzhiyun DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
849*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mixin Left PGA", DA7213_MIXIN_L_CTRL,
850*4882a593Smuzhiyun DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
851*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mixin Right PGA", DA7213_MIXIN_R_CTRL,
852*4882a593Smuzhiyun DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun /* Mic Biases */
855*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mic Bias 1", DA7213_MICBIAS_CTRL,
856*4882a593Smuzhiyun DA7213_MICBIAS1_EN_SHIFT, DA7213_NO_INVERT,
857*4882a593Smuzhiyun NULL, 0),
858*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mic Bias 2", DA7213_MICBIAS_CTRL,
859*4882a593Smuzhiyun DA7213_MICBIAS2_EN_SHIFT, DA7213_NO_INVERT,
860*4882a593Smuzhiyun NULL, 0),
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun /* Input Mixers */
863*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixin Left", SND_SOC_NOPM, 0, 0,
864*4882a593Smuzhiyun &da7213_dapm_mixinl_controls[0],
865*4882a593Smuzhiyun ARRAY_SIZE(da7213_dapm_mixinl_controls)),
866*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixin Right", SND_SOC_NOPM, 0, 0,
867*4882a593Smuzhiyun &da7213_dapm_mixinr_controls[0],
868*4882a593Smuzhiyun ARRAY_SIZE(da7213_dapm_mixinr_controls)),
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun /* ADCs */
871*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC Left", NULL, DA7213_ADC_L_CTRL,
872*4882a593Smuzhiyun DA7213_ADC_EN_SHIFT, DA7213_NO_INVERT),
873*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC Right", NULL, DA7213_ADC_R_CTRL,
874*4882a593Smuzhiyun DA7213_ADC_EN_SHIFT, DA7213_NO_INVERT),
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun /* DAI */
877*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAI Left Source MUX", SND_SOC_NOPM, 0, 0,
878*4882a593Smuzhiyun &da7213_dai_l_src_mux),
879*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAI Right Source MUX", SND_SOC_NOPM, 0, 0,
880*4882a593Smuzhiyun &da7213_dai_r_src_mux),
881*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("DAIOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
882*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("DAIOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun /*
885*4882a593Smuzhiyun * Output
886*4882a593Smuzhiyun */
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun /* DAI */
889*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("DAIINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
890*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("DAIINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
891*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAC Left Source MUX", SND_SOC_NOPM, 0, 0,
892*4882a593Smuzhiyun &da7213_dac_l_src_mux),
893*4882a593Smuzhiyun SND_SOC_DAPM_MUX("DAC Right Source MUX", SND_SOC_NOPM, 0, 0,
894*4882a593Smuzhiyun &da7213_dac_r_src_mux),
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun /* DACs */
897*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC Left", NULL, DA7213_DAC_L_CTRL,
898*4882a593Smuzhiyun DA7213_DAC_EN_SHIFT, DA7213_NO_INVERT),
899*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC Right", NULL, DA7213_DAC_R_CTRL,
900*4882a593Smuzhiyun DA7213_DAC_EN_SHIFT, DA7213_NO_INVERT),
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun /* Output Mixers */
903*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixout Left", SND_SOC_NOPM, 0, 0,
904*4882a593Smuzhiyun &da7213_dapm_mixoutl_controls[0],
905*4882a593Smuzhiyun ARRAY_SIZE(da7213_dapm_mixoutl_controls)),
906*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixout Right", SND_SOC_NOPM, 0, 0,
907*4882a593Smuzhiyun &da7213_dapm_mixoutr_controls[0],
908*4882a593Smuzhiyun ARRAY_SIZE(da7213_dapm_mixoutr_controls)),
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun /* Output PGAs */
911*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mixout Left PGA", DA7213_MIXOUT_L_CTRL,
912*4882a593Smuzhiyun DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
913*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mixout Right PGA", DA7213_MIXOUT_R_CTRL,
914*4882a593Smuzhiyun DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
915*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Lineout PGA", DA7213_LINE_CTRL, DA7213_AMP_EN_SHIFT,
916*4882a593Smuzhiyun DA7213_NO_INVERT, NULL, 0),
917*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Headphone Left PGA", DA7213_HP_L_CTRL,
918*4882a593Smuzhiyun DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
919*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Headphone Right PGA", DA7213_HP_R_CTRL,
920*4882a593Smuzhiyun DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun /* Charge Pump */
923*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Charge Pump", DA7213_CP_CTRL, DA7213_CP_EN_SHIFT,
924*4882a593Smuzhiyun DA7213_NO_INVERT, NULL, 0),
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun /* Output Lines */
927*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPL"),
928*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPR"),
929*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LINE"),
930*4882a593Smuzhiyun };
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun /*
934*4882a593Smuzhiyun * DAPM audio route definition
935*4882a593Smuzhiyun */
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun static const struct snd_soc_dapm_route da7213_audio_map[] = {
938*4882a593Smuzhiyun /* Dest Connecting Widget source */
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun /* Input path */
941*4882a593Smuzhiyun {"Mic Bias 1", NULL, "VDDMIC"},
942*4882a593Smuzhiyun {"Mic Bias 2", NULL, "VDDMIC"},
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun {"MIC1", NULL, "Mic Bias 1"},
945*4882a593Smuzhiyun {"MIC2", NULL, "Mic Bias 2"},
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun {"Mic 1 Amp Source MUX", "Differential", "MIC1"},
948*4882a593Smuzhiyun {"Mic 1 Amp Source MUX", "MIC_P", "MIC1"},
949*4882a593Smuzhiyun {"Mic 1 Amp Source MUX", "MIC_N", "MIC1"},
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun {"Mic 2 Amp Source MUX", "Differential", "MIC2"},
952*4882a593Smuzhiyun {"Mic 2 Amp Source MUX", "MIC_P", "MIC2"},
953*4882a593Smuzhiyun {"Mic 2 Amp Source MUX", "MIC_N", "MIC2"},
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun {"Mic 1 PGA", NULL, "Mic 1 Amp Source MUX"},
956*4882a593Smuzhiyun {"Mic 2 PGA", NULL, "Mic 2 Amp Source MUX"},
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun {"Aux Left PGA", NULL, "AUXL"},
959*4882a593Smuzhiyun {"Aux Right PGA", NULL, "AUXR"},
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun {"Mixin Left", "Aux Left Switch", "Aux Left PGA"},
962*4882a593Smuzhiyun {"Mixin Left", "Mic 1 Switch", "Mic 1 PGA"},
963*4882a593Smuzhiyun {"Mixin Left", "Mic 2 Switch", "Mic 2 PGA"},
964*4882a593Smuzhiyun {"Mixin Left", "Mixin Right Switch", "Mixin Right PGA"},
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun {"Mixin Right", "Aux Right Switch", "Aux Right PGA"},
967*4882a593Smuzhiyun {"Mixin Right", "Mic 2 Switch", "Mic 2 PGA"},
968*4882a593Smuzhiyun {"Mixin Right", "Mic 1 Switch", "Mic 1 PGA"},
969*4882a593Smuzhiyun {"Mixin Right", "Mixin Left Switch", "Mixin Left PGA"},
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun {"Mixin Left PGA", NULL, "Mixin Left"},
972*4882a593Smuzhiyun {"ADC Left", NULL, "Mixin Left PGA"},
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun {"Mixin Right PGA", NULL, "Mixin Right"},
975*4882a593Smuzhiyun {"ADC Right", NULL, "Mixin Right PGA"},
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun {"DAI Left Source MUX", "ADC Left", "ADC Left"},
978*4882a593Smuzhiyun {"DAI Left Source MUX", "ADC Right", "ADC Right"},
979*4882a593Smuzhiyun {"DAI Left Source MUX", "DAI Input Left", "DAIINL"},
980*4882a593Smuzhiyun {"DAI Left Source MUX", "DAI Input Right", "DAIINR"},
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun {"DAI Right Source MUX", "ADC Left", "ADC Left"},
983*4882a593Smuzhiyun {"DAI Right Source MUX", "ADC Right", "ADC Right"},
984*4882a593Smuzhiyun {"DAI Right Source MUX", "DAI Input Left", "DAIINL"},
985*4882a593Smuzhiyun {"DAI Right Source MUX", "DAI Input Right", "DAIINR"},
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun {"DAIOUTL", NULL, "DAI Left Source MUX"},
988*4882a593Smuzhiyun {"DAIOUTR", NULL, "DAI Right Source MUX"},
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun {"DAIOUTL", NULL, "DAI"},
991*4882a593Smuzhiyun {"DAIOUTR", NULL, "DAI"},
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun /* Output path */
994*4882a593Smuzhiyun {"DAIINL", NULL, "DAI"},
995*4882a593Smuzhiyun {"DAIINR", NULL, "DAI"},
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun {"DAC Left Source MUX", "ADC Output Left", "ADC Left"},
998*4882a593Smuzhiyun {"DAC Left Source MUX", "ADC Output Right", "ADC Right"},
999*4882a593Smuzhiyun {"DAC Left Source MUX", "DAI Input Left", "DAIINL"},
1000*4882a593Smuzhiyun {"DAC Left Source MUX", "DAI Input Right", "DAIINR"},
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun {"DAC Right Source MUX", "ADC Output Left", "ADC Left"},
1003*4882a593Smuzhiyun {"DAC Right Source MUX", "ADC Output Right", "ADC Right"},
1004*4882a593Smuzhiyun {"DAC Right Source MUX", "DAI Input Left", "DAIINL"},
1005*4882a593Smuzhiyun {"DAC Right Source MUX", "DAI Input Right", "DAIINR"},
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun {"DAC Left", NULL, "DAC Left Source MUX"},
1008*4882a593Smuzhiyun {"DAC Right", NULL, "DAC Right Source MUX"},
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun {"Mixout Left", "Aux Left Switch", "Aux Left PGA"},
1011*4882a593Smuzhiyun {"Mixout Left", "Mixin Left Switch", "Mixin Left PGA"},
1012*4882a593Smuzhiyun {"Mixout Left", "Mixin Right Switch", "Mixin Right PGA"},
1013*4882a593Smuzhiyun {"Mixout Left", "DAC Left Switch", "DAC Left"},
1014*4882a593Smuzhiyun {"Mixout Left", "Aux Left Invert Switch", "Aux Left PGA"},
1015*4882a593Smuzhiyun {"Mixout Left", "Mixin Left Invert Switch", "Mixin Left PGA"},
1016*4882a593Smuzhiyun {"Mixout Left", "Mixin Right Invert Switch", "Mixin Right PGA"},
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun {"Mixout Right", "Aux Right Switch", "Aux Right PGA"},
1019*4882a593Smuzhiyun {"Mixout Right", "Mixin Right Switch", "Mixin Right PGA"},
1020*4882a593Smuzhiyun {"Mixout Right", "Mixin Left Switch", "Mixin Left PGA"},
1021*4882a593Smuzhiyun {"Mixout Right", "DAC Right Switch", "DAC Right"},
1022*4882a593Smuzhiyun {"Mixout Right", "Aux Right Invert Switch", "Aux Right PGA"},
1023*4882a593Smuzhiyun {"Mixout Right", "Mixin Right Invert Switch", "Mixin Right PGA"},
1024*4882a593Smuzhiyun {"Mixout Right", "Mixin Left Invert Switch", "Mixin Left PGA"},
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun {"Mixout Left PGA", NULL, "Mixout Left"},
1027*4882a593Smuzhiyun {"Mixout Right PGA", NULL, "Mixout Right"},
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun {"Headphone Left PGA", NULL, "Mixout Left PGA"},
1030*4882a593Smuzhiyun {"Headphone Left PGA", NULL, "Charge Pump"},
1031*4882a593Smuzhiyun {"HPL", NULL, "Headphone Left PGA"},
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun {"Headphone Right PGA", NULL, "Mixout Right PGA"},
1034*4882a593Smuzhiyun {"Headphone Right PGA", NULL, "Charge Pump"},
1035*4882a593Smuzhiyun {"HPR", NULL, "Headphone Right PGA"},
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun {"Lineout PGA", NULL, "Mixout Right PGA"},
1038*4882a593Smuzhiyun {"LINE", NULL, "Lineout PGA"},
1039*4882a593Smuzhiyun };
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun static const struct reg_default da7213_reg_defaults[] = {
1042*4882a593Smuzhiyun { DA7213_DIG_ROUTING_DAI, 0x10 },
1043*4882a593Smuzhiyun { DA7213_SR, 0x0A },
1044*4882a593Smuzhiyun { DA7213_REFERENCES, 0x80 },
1045*4882a593Smuzhiyun { DA7213_PLL_FRAC_TOP, 0x00 },
1046*4882a593Smuzhiyun { DA7213_PLL_FRAC_BOT, 0x00 },
1047*4882a593Smuzhiyun { DA7213_PLL_INTEGER, 0x20 },
1048*4882a593Smuzhiyun { DA7213_PLL_CTRL, 0x0C },
1049*4882a593Smuzhiyun { DA7213_DAI_CLK_MODE, 0x01 },
1050*4882a593Smuzhiyun { DA7213_DAI_CTRL, 0x08 },
1051*4882a593Smuzhiyun { DA7213_DIG_ROUTING_DAC, 0x32 },
1052*4882a593Smuzhiyun { DA7213_AUX_L_GAIN, 0x35 },
1053*4882a593Smuzhiyun { DA7213_AUX_R_GAIN, 0x35 },
1054*4882a593Smuzhiyun { DA7213_MIXIN_L_SELECT, 0x00 },
1055*4882a593Smuzhiyun { DA7213_MIXIN_R_SELECT, 0x00 },
1056*4882a593Smuzhiyun { DA7213_MIXIN_L_GAIN, 0x03 },
1057*4882a593Smuzhiyun { DA7213_MIXIN_R_GAIN, 0x03 },
1058*4882a593Smuzhiyun { DA7213_ADC_L_GAIN, 0x6F },
1059*4882a593Smuzhiyun { DA7213_ADC_R_GAIN, 0x6F },
1060*4882a593Smuzhiyun { DA7213_ADC_FILTERS1, 0x80 },
1061*4882a593Smuzhiyun { DA7213_MIC_1_GAIN, 0x01 },
1062*4882a593Smuzhiyun { DA7213_MIC_2_GAIN, 0x01 },
1063*4882a593Smuzhiyun { DA7213_DAC_FILTERS5, 0x00 },
1064*4882a593Smuzhiyun { DA7213_DAC_FILTERS2, 0x88 },
1065*4882a593Smuzhiyun { DA7213_DAC_FILTERS3, 0x88 },
1066*4882a593Smuzhiyun { DA7213_DAC_FILTERS4, 0x08 },
1067*4882a593Smuzhiyun { DA7213_DAC_FILTERS1, 0x80 },
1068*4882a593Smuzhiyun { DA7213_DAC_L_GAIN, 0x6F },
1069*4882a593Smuzhiyun { DA7213_DAC_R_GAIN, 0x6F },
1070*4882a593Smuzhiyun { DA7213_CP_CTRL, 0x61 },
1071*4882a593Smuzhiyun { DA7213_HP_L_GAIN, 0x39 },
1072*4882a593Smuzhiyun { DA7213_HP_R_GAIN, 0x39 },
1073*4882a593Smuzhiyun { DA7213_LINE_GAIN, 0x30 },
1074*4882a593Smuzhiyun { DA7213_MIXOUT_L_SELECT, 0x00 },
1075*4882a593Smuzhiyun { DA7213_MIXOUT_R_SELECT, 0x00 },
1076*4882a593Smuzhiyun { DA7213_SYSTEM_MODES_INPUT, 0x00 },
1077*4882a593Smuzhiyun { DA7213_SYSTEM_MODES_OUTPUT, 0x00 },
1078*4882a593Smuzhiyun { DA7213_AUX_L_CTRL, 0x44 },
1079*4882a593Smuzhiyun { DA7213_AUX_R_CTRL, 0x44 },
1080*4882a593Smuzhiyun { DA7213_MICBIAS_CTRL, 0x11 },
1081*4882a593Smuzhiyun { DA7213_MIC_1_CTRL, 0x40 },
1082*4882a593Smuzhiyun { DA7213_MIC_2_CTRL, 0x40 },
1083*4882a593Smuzhiyun { DA7213_MIXIN_L_CTRL, 0x40 },
1084*4882a593Smuzhiyun { DA7213_MIXIN_R_CTRL, 0x40 },
1085*4882a593Smuzhiyun { DA7213_ADC_L_CTRL, 0x40 },
1086*4882a593Smuzhiyun { DA7213_ADC_R_CTRL, 0x40 },
1087*4882a593Smuzhiyun { DA7213_DAC_L_CTRL, 0x48 },
1088*4882a593Smuzhiyun { DA7213_DAC_R_CTRL, 0x40 },
1089*4882a593Smuzhiyun { DA7213_HP_L_CTRL, 0x41 },
1090*4882a593Smuzhiyun { DA7213_HP_R_CTRL, 0x40 },
1091*4882a593Smuzhiyun { DA7213_LINE_CTRL, 0x40 },
1092*4882a593Smuzhiyun { DA7213_MIXOUT_L_CTRL, 0x10 },
1093*4882a593Smuzhiyun { DA7213_MIXOUT_R_CTRL, 0x10 },
1094*4882a593Smuzhiyun { DA7213_LDO_CTRL, 0x00 },
1095*4882a593Smuzhiyun { DA7213_IO_CTRL, 0x00 },
1096*4882a593Smuzhiyun { DA7213_GAIN_RAMP_CTRL, 0x00},
1097*4882a593Smuzhiyun { DA7213_MIC_CONFIG, 0x00 },
1098*4882a593Smuzhiyun { DA7213_PC_COUNT, 0x00 },
1099*4882a593Smuzhiyun { DA7213_CP_VOL_THRESHOLD1, 0x32 },
1100*4882a593Smuzhiyun { DA7213_CP_DELAY, 0x95 },
1101*4882a593Smuzhiyun { DA7213_CP_DETECTOR, 0x00 },
1102*4882a593Smuzhiyun { DA7213_DAI_OFFSET, 0x00 },
1103*4882a593Smuzhiyun { DA7213_DIG_CTRL, 0x00 },
1104*4882a593Smuzhiyun { DA7213_ALC_CTRL2, 0x00 },
1105*4882a593Smuzhiyun { DA7213_ALC_CTRL3, 0x00 },
1106*4882a593Smuzhiyun { DA7213_ALC_NOISE, 0x3F },
1107*4882a593Smuzhiyun { DA7213_ALC_TARGET_MIN, 0x3F },
1108*4882a593Smuzhiyun { DA7213_ALC_TARGET_MAX, 0x00 },
1109*4882a593Smuzhiyun { DA7213_ALC_GAIN_LIMITS, 0xFF },
1110*4882a593Smuzhiyun { DA7213_ALC_ANA_GAIN_LIMITS, 0x71 },
1111*4882a593Smuzhiyun { DA7213_ALC_ANTICLIP_CTRL, 0x00 },
1112*4882a593Smuzhiyun { DA7213_ALC_ANTICLIP_LEVEL, 0x00 },
1113*4882a593Smuzhiyun { DA7213_ALC_OFFSET_MAN_M_L, 0x00 },
1114*4882a593Smuzhiyun { DA7213_ALC_OFFSET_MAN_U_L, 0x00 },
1115*4882a593Smuzhiyun { DA7213_ALC_OFFSET_MAN_M_R, 0x00 },
1116*4882a593Smuzhiyun { DA7213_ALC_OFFSET_MAN_U_R, 0x00 },
1117*4882a593Smuzhiyun { DA7213_ALC_CIC_OP_LVL_CTRL, 0x00 },
1118*4882a593Smuzhiyun { DA7213_DAC_NG_SETUP_TIME, 0x00 },
1119*4882a593Smuzhiyun { DA7213_DAC_NG_OFF_THRESHOLD, 0x00 },
1120*4882a593Smuzhiyun { DA7213_DAC_NG_ON_THRESHOLD, 0x00 },
1121*4882a593Smuzhiyun { DA7213_DAC_NG_CTRL, 0x00 },
1122*4882a593Smuzhiyun };
1123*4882a593Smuzhiyun
da7213_volatile_register(struct device * dev,unsigned int reg)1124*4882a593Smuzhiyun static bool da7213_volatile_register(struct device *dev, unsigned int reg)
1125*4882a593Smuzhiyun {
1126*4882a593Smuzhiyun switch (reg) {
1127*4882a593Smuzhiyun case DA7213_STATUS1:
1128*4882a593Smuzhiyun case DA7213_PLL_STATUS:
1129*4882a593Smuzhiyun case DA7213_AUX_L_GAIN_STATUS:
1130*4882a593Smuzhiyun case DA7213_AUX_R_GAIN_STATUS:
1131*4882a593Smuzhiyun case DA7213_MIC_1_GAIN_STATUS:
1132*4882a593Smuzhiyun case DA7213_MIC_2_GAIN_STATUS:
1133*4882a593Smuzhiyun case DA7213_MIXIN_L_GAIN_STATUS:
1134*4882a593Smuzhiyun case DA7213_MIXIN_R_GAIN_STATUS:
1135*4882a593Smuzhiyun case DA7213_ADC_L_GAIN_STATUS:
1136*4882a593Smuzhiyun case DA7213_ADC_R_GAIN_STATUS:
1137*4882a593Smuzhiyun case DA7213_DAC_L_GAIN_STATUS:
1138*4882a593Smuzhiyun case DA7213_DAC_R_GAIN_STATUS:
1139*4882a593Smuzhiyun case DA7213_HP_L_GAIN_STATUS:
1140*4882a593Smuzhiyun case DA7213_HP_R_GAIN_STATUS:
1141*4882a593Smuzhiyun case DA7213_LINE_GAIN_STATUS:
1142*4882a593Smuzhiyun case DA7213_ALC_CTRL1:
1143*4882a593Smuzhiyun case DA7213_ALC_OFFSET_AUTO_M_L:
1144*4882a593Smuzhiyun case DA7213_ALC_OFFSET_AUTO_U_L:
1145*4882a593Smuzhiyun case DA7213_ALC_OFFSET_AUTO_M_R:
1146*4882a593Smuzhiyun case DA7213_ALC_OFFSET_AUTO_U_R:
1147*4882a593Smuzhiyun case DA7213_ALC_CIC_OP_LVL_DATA:
1148*4882a593Smuzhiyun return true;
1149*4882a593Smuzhiyun default:
1150*4882a593Smuzhiyun return false;
1151*4882a593Smuzhiyun }
1152*4882a593Smuzhiyun }
1153*4882a593Smuzhiyun
da7213_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1154*4882a593Smuzhiyun static int da7213_hw_params(struct snd_pcm_substream *substream,
1155*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
1156*4882a593Smuzhiyun struct snd_soc_dai *dai)
1157*4882a593Smuzhiyun {
1158*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
1159*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
1160*4882a593Smuzhiyun u8 dai_ctrl = 0;
1161*4882a593Smuzhiyun u8 fs;
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun /* Set DAI format */
1164*4882a593Smuzhiyun switch (params_width(params)) {
1165*4882a593Smuzhiyun case 16:
1166*4882a593Smuzhiyun dai_ctrl |= DA7213_DAI_WORD_LENGTH_S16_LE;
1167*4882a593Smuzhiyun break;
1168*4882a593Smuzhiyun case 20:
1169*4882a593Smuzhiyun dai_ctrl |= DA7213_DAI_WORD_LENGTH_S20_LE;
1170*4882a593Smuzhiyun break;
1171*4882a593Smuzhiyun case 24:
1172*4882a593Smuzhiyun dai_ctrl |= DA7213_DAI_WORD_LENGTH_S24_LE;
1173*4882a593Smuzhiyun break;
1174*4882a593Smuzhiyun case 32:
1175*4882a593Smuzhiyun dai_ctrl |= DA7213_DAI_WORD_LENGTH_S32_LE;
1176*4882a593Smuzhiyun break;
1177*4882a593Smuzhiyun default:
1178*4882a593Smuzhiyun return -EINVAL;
1179*4882a593Smuzhiyun }
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun /* Set sampling rate */
1182*4882a593Smuzhiyun switch (params_rate(params)) {
1183*4882a593Smuzhiyun case 8000:
1184*4882a593Smuzhiyun fs = DA7213_SR_8000;
1185*4882a593Smuzhiyun da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
1186*4882a593Smuzhiyun break;
1187*4882a593Smuzhiyun case 11025:
1188*4882a593Smuzhiyun fs = DA7213_SR_11025;
1189*4882a593Smuzhiyun da7213->out_rate = DA7213_PLL_FREQ_OUT_90316800;
1190*4882a593Smuzhiyun break;
1191*4882a593Smuzhiyun case 12000:
1192*4882a593Smuzhiyun fs = DA7213_SR_12000;
1193*4882a593Smuzhiyun da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
1194*4882a593Smuzhiyun break;
1195*4882a593Smuzhiyun case 16000:
1196*4882a593Smuzhiyun fs = DA7213_SR_16000;
1197*4882a593Smuzhiyun da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
1198*4882a593Smuzhiyun break;
1199*4882a593Smuzhiyun case 22050:
1200*4882a593Smuzhiyun fs = DA7213_SR_22050;
1201*4882a593Smuzhiyun da7213->out_rate = DA7213_PLL_FREQ_OUT_90316800;
1202*4882a593Smuzhiyun break;
1203*4882a593Smuzhiyun case 32000:
1204*4882a593Smuzhiyun fs = DA7213_SR_32000;
1205*4882a593Smuzhiyun da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
1206*4882a593Smuzhiyun break;
1207*4882a593Smuzhiyun case 44100:
1208*4882a593Smuzhiyun fs = DA7213_SR_44100;
1209*4882a593Smuzhiyun da7213->out_rate = DA7213_PLL_FREQ_OUT_90316800;
1210*4882a593Smuzhiyun break;
1211*4882a593Smuzhiyun case 48000:
1212*4882a593Smuzhiyun fs = DA7213_SR_48000;
1213*4882a593Smuzhiyun da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
1214*4882a593Smuzhiyun break;
1215*4882a593Smuzhiyun case 88200:
1216*4882a593Smuzhiyun fs = DA7213_SR_88200;
1217*4882a593Smuzhiyun da7213->out_rate = DA7213_PLL_FREQ_OUT_90316800;
1218*4882a593Smuzhiyun break;
1219*4882a593Smuzhiyun case 96000:
1220*4882a593Smuzhiyun fs = DA7213_SR_96000;
1221*4882a593Smuzhiyun da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
1222*4882a593Smuzhiyun break;
1223*4882a593Smuzhiyun default:
1224*4882a593Smuzhiyun return -EINVAL;
1225*4882a593Smuzhiyun }
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAI_CTRL, DA7213_DAI_WORD_LENGTH_MASK,
1228*4882a593Smuzhiyun dai_ctrl);
1229*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_SR, fs);
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun return 0;
1232*4882a593Smuzhiyun }
1233*4882a593Smuzhiyun
da7213_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1234*4882a593Smuzhiyun static int da7213_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1235*4882a593Smuzhiyun {
1236*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
1237*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
1238*4882a593Smuzhiyun u8 dai_clk_mode = 0, dai_ctrl = 0;
1239*4882a593Smuzhiyun u8 dai_offset = 0;
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun /* Set master/slave mode */
1242*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1243*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
1244*4882a593Smuzhiyun da7213->master = true;
1245*4882a593Smuzhiyun break;
1246*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
1247*4882a593Smuzhiyun da7213->master = false;
1248*4882a593Smuzhiyun break;
1249*4882a593Smuzhiyun default:
1250*4882a593Smuzhiyun return -EINVAL;
1251*4882a593Smuzhiyun }
1252*4882a593Smuzhiyun
1253*4882a593Smuzhiyun /* Set clock normal/inverted */
1254*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1255*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
1256*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
1257*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
1258*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1259*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
1260*4882a593Smuzhiyun break;
1261*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
1262*4882a593Smuzhiyun dai_clk_mode |= DA7213_DAI_WCLK_POL_INV;
1263*4882a593Smuzhiyun break;
1264*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
1265*4882a593Smuzhiyun dai_clk_mode |= DA7213_DAI_CLK_POL_INV;
1266*4882a593Smuzhiyun break;
1267*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
1268*4882a593Smuzhiyun dai_clk_mode |= DA7213_DAI_WCLK_POL_INV |
1269*4882a593Smuzhiyun DA7213_DAI_CLK_POL_INV;
1270*4882a593Smuzhiyun break;
1271*4882a593Smuzhiyun default:
1272*4882a593Smuzhiyun return -EINVAL;
1273*4882a593Smuzhiyun }
1274*4882a593Smuzhiyun break;
1275*4882a593Smuzhiyun case SND_SOC_DAI_FORMAT_DSP_A:
1276*4882a593Smuzhiyun case SND_SOC_DAI_FORMAT_DSP_B:
1277*4882a593Smuzhiyun /* The bclk is inverted wrt ASoC conventions */
1278*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1279*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
1280*4882a593Smuzhiyun dai_clk_mode |= DA7213_DAI_CLK_POL_INV;
1281*4882a593Smuzhiyun break;
1282*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
1283*4882a593Smuzhiyun dai_clk_mode |= DA7213_DAI_WCLK_POL_INV |
1284*4882a593Smuzhiyun DA7213_DAI_CLK_POL_INV;
1285*4882a593Smuzhiyun break;
1286*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
1287*4882a593Smuzhiyun break;
1288*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
1289*4882a593Smuzhiyun dai_clk_mode |= DA7213_DAI_WCLK_POL_INV;
1290*4882a593Smuzhiyun break;
1291*4882a593Smuzhiyun default:
1292*4882a593Smuzhiyun return -EINVAL;
1293*4882a593Smuzhiyun }
1294*4882a593Smuzhiyun break;
1295*4882a593Smuzhiyun default:
1296*4882a593Smuzhiyun return -EINVAL;
1297*4882a593Smuzhiyun }
1298*4882a593Smuzhiyun
1299*4882a593Smuzhiyun /* Only I2S is supported */
1300*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1301*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
1302*4882a593Smuzhiyun dai_ctrl |= DA7213_DAI_FORMAT_I2S_MODE;
1303*4882a593Smuzhiyun break;
1304*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
1305*4882a593Smuzhiyun dai_ctrl |= DA7213_DAI_FORMAT_LEFT_J;
1306*4882a593Smuzhiyun break;
1307*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
1308*4882a593Smuzhiyun dai_ctrl |= DA7213_DAI_FORMAT_RIGHT_J;
1309*4882a593Smuzhiyun break;
1310*4882a593Smuzhiyun case SND_SOC_DAI_FORMAT_DSP_A: /* L data MSB after FRM LRC */
1311*4882a593Smuzhiyun dai_ctrl |= DA7213_DAI_FORMAT_DSP;
1312*4882a593Smuzhiyun dai_offset = 1;
1313*4882a593Smuzhiyun break;
1314*4882a593Smuzhiyun case SND_SOC_DAI_FORMAT_DSP_B: /* L data MSB during FRM LRC */
1315*4882a593Smuzhiyun dai_ctrl |= DA7213_DAI_FORMAT_DSP;
1316*4882a593Smuzhiyun break;
1317*4882a593Smuzhiyun default:
1318*4882a593Smuzhiyun return -EINVAL;
1319*4882a593Smuzhiyun }
1320*4882a593Smuzhiyun
1321*4882a593Smuzhiyun /* By default only 64 BCLK per WCLK is supported */
1322*4882a593Smuzhiyun dai_clk_mode |= DA7213_DAI_BCLKS_PER_WCLK_64;
1323*4882a593Smuzhiyun
1324*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAI_CLK_MODE,
1325*4882a593Smuzhiyun DA7213_DAI_BCLKS_PER_WCLK_MASK |
1326*4882a593Smuzhiyun DA7213_DAI_CLK_POL_MASK | DA7213_DAI_WCLK_POL_MASK,
1327*4882a593Smuzhiyun dai_clk_mode);
1328*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAI_CTRL, DA7213_DAI_FORMAT_MASK,
1329*4882a593Smuzhiyun dai_ctrl);
1330*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_DAI_OFFSET, dai_offset);
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun return 0;
1333*4882a593Smuzhiyun }
1334*4882a593Smuzhiyun
da7213_mute(struct snd_soc_dai * dai,int mute,int direction)1335*4882a593Smuzhiyun static int da7213_mute(struct snd_soc_dai *dai, int mute, int direction)
1336*4882a593Smuzhiyun {
1337*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
1338*4882a593Smuzhiyun
1339*4882a593Smuzhiyun if (mute) {
1340*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAC_L_CTRL,
1341*4882a593Smuzhiyun DA7213_MUTE_EN, DA7213_MUTE_EN);
1342*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAC_R_CTRL,
1343*4882a593Smuzhiyun DA7213_MUTE_EN, DA7213_MUTE_EN);
1344*4882a593Smuzhiyun } else {
1345*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAC_L_CTRL,
1346*4882a593Smuzhiyun DA7213_MUTE_EN, 0);
1347*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAC_R_CTRL,
1348*4882a593Smuzhiyun DA7213_MUTE_EN, 0);
1349*4882a593Smuzhiyun }
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun return 0;
1352*4882a593Smuzhiyun }
1353*4882a593Smuzhiyun
1354*4882a593Smuzhiyun #define DA7213_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1355*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1356*4882a593Smuzhiyun
da7213_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)1357*4882a593Smuzhiyun static int da7213_set_component_sysclk(struct snd_soc_component *component,
1358*4882a593Smuzhiyun int clk_id, int source,
1359*4882a593Smuzhiyun unsigned int freq, int dir)
1360*4882a593Smuzhiyun {
1361*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
1362*4882a593Smuzhiyun int ret = 0;
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun if ((da7213->clk_src == clk_id) && (da7213->mclk_rate == freq))
1365*4882a593Smuzhiyun return 0;
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun if (((freq < 5000000) && (freq != 32768)) || (freq > 54000000)) {
1368*4882a593Smuzhiyun dev_err(component->dev, "Unsupported MCLK value %d\n",
1369*4882a593Smuzhiyun freq);
1370*4882a593Smuzhiyun return -EINVAL;
1371*4882a593Smuzhiyun }
1372*4882a593Smuzhiyun
1373*4882a593Smuzhiyun switch (clk_id) {
1374*4882a593Smuzhiyun case DA7213_CLKSRC_MCLK:
1375*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_PLL_CTRL,
1376*4882a593Smuzhiyun DA7213_PLL_MCLK_SQR_EN, 0);
1377*4882a593Smuzhiyun break;
1378*4882a593Smuzhiyun case DA7213_CLKSRC_MCLK_SQR:
1379*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_PLL_CTRL,
1380*4882a593Smuzhiyun DA7213_PLL_MCLK_SQR_EN,
1381*4882a593Smuzhiyun DA7213_PLL_MCLK_SQR_EN);
1382*4882a593Smuzhiyun break;
1383*4882a593Smuzhiyun default:
1384*4882a593Smuzhiyun dev_err(component->dev, "Unknown clock source %d\n", clk_id);
1385*4882a593Smuzhiyun return -EINVAL;
1386*4882a593Smuzhiyun }
1387*4882a593Smuzhiyun
1388*4882a593Smuzhiyun da7213->clk_src = clk_id;
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun if (da7213->mclk) {
1391*4882a593Smuzhiyun freq = clk_round_rate(da7213->mclk, freq);
1392*4882a593Smuzhiyun ret = clk_set_rate(da7213->mclk, freq);
1393*4882a593Smuzhiyun if (ret) {
1394*4882a593Smuzhiyun dev_err(component->dev, "Failed to set clock rate %d\n",
1395*4882a593Smuzhiyun freq);
1396*4882a593Smuzhiyun return ret;
1397*4882a593Smuzhiyun }
1398*4882a593Smuzhiyun }
1399*4882a593Smuzhiyun
1400*4882a593Smuzhiyun da7213->mclk_rate = freq;
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun return 0;
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun /* Supported PLL input frequencies are 32KHz, 5MHz - 54MHz. */
_da7213_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int fref,unsigned int fout)1406*4882a593Smuzhiyun static int _da7213_set_component_pll(struct snd_soc_component *component,
1407*4882a593Smuzhiyun int pll_id, int source,
1408*4882a593Smuzhiyun unsigned int fref, unsigned int fout)
1409*4882a593Smuzhiyun {
1410*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun u8 pll_ctrl, indiv_bits, indiv;
1413*4882a593Smuzhiyun u8 pll_frac_top, pll_frac_bot, pll_integer;
1414*4882a593Smuzhiyun u32 freq_ref;
1415*4882a593Smuzhiyun u64 frac_div;
1416*4882a593Smuzhiyun
1417*4882a593Smuzhiyun /* Workout input divider based on MCLK rate */
1418*4882a593Smuzhiyun if (da7213->mclk_rate == 32768) {
1419*4882a593Smuzhiyun if (!da7213->master) {
1420*4882a593Smuzhiyun dev_err(component->dev,
1421*4882a593Smuzhiyun "32KHz only valid if codec is clock master\n");
1422*4882a593Smuzhiyun return -EINVAL;
1423*4882a593Smuzhiyun }
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun /* 32KHz PLL Mode */
1426*4882a593Smuzhiyun indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ;
1427*4882a593Smuzhiyun indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL;
1428*4882a593Smuzhiyun source = DA7213_SYSCLK_PLL_32KHZ;
1429*4882a593Smuzhiyun freq_ref = 3750000;
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun } else {
1432*4882a593Smuzhiyun if (da7213->mclk_rate < 5000000) {
1433*4882a593Smuzhiyun dev_err(component->dev,
1434*4882a593Smuzhiyun "PLL input clock %d below valid range\n",
1435*4882a593Smuzhiyun da7213->mclk_rate);
1436*4882a593Smuzhiyun return -EINVAL;
1437*4882a593Smuzhiyun } else if (da7213->mclk_rate <= 9000000) {
1438*4882a593Smuzhiyun indiv_bits = DA7213_PLL_INDIV_5_TO_9_MHZ;
1439*4882a593Smuzhiyun indiv = DA7213_PLL_INDIV_5_TO_9_MHZ_VAL;
1440*4882a593Smuzhiyun } else if (da7213->mclk_rate <= 18000000) {
1441*4882a593Smuzhiyun indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ;
1442*4882a593Smuzhiyun indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL;
1443*4882a593Smuzhiyun } else if (da7213->mclk_rate <= 36000000) {
1444*4882a593Smuzhiyun indiv_bits = DA7213_PLL_INDIV_18_TO_36_MHZ;
1445*4882a593Smuzhiyun indiv = DA7213_PLL_INDIV_18_TO_36_MHZ_VAL;
1446*4882a593Smuzhiyun } else if (da7213->mclk_rate <= 54000000) {
1447*4882a593Smuzhiyun indiv_bits = DA7213_PLL_INDIV_36_TO_54_MHZ;
1448*4882a593Smuzhiyun indiv = DA7213_PLL_INDIV_36_TO_54_MHZ_VAL;
1449*4882a593Smuzhiyun } else {
1450*4882a593Smuzhiyun dev_err(component->dev,
1451*4882a593Smuzhiyun "PLL input clock %d above valid range\n",
1452*4882a593Smuzhiyun da7213->mclk_rate);
1453*4882a593Smuzhiyun return -EINVAL;
1454*4882a593Smuzhiyun }
1455*4882a593Smuzhiyun freq_ref = (da7213->mclk_rate / indiv);
1456*4882a593Smuzhiyun }
1457*4882a593Smuzhiyun
1458*4882a593Smuzhiyun pll_ctrl = indiv_bits;
1459*4882a593Smuzhiyun
1460*4882a593Smuzhiyun /* Configure PLL */
1461*4882a593Smuzhiyun switch (source) {
1462*4882a593Smuzhiyun case DA7213_SYSCLK_MCLK:
1463*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_PLL_CTRL,
1464*4882a593Smuzhiyun DA7213_PLL_INDIV_MASK |
1465*4882a593Smuzhiyun DA7213_PLL_MODE_MASK, pll_ctrl);
1466*4882a593Smuzhiyun return 0;
1467*4882a593Smuzhiyun case DA7213_SYSCLK_PLL:
1468*4882a593Smuzhiyun break;
1469*4882a593Smuzhiyun case DA7213_SYSCLK_PLL_SRM:
1470*4882a593Smuzhiyun pll_ctrl |= DA7213_PLL_SRM_EN;
1471*4882a593Smuzhiyun fout = DA7213_PLL_FREQ_OUT_94310400;
1472*4882a593Smuzhiyun break;
1473*4882a593Smuzhiyun case DA7213_SYSCLK_PLL_32KHZ:
1474*4882a593Smuzhiyun if (da7213->mclk_rate != 32768) {
1475*4882a593Smuzhiyun dev_err(component->dev,
1476*4882a593Smuzhiyun "32KHz mode only valid with 32KHz MCLK\n");
1477*4882a593Smuzhiyun return -EINVAL;
1478*4882a593Smuzhiyun }
1479*4882a593Smuzhiyun
1480*4882a593Smuzhiyun pll_ctrl |= DA7213_PLL_32K_MODE | DA7213_PLL_SRM_EN;
1481*4882a593Smuzhiyun fout = DA7213_PLL_FREQ_OUT_94310400;
1482*4882a593Smuzhiyun break;
1483*4882a593Smuzhiyun default:
1484*4882a593Smuzhiyun dev_err(component->dev, "Invalid PLL config\n");
1485*4882a593Smuzhiyun return -EINVAL;
1486*4882a593Smuzhiyun }
1487*4882a593Smuzhiyun
1488*4882a593Smuzhiyun /* Calculate dividers for PLL */
1489*4882a593Smuzhiyun pll_integer = fout / freq_ref;
1490*4882a593Smuzhiyun frac_div = (u64)(fout % freq_ref) * 8192ULL;
1491*4882a593Smuzhiyun do_div(frac_div, freq_ref);
1492*4882a593Smuzhiyun pll_frac_top = (frac_div >> DA7213_BYTE_SHIFT) & DA7213_BYTE_MASK;
1493*4882a593Smuzhiyun pll_frac_bot = (frac_div) & DA7213_BYTE_MASK;
1494*4882a593Smuzhiyun
1495*4882a593Smuzhiyun /* Write PLL dividers */
1496*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_PLL_FRAC_TOP, pll_frac_top);
1497*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_PLL_FRAC_BOT, pll_frac_bot);
1498*4882a593Smuzhiyun snd_soc_component_write(component, DA7213_PLL_INTEGER, pll_integer);
1499*4882a593Smuzhiyun
1500*4882a593Smuzhiyun /* Enable PLL */
1501*4882a593Smuzhiyun pll_ctrl |= DA7213_PLL_EN;
1502*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_PLL_CTRL,
1503*4882a593Smuzhiyun DA7213_PLL_INDIV_MASK | DA7213_PLL_MODE_MASK,
1504*4882a593Smuzhiyun pll_ctrl);
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun /* Assist 32KHz mode PLL lock */
1507*4882a593Smuzhiyun if (source == DA7213_SYSCLK_PLL_32KHZ) {
1508*4882a593Smuzhiyun snd_soc_component_write(component, 0xF0, 0x8B);
1509*4882a593Smuzhiyun snd_soc_component_write(component, 0xF1, 0x03);
1510*4882a593Smuzhiyun snd_soc_component_write(component, 0xF1, 0x01);
1511*4882a593Smuzhiyun snd_soc_component_write(component, 0xF0, 0x00);
1512*4882a593Smuzhiyun }
1513*4882a593Smuzhiyun
1514*4882a593Smuzhiyun return 0;
1515*4882a593Smuzhiyun }
1516*4882a593Smuzhiyun
da7213_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int fref,unsigned int fout)1517*4882a593Smuzhiyun static int da7213_set_component_pll(struct snd_soc_component *component,
1518*4882a593Smuzhiyun int pll_id, int source,
1519*4882a593Smuzhiyun unsigned int fref, unsigned int fout)
1520*4882a593Smuzhiyun {
1521*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
1522*4882a593Smuzhiyun da7213->fixed_clk_auto_pll = false;
1523*4882a593Smuzhiyun
1524*4882a593Smuzhiyun return _da7213_set_component_pll(component, pll_id, source, fref, fout);
1525*4882a593Smuzhiyun }
1526*4882a593Smuzhiyun
1527*4882a593Smuzhiyun /* DAI operations */
1528*4882a593Smuzhiyun static const struct snd_soc_dai_ops da7213_dai_ops = {
1529*4882a593Smuzhiyun .hw_params = da7213_hw_params,
1530*4882a593Smuzhiyun .set_fmt = da7213_set_dai_fmt,
1531*4882a593Smuzhiyun .mute_stream = da7213_mute,
1532*4882a593Smuzhiyun .no_capture_mute = 1,
1533*4882a593Smuzhiyun };
1534*4882a593Smuzhiyun
1535*4882a593Smuzhiyun static struct snd_soc_dai_driver da7213_dai = {
1536*4882a593Smuzhiyun .name = "da7213-hifi",
1537*4882a593Smuzhiyun /* Playback Capabilities */
1538*4882a593Smuzhiyun .playback = {
1539*4882a593Smuzhiyun .stream_name = "Playback",
1540*4882a593Smuzhiyun .channels_min = 1,
1541*4882a593Smuzhiyun .channels_max = 2,
1542*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_96000,
1543*4882a593Smuzhiyun .formats = DA7213_FORMATS,
1544*4882a593Smuzhiyun },
1545*4882a593Smuzhiyun /* Capture Capabilities */
1546*4882a593Smuzhiyun .capture = {
1547*4882a593Smuzhiyun .stream_name = "Capture",
1548*4882a593Smuzhiyun .channels_min = 1,
1549*4882a593Smuzhiyun .channels_max = 2,
1550*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_96000,
1551*4882a593Smuzhiyun .formats = DA7213_FORMATS,
1552*4882a593Smuzhiyun },
1553*4882a593Smuzhiyun .ops = &da7213_dai_ops,
1554*4882a593Smuzhiyun .symmetric_rates = 1,
1555*4882a593Smuzhiyun };
1556*4882a593Smuzhiyun
da7213_set_auto_pll(struct snd_soc_component * component,bool enable)1557*4882a593Smuzhiyun static int da7213_set_auto_pll(struct snd_soc_component *component, bool enable)
1558*4882a593Smuzhiyun {
1559*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
1560*4882a593Smuzhiyun int mode;
1561*4882a593Smuzhiyun
1562*4882a593Smuzhiyun if (!da7213->fixed_clk_auto_pll)
1563*4882a593Smuzhiyun return 0;
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun da7213->mclk_rate = clk_get_rate(da7213->mclk);
1566*4882a593Smuzhiyun
1567*4882a593Smuzhiyun if (enable) {
1568*4882a593Smuzhiyun /* Slave mode needs SRM for non-harmonic frequencies */
1569*4882a593Smuzhiyun if (da7213->master)
1570*4882a593Smuzhiyun mode = DA7213_SYSCLK_PLL;
1571*4882a593Smuzhiyun else
1572*4882a593Smuzhiyun mode = DA7213_SYSCLK_PLL_SRM;
1573*4882a593Smuzhiyun
1574*4882a593Smuzhiyun /* PLL is not required for harmonic frequencies */
1575*4882a593Smuzhiyun switch (da7213->out_rate) {
1576*4882a593Smuzhiyun case DA7213_PLL_FREQ_OUT_90316800:
1577*4882a593Smuzhiyun if (da7213->mclk_rate == 11289600 ||
1578*4882a593Smuzhiyun da7213->mclk_rate == 22579200 ||
1579*4882a593Smuzhiyun da7213->mclk_rate == 45158400)
1580*4882a593Smuzhiyun mode = DA7213_SYSCLK_MCLK;
1581*4882a593Smuzhiyun break;
1582*4882a593Smuzhiyun case DA7213_PLL_FREQ_OUT_98304000:
1583*4882a593Smuzhiyun if (da7213->mclk_rate == 12288000 ||
1584*4882a593Smuzhiyun da7213->mclk_rate == 24576000 ||
1585*4882a593Smuzhiyun da7213->mclk_rate == 49152000)
1586*4882a593Smuzhiyun mode = DA7213_SYSCLK_MCLK;
1587*4882a593Smuzhiyun
1588*4882a593Smuzhiyun break;
1589*4882a593Smuzhiyun default:
1590*4882a593Smuzhiyun return -1;
1591*4882a593Smuzhiyun }
1592*4882a593Smuzhiyun } else {
1593*4882a593Smuzhiyun /* Disable PLL in standby */
1594*4882a593Smuzhiyun mode = DA7213_SYSCLK_MCLK;
1595*4882a593Smuzhiyun }
1596*4882a593Smuzhiyun
1597*4882a593Smuzhiyun return _da7213_set_component_pll(component, 0, mode,
1598*4882a593Smuzhiyun da7213->mclk_rate, da7213->out_rate);
1599*4882a593Smuzhiyun }
1600*4882a593Smuzhiyun
da7213_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1601*4882a593Smuzhiyun static int da7213_set_bias_level(struct snd_soc_component *component,
1602*4882a593Smuzhiyun enum snd_soc_bias_level level)
1603*4882a593Smuzhiyun {
1604*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
1605*4882a593Smuzhiyun int ret;
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun switch (level) {
1608*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
1609*4882a593Smuzhiyun break;
1610*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
1611*4882a593Smuzhiyun /* Enable MCLK for transition to ON state */
1612*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
1613*4882a593Smuzhiyun if (da7213->mclk) {
1614*4882a593Smuzhiyun ret = clk_prepare_enable(da7213->mclk);
1615*4882a593Smuzhiyun if (ret) {
1616*4882a593Smuzhiyun dev_err(component->dev,
1617*4882a593Smuzhiyun "Failed to enable mclk\n");
1618*4882a593Smuzhiyun return ret;
1619*4882a593Smuzhiyun }
1620*4882a593Smuzhiyun
1621*4882a593Smuzhiyun da7213_set_auto_pll(component, true);
1622*4882a593Smuzhiyun }
1623*4882a593Smuzhiyun }
1624*4882a593Smuzhiyun break;
1625*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
1626*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1627*4882a593Smuzhiyun /* Enable VMID reference & master bias */
1628*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_REFERENCES,
1629*4882a593Smuzhiyun DA7213_VMID_EN | DA7213_BIAS_EN,
1630*4882a593Smuzhiyun DA7213_VMID_EN | DA7213_BIAS_EN);
1631*4882a593Smuzhiyun } else {
1632*4882a593Smuzhiyun /* Remove MCLK */
1633*4882a593Smuzhiyun if (da7213->mclk) {
1634*4882a593Smuzhiyun da7213_set_auto_pll(component, false);
1635*4882a593Smuzhiyun clk_disable_unprepare(da7213->mclk);
1636*4882a593Smuzhiyun }
1637*4882a593Smuzhiyun }
1638*4882a593Smuzhiyun break;
1639*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
1640*4882a593Smuzhiyun /* Disable VMID reference & master bias */
1641*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_REFERENCES,
1642*4882a593Smuzhiyun DA7213_VMID_EN | DA7213_BIAS_EN, 0);
1643*4882a593Smuzhiyun break;
1644*4882a593Smuzhiyun }
1645*4882a593Smuzhiyun return 0;
1646*4882a593Smuzhiyun }
1647*4882a593Smuzhiyun
1648*4882a593Smuzhiyun #if defined(CONFIG_OF)
1649*4882a593Smuzhiyun /* DT */
1650*4882a593Smuzhiyun static const struct of_device_id da7213_of_match[] = {
1651*4882a593Smuzhiyun { .compatible = "dlg,da7212", },
1652*4882a593Smuzhiyun { .compatible = "dlg,da7213", },
1653*4882a593Smuzhiyun { }
1654*4882a593Smuzhiyun };
1655*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, da7213_of_match);
1656*4882a593Smuzhiyun #endif
1657*4882a593Smuzhiyun
1658*4882a593Smuzhiyun #ifdef CONFIG_ACPI
1659*4882a593Smuzhiyun static const struct acpi_device_id da7213_acpi_match[] = {
1660*4882a593Smuzhiyun { "DLGS7212", 0},
1661*4882a593Smuzhiyun { "DLGS7213", 0},
1662*4882a593Smuzhiyun { },
1663*4882a593Smuzhiyun };
1664*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, da7213_acpi_match);
1665*4882a593Smuzhiyun #endif
1666*4882a593Smuzhiyun
1667*4882a593Smuzhiyun static enum da7213_micbias_voltage
da7213_of_micbias_lvl(struct snd_soc_component * component,u32 val)1668*4882a593Smuzhiyun da7213_of_micbias_lvl(struct snd_soc_component *component, u32 val)
1669*4882a593Smuzhiyun {
1670*4882a593Smuzhiyun switch (val) {
1671*4882a593Smuzhiyun case 1600:
1672*4882a593Smuzhiyun return DA7213_MICBIAS_1_6V;
1673*4882a593Smuzhiyun case 2200:
1674*4882a593Smuzhiyun return DA7213_MICBIAS_2_2V;
1675*4882a593Smuzhiyun case 2500:
1676*4882a593Smuzhiyun return DA7213_MICBIAS_2_5V;
1677*4882a593Smuzhiyun case 3000:
1678*4882a593Smuzhiyun return DA7213_MICBIAS_3_0V;
1679*4882a593Smuzhiyun default:
1680*4882a593Smuzhiyun dev_warn(component->dev, "Invalid micbias level\n");
1681*4882a593Smuzhiyun return DA7213_MICBIAS_2_2V;
1682*4882a593Smuzhiyun }
1683*4882a593Smuzhiyun }
1684*4882a593Smuzhiyun
1685*4882a593Smuzhiyun static enum da7213_dmic_data_sel
da7213_of_dmic_data_sel(struct snd_soc_component * component,const char * str)1686*4882a593Smuzhiyun da7213_of_dmic_data_sel(struct snd_soc_component *component, const char *str)
1687*4882a593Smuzhiyun {
1688*4882a593Smuzhiyun if (!strcmp(str, "lrise_rfall")) {
1689*4882a593Smuzhiyun return DA7213_DMIC_DATA_LRISE_RFALL;
1690*4882a593Smuzhiyun } else if (!strcmp(str, "lfall_rrise")) {
1691*4882a593Smuzhiyun return DA7213_DMIC_DATA_LFALL_RRISE;
1692*4882a593Smuzhiyun } else {
1693*4882a593Smuzhiyun dev_warn(component->dev, "Invalid DMIC data select type\n");
1694*4882a593Smuzhiyun return DA7213_DMIC_DATA_LRISE_RFALL;
1695*4882a593Smuzhiyun }
1696*4882a593Smuzhiyun }
1697*4882a593Smuzhiyun
1698*4882a593Smuzhiyun static enum da7213_dmic_samplephase
da7213_of_dmic_samplephase(struct snd_soc_component * component,const char * str)1699*4882a593Smuzhiyun da7213_of_dmic_samplephase(struct snd_soc_component *component, const char *str)
1700*4882a593Smuzhiyun {
1701*4882a593Smuzhiyun if (!strcmp(str, "on_clkedge")) {
1702*4882a593Smuzhiyun return DA7213_DMIC_SAMPLE_ON_CLKEDGE;
1703*4882a593Smuzhiyun } else if (!strcmp(str, "between_clkedge")) {
1704*4882a593Smuzhiyun return DA7213_DMIC_SAMPLE_BETWEEN_CLKEDGE;
1705*4882a593Smuzhiyun } else {
1706*4882a593Smuzhiyun dev_warn(component->dev, "Invalid DMIC sample phase\n");
1707*4882a593Smuzhiyun return DA7213_DMIC_SAMPLE_ON_CLKEDGE;
1708*4882a593Smuzhiyun }
1709*4882a593Smuzhiyun }
1710*4882a593Smuzhiyun
1711*4882a593Smuzhiyun static enum da7213_dmic_clk_rate
da7213_of_dmic_clkrate(struct snd_soc_component * component,u32 val)1712*4882a593Smuzhiyun da7213_of_dmic_clkrate(struct snd_soc_component *component, u32 val)
1713*4882a593Smuzhiyun {
1714*4882a593Smuzhiyun switch (val) {
1715*4882a593Smuzhiyun case 1500000:
1716*4882a593Smuzhiyun return DA7213_DMIC_CLK_1_5MHZ;
1717*4882a593Smuzhiyun case 3000000:
1718*4882a593Smuzhiyun return DA7213_DMIC_CLK_3_0MHZ;
1719*4882a593Smuzhiyun default:
1720*4882a593Smuzhiyun dev_warn(component->dev, "Invalid DMIC clock rate\n");
1721*4882a593Smuzhiyun return DA7213_DMIC_CLK_1_5MHZ;
1722*4882a593Smuzhiyun }
1723*4882a593Smuzhiyun }
1724*4882a593Smuzhiyun
1725*4882a593Smuzhiyun static struct da7213_platform_data
da7213_fw_to_pdata(struct snd_soc_component * component)1726*4882a593Smuzhiyun *da7213_fw_to_pdata(struct snd_soc_component *component)
1727*4882a593Smuzhiyun {
1728*4882a593Smuzhiyun struct device *dev = component->dev;
1729*4882a593Smuzhiyun struct da7213_platform_data *pdata;
1730*4882a593Smuzhiyun const char *fw_str;
1731*4882a593Smuzhiyun u32 fw_val32;
1732*4882a593Smuzhiyun
1733*4882a593Smuzhiyun pdata = devm_kzalloc(component->dev, sizeof(*pdata), GFP_KERNEL);
1734*4882a593Smuzhiyun if (!pdata)
1735*4882a593Smuzhiyun return NULL;
1736*4882a593Smuzhiyun
1737*4882a593Smuzhiyun if (device_property_read_u32(dev, "dlg,micbias1-lvl", &fw_val32) >= 0)
1738*4882a593Smuzhiyun pdata->micbias1_lvl = da7213_of_micbias_lvl(component, fw_val32);
1739*4882a593Smuzhiyun else
1740*4882a593Smuzhiyun pdata->micbias1_lvl = DA7213_MICBIAS_2_2V;
1741*4882a593Smuzhiyun
1742*4882a593Smuzhiyun if (device_property_read_u32(dev, "dlg,micbias2-lvl", &fw_val32) >= 0)
1743*4882a593Smuzhiyun pdata->micbias2_lvl = da7213_of_micbias_lvl(component, fw_val32);
1744*4882a593Smuzhiyun else
1745*4882a593Smuzhiyun pdata->micbias2_lvl = DA7213_MICBIAS_2_2V;
1746*4882a593Smuzhiyun
1747*4882a593Smuzhiyun if (!device_property_read_string(dev, "dlg,dmic-data-sel", &fw_str))
1748*4882a593Smuzhiyun pdata->dmic_data_sel = da7213_of_dmic_data_sel(component, fw_str);
1749*4882a593Smuzhiyun else
1750*4882a593Smuzhiyun pdata->dmic_data_sel = DA7213_DMIC_DATA_LRISE_RFALL;
1751*4882a593Smuzhiyun
1752*4882a593Smuzhiyun if (!device_property_read_string(dev, "dlg,dmic-samplephase", &fw_str))
1753*4882a593Smuzhiyun pdata->dmic_samplephase =
1754*4882a593Smuzhiyun da7213_of_dmic_samplephase(component, fw_str);
1755*4882a593Smuzhiyun else
1756*4882a593Smuzhiyun pdata->dmic_samplephase = DA7213_DMIC_SAMPLE_ON_CLKEDGE;
1757*4882a593Smuzhiyun
1758*4882a593Smuzhiyun if (device_property_read_u32(dev, "dlg,dmic-clkrate", &fw_val32) >= 0)
1759*4882a593Smuzhiyun pdata->dmic_clk_rate = da7213_of_dmic_clkrate(component, fw_val32);
1760*4882a593Smuzhiyun else
1761*4882a593Smuzhiyun pdata->dmic_clk_rate = DA7213_DMIC_CLK_3_0MHZ;
1762*4882a593Smuzhiyun
1763*4882a593Smuzhiyun return pdata;
1764*4882a593Smuzhiyun }
1765*4882a593Smuzhiyun
da7213_probe(struct snd_soc_component * component)1766*4882a593Smuzhiyun static int da7213_probe(struct snd_soc_component *component)
1767*4882a593Smuzhiyun {
1768*4882a593Smuzhiyun struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
1769*4882a593Smuzhiyun
1770*4882a593Smuzhiyun pm_runtime_get_sync(component->dev);
1771*4882a593Smuzhiyun
1772*4882a593Smuzhiyun /* Default to using ALC auto offset calibration mode. */
1773*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_ALC_CTRL1,
1774*4882a593Smuzhiyun DA7213_ALC_CALIB_MODE_MAN, 0);
1775*4882a593Smuzhiyun da7213->alc_calib_auto = true;
1776*4882a593Smuzhiyun
1777*4882a593Smuzhiyun /* Default PC counter to free-running */
1778*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_PC_COUNT, DA7213_PC_FREERUN_MASK,
1779*4882a593Smuzhiyun DA7213_PC_FREERUN_MASK);
1780*4882a593Smuzhiyun
1781*4882a593Smuzhiyun /* Enable all Gain Ramps */
1782*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_AUX_L_CTRL,
1783*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1784*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_AUX_R_CTRL,
1785*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1786*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIXIN_L_CTRL,
1787*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1788*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIXIN_R_CTRL,
1789*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1790*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_ADC_L_CTRL,
1791*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1792*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_ADC_R_CTRL,
1793*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1794*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAC_L_CTRL,
1795*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1796*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_DAC_R_CTRL,
1797*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1798*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_HP_L_CTRL,
1799*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1800*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_HP_R_CTRL,
1801*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1802*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_LINE_CTRL,
1803*4882a593Smuzhiyun DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
1804*4882a593Smuzhiyun
1805*4882a593Smuzhiyun /*
1806*4882a593Smuzhiyun * There are two separate control bits for input and output mixers as
1807*4882a593Smuzhiyun * well as headphone and line outs.
1808*4882a593Smuzhiyun * One to enable corresponding amplifier and other to enable its
1809*4882a593Smuzhiyun * output. As amplifier bits are related to power control, they are
1810*4882a593Smuzhiyun * being managed by DAPM while other (non power related) bits are
1811*4882a593Smuzhiyun * enabled here
1812*4882a593Smuzhiyun */
1813*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIXIN_L_CTRL,
1814*4882a593Smuzhiyun DA7213_MIXIN_MIX_EN, DA7213_MIXIN_MIX_EN);
1815*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIXIN_R_CTRL,
1816*4882a593Smuzhiyun DA7213_MIXIN_MIX_EN, DA7213_MIXIN_MIX_EN);
1817*4882a593Smuzhiyun
1818*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIXOUT_L_CTRL,
1819*4882a593Smuzhiyun DA7213_MIXOUT_MIX_EN, DA7213_MIXOUT_MIX_EN);
1820*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIXOUT_R_CTRL,
1821*4882a593Smuzhiyun DA7213_MIXOUT_MIX_EN, DA7213_MIXOUT_MIX_EN);
1822*4882a593Smuzhiyun
1823*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_HP_L_CTRL,
1824*4882a593Smuzhiyun DA7213_HP_AMP_OE, DA7213_HP_AMP_OE);
1825*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_HP_R_CTRL,
1826*4882a593Smuzhiyun DA7213_HP_AMP_OE, DA7213_HP_AMP_OE);
1827*4882a593Smuzhiyun
1828*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_LINE_CTRL,
1829*4882a593Smuzhiyun DA7213_LINE_AMP_OE, DA7213_LINE_AMP_OE);
1830*4882a593Smuzhiyun
1831*4882a593Smuzhiyun /* Handle DT/Platform data */
1832*4882a593Smuzhiyun da7213->pdata = dev_get_platdata(component->dev);
1833*4882a593Smuzhiyun if (!da7213->pdata)
1834*4882a593Smuzhiyun da7213->pdata = da7213_fw_to_pdata(component);
1835*4882a593Smuzhiyun
1836*4882a593Smuzhiyun /* Set platform data values */
1837*4882a593Smuzhiyun if (da7213->pdata) {
1838*4882a593Smuzhiyun struct da7213_platform_data *pdata = da7213->pdata;
1839*4882a593Smuzhiyun u8 micbias_lvl = 0, dmic_cfg = 0;
1840*4882a593Smuzhiyun
1841*4882a593Smuzhiyun /* Set Mic Bias voltages */
1842*4882a593Smuzhiyun switch (pdata->micbias1_lvl) {
1843*4882a593Smuzhiyun case DA7213_MICBIAS_1_6V:
1844*4882a593Smuzhiyun case DA7213_MICBIAS_2_2V:
1845*4882a593Smuzhiyun case DA7213_MICBIAS_2_5V:
1846*4882a593Smuzhiyun case DA7213_MICBIAS_3_0V:
1847*4882a593Smuzhiyun micbias_lvl |= (pdata->micbias1_lvl <<
1848*4882a593Smuzhiyun DA7213_MICBIAS1_LEVEL_SHIFT);
1849*4882a593Smuzhiyun break;
1850*4882a593Smuzhiyun }
1851*4882a593Smuzhiyun switch (pdata->micbias2_lvl) {
1852*4882a593Smuzhiyun case DA7213_MICBIAS_1_6V:
1853*4882a593Smuzhiyun case DA7213_MICBIAS_2_2V:
1854*4882a593Smuzhiyun case DA7213_MICBIAS_2_5V:
1855*4882a593Smuzhiyun case DA7213_MICBIAS_3_0V:
1856*4882a593Smuzhiyun micbias_lvl |= (pdata->micbias2_lvl <<
1857*4882a593Smuzhiyun DA7213_MICBIAS2_LEVEL_SHIFT);
1858*4882a593Smuzhiyun break;
1859*4882a593Smuzhiyun }
1860*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MICBIAS_CTRL,
1861*4882a593Smuzhiyun DA7213_MICBIAS1_LEVEL_MASK |
1862*4882a593Smuzhiyun DA7213_MICBIAS2_LEVEL_MASK, micbias_lvl);
1863*4882a593Smuzhiyun
1864*4882a593Smuzhiyun /* Set DMIC configuration */
1865*4882a593Smuzhiyun switch (pdata->dmic_data_sel) {
1866*4882a593Smuzhiyun case DA7213_DMIC_DATA_LFALL_RRISE:
1867*4882a593Smuzhiyun case DA7213_DMIC_DATA_LRISE_RFALL:
1868*4882a593Smuzhiyun dmic_cfg |= (pdata->dmic_data_sel <<
1869*4882a593Smuzhiyun DA7213_DMIC_DATA_SEL_SHIFT);
1870*4882a593Smuzhiyun break;
1871*4882a593Smuzhiyun }
1872*4882a593Smuzhiyun switch (pdata->dmic_samplephase) {
1873*4882a593Smuzhiyun case DA7213_DMIC_SAMPLE_ON_CLKEDGE:
1874*4882a593Smuzhiyun case DA7213_DMIC_SAMPLE_BETWEEN_CLKEDGE:
1875*4882a593Smuzhiyun dmic_cfg |= (pdata->dmic_samplephase <<
1876*4882a593Smuzhiyun DA7213_DMIC_SAMPLEPHASE_SHIFT);
1877*4882a593Smuzhiyun break;
1878*4882a593Smuzhiyun }
1879*4882a593Smuzhiyun switch (pdata->dmic_clk_rate) {
1880*4882a593Smuzhiyun case DA7213_DMIC_CLK_3_0MHZ:
1881*4882a593Smuzhiyun case DA7213_DMIC_CLK_1_5MHZ:
1882*4882a593Smuzhiyun dmic_cfg |= (pdata->dmic_clk_rate <<
1883*4882a593Smuzhiyun DA7213_DMIC_CLK_RATE_SHIFT);
1884*4882a593Smuzhiyun break;
1885*4882a593Smuzhiyun }
1886*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7213_MIC_CONFIG,
1887*4882a593Smuzhiyun DA7213_DMIC_DATA_SEL_MASK |
1888*4882a593Smuzhiyun DA7213_DMIC_SAMPLEPHASE_MASK |
1889*4882a593Smuzhiyun DA7213_DMIC_CLK_RATE_MASK, dmic_cfg);
1890*4882a593Smuzhiyun }
1891*4882a593Smuzhiyun
1892*4882a593Smuzhiyun pm_runtime_put_sync(component->dev);
1893*4882a593Smuzhiyun
1894*4882a593Smuzhiyun /* Check if MCLK provided */
1895*4882a593Smuzhiyun da7213->mclk = devm_clk_get(component->dev, "mclk");
1896*4882a593Smuzhiyun if (IS_ERR(da7213->mclk)) {
1897*4882a593Smuzhiyun if (PTR_ERR(da7213->mclk) != -ENOENT)
1898*4882a593Smuzhiyun return PTR_ERR(da7213->mclk);
1899*4882a593Smuzhiyun else
1900*4882a593Smuzhiyun da7213->mclk = NULL;
1901*4882a593Smuzhiyun } else {
1902*4882a593Smuzhiyun /* Do automatic PLL handling assuming fixed clock until
1903*4882a593Smuzhiyun * set_pll() has been called. This makes the codec usable
1904*4882a593Smuzhiyun * with the simple-audio-card driver. */
1905*4882a593Smuzhiyun da7213->fixed_clk_auto_pll = true;
1906*4882a593Smuzhiyun }
1907*4882a593Smuzhiyun
1908*4882a593Smuzhiyun return 0;
1909*4882a593Smuzhiyun }
1910*4882a593Smuzhiyun
1911*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_da7213 = {
1912*4882a593Smuzhiyun .probe = da7213_probe,
1913*4882a593Smuzhiyun .set_bias_level = da7213_set_bias_level,
1914*4882a593Smuzhiyun .controls = da7213_snd_controls,
1915*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(da7213_snd_controls),
1916*4882a593Smuzhiyun .dapm_widgets = da7213_dapm_widgets,
1917*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(da7213_dapm_widgets),
1918*4882a593Smuzhiyun .dapm_routes = da7213_audio_map,
1919*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(da7213_audio_map),
1920*4882a593Smuzhiyun .set_sysclk = da7213_set_component_sysclk,
1921*4882a593Smuzhiyun .set_pll = da7213_set_component_pll,
1922*4882a593Smuzhiyun .idle_bias_on = 1,
1923*4882a593Smuzhiyun .use_pmdown_time = 1,
1924*4882a593Smuzhiyun .endianness = 1,
1925*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
1926*4882a593Smuzhiyun };
1927*4882a593Smuzhiyun
1928*4882a593Smuzhiyun static const struct regmap_config da7213_regmap_config = {
1929*4882a593Smuzhiyun .reg_bits = 8,
1930*4882a593Smuzhiyun .val_bits = 8,
1931*4882a593Smuzhiyun
1932*4882a593Smuzhiyun .reg_defaults = da7213_reg_defaults,
1933*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(da7213_reg_defaults),
1934*4882a593Smuzhiyun .volatile_reg = da7213_volatile_register,
1935*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
1936*4882a593Smuzhiyun };
1937*4882a593Smuzhiyun
da7213_power_off(void * data)1938*4882a593Smuzhiyun static void da7213_power_off(void *data)
1939*4882a593Smuzhiyun {
1940*4882a593Smuzhiyun struct da7213_priv *da7213 = data;
1941*4882a593Smuzhiyun regulator_bulk_disable(DA7213_NUM_SUPPLIES, da7213->supplies);
1942*4882a593Smuzhiyun }
1943*4882a593Smuzhiyun
1944*4882a593Smuzhiyun static const char *da7213_supply_names[DA7213_NUM_SUPPLIES] = {
1945*4882a593Smuzhiyun [DA7213_SUPPLY_VDDA] = "VDDA",
1946*4882a593Smuzhiyun [DA7213_SUPPLY_VDDIO] = "VDDIO",
1947*4882a593Smuzhiyun };
1948*4882a593Smuzhiyun
da7213_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1949*4882a593Smuzhiyun static int da7213_i2c_probe(struct i2c_client *i2c,
1950*4882a593Smuzhiyun const struct i2c_device_id *id)
1951*4882a593Smuzhiyun {
1952*4882a593Smuzhiyun struct da7213_priv *da7213;
1953*4882a593Smuzhiyun int i, ret;
1954*4882a593Smuzhiyun
1955*4882a593Smuzhiyun da7213 = devm_kzalloc(&i2c->dev, sizeof(*da7213), GFP_KERNEL);
1956*4882a593Smuzhiyun if (!da7213)
1957*4882a593Smuzhiyun return -ENOMEM;
1958*4882a593Smuzhiyun
1959*4882a593Smuzhiyun i2c_set_clientdata(i2c, da7213);
1960*4882a593Smuzhiyun
1961*4882a593Smuzhiyun /* Get required supplies */
1962*4882a593Smuzhiyun for (i = 0; i < DA7213_NUM_SUPPLIES; ++i)
1963*4882a593Smuzhiyun da7213->supplies[i].supply = da7213_supply_names[i];
1964*4882a593Smuzhiyun
1965*4882a593Smuzhiyun ret = devm_regulator_bulk_get(&i2c->dev, DA7213_NUM_SUPPLIES,
1966*4882a593Smuzhiyun da7213->supplies);
1967*4882a593Smuzhiyun if (ret) {
1968*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to get supplies: %d\n", ret);
1969*4882a593Smuzhiyun return ret;
1970*4882a593Smuzhiyun }
1971*4882a593Smuzhiyun
1972*4882a593Smuzhiyun ret = regulator_bulk_enable(DA7213_NUM_SUPPLIES, da7213->supplies);
1973*4882a593Smuzhiyun if (ret < 0)
1974*4882a593Smuzhiyun return ret;
1975*4882a593Smuzhiyun
1976*4882a593Smuzhiyun ret = devm_add_action_or_reset(&i2c->dev, da7213_power_off, da7213);
1977*4882a593Smuzhiyun if (ret < 0)
1978*4882a593Smuzhiyun return ret;
1979*4882a593Smuzhiyun
1980*4882a593Smuzhiyun da7213->regmap = devm_regmap_init_i2c(i2c, &da7213_regmap_config);
1981*4882a593Smuzhiyun if (IS_ERR(da7213->regmap)) {
1982*4882a593Smuzhiyun ret = PTR_ERR(da7213->regmap);
1983*4882a593Smuzhiyun dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1984*4882a593Smuzhiyun return ret;
1985*4882a593Smuzhiyun }
1986*4882a593Smuzhiyun
1987*4882a593Smuzhiyun pm_runtime_set_autosuspend_delay(&i2c->dev, 100);
1988*4882a593Smuzhiyun pm_runtime_use_autosuspend(&i2c->dev);
1989*4882a593Smuzhiyun pm_runtime_set_active(&i2c->dev);
1990*4882a593Smuzhiyun pm_runtime_enable(&i2c->dev);
1991*4882a593Smuzhiyun
1992*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev,
1993*4882a593Smuzhiyun &soc_component_dev_da7213, &da7213_dai, 1);
1994*4882a593Smuzhiyun if (ret < 0) {
1995*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to register da7213 component: %d\n",
1996*4882a593Smuzhiyun ret);
1997*4882a593Smuzhiyun }
1998*4882a593Smuzhiyun return ret;
1999*4882a593Smuzhiyun }
2000*4882a593Smuzhiyun
da7213_runtime_suspend(struct device * dev)2001*4882a593Smuzhiyun static int __maybe_unused da7213_runtime_suspend(struct device *dev)
2002*4882a593Smuzhiyun {
2003*4882a593Smuzhiyun struct da7213_priv *da7213 = dev_get_drvdata(dev);
2004*4882a593Smuzhiyun
2005*4882a593Smuzhiyun regcache_cache_only(da7213->regmap, true);
2006*4882a593Smuzhiyun regcache_mark_dirty(da7213->regmap);
2007*4882a593Smuzhiyun regulator_bulk_disable(DA7213_NUM_SUPPLIES, da7213->supplies);
2008*4882a593Smuzhiyun
2009*4882a593Smuzhiyun return 0;
2010*4882a593Smuzhiyun }
2011*4882a593Smuzhiyun
da7213_runtime_resume(struct device * dev)2012*4882a593Smuzhiyun static int __maybe_unused da7213_runtime_resume(struct device *dev)
2013*4882a593Smuzhiyun {
2014*4882a593Smuzhiyun struct da7213_priv *da7213 = dev_get_drvdata(dev);
2015*4882a593Smuzhiyun int ret;
2016*4882a593Smuzhiyun
2017*4882a593Smuzhiyun ret = regulator_bulk_enable(DA7213_NUM_SUPPLIES, da7213->supplies);
2018*4882a593Smuzhiyun if (ret < 0)
2019*4882a593Smuzhiyun return ret;
2020*4882a593Smuzhiyun regcache_cache_only(da7213->regmap, false);
2021*4882a593Smuzhiyun regcache_sync(da7213->regmap);
2022*4882a593Smuzhiyun return 0;
2023*4882a593Smuzhiyun }
2024*4882a593Smuzhiyun
2025*4882a593Smuzhiyun static const struct dev_pm_ops da7213_pm = {
2026*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(da7213_runtime_suspend, da7213_runtime_resume, NULL)
2027*4882a593Smuzhiyun };
2028*4882a593Smuzhiyun
2029*4882a593Smuzhiyun static const struct i2c_device_id da7213_i2c_id[] = {
2030*4882a593Smuzhiyun { "da7213", 0 },
2031*4882a593Smuzhiyun { }
2032*4882a593Smuzhiyun };
2033*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, da7213_i2c_id);
2034*4882a593Smuzhiyun
2035*4882a593Smuzhiyun /* I2C codec control layer */
2036*4882a593Smuzhiyun static struct i2c_driver da7213_i2c_driver = {
2037*4882a593Smuzhiyun .driver = {
2038*4882a593Smuzhiyun .name = "da7213",
2039*4882a593Smuzhiyun .of_match_table = of_match_ptr(da7213_of_match),
2040*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(da7213_acpi_match),
2041*4882a593Smuzhiyun .pm = &da7213_pm,
2042*4882a593Smuzhiyun },
2043*4882a593Smuzhiyun .probe = da7213_i2c_probe,
2044*4882a593Smuzhiyun .id_table = da7213_i2c_id,
2045*4882a593Smuzhiyun };
2046*4882a593Smuzhiyun
2047*4882a593Smuzhiyun module_i2c_driver(da7213_i2c_driver);
2048*4882a593Smuzhiyun
2049*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC DA7213 Codec driver");
2050*4882a593Smuzhiyun MODULE_AUTHOR("Adam Thomson <Adam.Thomson.Opensource@diasemi.com>");
2051*4882a593Smuzhiyun MODULE_LICENSE("GPL");
2052