xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/da7210.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // DA7210 ALSA Soc codec driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2009 Dialog Semiconductor
6*4882a593Smuzhiyun // Written by David Chen <Dajun.chen@diasemi.com>
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun // Copyright (C) 2009 Renesas Solutions Corp.
9*4882a593Smuzhiyun // Cleanups by Kuninori Morimoto <morimoto.kuninori@renesas.com>
10*4882a593Smuzhiyun //
11*4882a593Smuzhiyun // Tested on SuperH Ecovec24 board with S16/S24 LE in 48KHz using I2S
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/spi/spi.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <sound/pcm.h>
20*4882a593Smuzhiyun #include <sound/pcm_params.h>
21*4882a593Smuzhiyun #include <sound/soc.h>
22*4882a593Smuzhiyun #include <sound/initval.h>
23*4882a593Smuzhiyun #include <sound/tlv.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /* DA7210 register space */
26*4882a593Smuzhiyun #define DA7210_PAGE_CONTROL		0x00
27*4882a593Smuzhiyun #define DA7210_CONTROL			0x01
28*4882a593Smuzhiyun #define DA7210_STATUS			0x02
29*4882a593Smuzhiyun #define DA7210_STARTUP1			0x03
30*4882a593Smuzhiyun #define DA7210_STARTUP2			0x04
31*4882a593Smuzhiyun #define DA7210_STARTUP3			0x05
32*4882a593Smuzhiyun #define DA7210_MIC_L			0x07
33*4882a593Smuzhiyun #define DA7210_MIC_R			0x08
34*4882a593Smuzhiyun #define DA7210_AUX1_L			0x09
35*4882a593Smuzhiyun #define DA7210_AUX1_R			0x0A
36*4882a593Smuzhiyun #define DA7210_AUX2			0x0B
37*4882a593Smuzhiyun #define DA7210_IN_GAIN			0x0C
38*4882a593Smuzhiyun #define DA7210_INMIX_L			0x0D
39*4882a593Smuzhiyun #define DA7210_INMIX_R			0x0E
40*4882a593Smuzhiyun #define DA7210_ADC_HPF			0x0F
41*4882a593Smuzhiyun #define DA7210_ADC			0x10
42*4882a593Smuzhiyun #define DA7210_ADC_EQ1_2		0X11
43*4882a593Smuzhiyun #define DA7210_ADC_EQ3_4		0x12
44*4882a593Smuzhiyun #define DA7210_ADC_EQ5			0x13
45*4882a593Smuzhiyun #define DA7210_DAC_HPF			0x14
46*4882a593Smuzhiyun #define DA7210_DAC_L			0x15
47*4882a593Smuzhiyun #define DA7210_DAC_R			0x16
48*4882a593Smuzhiyun #define DA7210_DAC_SEL			0x17
49*4882a593Smuzhiyun #define DA7210_SOFTMUTE			0x18
50*4882a593Smuzhiyun #define DA7210_DAC_EQ1_2		0x19
51*4882a593Smuzhiyun #define DA7210_DAC_EQ3_4		0x1A
52*4882a593Smuzhiyun #define DA7210_DAC_EQ5			0x1B
53*4882a593Smuzhiyun #define DA7210_OUTMIX_L			0x1C
54*4882a593Smuzhiyun #define DA7210_OUTMIX_R			0x1D
55*4882a593Smuzhiyun #define DA7210_OUT1_L			0x1E
56*4882a593Smuzhiyun #define DA7210_OUT1_R			0x1F
57*4882a593Smuzhiyun #define DA7210_OUT2			0x20
58*4882a593Smuzhiyun #define DA7210_HP_L_VOL			0x21
59*4882a593Smuzhiyun #define DA7210_HP_R_VOL			0x22
60*4882a593Smuzhiyun #define DA7210_HP_CFG			0x23
61*4882a593Smuzhiyun #define DA7210_ZERO_CROSS		0x24
62*4882a593Smuzhiyun #define DA7210_DAI_SRC_SEL		0x25
63*4882a593Smuzhiyun #define DA7210_DAI_CFG1			0x26
64*4882a593Smuzhiyun #define DA7210_DAI_CFG3			0x28
65*4882a593Smuzhiyun #define DA7210_PLL_DIV1			0x29
66*4882a593Smuzhiyun #define DA7210_PLL_DIV2			0x2A
67*4882a593Smuzhiyun #define DA7210_PLL_DIV3			0x2B
68*4882a593Smuzhiyun #define DA7210_PLL			0x2C
69*4882a593Smuzhiyun #define DA7210_ALC_MAX			0x83
70*4882a593Smuzhiyun #define DA7210_ALC_MIN			0x84
71*4882a593Smuzhiyun #define DA7210_ALC_NOIS			0x85
72*4882a593Smuzhiyun #define DA7210_ALC_ATT			0x86
73*4882a593Smuzhiyun #define DA7210_ALC_REL			0x87
74*4882a593Smuzhiyun #define DA7210_ALC_DEL			0x88
75*4882a593Smuzhiyun #define DA7210_A_HID_UNLOCK		0x8A
76*4882a593Smuzhiyun #define DA7210_A_TEST_UNLOCK		0x8B
77*4882a593Smuzhiyun #define DA7210_A_PLL1			0x90
78*4882a593Smuzhiyun #define DA7210_A_CP_MODE		0xA7
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* STARTUP1 bit fields */
81*4882a593Smuzhiyun #define DA7210_SC_MST_EN		(1 << 0)
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /* MIC_L bit fields */
84*4882a593Smuzhiyun #define DA7210_MICBIAS_EN		(1 << 6)
85*4882a593Smuzhiyun #define DA7210_MIC_L_EN			(1 << 7)
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /* MIC_R bit fields */
88*4882a593Smuzhiyun #define DA7210_MIC_R_EN			(1 << 7)
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /* INMIX_L bit fields */
91*4882a593Smuzhiyun #define DA7210_IN_L_EN			(1 << 7)
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun /* INMIX_R bit fields */
94*4882a593Smuzhiyun #define DA7210_IN_R_EN			(1 << 7)
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /* ADC bit fields */
97*4882a593Smuzhiyun #define DA7210_ADC_ALC_EN		(1 << 0)
98*4882a593Smuzhiyun #define DA7210_ADC_L_EN			(1 << 3)
99*4882a593Smuzhiyun #define DA7210_ADC_R_EN			(1 << 7)
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* DAC/ADC HPF fields */
102*4882a593Smuzhiyun #define DA7210_VOICE_F0_MASK		(0x7 << 4)
103*4882a593Smuzhiyun #define DA7210_VOICE_F0_25		(1 << 4)
104*4882a593Smuzhiyun #define DA7210_VOICE_EN			(1 << 7)
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /* DAC_SEL bit fields */
107*4882a593Smuzhiyun #define DA7210_DAC_L_SRC_DAI_L		(4 << 0)
108*4882a593Smuzhiyun #define DA7210_DAC_L_EN			(1 << 3)
109*4882a593Smuzhiyun #define DA7210_DAC_R_SRC_DAI_R		(5 << 4)
110*4882a593Smuzhiyun #define DA7210_DAC_R_EN			(1 << 7)
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /* OUTMIX_L bit fields */
113*4882a593Smuzhiyun #define DA7210_OUT_L_EN			(1 << 7)
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /* OUTMIX_R bit fields */
116*4882a593Smuzhiyun #define DA7210_OUT_R_EN			(1 << 7)
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun /* HP_CFG bit fields */
119*4882a593Smuzhiyun #define DA7210_HP_2CAP_MODE		(1 << 1)
120*4882a593Smuzhiyun #define DA7210_HP_SENSE_EN		(1 << 2)
121*4882a593Smuzhiyun #define DA7210_HP_L_EN			(1 << 3)
122*4882a593Smuzhiyun #define DA7210_HP_MODE			(1 << 6)
123*4882a593Smuzhiyun #define DA7210_HP_R_EN			(1 << 7)
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun /* DAI_SRC_SEL bit fields */
126*4882a593Smuzhiyun #define DA7210_DAI_OUT_L_SRC		(6 << 0)
127*4882a593Smuzhiyun #define DA7210_DAI_OUT_R_SRC		(7 << 4)
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /* DAI_CFG1 bit fields */
130*4882a593Smuzhiyun #define DA7210_DAI_WORD_S16_LE		(0 << 0)
131*4882a593Smuzhiyun #define DA7210_DAI_WORD_S20_3LE		(1 << 0)
132*4882a593Smuzhiyun #define DA7210_DAI_WORD_S24_LE		(2 << 0)
133*4882a593Smuzhiyun #define DA7210_DAI_WORD_S32_LE		(3 << 0)
134*4882a593Smuzhiyun #define DA7210_DAI_FLEN_64BIT		(1 << 2)
135*4882a593Smuzhiyun #define DA7210_DAI_MODE_SLAVE		(0 << 7)
136*4882a593Smuzhiyun #define DA7210_DAI_MODE_MASTER		(1 << 7)
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun /* DAI_CFG3 bit fields */
139*4882a593Smuzhiyun #define DA7210_DAI_FORMAT_I2SMODE	(0 << 0)
140*4882a593Smuzhiyun #define DA7210_DAI_FORMAT_LEFT_J	(1 << 0)
141*4882a593Smuzhiyun #define DA7210_DAI_FORMAT_RIGHT_J	(2 << 0)
142*4882a593Smuzhiyun #define DA7210_DAI_OE			(1 << 3)
143*4882a593Smuzhiyun #define DA7210_DAI_EN			(1 << 7)
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /*PLL_DIV3 bit fields */
146*4882a593Smuzhiyun #define DA7210_PLL_DIV_L_MASK		(0xF << 0)
147*4882a593Smuzhiyun #define DA7210_MCLK_RANGE_10_20_MHZ	(1 << 4)
148*4882a593Smuzhiyun #define DA7210_PLL_BYP			(1 << 6)
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun /* PLL bit fields */
151*4882a593Smuzhiyun #define DA7210_PLL_FS_MASK		(0xF << 0)
152*4882a593Smuzhiyun #define DA7210_PLL_FS_8000		(0x1 << 0)
153*4882a593Smuzhiyun #define DA7210_PLL_FS_11025		(0x2 << 0)
154*4882a593Smuzhiyun #define DA7210_PLL_FS_12000		(0x3 << 0)
155*4882a593Smuzhiyun #define DA7210_PLL_FS_16000		(0x5 << 0)
156*4882a593Smuzhiyun #define DA7210_PLL_FS_22050		(0x6 << 0)
157*4882a593Smuzhiyun #define DA7210_PLL_FS_24000		(0x7 << 0)
158*4882a593Smuzhiyun #define DA7210_PLL_FS_32000		(0x9 << 0)
159*4882a593Smuzhiyun #define DA7210_PLL_FS_44100		(0xA << 0)
160*4882a593Smuzhiyun #define DA7210_PLL_FS_48000		(0xB << 0)
161*4882a593Smuzhiyun #define DA7210_PLL_FS_88200		(0xE << 0)
162*4882a593Smuzhiyun #define DA7210_PLL_FS_96000		(0xF << 0)
163*4882a593Smuzhiyun #define DA7210_MCLK_DET_EN		(0x1 << 5)
164*4882a593Smuzhiyun #define DA7210_MCLK_SRM_EN		(0x1 << 6)
165*4882a593Smuzhiyun #define DA7210_PLL_EN			(0x1 << 7)
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun /* SOFTMUTE bit fields */
168*4882a593Smuzhiyun #define DA7210_RAMP_EN			(1 << 6)
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /* CONTROL bit fields */
171*4882a593Smuzhiyun #define DA7210_REG_EN			(1 << 0)
172*4882a593Smuzhiyun #define DA7210_BIAS_EN			(1 << 2)
173*4882a593Smuzhiyun #define DA7210_NOISE_SUP_EN		(1 << 3)
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun /* IN_GAIN bit fields */
176*4882a593Smuzhiyun #define DA7210_INPGA_L_VOL		(0x0F << 0)
177*4882a593Smuzhiyun #define DA7210_INPGA_R_VOL		(0xF0 << 0)
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun /* ZERO_CROSS bit fields */
180*4882a593Smuzhiyun #define DA7210_AUX1_L_ZC		(1 << 0)
181*4882a593Smuzhiyun #define DA7210_AUX1_R_ZC		(1 << 1)
182*4882a593Smuzhiyun #define DA7210_HP_L_ZC			(1 << 6)
183*4882a593Smuzhiyun #define DA7210_HP_R_ZC			(1 << 7)
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun /* AUX1_L bit fields */
186*4882a593Smuzhiyun #define DA7210_AUX1_L_VOL		(0x3F << 0)
187*4882a593Smuzhiyun #define DA7210_AUX1_L_EN		(1 << 7)
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /* AUX1_R bit fields */
190*4882a593Smuzhiyun #define DA7210_AUX1_R_VOL		(0x3F << 0)
191*4882a593Smuzhiyun #define DA7210_AUX1_R_EN		(1 << 7)
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun /* AUX2 bit fields */
194*4882a593Smuzhiyun #define DA7210_AUX2_EN			(1 << 3)
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun /* Minimum INPGA and AUX1 volume to enable noise suppression */
197*4882a593Smuzhiyun #define DA7210_INPGA_MIN_VOL_NS		0x0A  /* 10.5dB */
198*4882a593Smuzhiyun #define DA7210_AUX1_MIN_VOL_NS		0x35  /* 6dB */
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun /* OUT1_L bit fields */
201*4882a593Smuzhiyun #define DA7210_OUT1_L_EN		(1 << 7)
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun /* OUT1_R bit fields */
204*4882a593Smuzhiyun #define DA7210_OUT1_R_EN		(1 << 7)
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun /* OUT2 bit fields */
207*4882a593Smuzhiyun #define DA7210_OUT2_OUTMIX_R		(1 << 5)
208*4882a593Smuzhiyun #define DA7210_OUT2_OUTMIX_L		(1 << 6)
209*4882a593Smuzhiyun #define DA7210_OUT2_EN			(1 << 7)
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun struct pll_div {
212*4882a593Smuzhiyun 	int fref;
213*4882a593Smuzhiyun 	int fout;
214*4882a593Smuzhiyun 	u8 div1;
215*4882a593Smuzhiyun 	u8 div2;
216*4882a593Smuzhiyun 	u8 div3;
217*4882a593Smuzhiyun 	u8 mode;	/* 0 = slave, 1 = master */
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun /* PLL dividers table */
221*4882a593Smuzhiyun static const struct pll_div da7210_pll_div[] = {
222*4882a593Smuzhiyun 	/* for MASTER mode, fs = 44.1Khz */
223*4882a593Smuzhiyun 	{ 12000000, 2822400, 0xE8, 0x6C, 0x2, 1},	/* MCLK=12Mhz */
224*4882a593Smuzhiyun 	{ 13000000, 2822400, 0xDF, 0x28, 0xC, 1},	/* MCLK=13Mhz */
225*4882a593Smuzhiyun 	{ 13500000, 2822400, 0xDB, 0x0A, 0xD, 1},	/* MCLK=13.5Mhz */
226*4882a593Smuzhiyun 	{ 14400000, 2822400, 0xD4, 0x5A, 0x2, 1},	/* MCLK=14.4Mhz */
227*4882a593Smuzhiyun 	{ 19200000, 2822400, 0xBB, 0x43, 0x9, 1},	/* MCLK=19.2Mhz */
228*4882a593Smuzhiyun 	{ 19680000, 2822400, 0xB9, 0x6D, 0xA, 1},	/* MCLK=19.68Mhz */
229*4882a593Smuzhiyun 	{ 19800000, 2822400, 0xB8, 0xFB, 0xB, 1},	/* MCLK=19.8Mhz */
230*4882a593Smuzhiyun 	/* for MASTER mode, fs = 48Khz */
231*4882a593Smuzhiyun 	{ 12000000, 3072000, 0xF3, 0x12, 0x7, 1},	/* MCLK=12Mhz */
232*4882a593Smuzhiyun 	{ 13000000, 3072000, 0xE8, 0xFD, 0x5, 1},	/* MCLK=13Mhz */
233*4882a593Smuzhiyun 	{ 13500000, 3072000, 0xE4, 0x82, 0x3, 1},	/* MCLK=13.5Mhz */
234*4882a593Smuzhiyun 	{ 14400000, 3072000, 0xDD, 0x3A, 0x0, 1},	/* MCLK=14.4Mhz */
235*4882a593Smuzhiyun 	{ 19200000, 3072000, 0xC1, 0xEB, 0x8, 1},	/* MCLK=19.2Mhz */
236*4882a593Smuzhiyun 	{ 19680000, 3072000, 0xBF, 0xEC, 0x0, 1},	/* MCLK=19.68Mhz */
237*4882a593Smuzhiyun 	{ 19800000, 3072000, 0xBF, 0x70, 0x0, 1},	/* MCLK=19.8Mhz */
238*4882a593Smuzhiyun 	/* for SLAVE mode with SRM */
239*4882a593Smuzhiyun 	{ 12000000, 2822400, 0xED, 0xBF, 0x5, 0},	/* MCLK=12Mhz */
240*4882a593Smuzhiyun 	{ 13000000, 2822400, 0xE4, 0x13, 0x0, 0},	/* MCLK=13Mhz */
241*4882a593Smuzhiyun 	{ 13500000, 2822400, 0xDF, 0xC6, 0x8, 0},	/* MCLK=13.5Mhz */
242*4882a593Smuzhiyun 	{ 14400000, 2822400, 0xD8, 0xCA, 0x1, 0},	/* MCLK=14.4Mhz */
243*4882a593Smuzhiyun 	{ 19200000, 2822400, 0xBE, 0x97, 0x9, 0},	/* MCLK=19.2Mhz */
244*4882a593Smuzhiyun 	{ 19680000, 2822400, 0xBC, 0xAC, 0xD, 0},	/* MCLK=19.68Mhz */
245*4882a593Smuzhiyun 	{ 19800000, 2822400, 0xBC, 0x35, 0xE, 0},	/* MCLK=19.8Mhz  */
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun enum clk_src {
249*4882a593Smuzhiyun 	DA7210_CLKSRC_MCLK
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun #define DA7210_VERSION "0.0.1"
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun /*
255*4882a593Smuzhiyun  * Playback Volume
256*4882a593Smuzhiyun  *
257*4882a593Smuzhiyun  * max		: 0x3F (+15.0 dB)
258*4882a593Smuzhiyun  *		   (1.5 dB step)
259*4882a593Smuzhiyun  * min		: 0x11 (-54.0 dB)
260*4882a593Smuzhiyun  * mute		: 0x10
261*4882a593Smuzhiyun  * reserved	: 0x00 - 0x0F
262*4882a593Smuzhiyun  *
263*4882a593Smuzhiyun  * Reserved area are considered as "mute".
264*4882a593Smuzhiyun  */
265*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(hp_out_tlv,
266*4882a593Smuzhiyun 	0x0, 0x10, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
267*4882a593Smuzhiyun 	/* -54 dB to +15 dB */
268*4882a593Smuzhiyun 	0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
269*4882a593Smuzhiyun );
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(lineout_vol_tlv,
272*4882a593Smuzhiyun 	0x0, 0x10, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
273*4882a593Smuzhiyun 	/* -54dB to 15dB */
274*4882a593Smuzhiyun 	0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
275*4882a593Smuzhiyun );
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(mono_vol_tlv,
278*4882a593Smuzhiyun 	0x0, 0x2, TLV_DB_SCALE_ITEM(-1800, 0, 1),
279*4882a593Smuzhiyun 	/* -18dB to 6dB */
280*4882a593Smuzhiyun 	0x3, 0x7, TLV_DB_SCALE_ITEM(-1800, 600, 0)
281*4882a593Smuzhiyun );
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(aux1_vol_tlv,
284*4882a593Smuzhiyun 	0x0, 0x10, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
285*4882a593Smuzhiyun 	/* -48dB to 21dB */
286*4882a593Smuzhiyun 	0x11, 0x3f, TLV_DB_SCALE_ITEM(-4800, 150, 0)
287*4882a593Smuzhiyun );
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
290*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(adc_eq_master_gain_tlv, -1800, 600, 1);
291*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(dac_gain_tlv, -7725, 75, 0);
292*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
293*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(aux2_vol_tlv, -600, 600, 0);
294*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(inpga_gain_tlv, -450, 150, 0);
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun /* ADC and DAC high pass filter f0 value */
297*4882a593Smuzhiyun static const char * const da7210_hpf_cutoff_txt[] = {
298*4882a593Smuzhiyun 	"Fs/8192*pi", "Fs/4096*pi", "Fs/2048*pi", "Fs/1024*pi"
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7210_dac_hpf_cutoff,
302*4882a593Smuzhiyun 			    DA7210_DAC_HPF, 0, da7210_hpf_cutoff_txt);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7210_adc_hpf_cutoff,
305*4882a593Smuzhiyun 			    DA7210_ADC_HPF, 0, da7210_hpf_cutoff_txt);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun /* ADC and DAC voice (8kHz) high pass cutoff value */
308*4882a593Smuzhiyun static const char * const da7210_vf_cutoff_txt[] = {
309*4882a593Smuzhiyun 	"2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7210_dac_vf_cutoff,
313*4882a593Smuzhiyun 			    DA7210_DAC_HPF, 4, da7210_vf_cutoff_txt);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7210_adc_vf_cutoff,
316*4882a593Smuzhiyun 			    DA7210_ADC_HPF, 4, da7210_vf_cutoff_txt);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun static const char *da7210_hp_mode_txt[] = {
319*4882a593Smuzhiyun 	"Class H", "Class G"
320*4882a593Smuzhiyun };
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(da7210_hp_mode_sel,
323*4882a593Smuzhiyun 			    DA7210_HP_CFG, 0, da7210_hp_mode_txt);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun /* ALC can be enabled only if noise suppression is disabled */
da7210_put_alc_sw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)326*4882a593Smuzhiyun static int da7210_put_alc_sw(struct snd_kcontrol *kcontrol,
327*4882a593Smuzhiyun 			     struct snd_ctl_elem_value *ucontrol)
328*4882a593Smuzhiyun {
329*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	if (ucontrol->value.integer.value[0]) {
332*4882a593Smuzhiyun 		/* Check if noise suppression is enabled */
333*4882a593Smuzhiyun 		if (snd_soc_component_read(component, DA7210_CONTROL) & DA7210_NOISE_SUP_EN) {
334*4882a593Smuzhiyun 			dev_dbg(component->dev,
335*4882a593Smuzhiyun 				"Disable noise suppression to enable ALC\n");
336*4882a593Smuzhiyun 			return -EINVAL;
337*4882a593Smuzhiyun 		}
338*4882a593Smuzhiyun 	}
339*4882a593Smuzhiyun 	/* If all conditions are met or we are actually disabling ALC */
340*4882a593Smuzhiyun 	return snd_soc_put_volsw(kcontrol, ucontrol);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun /* Noise suppression can be enabled only if following conditions are met
344*4882a593Smuzhiyun  *  ALC disabled
345*4882a593Smuzhiyun  *  ZC enabled for HP and AUX1 PGA
346*4882a593Smuzhiyun  *  INPGA_L_VOL and INPGA_R_VOL >= 10.5 dB
347*4882a593Smuzhiyun  *  AUX1_L_VOL and AUX1_R_VOL >= 6 dB
348*4882a593Smuzhiyun  */
da7210_put_noise_sup_sw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)349*4882a593Smuzhiyun static int da7210_put_noise_sup_sw(struct snd_kcontrol *kcontrol,
350*4882a593Smuzhiyun 				   struct snd_ctl_elem_value *ucontrol)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
353*4882a593Smuzhiyun 	u8 val;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	if (ucontrol->value.integer.value[0]) {
356*4882a593Smuzhiyun 		/* Check if ALC is enabled */
357*4882a593Smuzhiyun 		if (snd_soc_component_read(component, DA7210_ADC) & DA7210_ADC_ALC_EN)
358*4882a593Smuzhiyun 			goto err;
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 		/* Check ZC for HP and AUX1 PGA */
361*4882a593Smuzhiyun 		if ((snd_soc_component_read(component, DA7210_ZERO_CROSS) &
362*4882a593Smuzhiyun 			(DA7210_AUX1_L_ZC | DA7210_AUX1_R_ZC | DA7210_HP_L_ZC |
363*4882a593Smuzhiyun 			DA7210_HP_R_ZC)) != (DA7210_AUX1_L_ZC |
364*4882a593Smuzhiyun 			DA7210_AUX1_R_ZC | DA7210_HP_L_ZC | DA7210_HP_R_ZC))
365*4882a593Smuzhiyun 			goto err;
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 		/* Check INPGA_L_VOL and INPGA_R_VOL */
368*4882a593Smuzhiyun 		val = snd_soc_component_read(component, DA7210_IN_GAIN);
369*4882a593Smuzhiyun 		if (((val & DA7210_INPGA_L_VOL) < DA7210_INPGA_MIN_VOL_NS) ||
370*4882a593Smuzhiyun 			(((val & DA7210_INPGA_R_VOL) >> 4) <
371*4882a593Smuzhiyun 			DA7210_INPGA_MIN_VOL_NS))
372*4882a593Smuzhiyun 			goto err;
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 		/* Check AUX1_L_VOL and AUX1_R_VOL */
375*4882a593Smuzhiyun 		if (((snd_soc_component_read(component, DA7210_AUX1_L) & DA7210_AUX1_L_VOL) <
376*4882a593Smuzhiyun 		    DA7210_AUX1_MIN_VOL_NS) ||
377*4882a593Smuzhiyun 		    ((snd_soc_component_read(component, DA7210_AUX1_R) & DA7210_AUX1_R_VOL) <
378*4882a593Smuzhiyun 		    DA7210_AUX1_MIN_VOL_NS))
379*4882a593Smuzhiyun 			goto err;
380*4882a593Smuzhiyun 	}
381*4882a593Smuzhiyun 	/* If all conditions are met or we are actually disabling Noise sup */
382*4882a593Smuzhiyun 	return snd_soc_put_volsw(kcontrol, ucontrol);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun err:
385*4882a593Smuzhiyun 	return -EINVAL;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun static const struct snd_kcontrol_new da7210_snd_controls[] = {
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("HeadPhone Playback Volume",
391*4882a593Smuzhiyun 			 DA7210_HP_L_VOL, DA7210_HP_R_VOL,
392*4882a593Smuzhiyun 			 0, 0x3F, 0, hp_out_tlv),
393*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("Digital Playback Volume",
394*4882a593Smuzhiyun 			 DA7210_DAC_L, DA7210_DAC_R,
395*4882a593Smuzhiyun 			 0, 0x77, 1, dac_gain_tlv),
396*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("Lineout Playback Volume",
397*4882a593Smuzhiyun 			 DA7210_OUT1_L, DA7210_OUT1_R,
398*4882a593Smuzhiyun 			 0, 0x3f, 0, lineout_vol_tlv),
399*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Mono Playback Volume", DA7210_OUT2, 0, 0x7, 0,
400*4882a593Smuzhiyun 		       mono_vol_tlv),
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("Mic Capture Volume",
403*4882a593Smuzhiyun 			 DA7210_MIC_L, DA7210_MIC_R,
404*4882a593Smuzhiyun 			 0, 0x5, 0, mic_vol_tlv),
405*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("Aux1 Capture Volume",
406*4882a593Smuzhiyun 			 DA7210_AUX1_L, DA7210_AUX1_R,
407*4882a593Smuzhiyun 			 0, 0x3f, 0, aux1_vol_tlv),
408*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Aux2 Capture Volume", DA7210_AUX2, 0, 0x3, 0,
409*4882a593Smuzhiyun 		       aux2_vol_tlv),
410*4882a593Smuzhiyun 	SOC_DOUBLE_TLV("In PGA Capture Volume", DA7210_IN_GAIN, 0, 4, 0xF, 0,
411*4882a593Smuzhiyun 		       inpga_gain_tlv),
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	/* DAC Equalizer  controls */
414*4882a593Smuzhiyun 	SOC_SINGLE("DAC EQ Switch", DA7210_DAC_EQ5, 7, 1, 0),
415*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DAC EQ1 Volume", DA7210_DAC_EQ1_2, 0, 0xf, 1,
416*4882a593Smuzhiyun 		       eq_gain_tlv),
417*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DAC EQ2 Volume", DA7210_DAC_EQ1_2, 4, 0xf, 1,
418*4882a593Smuzhiyun 		       eq_gain_tlv),
419*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DAC EQ3 Volume", DA7210_DAC_EQ3_4, 0, 0xf, 1,
420*4882a593Smuzhiyun 		       eq_gain_tlv),
421*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DAC EQ4 Volume", DA7210_DAC_EQ3_4, 4, 0xf, 1,
422*4882a593Smuzhiyun 		       eq_gain_tlv),
423*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DAC EQ5 Volume", DA7210_DAC_EQ5, 0, 0xf, 1,
424*4882a593Smuzhiyun 		       eq_gain_tlv),
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	/* ADC Equalizer  controls */
427*4882a593Smuzhiyun 	SOC_SINGLE("ADC EQ Switch", DA7210_ADC_EQ5, 7, 1, 0),
428*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ADC EQ Master Volume", DA7210_ADC_EQ5, 4, 0x3,
429*4882a593Smuzhiyun 		       1, adc_eq_master_gain_tlv),
430*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ADC EQ1 Volume", DA7210_ADC_EQ1_2, 0, 0xf, 1,
431*4882a593Smuzhiyun 		       eq_gain_tlv),
432*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ADC EQ2 Volume", DA7210_ADC_EQ1_2, 4, 0xf, 1,
433*4882a593Smuzhiyun 		       eq_gain_tlv),
434*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ADC EQ3 Volume", DA7210_ADC_EQ3_4, 0, 0xf, 1,
435*4882a593Smuzhiyun 		       eq_gain_tlv),
436*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ADC EQ4 Volume", DA7210_ADC_EQ3_4, 4, 0xf, 1,
437*4882a593Smuzhiyun 		       eq_gain_tlv),
438*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ADC EQ5 Volume", DA7210_ADC_EQ5, 0, 0xf, 1,
439*4882a593Smuzhiyun 		       eq_gain_tlv),
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	SOC_SINGLE("DAC HPF Switch", DA7210_DAC_HPF, 3, 1, 0),
442*4882a593Smuzhiyun 	SOC_ENUM("DAC HPF Cutoff", da7210_dac_hpf_cutoff),
443*4882a593Smuzhiyun 	SOC_SINGLE("DAC Voice Mode Switch", DA7210_DAC_HPF, 7, 1, 0),
444*4882a593Smuzhiyun 	SOC_ENUM("DAC Voice Cutoff", da7210_dac_vf_cutoff),
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	SOC_SINGLE("ADC HPF Switch", DA7210_ADC_HPF, 3, 1, 0),
447*4882a593Smuzhiyun 	SOC_ENUM("ADC HPF Cutoff", da7210_adc_hpf_cutoff),
448*4882a593Smuzhiyun 	SOC_SINGLE("ADC Voice Mode Switch", DA7210_ADC_HPF, 7, 1, 0),
449*4882a593Smuzhiyun 	SOC_ENUM("ADC Voice Cutoff", da7210_adc_vf_cutoff),
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	/* Mute controls */
452*4882a593Smuzhiyun 	SOC_DOUBLE_R("Mic Capture Switch", DA7210_MIC_L, DA7210_MIC_R, 3, 1, 0),
453*4882a593Smuzhiyun 	SOC_SINGLE("Aux2 Capture Switch", DA7210_AUX2, 2, 1, 0),
454*4882a593Smuzhiyun 	SOC_DOUBLE("ADC Capture Switch", DA7210_ADC, 2, 6, 1, 0),
455*4882a593Smuzhiyun 	SOC_SINGLE("Digital Soft Mute Switch", DA7210_SOFTMUTE, 7, 1, 0),
456*4882a593Smuzhiyun 	SOC_SINGLE("Digital Soft Mute Rate", DA7210_SOFTMUTE, 0, 0x7, 0),
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	/* Zero cross controls */
459*4882a593Smuzhiyun 	SOC_DOUBLE("Aux1 ZC Switch", DA7210_ZERO_CROSS, 0, 1, 1, 0),
460*4882a593Smuzhiyun 	SOC_DOUBLE("In PGA ZC Switch", DA7210_ZERO_CROSS, 2, 3, 1, 0),
461*4882a593Smuzhiyun 	SOC_DOUBLE("Lineout ZC Switch", DA7210_ZERO_CROSS, 4, 5, 1, 0),
462*4882a593Smuzhiyun 	SOC_DOUBLE("Headphone ZC Switch", DA7210_ZERO_CROSS, 6, 7, 1, 0),
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	SOC_ENUM("Headphone Class", da7210_hp_mode_sel),
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	/* ALC controls */
467*4882a593Smuzhiyun 	SOC_SINGLE_EXT("ALC Enable Switch", DA7210_ADC, 0, 1, 0,
468*4882a593Smuzhiyun 		       snd_soc_get_volsw, da7210_put_alc_sw),
469*4882a593Smuzhiyun 	SOC_SINGLE("ALC Capture Max Volume", DA7210_ALC_MAX, 0, 0x3F, 0),
470*4882a593Smuzhiyun 	SOC_SINGLE("ALC Capture Min Volume", DA7210_ALC_MIN, 0, 0x3F, 0),
471*4882a593Smuzhiyun 	SOC_SINGLE("ALC Capture Noise Volume", DA7210_ALC_NOIS, 0, 0x3F, 0),
472*4882a593Smuzhiyun 	SOC_SINGLE("ALC Capture Attack Rate", DA7210_ALC_ATT, 0, 0xFF, 0),
473*4882a593Smuzhiyun 	SOC_SINGLE("ALC Capture Release Rate", DA7210_ALC_REL, 0, 0xFF, 0),
474*4882a593Smuzhiyun 	SOC_SINGLE("ALC Capture Release Delay", DA7210_ALC_DEL, 0, 0xFF, 0),
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	SOC_SINGLE_EXT("Noise Suppression Enable Switch", DA7210_CONTROL, 3, 1,
477*4882a593Smuzhiyun 		       0, snd_soc_get_volsw, da7210_put_noise_sup_sw),
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun /*
481*4882a593Smuzhiyun  * DAPM Controls
482*4882a593Smuzhiyun  *
483*4882a593Smuzhiyun  * Current DAPM implementation covers almost all codec components e.g. IOs,
484*4882a593Smuzhiyun  * mixers, PGAs,ADC and DAC.
485*4882a593Smuzhiyun  */
486*4882a593Smuzhiyun /* In Mixer Left */
487*4882a593Smuzhiyun static const struct snd_kcontrol_new da7210_dapm_inmixl_controls[] = {
488*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Mic Left Switch", DA7210_INMIX_L, 0, 1, 0),
489*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Mic Right Switch", DA7210_INMIX_L, 1, 1, 0),
490*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Aux1 Left Switch", DA7210_INMIX_L, 2, 1, 0),
491*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Aux2 Switch", DA7210_INMIX_L, 3, 1, 0),
492*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Outmix Left Switch", DA7210_INMIX_L, 4, 1, 0),
493*4882a593Smuzhiyun };
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun /* In Mixer Right */
496*4882a593Smuzhiyun static const struct snd_kcontrol_new da7210_dapm_inmixr_controls[] = {
497*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Mic Right Switch", DA7210_INMIX_R, 0, 1, 0),
498*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Mic Left Switch", DA7210_INMIX_R, 1, 1, 0),
499*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Aux1 Right Switch", DA7210_INMIX_R, 2, 1, 0),
500*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Aux2 Switch", DA7210_INMIX_R, 3, 1, 0),
501*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Outmix Right Switch", DA7210_INMIX_R, 4, 1, 0),
502*4882a593Smuzhiyun };
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun /* Out Mixer Left */
505*4882a593Smuzhiyun static const struct snd_kcontrol_new da7210_dapm_outmixl_controls[] = {
506*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Aux1 Left Switch", DA7210_OUTMIX_L, 0, 1, 0),
507*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Aux2 Switch", DA7210_OUTMIX_L, 1, 1, 0),
508*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("INPGA Left Switch", DA7210_OUTMIX_L, 2, 1, 0),
509*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("INPGA Right Switch", DA7210_OUTMIX_L, 3, 1, 0),
510*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("DAC Left Switch", DA7210_OUTMIX_L, 4, 1, 0),
511*4882a593Smuzhiyun };
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun /* Out Mixer Right */
514*4882a593Smuzhiyun static const struct snd_kcontrol_new da7210_dapm_outmixr_controls[] = {
515*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Aux1 Right Switch", DA7210_OUTMIX_R, 0, 1, 0),
516*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Aux2 Switch", DA7210_OUTMIX_R, 1, 1, 0),
517*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("INPGA Left Switch", DA7210_OUTMIX_R, 2, 1, 0),
518*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("INPGA Right Switch", DA7210_OUTMIX_R, 3, 1, 0),
519*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("DAC Right Switch", DA7210_OUTMIX_R, 4, 1, 0),
520*4882a593Smuzhiyun };
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun /* Mono Mixer */
523*4882a593Smuzhiyun static const struct snd_kcontrol_new da7210_dapm_monomix_controls[] = {
524*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("INPGA Right Switch", DA7210_OUT2, 3, 1, 0),
525*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("INPGA Left Switch", DA7210_OUT2, 4, 1, 0),
526*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Outmix Right Switch", DA7210_OUT2, 5, 1, 0),
527*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Outmix Left Switch", DA7210_OUT2, 6, 1, 0),
528*4882a593Smuzhiyun };
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun /* DAPM widgets */
531*4882a593Smuzhiyun static const struct snd_soc_dapm_widget da7210_dapm_widgets[] = {
532*4882a593Smuzhiyun 	/* Input Side */
533*4882a593Smuzhiyun 	/* Input Lines */
534*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("MICL"),
535*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("MICR"),
536*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AUX1L"),
537*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AUX1R"),
538*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AUX2"),
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	/* Input PGAs */
541*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Mic Left", DA7210_STARTUP3, 0, 1, NULL, 0),
542*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Mic Right", DA7210_STARTUP3, 1, 1, NULL, 0),
543*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Aux1 Left", DA7210_STARTUP3, 2, 1, NULL, 0),
544*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Aux1 Right", DA7210_STARTUP3, 3, 1, NULL, 0),
545*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Aux2 Mono", DA7210_STARTUP3, 4, 1, NULL, 0),
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("INPGA Left", DA7210_INMIX_L, 7, 0, NULL, 0),
548*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("INPGA Right", DA7210_INMIX_R, 7, 0, NULL, 0),
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	/* MICBIAS */
551*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Mic Bias", DA7210_MIC_L, 6, 0, NULL, 0),
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	/* Input Mixers */
554*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0,
555*4882a593Smuzhiyun 		&da7210_dapm_inmixl_controls[0],
556*4882a593Smuzhiyun 		ARRAY_SIZE(da7210_dapm_inmixl_controls)),
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0,
559*4882a593Smuzhiyun 		&da7210_dapm_inmixr_controls[0],
560*4882a593Smuzhiyun 		ARRAY_SIZE(da7210_dapm_inmixr_controls)),
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 	/* ADCs */
563*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADC Left", "Capture", DA7210_STARTUP3, 5, 1),
564*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADC Right", "Capture", DA7210_STARTUP3, 6, 1),
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	/* Output Side */
567*4882a593Smuzhiyun 	/* DACs */
568*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DAC Left", "Playback", DA7210_STARTUP2, 5, 1),
569*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DAC Right", "Playback", DA7210_STARTUP2, 6, 1),
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	/* Output Mixers */
572*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0,
573*4882a593Smuzhiyun 		&da7210_dapm_outmixl_controls[0],
574*4882a593Smuzhiyun 		ARRAY_SIZE(da7210_dapm_outmixl_controls)),
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0,
577*4882a593Smuzhiyun 		&da7210_dapm_outmixr_controls[0],
578*4882a593Smuzhiyun 		ARRAY_SIZE(da7210_dapm_outmixr_controls)),
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
581*4882a593Smuzhiyun 		&da7210_dapm_monomix_controls[0],
582*4882a593Smuzhiyun 		ARRAY_SIZE(da7210_dapm_monomix_controls)),
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	/* Output PGAs */
585*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("OUTPGA Left Enable", DA7210_OUTMIX_L, 7, 0, NULL, 0),
586*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("OUTPGA Right Enable", DA7210_OUTMIX_R, 7, 0, NULL, 0),
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Out1 Left", DA7210_STARTUP2, 0, 1, NULL, 0),
589*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Out1 Right", DA7210_STARTUP2, 1, 1, NULL, 0),
590*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Out2 Mono", DA7210_STARTUP2, 2, 1, NULL, 0),
591*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Headphone Left", DA7210_STARTUP2, 3, 1, NULL, 0),
592*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("Headphone Right", DA7210_STARTUP2, 4, 1, NULL, 0),
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	/* Output Lines */
595*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("OUT1L"),
596*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("OUT1R"),
597*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HPL"),
598*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HPR"),
599*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("OUT2"),
600*4882a593Smuzhiyun };
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun /* DAPM audio route definition */
603*4882a593Smuzhiyun static const struct snd_soc_dapm_route da7210_audio_map[] = {
604*4882a593Smuzhiyun 	/* Dest       Connecting Widget    source */
605*4882a593Smuzhiyun 	/* Input path */
606*4882a593Smuzhiyun 	{"Mic Left", NULL, "MICL"},
607*4882a593Smuzhiyun 	{"Mic Right", NULL, "MICR"},
608*4882a593Smuzhiyun 	{"Aux1 Left", NULL, "AUX1L"},
609*4882a593Smuzhiyun 	{"Aux1 Right", NULL, "AUX1R"},
610*4882a593Smuzhiyun 	{"Aux2 Mono", NULL, "AUX2"},
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 	{"In Mixer Left", "Mic Left Switch", "Mic Left"},
613*4882a593Smuzhiyun 	{"In Mixer Left", "Mic Right Switch", "Mic Right"},
614*4882a593Smuzhiyun 	{"In Mixer Left", "Aux1 Left Switch", "Aux1 Left"},
615*4882a593Smuzhiyun 	{"In Mixer Left", "Aux2 Switch", "Aux2 Mono"},
616*4882a593Smuzhiyun 	{"In Mixer Left", "Outmix Left Switch", "Out Mixer Left"},
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	{"In Mixer Right", "Mic Right Switch", "Mic Right"},
619*4882a593Smuzhiyun 	{"In Mixer Right", "Mic Left Switch", "Mic Left"},
620*4882a593Smuzhiyun 	{"In Mixer Right", "Aux1 Right Switch", "Aux1 Right"},
621*4882a593Smuzhiyun 	{"In Mixer Right", "Aux2 Switch", "Aux2 Mono"},
622*4882a593Smuzhiyun 	{"In Mixer Right", "Outmix Right Switch", "Out Mixer Right"},
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	{"INPGA Left", NULL, "In Mixer Left"},
625*4882a593Smuzhiyun 	{"ADC Left", NULL, "INPGA Left"},
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	{"INPGA Right", NULL, "In Mixer Right"},
628*4882a593Smuzhiyun 	{"ADC Right", NULL, "INPGA Right"},
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	/* Output path */
631*4882a593Smuzhiyun 	{"Out Mixer Left", "Aux1 Left Switch", "Aux1 Left"},
632*4882a593Smuzhiyun 	{"Out Mixer Left", "Aux2 Switch", "Aux2 Mono"},
633*4882a593Smuzhiyun 	{"Out Mixer Left", "INPGA Left Switch", "INPGA Left"},
634*4882a593Smuzhiyun 	{"Out Mixer Left", "INPGA Right Switch", "INPGA Right"},
635*4882a593Smuzhiyun 	{"Out Mixer Left", "DAC Left Switch", "DAC Left"},
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	{"Out Mixer Right", "Aux1 Right Switch", "Aux1 Right"},
638*4882a593Smuzhiyun 	{"Out Mixer Right", "Aux2 Switch", "Aux2 Mono"},
639*4882a593Smuzhiyun 	{"Out Mixer Right", "INPGA Right Switch", "INPGA Right"},
640*4882a593Smuzhiyun 	{"Out Mixer Right", "INPGA Left Switch", "INPGA Left"},
641*4882a593Smuzhiyun 	{"Out Mixer Right", "DAC Right Switch", "DAC Right"},
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun 	{"Mono Mixer", "INPGA Right Switch", "INPGA Right"},
644*4882a593Smuzhiyun 	{"Mono Mixer", "INPGA Left Switch", "INPGA Left"},
645*4882a593Smuzhiyun 	{"Mono Mixer", "Outmix Right Switch", "Out Mixer Right"},
646*4882a593Smuzhiyun 	{"Mono Mixer", "Outmix Left Switch", "Out Mixer Left"},
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	{"OUTPGA Left Enable", NULL, "Out Mixer Left"},
649*4882a593Smuzhiyun 	{"OUTPGA Right Enable", NULL, "Out Mixer Right"},
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 	{"Out1 Left", NULL, "OUTPGA Left Enable"},
652*4882a593Smuzhiyun 	{"OUT1L", NULL, "Out1 Left"},
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	{"Out1 Right", NULL, "OUTPGA Right Enable"},
655*4882a593Smuzhiyun 	{"OUT1R", NULL, "Out1 Right"},
656*4882a593Smuzhiyun 
657*4882a593Smuzhiyun 	{"Headphone Left", NULL, "OUTPGA Left Enable"},
658*4882a593Smuzhiyun 	{"HPL", NULL, "Headphone Left"},
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	{"Headphone Right", NULL, "OUTPGA Right Enable"},
661*4882a593Smuzhiyun 	{"HPR", NULL, "Headphone Right"},
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 	{"Out2 Mono", NULL, "Mono Mixer"},
664*4882a593Smuzhiyun 	{"OUT2", NULL, "Out2 Mono"},
665*4882a593Smuzhiyun };
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun /* Codec private data */
668*4882a593Smuzhiyun struct da7210_priv {
669*4882a593Smuzhiyun 	struct regmap *regmap;
670*4882a593Smuzhiyun 	unsigned int mclk_rate;
671*4882a593Smuzhiyun 	int master;
672*4882a593Smuzhiyun };
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun static const struct reg_default da7210_reg_defaults[] = {
675*4882a593Smuzhiyun 	{ 0x00, 0x00 },
676*4882a593Smuzhiyun 	{ 0x01, 0x11 },
677*4882a593Smuzhiyun 	{ 0x03, 0x00 },
678*4882a593Smuzhiyun 	{ 0x04, 0x00 },
679*4882a593Smuzhiyun 	{ 0x05, 0x00 },
680*4882a593Smuzhiyun 	{ 0x06, 0x00 },
681*4882a593Smuzhiyun 	{ 0x07, 0x00 },
682*4882a593Smuzhiyun 	{ 0x08, 0x00 },
683*4882a593Smuzhiyun 	{ 0x09, 0x00 },
684*4882a593Smuzhiyun 	{ 0x0a, 0x00 },
685*4882a593Smuzhiyun 	{ 0x0b, 0x00 },
686*4882a593Smuzhiyun 	{ 0x0c, 0x00 },
687*4882a593Smuzhiyun 	{ 0x0d, 0x00 },
688*4882a593Smuzhiyun 	{ 0x0e, 0x00 },
689*4882a593Smuzhiyun 	{ 0x0f, 0x08 },
690*4882a593Smuzhiyun 	{ 0x10, 0x00 },
691*4882a593Smuzhiyun 	{ 0x11, 0x00 },
692*4882a593Smuzhiyun 	{ 0x12, 0x00 },
693*4882a593Smuzhiyun 	{ 0x13, 0x00 },
694*4882a593Smuzhiyun 	{ 0x14, 0x08 },
695*4882a593Smuzhiyun 	{ 0x15, 0x10 },
696*4882a593Smuzhiyun 	{ 0x16, 0x10 },
697*4882a593Smuzhiyun 	{ 0x17, 0x54 },
698*4882a593Smuzhiyun 	{ 0x18, 0x40 },
699*4882a593Smuzhiyun 	{ 0x19, 0x00 },
700*4882a593Smuzhiyun 	{ 0x1a, 0x00 },
701*4882a593Smuzhiyun 	{ 0x1b, 0x00 },
702*4882a593Smuzhiyun 	{ 0x1c, 0x00 },
703*4882a593Smuzhiyun 	{ 0x1d, 0x00 },
704*4882a593Smuzhiyun 	{ 0x1e, 0x00 },
705*4882a593Smuzhiyun 	{ 0x1f, 0x00 },
706*4882a593Smuzhiyun 	{ 0x20, 0x00 },
707*4882a593Smuzhiyun 	{ 0x21, 0x00 },
708*4882a593Smuzhiyun 	{ 0x22, 0x00 },
709*4882a593Smuzhiyun 	{ 0x23, 0x02 },
710*4882a593Smuzhiyun 	{ 0x24, 0x00 },
711*4882a593Smuzhiyun 	{ 0x25, 0x76 },
712*4882a593Smuzhiyun 	{ 0x26, 0x00 },
713*4882a593Smuzhiyun 	{ 0x27, 0x00 },
714*4882a593Smuzhiyun 	{ 0x28, 0x04 },
715*4882a593Smuzhiyun 	{ 0x29, 0x00 },
716*4882a593Smuzhiyun 	{ 0x2a, 0x00 },
717*4882a593Smuzhiyun 	{ 0x2b, 0x30 },
718*4882a593Smuzhiyun 	{ 0x2c, 0x2A },
719*4882a593Smuzhiyun 	{ 0x83, 0x00 },
720*4882a593Smuzhiyun 	{ 0x84, 0x00 },
721*4882a593Smuzhiyun 	{ 0x85, 0x00 },
722*4882a593Smuzhiyun 	{ 0x86, 0x00 },
723*4882a593Smuzhiyun 	{ 0x87, 0x00 },
724*4882a593Smuzhiyun 	{ 0x88, 0x00 },
725*4882a593Smuzhiyun };
726*4882a593Smuzhiyun 
da7210_readable_register(struct device * dev,unsigned int reg)727*4882a593Smuzhiyun static bool da7210_readable_register(struct device *dev, unsigned int reg)
728*4882a593Smuzhiyun {
729*4882a593Smuzhiyun 	switch (reg) {
730*4882a593Smuzhiyun 	case DA7210_A_HID_UNLOCK:
731*4882a593Smuzhiyun 	case DA7210_A_TEST_UNLOCK:
732*4882a593Smuzhiyun 	case DA7210_A_PLL1:
733*4882a593Smuzhiyun 	case DA7210_A_CP_MODE:
734*4882a593Smuzhiyun 		return false;
735*4882a593Smuzhiyun 	default:
736*4882a593Smuzhiyun 		return true;
737*4882a593Smuzhiyun 	}
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun 
da7210_volatile_register(struct device * dev,unsigned int reg)740*4882a593Smuzhiyun static bool da7210_volatile_register(struct device *dev,
741*4882a593Smuzhiyun 				    unsigned int reg)
742*4882a593Smuzhiyun {
743*4882a593Smuzhiyun 	switch (reg) {
744*4882a593Smuzhiyun 	case DA7210_STATUS:
745*4882a593Smuzhiyun 		return true;
746*4882a593Smuzhiyun 	default:
747*4882a593Smuzhiyun 		return false;
748*4882a593Smuzhiyun 	}
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun /*
752*4882a593Smuzhiyun  * Set PCM DAI word length.
753*4882a593Smuzhiyun  */
da7210_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)754*4882a593Smuzhiyun static int da7210_hw_params(struct snd_pcm_substream *substream,
755*4882a593Smuzhiyun 			    struct snd_pcm_hw_params *params,
756*4882a593Smuzhiyun 			    struct snd_soc_dai *dai)
757*4882a593Smuzhiyun {
758*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
759*4882a593Smuzhiyun 	struct da7210_priv *da7210 = snd_soc_component_get_drvdata(component);
760*4882a593Smuzhiyun 	u32 dai_cfg1;
761*4882a593Smuzhiyun 	u32 fs, sysclk;
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun 	/* set DAI source to Left and Right ADC */
764*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_DAI_SRC_SEL,
765*4882a593Smuzhiyun 		     DA7210_DAI_OUT_R_SRC | DA7210_DAI_OUT_L_SRC);
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun 	/* Enable DAI */
768*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_DAI_CFG3, DA7210_DAI_OE | DA7210_DAI_EN);
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	dai_cfg1 = 0xFC & snd_soc_component_read(component, DA7210_DAI_CFG1);
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun 	switch (params_width(params)) {
773*4882a593Smuzhiyun 	case 16:
774*4882a593Smuzhiyun 		dai_cfg1 |= DA7210_DAI_WORD_S16_LE;
775*4882a593Smuzhiyun 		break;
776*4882a593Smuzhiyun 	case 20:
777*4882a593Smuzhiyun 		dai_cfg1 |= DA7210_DAI_WORD_S20_3LE;
778*4882a593Smuzhiyun 		break;
779*4882a593Smuzhiyun 	case 24:
780*4882a593Smuzhiyun 		dai_cfg1 |= DA7210_DAI_WORD_S24_LE;
781*4882a593Smuzhiyun 		break;
782*4882a593Smuzhiyun 	case 32:
783*4882a593Smuzhiyun 		dai_cfg1 |= DA7210_DAI_WORD_S32_LE;
784*4882a593Smuzhiyun 		break;
785*4882a593Smuzhiyun 	default:
786*4882a593Smuzhiyun 		return -EINVAL;
787*4882a593Smuzhiyun 	}
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_DAI_CFG1, dai_cfg1);
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun 	switch (params_rate(params)) {
792*4882a593Smuzhiyun 	case 8000:
793*4882a593Smuzhiyun 		fs		= DA7210_PLL_FS_8000;
794*4882a593Smuzhiyun 		sysclk		= 3072000;
795*4882a593Smuzhiyun 		break;
796*4882a593Smuzhiyun 	case 11025:
797*4882a593Smuzhiyun 		fs		= DA7210_PLL_FS_11025;
798*4882a593Smuzhiyun 		sysclk		= 2822400;
799*4882a593Smuzhiyun 		break;
800*4882a593Smuzhiyun 	case 12000:
801*4882a593Smuzhiyun 		fs		= DA7210_PLL_FS_12000;
802*4882a593Smuzhiyun 		sysclk		= 3072000;
803*4882a593Smuzhiyun 		break;
804*4882a593Smuzhiyun 	case 16000:
805*4882a593Smuzhiyun 		fs		= DA7210_PLL_FS_16000;
806*4882a593Smuzhiyun 		sysclk		= 3072000;
807*4882a593Smuzhiyun 		break;
808*4882a593Smuzhiyun 	case 22050:
809*4882a593Smuzhiyun 		fs		= DA7210_PLL_FS_22050;
810*4882a593Smuzhiyun 		sysclk		= 2822400;
811*4882a593Smuzhiyun 		break;
812*4882a593Smuzhiyun 	case 32000:
813*4882a593Smuzhiyun 		fs		= DA7210_PLL_FS_32000;
814*4882a593Smuzhiyun 		sysclk		= 3072000;
815*4882a593Smuzhiyun 		break;
816*4882a593Smuzhiyun 	case 44100:
817*4882a593Smuzhiyun 		fs		= DA7210_PLL_FS_44100;
818*4882a593Smuzhiyun 		sysclk		= 2822400;
819*4882a593Smuzhiyun 		break;
820*4882a593Smuzhiyun 	case 48000:
821*4882a593Smuzhiyun 		fs		= DA7210_PLL_FS_48000;
822*4882a593Smuzhiyun 		sysclk		= 3072000;
823*4882a593Smuzhiyun 		break;
824*4882a593Smuzhiyun 	case 88200:
825*4882a593Smuzhiyun 		fs		= DA7210_PLL_FS_88200;
826*4882a593Smuzhiyun 		sysclk		= 2822400;
827*4882a593Smuzhiyun 		break;
828*4882a593Smuzhiyun 	case 96000:
829*4882a593Smuzhiyun 		fs		= DA7210_PLL_FS_96000;
830*4882a593Smuzhiyun 		sysclk		= 3072000;
831*4882a593Smuzhiyun 		break;
832*4882a593Smuzhiyun 	default:
833*4882a593Smuzhiyun 		return -EINVAL;
834*4882a593Smuzhiyun 	}
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun 	/* Disable active mode */
837*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, DA7210_STARTUP1, DA7210_SC_MST_EN, 0);
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, DA7210_PLL, DA7210_PLL_FS_MASK, fs);
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun 	if (da7210->mclk_rate && (da7210->mclk_rate != sysclk)) {
842*4882a593Smuzhiyun 		/* PLL mode, disable PLL bypass */
843*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, DA7210_PLL_DIV3, DA7210_PLL_BYP, 0);
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun 		if (!da7210->master) {
846*4882a593Smuzhiyun 			/* PLL slave mode, also enable SRM */
847*4882a593Smuzhiyun 			snd_soc_component_update_bits(component, DA7210_PLL,
848*4882a593Smuzhiyun 						   (DA7210_MCLK_SRM_EN |
849*4882a593Smuzhiyun 						    DA7210_MCLK_DET_EN),
850*4882a593Smuzhiyun 						   (DA7210_MCLK_SRM_EN |
851*4882a593Smuzhiyun 						    DA7210_MCLK_DET_EN));
852*4882a593Smuzhiyun 		}
853*4882a593Smuzhiyun 	} else {
854*4882a593Smuzhiyun 		/* PLL bypass mode, enable PLL bypass and Auto Detection */
855*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, DA7210_PLL, DA7210_MCLK_DET_EN,
856*4882a593Smuzhiyun 						       DA7210_MCLK_DET_EN);
857*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, DA7210_PLL_DIV3, DA7210_PLL_BYP,
858*4882a593Smuzhiyun 							    DA7210_PLL_BYP);
859*4882a593Smuzhiyun 	}
860*4882a593Smuzhiyun 	/* Enable active mode */
861*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, DA7210_STARTUP1,
862*4882a593Smuzhiyun 			    DA7210_SC_MST_EN, DA7210_SC_MST_EN);
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun 	return 0;
865*4882a593Smuzhiyun }
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun /*
868*4882a593Smuzhiyun  * Set DAI mode and Format
869*4882a593Smuzhiyun  */
da7210_set_dai_fmt(struct snd_soc_dai * codec_dai,u32 fmt)870*4882a593Smuzhiyun static int da7210_set_dai_fmt(struct snd_soc_dai *codec_dai, u32 fmt)
871*4882a593Smuzhiyun {
872*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
873*4882a593Smuzhiyun 	struct da7210_priv *da7210 = snd_soc_component_get_drvdata(component);
874*4882a593Smuzhiyun 	u32 dai_cfg1;
875*4882a593Smuzhiyun 	u32 dai_cfg3;
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	dai_cfg1 = 0x7f & snd_soc_component_read(component, DA7210_DAI_CFG1);
878*4882a593Smuzhiyun 	dai_cfg3 = 0xfc & snd_soc_component_read(component, DA7210_DAI_CFG3);
879*4882a593Smuzhiyun 
880*4882a593Smuzhiyun 	if ((snd_soc_component_read(component, DA7210_PLL) & DA7210_PLL_EN) &&
881*4882a593Smuzhiyun 		(!(snd_soc_component_read(component, DA7210_PLL_DIV3) & DA7210_PLL_BYP)))
882*4882a593Smuzhiyun 		return -EINVAL;
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
885*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
886*4882a593Smuzhiyun 		da7210->master = 1;
887*4882a593Smuzhiyun 		dai_cfg1 |= DA7210_DAI_MODE_MASTER;
888*4882a593Smuzhiyun 		break;
889*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
890*4882a593Smuzhiyun 		da7210->master = 0;
891*4882a593Smuzhiyun 		dai_cfg1 |= DA7210_DAI_MODE_SLAVE;
892*4882a593Smuzhiyun 		break;
893*4882a593Smuzhiyun 	default:
894*4882a593Smuzhiyun 		return -EINVAL;
895*4882a593Smuzhiyun 	}
896*4882a593Smuzhiyun 
897*4882a593Smuzhiyun 	/* FIXME
898*4882a593Smuzhiyun 	 *
899*4882a593Smuzhiyun 	 * It support I2S only now
900*4882a593Smuzhiyun 	 */
901*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
902*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_I2S:
903*4882a593Smuzhiyun 		dai_cfg3 |= DA7210_DAI_FORMAT_I2SMODE;
904*4882a593Smuzhiyun 		break;
905*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_LEFT_J:
906*4882a593Smuzhiyun 		dai_cfg3 |= DA7210_DAI_FORMAT_LEFT_J;
907*4882a593Smuzhiyun 		break;
908*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_RIGHT_J:
909*4882a593Smuzhiyun 		dai_cfg3 |= DA7210_DAI_FORMAT_RIGHT_J;
910*4882a593Smuzhiyun 		break;
911*4882a593Smuzhiyun 	default:
912*4882a593Smuzhiyun 		return -EINVAL;
913*4882a593Smuzhiyun 	}
914*4882a593Smuzhiyun 
915*4882a593Smuzhiyun 	/* FIXME
916*4882a593Smuzhiyun 	 *
917*4882a593Smuzhiyun 	 * It support 64bit data transmission only now
918*4882a593Smuzhiyun 	 */
919*4882a593Smuzhiyun 	dai_cfg1 |= DA7210_DAI_FLEN_64BIT;
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_DAI_CFG1, dai_cfg1);
922*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_DAI_CFG3, dai_cfg3);
923*4882a593Smuzhiyun 
924*4882a593Smuzhiyun 	return 0;
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun 
da7210_mute(struct snd_soc_dai * dai,int mute,int direction)927*4882a593Smuzhiyun static int da7210_mute(struct snd_soc_dai *dai, int mute, int direction)
928*4882a593Smuzhiyun {
929*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
930*4882a593Smuzhiyun 	u8 mute_reg = snd_soc_component_read(component, DA7210_DAC_HPF) & 0xFB;
931*4882a593Smuzhiyun 
932*4882a593Smuzhiyun 	if (mute)
933*4882a593Smuzhiyun 		snd_soc_component_write(component, DA7210_DAC_HPF, mute_reg | 0x4);
934*4882a593Smuzhiyun 	else
935*4882a593Smuzhiyun 		snd_soc_component_write(component, DA7210_DAC_HPF, mute_reg);
936*4882a593Smuzhiyun 	return 0;
937*4882a593Smuzhiyun }
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun #define DA7210_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
940*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
941*4882a593Smuzhiyun 
da7210_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)942*4882a593Smuzhiyun static int da7210_set_dai_sysclk(struct snd_soc_dai *codec_dai,
943*4882a593Smuzhiyun 				 int clk_id, unsigned int freq, int dir)
944*4882a593Smuzhiyun {
945*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
946*4882a593Smuzhiyun 	struct da7210_priv *da7210 = snd_soc_component_get_drvdata(component);
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun 	switch (clk_id) {
949*4882a593Smuzhiyun 	case DA7210_CLKSRC_MCLK:
950*4882a593Smuzhiyun 		switch (freq) {
951*4882a593Smuzhiyun 		case 12000000:
952*4882a593Smuzhiyun 		case 13000000:
953*4882a593Smuzhiyun 		case 13500000:
954*4882a593Smuzhiyun 		case 14400000:
955*4882a593Smuzhiyun 		case 19200000:
956*4882a593Smuzhiyun 		case 19680000:
957*4882a593Smuzhiyun 		case 19800000:
958*4882a593Smuzhiyun 			da7210->mclk_rate = freq;
959*4882a593Smuzhiyun 			return 0;
960*4882a593Smuzhiyun 		default:
961*4882a593Smuzhiyun 			dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
962*4882a593Smuzhiyun 				freq);
963*4882a593Smuzhiyun 			return -EINVAL;
964*4882a593Smuzhiyun 		}
965*4882a593Smuzhiyun 		break;
966*4882a593Smuzhiyun 	default:
967*4882a593Smuzhiyun 		dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
968*4882a593Smuzhiyun 		return -EINVAL;
969*4882a593Smuzhiyun 	}
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun 
972*4882a593Smuzhiyun /**
973*4882a593Smuzhiyun  * da7210_set_dai_pll	:Configure the codec PLL
974*4882a593Smuzhiyun  * @codec_dai: pointer to codec DAI
975*4882a593Smuzhiyun  * @pll_id: da7210 has only one pll, so pll_id is always zero
976*4882a593Smuzhiyun  * @source: clock source
977*4882a593Smuzhiyun  * @fref: MCLK frequency, should be < 20MHz
978*4882a593Smuzhiyun  * @fout: FsDM value, Refer page 44 & 45 of datasheet
979*4882a593Smuzhiyun  *
980*4882a593Smuzhiyun  * Note: Supported PLL input frequencies are 12MHz, 13MHz, 13.5MHz, 14.4MHz,
981*4882a593Smuzhiyun  *       19.2MHz, 19.6MHz and 19.8MHz
982*4882a593Smuzhiyun  *
983*4882a593Smuzhiyun  * Return: Zero for success, negative error code for error
984*4882a593Smuzhiyun  */
da7210_set_dai_pll(struct snd_soc_dai * codec_dai,int pll_id,int source,unsigned int fref,unsigned int fout)985*4882a593Smuzhiyun static int da7210_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
986*4882a593Smuzhiyun 			      int source, unsigned int fref, unsigned int fout)
987*4882a593Smuzhiyun {
988*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
989*4882a593Smuzhiyun 	struct da7210_priv *da7210 = snd_soc_component_get_drvdata(component);
990*4882a593Smuzhiyun 
991*4882a593Smuzhiyun 	u8 pll_div1, pll_div2, pll_div3, cnt;
992*4882a593Smuzhiyun 
993*4882a593Smuzhiyun 	/* In slave mode, there is only one set of divisors */
994*4882a593Smuzhiyun 	if (!da7210->master)
995*4882a593Smuzhiyun 		fout = 2822400;
996*4882a593Smuzhiyun 
997*4882a593Smuzhiyun 	/* Search pll div array for correct divisors */
998*4882a593Smuzhiyun 	for (cnt = 0; cnt < ARRAY_SIZE(da7210_pll_div); cnt++) {
999*4882a593Smuzhiyun 		/* check fref, mode  and fout */
1000*4882a593Smuzhiyun 		if ((fref == da7210_pll_div[cnt].fref) &&
1001*4882a593Smuzhiyun 		    (da7210->master ==  da7210_pll_div[cnt].mode) &&
1002*4882a593Smuzhiyun 		    (fout == da7210_pll_div[cnt].fout)) {
1003*4882a593Smuzhiyun 			/* all match, pick up divisors */
1004*4882a593Smuzhiyun 			pll_div1 = da7210_pll_div[cnt].div1;
1005*4882a593Smuzhiyun 			pll_div2 = da7210_pll_div[cnt].div2;
1006*4882a593Smuzhiyun 			pll_div3 = da7210_pll_div[cnt].div3;
1007*4882a593Smuzhiyun 			break;
1008*4882a593Smuzhiyun 		}
1009*4882a593Smuzhiyun 	}
1010*4882a593Smuzhiyun 	if (cnt >= ARRAY_SIZE(da7210_pll_div))
1011*4882a593Smuzhiyun 		goto err;
1012*4882a593Smuzhiyun 
1013*4882a593Smuzhiyun 	/* Disable active mode */
1014*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, DA7210_STARTUP1, DA7210_SC_MST_EN, 0);
1015*4882a593Smuzhiyun 	/* Write PLL dividers */
1016*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_PLL_DIV1, pll_div1);
1017*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_PLL_DIV2, pll_div2);
1018*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, DA7210_PLL_DIV3,
1019*4882a593Smuzhiyun 				   DA7210_PLL_DIV_L_MASK, pll_div3);
1020*4882a593Smuzhiyun 
1021*4882a593Smuzhiyun 	/* Enable PLL */
1022*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, DA7210_PLL, DA7210_PLL_EN, DA7210_PLL_EN);
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	/* Enable active mode */
1025*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, DA7210_STARTUP1, DA7210_SC_MST_EN,
1026*4882a593Smuzhiyun 						    DA7210_SC_MST_EN);
1027*4882a593Smuzhiyun 	return 0;
1028*4882a593Smuzhiyun err:
1029*4882a593Smuzhiyun 	dev_err(codec_dai->dev, "Unsupported PLL input frequency %d\n", fref);
1030*4882a593Smuzhiyun 	return -EINVAL;
1031*4882a593Smuzhiyun }
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun /* DAI operations */
1034*4882a593Smuzhiyun static const struct snd_soc_dai_ops da7210_dai_ops = {
1035*4882a593Smuzhiyun 	.hw_params	= da7210_hw_params,
1036*4882a593Smuzhiyun 	.set_fmt	= da7210_set_dai_fmt,
1037*4882a593Smuzhiyun 	.set_sysclk	= da7210_set_dai_sysclk,
1038*4882a593Smuzhiyun 	.set_pll	= da7210_set_dai_pll,
1039*4882a593Smuzhiyun 	.mute_stream	= da7210_mute,
1040*4882a593Smuzhiyun 	.no_capture_mute = 1,
1041*4882a593Smuzhiyun };
1042*4882a593Smuzhiyun 
1043*4882a593Smuzhiyun static struct snd_soc_dai_driver da7210_dai = {
1044*4882a593Smuzhiyun 	.name = "da7210-hifi",
1045*4882a593Smuzhiyun 	/* playback capabilities */
1046*4882a593Smuzhiyun 	.playback = {
1047*4882a593Smuzhiyun 		.stream_name = "Playback",
1048*4882a593Smuzhiyun 		.channels_min = 1,
1049*4882a593Smuzhiyun 		.channels_max = 2,
1050*4882a593Smuzhiyun 		.rates = SNDRV_PCM_RATE_8000_96000,
1051*4882a593Smuzhiyun 		.formats = DA7210_FORMATS,
1052*4882a593Smuzhiyun 	},
1053*4882a593Smuzhiyun 	/* capture capabilities */
1054*4882a593Smuzhiyun 	.capture = {
1055*4882a593Smuzhiyun 		.stream_name = "Capture",
1056*4882a593Smuzhiyun 		.channels_min = 1,
1057*4882a593Smuzhiyun 		.channels_max = 2,
1058*4882a593Smuzhiyun 		.rates = SNDRV_PCM_RATE_8000_96000,
1059*4882a593Smuzhiyun 		.formats = DA7210_FORMATS,
1060*4882a593Smuzhiyun 	},
1061*4882a593Smuzhiyun 	.ops = &da7210_dai_ops,
1062*4882a593Smuzhiyun 	.symmetric_rates = 1,
1063*4882a593Smuzhiyun };
1064*4882a593Smuzhiyun 
da7210_probe(struct snd_soc_component * component)1065*4882a593Smuzhiyun static int da7210_probe(struct snd_soc_component *component)
1066*4882a593Smuzhiyun {
1067*4882a593Smuzhiyun 	struct da7210_priv *da7210 = snd_soc_component_get_drvdata(component);
1068*4882a593Smuzhiyun 
1069*4882a593Smuzhiyun 	dev_info(component->dev, "DA7210 Audio Codec %s\n", DA7210_VERSION);
1070*4882a593Smuzhiyun 
1071*4882a593Smuzhiyun 	da7210->mclk_rate       = 0;    /* This will be set from set_sysclk() */
1072*4882a593Smuzhiyun 	da7210->master          = 0;    /* This will be set from set_fmt() */
1073*4882a593Smuzhiyun 
1074*4882a593Smuzhiyun 	/* Enable internal regulator & bias current */
1075*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_CONTROL, DA7210_REG_EN | DA7210_BIAS_EN);
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 	/*
1078*4882a593Smuzhiyun 	 * ADC settings
1079*4882a593Smuzhiyun 	 */
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	/* Enable Left & Right MIC PGA and Mic Bias */
1082*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_MIC_L, DA7210_MIC_L_EN | DA7210_MICBIAS_EN);
1083*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_MIC_R, DA7210_MIC_R_EN);
1084*4882a593Smuzhiyun 
1085*4882a593Smuzhiyun 	/* Enable Left and Right input PGA */
1086*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_INMIX_L, DA7210_IN_L_EN);
1087*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_INMIX_R, DA7210_IN_R_EN);
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun 	/* Enable Left and Right ADC */
1090*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_ADC, DA7210_ADC_L_EN | DA7210_ADC_R_EN);
1091*4882a593Smuzhiyun 
1092*4882a593Smuzhiyun 	/*
1093*4882a593Smuzhiyun 	 * DAC settings
1094*4882a593Smuzhiyun 	 */
1095*4882a593Smuzhiyun 
1096*4882a593Smuzhiyun 	/* Enable Left and Right DAC */
1097*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_DAC_SEL,
1098*4882a593Smuzhiyun 		     DA7210_DAC_L_SRC_DAI_L | DA7210_DAC_L_EN |
1099*4882a593Smuzhiyun 		     DA7210_DAC_R_SRC_DAI_R | DA7210_DAC_R_EN);
1100*4882a593Smuzhiyun 
1101*4882a593Smuzhiyun 	/* Enable Left and Right out PGA */
1102*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_OUTMIX_L, DA7210_OUT_L_EN);
1103*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_OUTMIX_R, DA7210_OUT_R_EN);
1104*4882a593Smuzhiyun 
1105*4882a593Smuzhiyun 	/* Enable Left and Right HeadPhone PGA */
1106*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_HP_CFG,
1107*4882a593Smuzhiyun 		     DA7210_HP_2CAP_MODE | DA7210_HP_SENSE_EN |
1108*4882a593Smuzhiyun 		     DA7210_HP_L_EN | DA7210_HP_MODE | DA7210_HP_R_EN);
1109*4882a593Smuzhiyun 
1110*4882a593Smuzhiyun 	/* Enable ramp mode for DAC gain update */
1111*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_SOFTMUTE, DA7210_RAMP_EN);
1112*4882a593Smuzhiyun 
1113*4882a593Smuzhiyun 	/*
1114*4882a593Smuzhiyun 	 * For DA7210 codec, there are two ways to enable/disable analog IOs
1115*4882a593Smuzhiyun 	 * and ADC/DAC,
1116*4882a593Smuzhiyun 	 * (1) Using "Enable Bit" of register associated with that IO
1117*4882a593Smuzhiyun 	 * (or ADC/DAC)
1118*4882a593Smuzhiyun 	 *	e.g. Mic Left can be enabled using bit 7 of MIC_L(0x7) reg
1119*4882a593Smuzhiyun 	 *
1120*4882a593Smuzhiyun 	 * (2) Using "Standby Bit" of STARTUP2 or STARTUP3 register
1121*4882a593Smuzhiyun 	 *	e.g. Mic left can be put to STANDBY using bit 0 of STARTUP3(0x5)
1122*4882a593Smuzhiyun 	 *
1123*4882a593Smuzhiyun 	 * Out of these two methods, the one using STANDBY bits is preferred
1124*4882a593Smuzhiyun 	 * way to enable/disable individual blocks. This is because STANDBY
1125*4882a593Smuzhiyun 	 * registers are part of system controller which allows system power
1126*4882a593Smuzhiyun 	 * up/down in a controlled, pop-free manner. Also, as per application
1127*4882a593Smuzhiyun 	 * note of DA7210, STANDBY register bits are only effective if a
1128*4882a593Smuzhiyun 	 * particular IO (or ADC/DAC) is already enabled using enable/disable
1129*4882a593Smuzhiyun 	 * register bits. Keeping these things in mind, current DAPM
1130*4882a593Smuzhiyun 	 * implementation manipulates only STANDBY bits.
1131*4882a593Smuzhiyun 	 *
1132*4882a593Smuzhiyun 	 * Overall implementation can be outlined as below,
1133*4882a593Smuzhiyun 	 *
1134*4882a593Smuzhiyun 	 * - "Enable bit" of an IO or ADC/DAC is used to enable it in probe()
1135*4882a593Smuzhiyun 	 * - "STANDBY bit" is controlled by DAPM
1136*4882a593Smuzhiyun 	 */
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	/* Enable Line out amplifiers */
1139*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_OUT1_L, DA7210_OUT1_L_EN);
1140*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_OUT1_R, DA7210_OUT1_R_EN);
1141*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_OUT2, DA7210_OUT2_EN |
1142*4882a593Smuzhiyun 		     DA7210_OUT2_OUTMIX_L | DA7210_OUT2_OUTMIX_R);
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun 	/* Enable Aux1 */
1145*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_AUX1_L, DA7210_AUX1_L_EN);
1146*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_AUX1_R, DA7210_AUX1_R_EN);
1147*4882a593Smuzhiyun 	/* Enable Aux2 */
1148*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_AUX2, DA7210_AUX2_EN);
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun 	/* Set PLL Master clock range 10-20 MHz, enable PLL bypass */
1151*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_PLL_DIV3, DA7210_MCLK_RANGE_10_20_MHZ |
1152*4882a593Smuzhiyun 					      DA7210_PLL_BYP);
1153*4882a593Smuzhiyun 
1154*4882a593Smuzhiyun 	/* Diable PLL and bypass it */
1155*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_PLL, DA7210_PLL_FS_48000);
1156*4882a593Smuzhiyun 
1157*4882a593Smuzhiyun 	/* Activate all enabled subsystem */
1158*4882a593Smuzhiyun 	snd_soc_component_write(component, DA7210_STARTUP1, DA7210_SC_MST_EN);
1159*4882a593Smuzhiyun 
1160*4882a593Smuzhiyun 	dev_info(component->dev, "DA7210 Audio Codec %s\n", DA7210_VERSION);
1161*4882a593Smuzhiyun 
1162*4882a593Smuzhiyun 	return 0;
1163*4882a593Smuzhiyun }
1164*4882a593Smuzhiyun 
1165*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_da7210 = {
1166*4882a593Smuzhiyun 	.probe			= da7210_probe,
1167*4882a593Smuzhiyun 	.controls		= da7210_snd_controls,
1168*4882a593Smuzhiyun 	.num_controls		= ARRAY_SIZE(da7210_snd_controls),
1169*4882a593Smuzhiyun 	.dapm_widgets		= da7210_dapm_widgets,
1170*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(da7210_dapm_widgets),
1171*4882a593Smuzhiyun 	.dapm_routes		= da7210_audio_map,
1172*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(da7210_audio_map),
1173*4882a593Smuzhiyun 	.idle_bias_on		= 1,
1174*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
1175*4882a593Smuzhiyun 	.endianness		= 1,
1176*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
1177*4882a593Smuzhiyun };
1178*4882a593Smuzhiyun 
1179*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun static const struct reg_sequence da7210_regmap_i2c_patch[] = {
1182*4882a593Smuzhiyun 
1183*4882a593Smuzhiyun 	/* System controller master disable */
1184*4882a593Smuzhiyun 	{ DA7210_STARTUP1, 0x00 },
1185*4882a593Smuzhiyun 	/* Set PLL Master clock range 10-20 MHz */
1186*4882a593Smuzhiyun 	{ DA7210_PLL_DIV3, DA7210_MCLK_RANGE_10_20_MHZ },
1187*4882a593Smuzhiyun 
1188*4882a593Smuzhiyun 	/* to unlock */
1189*4882a593Smuzhiyun 	{ DA7210_A_HID_UNLOCK, 0x8B},
1190*4882a593Smuzhiyun 	{ DA7210_A_TEST_UNLOCK, 0xB4},
1191*4882a593Smuzhiyun 	{ DA7210_A_PLL1, 0x01},
1192*4882a593Smuzhiyun 	{ DA7210_A_CP_MODE, 0x7C},
1193*4882a593Smuzhiyun 	/* to re-lock */
1194*4882a593Smuzhiyun 	{ DA7210_A_HID_UNLOCK, 0x00},
1195*4882a593Smuzhiyun 	{ DA7210_A_TEST_UNLOCK, 0x00},
1196*4882a593Smuzhiyun };
1197*4882a593Smuzhiyun 
1198*4882a593Smuzhiyun static const struct regmap_config da7210_regmap_config_i2c = {
1199*4882a593Smuzhiyun 	.reg_bits = 8,
1200*4882a593Smuzhiyun 	.val_bits = 8,
1201*4882a593Smuzhiyun 
1202*4882a593Smuzhiyun 	.reg_defaults = da7210_reg_defaults,
1203*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(da7210_reg_defaults),
1204*4882a593Smuzhiyun 	.volatile_reg = da7210_volatile_register,
1205*4882a593Smuzhiyun 	.readable_reg = da7210_readable_register,
1206*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
1207*4882a593Smuzhiyun };
1208*4882a593Smuzhiyun 
da7210_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1209*4882a593Smuzhiyun static int da7210_i2c_probe(struct i2c_client *i2c,
1210*4882a593Smuzhiyun 			    const struct i2c_device_id *id)
1211*4882a593Smuzhiyun {
1212*4882a593Smuzhiyun 	struct da7210_priv *da7210;
1213*4882a593Smuzhiyun 	int ret;
1214*4882a593Smuzhiyun 
1215*4882a593Smuzhiyun 	da7210 = devm_kzalloc(&i2c->dev, sizeof(struct da7210_priv),
1216*4882a593Smuzhiyun 			      GFP_KERNEL);
1217*4882a593Smuzhiyun 	if (!da7210)
1218*4882a593Smuzhiyun 		return -ENOMEM;
1219*4882a593Smuzhiyun 
1220*4882a593Smuzhiyun 	i2c_set_clientdata(i2c, da7210);
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun 	da7210->regmap = devm_regmap_init_i2c(i2c, &da7210_regmap_config_i2c);
1223*4882a593Smuzhiyun 	if (IS_ERR(da7210->regmap)) {
1224*4882a593Smuzhiyun 		ret = PTR_ERR(da7210->regmap);
1225*4882a593Smuzhiyun 		dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1226*4882a593Smuzhiyun 		return ret;
1227*4882a593Smuzhiyun 	}
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun 	ret = regmap_register_patch(da7210->regmap, da7210_regmap_i2c_patch,
1230*4882a593Smuzhiyun 				    ARRAY_SIZE(da7210_regmap_i2c_patch));
1231*4882a593Smuzhiyun 	if (ret != 0)
1232*4882a593Smuzhiyun 		dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1233*4882a593Smuzhiyun 
1234*4882a593Smuzhiyun 	ret =  devm_snd_soc_register_component(&i2c->dev,
1235*4882a593Smuzhiyun 			&soc_component_dev_da7210, &da7210_dai, 1);
1236*4882a593Smuzhiyun 	if (ret < 0)
1237*4882a593Smuzhiyun 		dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
1238*4882a593Smuzhiyun 
1239*4882a593Smuzhiyun 	return ret;
1240*4882a593Smuzhiyun }
1241*4882a593Smuzhiyun 
1242*4882a593Smuzhiyun static const struct i2c_device_id da7210_i2c_id[] = {
1243*4882a593Smuzhiyun 	{ "da7210", 0 },
1244*4882a593Smuzhiyun 	{ }
1245*4882a593Smuzhiyun };
1246*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, da7210_i2c_id);
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun /* I2C codec control layer */
1249*4882a593Smuzhiyun static struct i2c_driver da7210_i2c_driver = {
1250*4882a593Smuzhiyun 	.driver = {
1251*4882a593Smuzhiyun 		.name = "da7210",
1252*4882a593Smuzhiyun 	},
1253*4882a593Smuzhiyun 	.probe		= da7210_i2c_probe,
1254*4882a593Smuzhiyun 	.id_table	= da7210_i2c_id,
1255*4882a593Smuzhiyun };
1256*4882a593Smuzhiyun #endif
1257*4882a593Smuzhiyun 
1258*4882a593Smuzhiyun #if defined(CONFIG_SPI_MASTER)
1259*4882a593Smuzhiyun 
1260*4882a593Smuzhiyun static const struct reg_sequence da7210_regmap_spi_patch[] = {
1261*4882a593Smuzhiyun 	/* Dummy read to give two pulses over nCS for SPI */
1262*4882a593Smuzhiyun 	{ DA7210_AUX2, 0x00 },
1263*4882a593Smuzhiyun 	{ DA7210_AUX2, 0x00 },
1264*4882a593Smuzhiyun 
1265*4882a593Smuzhiyun 	/* System controller master disable */
1266*4882a593Smuzhiyun 	{ DA7210_STARTUP1, 0x00 },
1267*4882a593Smuzhiyun 	/* Set PLL Master clock range 10-20 MHz */
1268*4882a593Smuzhiyun 	{ DA7210_PLL_DIV3, DA7210_MCLK_RANGE_10_20_MHZ },
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun 	/* to set PAGE1 of SPI register space */
1271*4882a593Smuzhiyun 	{ DA7210_PAGE_CONTROL, 0x80 },
1272*4882a593Smuzhiyun 	/* to unlock */
1273*4882a593Smuzhiyun 	{ DA7210_A_HID_UNLOCK, 0x8B},
1274*4882a593Smuzhiyun 	{ DA7210_A_TEST_UNLOCK, 0xB4},
1275*4882a593Smuzhiyun 	{ DA7210_A_PLL1, 0x01},
1276*4882a593Smuzhiyun 	{ DA7210_A_CP_MODE, 0x7C},
1277*4882a593Smuzhiyun 	/* to re-lock */
1278*4882a593Smuzhiyun 	{ DA7210_A_HID_UNLOCK, 0x00},
1279*4882a593Smuzhiyun 	{ DA7210_A_TEST_UNLOCK, 0x00},
1280*4882a593Smuzhiyun 	/* to set back PAGE0 of SPI register space */
1281*4882a593Smuzhiyun 	{ DA7210_PAGE_CONTROL, 0x00 },
1282*4882a593Smuzhiyun };
1283*4882a593Smuzhiyun 
1284*4882a593Smuzhiyun static const struct regmap_config da7210_regmap_config_spi = {
1285*4882a593Smuzhiyun 	.reg_bits = 8,
1286*4882a593Smuzhiyun 	.val_bits = 8,
1287*4882a593Smuzhiyun 	.read_flag_mask = 0x01,
1288*4882a593Smuzhiyun 	.write_flag_mask = 0x00,
1289*4882a593Smuzhiyun 
1290*4882a593Smuzhiyun 	.reg_defaults = da7210_reg_defaults,
1291*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(da7210_reg_defaults),
1292*4882a593Smuzhiyun 	.volatile_reg = da7210_volatile_register,
1293*4882a593Smuzhiyun 	.readable_reg = da7210_readable_register,
1294*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
1295*4882a593Smuzhiyun };
1296*4882a593Smuzhiyun 
da7210_spi_probe(struct spi_device * spi)1297*4882a593Smuzhiyun static int da7210_spi_probe(struct spi_device *spi)
1298*4882a593Smuzhiyun {
1299*4882a593Smuzhiyun 	struct da7210_priv *da7210;
1300*4882a593Smuzhiyun 	int ret;
1301*4882a593Smuzhiyun 
1302*4882a593Smuzhiyun 	da7210 = devm_kzalloc(&spi->dev, sizeof(struct da7210_priv),
1303*4882a593Smuzhiyun 			      GFP_KERNEL);
1304*4882a593Smuzhiyun 	if (!da7210)
1305*4882a593Smuzhiyun 		return -ENOMEM;
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun 	spi_set_drvdata(spi, da7210);
1308*4882a593Smuzhiyun 	da7210->regmap = devm_regmap_init_spi(spi, &da7210_regmap_config_spi);
1309*4882a593Smuzhiyun 	if (IS_ERR(da7210->regmap)) {
1310*4882a593Smuzhiyun 		ret = PTR_ERR(da7210->regmap);
1311*4882a593Smuzhiyun 		dev_err(&spi->dev, "Failed to register regmap: %d\n", ret);
1312*4882a593Smuzhiyun 		return ret;
1313*4882a593Smuzhiyun 	}
1314*4882a593Smuzhiyun 
1315*4882a593Smuzhiyun 	ret = regmap_register_patch(da7210->regmap, da7210_regmap_spi_patch,
1316*4882a593Smuzhiyun 				    ARRAY_SIZE(da7210_regmap_spi_patch));
1317*4882a593Smuzhiyun 	if (ret != 0)
1318*4882a593Smuzhiyun 		dev_warn(&spi->dev, "Failed to apply regmap patch: %d\n", ret);
1319*4882a593Smuzhiyun 
1320*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(&spi->dev,
1321*4882a593Smuzhiyun 			&soc_component_dev_da7210, &da7210_dai, 1);
1322*4882a593Smuzhiyun 
1323*4882a593Smuzhiyun 	return ret;
1324*4882a593Smuzhiyun }
1325*4882a593Smuzhiyun 
1326*4882a593Smuzhiyun static struct spi_driver da7210_spi_driver = {
1327*4882a593Smuzhiyun 	.driver = {
1328*4882a593Smuzhiyun 		.name = "da7210",
1329*4882a593Smuzhiyun 	},
1330*4882a593Smuzhiyun 	.probe = da7210_spi_probe,
1331*4882a593Smuzhiyun };
1332*4882a593Smuzhiyun #endif
1333*4882a593Smuzhiyun 
da7210_modinit(void)1334*4882a593Smuzhiyun static int __init da7210_modinit(void)
1335*4882a593Smuzhiyun {
1336*4882a593Smuzhiyun 	int ret = 0;
1337*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
1338*4882a593Smuzhiyun 	ret = i2c_add_driver(&da7210_i2c_driver);
1339*4882a593Smuzhiyun 	if (ret)
1340*4882a593Smuzhiyun 		return ret;
1341*4882a593Smuzhiyun #endif
1342*4882a593Smuzhiyun #if defined(CONFIG_SPI_MASTER)
1343*4882a593Smuzhiyun 	ret = spi_register_driver(&da7210_spi_driver);
1344*4882a593Smuzhiyun 	if (ret) {
1345*4882a593Smuzhiyun 		printk(KERN_ERR "Failed to register da7210 SPI driver: %d\n",
1346*4882a593Smuzhiyun 		       ret);
1347*4882a593Smuzhiyun 	}
1348*4882a593Smuzhiyun #endif
1349*4882a593Smuzhiyun 	return ret;
1350*4882a593Smuzhiyun }
1351*4882a593Smuzhiyun module_init(da7210_modinit);
1352*4882a593Smuzhiyun 
da7210_exit(void)1353*4882a593Smuzhiyun static void __exit da7210_exit(void)
1354*4882a593Smuzhiyun {
1355*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
1356*4882a593Smuzhiyun 	i2c_del_driver(&da7210_i2c_driver);
1357*4882a593Smuzhiyun #endif
1358*4882a593Smuzhiyun #if defined(CONFIG_SPI_MASTER)
1359*4882a593Smuzhiyun 	spi_unregister_driver(&da7210_spi_driver);
1360*4882a593Smuzhiyun #endif
1361*4882a593Smuzhiyun }
1362*4882a593Smuzhiyun module_exit(da7210_exit);
1363*4882a593Smuzhiyun 
1364*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC DA7210 driver");
1365*4882a593Smuzhiyun MODULE_AUTHOR("David Chen, Kuninori Morimoto");
1366*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1367