1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ALSA SoC CS53L30 codec driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2015 Cirrus Logic, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Paul Handrigan <Paul.Handrigan@cirrus.com>, 8*4882a593Smuzhiyun * Tim Howe <Tim.Howe@cirrus.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __CS53L30_H__ 12*4882a593Smuzhiyun #define __CS53L30_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* I2C Registers */ 15*4882a593Smuzhiyun #define CS53L30_DEVID_AB 0x01 /* Device ID A & B [RO]. */ 16*4882a593Smuzhiyun #define CS53L30_DEVID_CD 0x02 /* Device ID C & D [RO]. */ 17*4882a593Smuzhiyun #define CS53L30_DEVID_E 0x03 /* Device ID E [RO]. */ 18*4882a593Smuzhiyun #define CS53L30_REVID 0x05 /* Revision ID [RO]. */ 19*4882a593Smuzhiyun #define CS53L30_PWRCTL 0x06 /* Power Control. */ 20*4882a593Smuzhiyun #define CS53L30_MCLKCTL 0x07 /* MCLK Control. */ 21*4882a593Smuzhiyun #define CS53L30_INT_SR_CTL 0x08 /* Internal Sample Rate Control. */ 22*4882a593Smuzhiyun #define CS53L30_MICBIAS_CTL 0x0A /* Mic Bias Control. */ 23*4882a593Smuzhiyun #define CS53L30_ASPCFG_CTL 0x0C /* ASP Config Control. */ 24*4882a593Smuzhiyun #define CS53L30_ASP_CTL1 0x0D /* ASP1 Control. */ 25*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_CTL1 0x0E /* ASP1 TDM TX Control 1 */ 26*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_CTL2 0x0F /* ASP1 TDM TX Control 2 */ 27*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_CTL3 0x10 /* ASP1 TDM TX Control 3 */ 28*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_CTL4 0x11 /* ASP1 TDM TX Control 4 */ 29*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_EN1 0x12 /* ASP1 TDM TX Enable 1 */ 30*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_EN2 0x13 /* ASP1 TDM TX Enable 2 */ 31*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_EN3 0x14 /* ASP1 TDM TX Enable 3 */ 32*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_EN4 0x15 /* ASP1 TDM TX Enable 4 */ 33*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_EN5 0x16 /* ASP1 TDM TX Enable 5 */ 34*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_EN6 0x17 /* ASP1 TDM TX Enable 6 */ 35*4882a593Smuzhiyun #define CS53L30_ASP_CTL2 0x18 /* ASP2 Control. */ 36*4882a593Smuzhiyun #define CS53L30_SFT_RAMP 0x1A /* Soft Ramp Control. */ 37*4882a593Smuzhiyun #define CS53L30_LRCK_CTL1 0x1B /* LRCK Control 1. */ 38*4882a593Smuzhiyun #define CS53L30_LRCK_CTL2 0x1C /* LRCK Control 2. */ 39*4882a593Smuzhiyun #define CS53L30_MUTEP_CTL1 0x1F /* Mute Pin Control 1. */ 40*4882a593Smuzhiyun #define CS53L30_MUTEP_CTL2 0x20 /* Mute Pin Control 2. */ 41*4882a593Smuzhiyun #define CS53L30_INBIAS_CTL1 0x21 /* Input Bias Control 1. */ 42*4882a593Smuzhiyun #define CS53L30_INBIAS_CTL2 0x22 /* Input Bias Control 2. */ 43*4882a593Smuzhiyun #define CS53L30_DMIC1_STR_CTL 0x23 /* DMIC1 Stereo Control. */ 44*4882a593Smuzhiyun #define CS53L30_DMIC2_STR_CTL 0x24 /* DMIC2 Stereo Control. */ 45*4882a593Smuzhiyun #define CS53L30_ADCDMIC1_CTL1 0x25 /* ADC1/DMIC1 Control 1. */ 46*4882a593Smuzhiyun #define CS53L30_ADCDMIC1_CTL2 0x26 /* ADC1/DMIC1 Control 2. */ 47*4882a593Smuzhiyun #define CS53L30_ADC1_CTL3 0x27 /* ADC1 Control 3. */ 48*4882a593Smuzhiyun #define CS53L30_ADC1_NG_CTL 0x28 /* ADC1 Noise Gate Control. */ 49*4882a593Smuzhiyun #define CS53L30_ADC1A_AFE_CTL 0x29 /* ADC1A AFE Control. */ 50*4882a593Smuzhiyun #define CS53L30_ADC1B_AFE_CTL 0x2A /* ADC1B AFE Control. */ 51*4882a593Smuzhiyun #define CS53L30_ADC1A_DIG_VOL 0x2B /* ADC1A Digital Volume. */ 52*4882a593Smuzhiyun #define CS53L30_ADC1B_DIG_VOL 0x2C /* ADC1B Digital Volume. */ 53*4882a593Smuzhiyun #define CS53L30_ADCDMIC2_CTL1 0x2D /* ADC2/DMIC2 Control 1. */ 54*4882a593Smuzhiyun #define CS53L30_ADCDMIC2_CTL2 0x2E /* ADC2/DMIC2 Control 2. */ 55*4882a593Smuzhiyun #define CS53L30_ADC2_CTL3 0x2F /* ADC2 Control 3. */ 56*4882a593Smuzhiyun #define CS53L30_ADC2_NG_CTL 0x30 /* ADC2 Noise Gate Control. */ 57*4882a593Smuzhiyun #define CS53L30_ADC2A_AFE_CTL 0x31 /* ADC2A AFE Control. */ 58*4882a593Smuzhiyun #define CS53L30_ADC2B_AFE_CTL 0x32 /* ADC2B AFE Control. */ 59*4882a593Smuzhiyun #define CS53L30_ADC2A_DIG_VOL 0x33 /* ADC2A Digital Volume. */ 60*4882a593Smuzhiyun #define CS53L30_ADC2B_DIG_VOL 0x34 /* ADC2B Digital Volume. */ 61*4882a593Smuzhiyun #define CS53L30_INT_MASK 0x35 /* Interrupt Mask. */ 62*4882a593Smuzhiyun #define CS53L30_IS 0x36 /* Interrupt Status. */ 63*4882a593Smuzhiyun #define CS53L30_MAX_REGISTER 0x36 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define CS53L30_TDM_SLOT_MAX 4 66*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_CTL(x) (CS53L30_ASP_TDMTX_CTL1 + (x)) 67*4882a593Smuzhiyun /* x : index for registers; n : index for slot; 8 slots per register */ 68*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_ENx(x) (CS53L30_ASP_TDMTX_EN6 - (x)) 69*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_ENn(n) CS53L30_ASP_TDMTX_ENx((n) >> 3) 70*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_ENx_MAX 6 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Device ID */ 73*4882a593Smuzhiyun #define CS53L30_DEVID 0x53A30 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* PDN_DONE Poll Maximum 76*4882a593Smuzhiyun * If soft ramp is set it will take much longer to power down 77*4882a593Smuzhiyun * the system. 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun #define CS53L30_PDN_POLL_MAX 90 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* Bitfield Definitions */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* R6 (0x06) CS53L30_PWRCTL - Power Control */ 84*4882a593Smuzhiyun #define CS53L30_PDN_ULP_SHIFT 7 85*4882a593Smuzhiyun #define CS53L30_PDN_ULP_MASK (1 << CS53L30_PDN_ULP_SHIFT) 86*4882a593Smuzhiyun #define CS53L30_PDN_ULP (1 << CS53L30_PDN_ULP_SHIFT) 87*4882a593Smuzhiyun #define CS53L30_PDN_LP_SHIFT 6 88*4882a593Smuzhiyun #define CS53L30_PDN_LP_MASK (1 << CS53L30_PDN_LP_SHIFT) 89*4882a593Smuzhiyun #define CS53L30_PDN_LP (1 << CS53L30_PDN_LP_SHIFT) 90*4882a593Smuzhiyun #define CS53L30_DISCHARGE_FILT_SHIFT 5 91*4882a593Smuzhiyun #define CS53L30_DISCHARGE_FILT_MASK (1 << CS53L30_DISCHARGE_FILT_SHIFT) 92*4882a593Smuzhiyun #define CS53L30_DISCHARGE_FILT (1 << CS53L30_DISCHARGE_FILT_SHIFT) 93*4882a593Smuzhiyun #define CS53L30_THMS_PDN_SHIFT 4 94*4882a593Smuzhiyun #define CS53L30_THMS_PDN_MASK (1 << CS53L30_THMS_PDN_SHIFT) 95*4882a593Smuzhiyun #define CS53L30_THMS_PDN (1 << CS53L30_THMS_PDN_SHIFT) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define CS53L30_PWRCTL_DEFAULT (CS53L30_THMS_PDN) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* R7 (0x07) CS53L30_MCLKCTL - MCLK Control */ 100*4882a593Smuzhiyun #define CS53L30_MCLK_DIS_SHIFT 7 101*4882a593Smuzhiyun #define CS53L30_MCLK_DIS_MASK (1 << CS53L30_MCLK_DIS_SHIFT) 102*4882a593Smuzhiyun #define CS53L30_MCLK_DIS (1 << CS53L30_MCLK_DIS_SHIFT) 103*4882a593Smuzhiyun #define CS53L30_MCLK_INT_SCALE_SHIFT 6 104*4882a593Smuzhiyun #define CS53L30_MCLK_INT_SCALE_MASK (1 << CS53L30_MCLK_INT_SCALE_SHIFT) 105*4882a593Smuzhiyun #define CS53L30_MCLK_INT_SCALE (1 << CS53L30_MCLK_INT_SCALE_SHIFT) 106*4882a593Smuzhiyun #define CS53L30_DMIC_DRIVE_SHIFT 5 107*4882a593Smuzhiyun #define CS53L30_DMIC_DRIVE_MASK (1 << CS53L30_DMIC_DRIVE_SHIFT) 108*4882a593Smuzhiyun #define CS53L30_DMIC_DRIVE (1 << CS53L30_DMIC_DRIVE_SHIFT) 109*4882a593Smuzhiyun #define CS53L30_MCLK_DIV_SHIFT 2 110*4882a593Smuzhiyun #define CS53L30_MCLK_DIV_WIDTH 2 111*4882a593Smuzhiyun #define CS53L30_MCLK_DIV_MASK (((1 << CS53L30_MCLK_DIV_WIDTH) - 1) << CS53L30_MCLK_DIV_SHIFT) 112*4882a593Smuzhiyun #define CS53L30_MCLK_DIV_BY_1 (0x0 << CS53L30_MCLK_DIV_SHIFT) 113*4882a593Smuzhiyun #define CS53L30_MCLK_DIV_BY_2 (0x1 << CS53L30_MCLK_DIV_SHIFT) 114*4882a593Smuzhiyun #define CS53L30_MCLK_DIV_BY_3 (0x2 << CS53L30_MCLK_DIV_SHIFT) 115*4882a593Smuzhiyun #define CS53L30_SYNC_EN_SHIFT 1 116*4882a593Smuzhiyun #define CS53L30_SYNC_EN_MASK (1 << CS53L30_SYNC_EN_SHIFT) 117*4882a593Smuzhiyun #define CS53L30_SYNC_EN (1 << CS53L30_SYNC_EN_SHIFT) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define CS53L30_MCLKCTL_DEFAULT (CS53L30_MCLK_DIV_BY_2) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* R8 (0x08) CS53L30_INT_SR_CTL - Internal Sample Rate Control */ 122*4882a593Smuzhiyun #define CS53L30_INTRNL_FS_RATIO_SHIFT 4 123*4882a593Smuzhiyun #define CS53L30_INTRNL_FS_RATIO_MASK (1 << CS53L30_INTRNL_FS_RATIO_SHIFT) 124*4882a593Smuzhiyun #define CS53L30_INTRNL_FS_RATIO (1 << CS53L30_INTRNL_FS_RATIO_SHIFT) 125*4882a593Smuzhiyun #define CS53L30_MCLK_19MHZ_EN_SHIFT 0 126*4882a593Smuzhiyun #define CS53L30_MCLK_19MHZ_EN_MASK (1 << CS53L30_MCLK_19MHZ_EN_SHIFT) 127*4882a593Smuzhiyun #define CS53L30_MCLK_19MHZ_EN (1 << CS53L30_MCLK_19MHZ_EN_SHIFT) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* 0x6 << 1 is reserved bits */ 130*4882a593Smuzhiyun #define CS53L30_INT_SR_CTL_DEFAULT (CS53L30_INTRNL_FS_RATIO | 0x6 << 1) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* R10 (0x0A) CS53L30_MICBIAS_CTL - Mic Bias Control */ 133*4882a593Smuzhiyun #define CS53L30_MIC4_BIAS_PDN_SHIFT 7 134*4882a593Smuzhiyun #define CS53L30_MIC4_BIAS_PDN_MASK (1 << CS53L30_MIC4_BIAS_PDN_SHIFT) 135*4882a593Smuzhiyun #define CS53L30_MIC4_BIAS_PDN (1 << CS53L30_MIC4_BIAS_PDN_SHIFT) 136*4882a593Smuzhiyun #define CS53L30_MIC3_BIAS_PDN_SHIFT 6 137*4882a593Smuzhiyun #define CS53L30_MIC3_BIAS_PDN_MASK (1 << CS53L30_MIC3_BIAS_PDN_SHIFT) 138*4882a593Smuzhiyun #define CS53L30_MIC3_BIAS_PDN (1 << CS53L30_MIC3_BIAS_PDN_SHIFT) 139*4882a593Smuzhiyun #define CS53L30_MIC2_BIAS_PDN_SHIFT 5 140*4882a593Smuzhiyun #define CS53L30_MIC2_BIAS_PDN_MASK (1 << CS53L30_MIC2_BIAS_PDN_SHIFT) 141*4882a593Smuzhiyun #define CS53L30_MIC2_BIAS_PDN (1 << CS53L30_MIC2_BIAS_PDN_SHIFT) 142*4882a593Smuzhiyun #define CS53L30_MIC1_BIAS_PDN_SHIFT 4 143*4882a593Smuzhiyun #define CS53L30_MIC1_BIAS_PDN_MASK (1 << CS53L30_MIC1_BIAS_PDN_SHIFT) 144*4882a593Smuzhiyun #define CS53L30_MIC1_BIAS_PDN (1 << CS53L30_MIC1_BIAS_PDN_SHIFT) 145*4882a593Smuzhiyun #define CS53L30_MICx_BIAS_PDN (0xf << CS53L30_MIC1_BIAS_PDN_SHIFT) 146*4882a593Smuzhiyun #define CS53L30_VP_MIN_SHIFT 2 147*4882a593Smuzhiyun #define CS53L30_VP_MIN_MASK (1 << CS53L30_VP_MIN_SHIFT) 148*4882a593Smuzhiyun #define CS53L30_VP_MIN (1 << CS53L30_VP_MIN_SHIFT) 149*4882a593Smuzhiyun #define CS53L30_MIC_BIAS_CTRL_SHIFT 0 150*4882a593Smuzhiyun #define CS53L30_MIC_BIAS_CTRL_WIDTH 2 151*4882a593Smuzhiyun #define CS53L30_MIC_BIAS_CTRL_MASK (((1 << CS53L30_MIC_BIAS_CTRL_WIDTH) - 1) << CS53L30_MIC_BIAS_CTRL_SHIFT) 152*4882a593Smuzhiyun #define CS53L30_MIC_BIAS_CTRL_HIZ (0 << CS53L30_MIC_BIAS_CTRL_SHIFT) 153*4882a593Smuzhiyun #define CS53L30_MIC_BIAS_CTRL_1V8 (1 << CS53L30_MIC_BIAS_CTRL_SHIFT) 154*4882a593Smuzhiyun #define CS53L30_MIC_BIAS_CTRL_2V75 (2 << CS53L30_MIC_BIAS_CTRL_SHIFT) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define CS53L30_MICBIAS_CTL_DEFAULT (CS53L30_MICx_BIAS_PDN | CS53L30_VP_MIN) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* R12 (0x0C) CS53L30_ASPCFG_CTL - ASP Configuration Control */ 159*4882a593Smuzhiyun #define CS53L30_ASP_MS_SHIFT 7 160*4882a593Smuzhiyun #define CS53L30_ASP_MS_MASK (1 << CS53L30_ASP_MS_SHIFT) 161*4882a593Smuzhiyun #define CS53L30_ASP_MS (1 << CS53L30_ASP_MS_SHIFT) 162*4882a593Smuzhiyun #define CS53L30_ASP_SCLK_INV_SHIFT 4 163*4882a593Smuzhiyun #define CS53L30_ASP_SCLK_INV_MASK (1 << CS53L30_ASP_SCLK_INV_SHIFT) 164*4882a593Smuzhiyun #define CS53L30_ASP_SCLK_INV (1 << CS53L30_ASP_SCLK_INV_SHIFT) 165*4882a593Smuzhiyun #define CS53L30_ASP_RATE_SHIFT 0 166*4882a593Smuzhiyun #define CS53L30_ASP_RATE_WIDTH 4 167*4882a593Smuzhiyun #define CS53L30_ASP_RATE_MASK (((1 << CS53L30_ASP_RATE_WIDTH) - 1) << CS53L30_ASP_RATE_SHIFT) 168*4882a593Smuzhiyun #define CS53L30_ASP_RATE_48K (0xc << CS53L30_ASP_RATE_SHIFT) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define CS53L30_ASPCFG_CTL_DEFAULT (CS53L30_ASP_RATE_48K) 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* R13/R24 (0x0D/0x18) CS53L30_ASP_CTL1 & CS53L30_ASP_CTL2 - ASP Control 1~2 */ 173*4882a593Smuzhiyun #define CS53L30_ASP_TDM_PDN_SHIFT 7 174*4882a593Smuzhiyun #define CS53L30_ASP_TDM_PDN_MASK (1 << CS53L30_ASP_TDM_PDN_SHIFT) 175*4882a593Smuzhiyun #define CS53L30_ASP_TDM_PDN (1 << CS53L30_ASP_TDM_PDN_SHIFT) 176*4882a593Smuzhiyun #define CS53L30_ASP_SDOUTx_PDN_SHIFT 6 177*4882a593Smuzhiyun #define CS53L30_ASP_SDOUTx_PDN_MASK (1 << CS53L30_ASP_SDOUTx_PDN_SHIFT) 178*4882a593Smuzhiyun #define CS53L30_ASP_SDOUTx_PDN (1 << CS53L30_ASP_SDOUTx_PDN_SHIFT) 179*4882a593Smuzhiyun #define CS53L30_ASP_3ST_SHIFT 5 180*4882a593Smuzhiyun #define CS53L30_ASP_3ST_MASK (1 << CS53L30_ASP_3ST_SHIFT) 181*4882a593Smuzhiyun #define CS53L30_ASP_3ST (1 << CS53L30_ASP_3ST_SHIFT) 182*4882a593Smuzhiyun #define CS53L30_SHIFT_LEFT_SHIFT 4 183*4882a593Smuzhiyun #define CS53L30_SHIFT_LEFT_MASK (1 << CS53L30_SHIFT_LEFT_SHIFT) 184*4882a593Smuzhiyun #define CS53L30_SHIFT_LEFT (1 << CS53L30_SHIFT_LEFT_SHIFT) 185*4882a593Smuzhiyun #define CS53L30_ASP_SDOUTx_DRIVE_SHIFT 0 186*4882a593Smuzhiyun #define CS53L30_ASP_SDOUTx_DRIVE_MASK (1 << CS53L30_ASP_SDOUTx_DRIVE_SHIFT) 187*4882a593Smuzhiyun #define CS53L30_ASP_SDOUTx_DRIVE (1 << CS53L30_ASP_SDOUTx_DRIVE_SHIFT) 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #define CS53L30_ASP_CTL1_DEFAULT (CS53L30_ASP_TDM_PDN) 190*4882a593Smuzhiyun #define CS53L30_ASP_CTL2_DEFAULT (0) 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* R14 (0x0E) ~ R17 (0x11) CS53L30_ASP_TDMTX_CTLx - ASP TDM TX Control 1~4 */ 193*4882a593Smuzhiyun #define CS53L30_ASP_CHx_TX_STATE_SHIFT 7 194*4882a593Smuzhiyun #define CS53L30_ASP_CHx_TX_STATE_MASK (1 << CS53L30_ASP_CHx_TX_STATE_SHIFT) 195*4882a593Smuzhiyun #define CS53L30_ASP_CHx_TX_STATE (1 << CS53L30_ASP_CHx_TX_STATE_SHIFT) 196*4882a593Smuzhiyun #define CS53L30_ASP_CHx_TX_LOC_SHIFT 0 197*4882a593Smuzhiyun #define CS53L30_ASP_CHx_TX_LOC_WIDTH 6 198*4882a593Smuzhiyun #define CS53L30_ASP_CHx_TX_LOC_MASK (((1 << CS53L30_ASP_CHx_TX_LOC_WIDTH) - 1) << CS53L30_ASP_CHx_TX_LOC_SHIFT) 199*4882a593Smuzhiyun #define CS53L30_ASP_CHx_TX_LOC_MAX (47 << CS53L30_ASP_CHx_TX_LOC_SHIFT) 200*4882a593Smuzhiyun #define CS53L30_ASP_CHx_TX_LOC(x) ((x) << CS53L30_ASP_CHx_TX_LOC_SHIFT) 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_CTLx_DEFAULT (CS53L30_ASP_CHx_TX_LOC_MAX) 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun /* R18 (0x12) ~ R23 (0x17) CS53L30_ASP_TDMTX_ENx - ASP TDM TX Enable 1~6 */ 205*4882a593Smuzhiyun #define CS53L30_ASP_TDMTX_ENx_DEFAULT (0) 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* R26 (0x1A) CS53L30_SFT_RAMP - Soft Ramp Control */ 208*4882a593Smuzhiyun #define CS53L30_DIGSFT_SHIFT 5 209*4882a593Smuzhiyun #define CS53L30_DIGSFT_MASK (1 << CS53L30_DIGSFT_SHIFT) 210*4882a593Smuzhiyun #define CS53L30_DIGSFT (1 << CS53L30_DIGSFT_SHIFT) 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun #define CS53L30_SFT_RMP_DEFAULT (0) 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* R28 (0x1C) CS53L30_LRCK_CTL2 - LRCK Control 2 */ 215*4882a593Smuzhiyun #define CS53L30_LRCK_50_NPW_SHIFT 3 216*4882a593Smuzhiyun #define CS53L30_LRCK_50_NPW_MASK (1 << CS53L30_LRCK_50_NPW_SHIFT) 217*4882a593Smuzhiyun #define CS53L30_LRCK_50_NPW (1 << CS53L30_LRCK_50_NPW_SHIFT) 218*4882a593Smuzhiyun #define CS53L30_LRCK_TPWH_SHIFT 0 219*4882a593Smuzhiyun #define CS53L30_LRCK_TPWH_WIDTH 3 220*4882a593Smuzhiyun #define CS53L30_LRCK_TPWH_MASK (((1 << CS53L30_LRCK_TPWH_WIDTH) - 1) << CS53L30_LRCK_TPWH_SHIFT) 221*4882a593Smuzhiyun #define CS53L30_LRCK_TPWH(x) (((x) << CS53L30_LRCK_TPWH_SHIFT) & CS53L30_LRCK_TPWH_MASK) 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun #define CS53L30_LRCK_CTLx_DEFAULT (0) 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun /* R31 (0x1F) CS53L30_MUTEP_CTL1 - MUTE Pin Control 1 */ 226*4882a593Smuzhiyun #define CS53L30_MUTE_PDN_ULP_SHIFT 7 227*4882a593Smuzhiyun #define CS53L30_MUTE_PDN_ULP_MASK (1 << CS53L30_MUTE_PDN_ULP_SHIFT) 228*4882a593Smuzhiyun #define CS53L30_MUTE_PDN_ULP (1 << CS53L30_MUTE_PDN_ULP_SHIFT) 229*4882a593Smuzhiyun #define CS53L30_MUTE_PDN_LP_SHIFT 6 230*4882a593Smuzhiyun #define CS53L30_MUTE_PDN_LP_MASK (1 << CS53L30_MUTE_PDN_LP_SHIFT) 231*4882a593Smuzhiyun #define CS53L30_MUTE_PDN_LP (1 << CS53L30_MUTE_PDN_LP_SHIFT) 232*4882a593Smuzhiyun #define CS53L30_MUTE_M4B_PDN_SHIFT 4 233*4882a593Smuzhiyun #define CS53L30_MUTE_M4B_PDN_MASK (1 << CS53L30_MUTE_M4B_PDN_SHIFT) 234*4882a593Smuzhiyun #define CS53L30_MUTE_M4B_PDN (1 << CS53L30_MUTE_M4B_PDN_SHIFT) 235*4882a593Smuzhiyun #define CS53L30_MUTE_M3B_PDN_SHIFT 3 236*4882a593Smuzhiyun #define CS53L30_MUTE_M3B_PDN_MASK (1 << CS53L30_MUTE_M3B_PDN_SHIFT) 237*4882a593Smuzhiyun #define CS53L30_MUTE_M3B_PDN (1 << CS53L30_MUTE_M3B_PDN_SHIFT) 238*4882a593Smuzhiyun #define CS53L30_MUTE_M2B_PDN_SHIFT 2 239*4882a593Smuzhiyun #define CS53L30_MUTE_M2B_PDN_MASK (1 << CS53L30_MUTE_M2B_PDN_SHIFT) 240*4882a593Smuzhiyun #define CS53L30_MUTE_M2B_PDN (1 << CS53L30_MUTE_M2B_PDN_SHIFT) 241*4882a593Smuzhiyun #define CS53L30_MUTE_M1B_PDN_SHIFT 1 242*4882a593Smuzhiyun #define CS53L30_MUTE_M1B_PDN_MASK (1 << CS53L30_MUTE_M1B_PDN_SHIFT) 243*4882a593Smuzhiyun #define CS53L30_MUTE_M1B_PDN (1 << CS53L30_MUTE_M1B_PDN_SHIFT) 244*4882a593Smuzhiyun /* Note: be careful - x starts from 0 */ 245*4882a593Smuzhiyun #define CS53L30_MUTE_MxB_PDN_SHIFT(x) (CS53L30_MUTE_M1B_PDN_SHIFT + (x)) 246*4882a593Smuzhiyun #define CS53L30_MUTE_MxB_PDN_MASK(x) (1 << CS53L30_MUTE_MxB_PDN_SHIFT(x)) 247*4882a593Smuzhiyun #define CS53L30_MUTE_MxB_PDN(x) (1 << CS53L30_MUTE_MxB_PDN_SHIFT(x)) 248*4882a593Smuzhiyun #define CS53L30_MUTE_MB_ALL_PDN_SHIFT 0 249*4882a593Smuzhiyun #define CS53L30_MUTE_MB_ALL_PDN_MASK (1 << CS53L30_MUTE_MB_ALL_PDN_SHIFT) 250*4882a593Smuzhiyun #define CS53L30_MUTE_MB_ALL_PDN (1 << CS53L30_MUTE_MB_ALL_PDN_SHIFT) 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #define CS53L30_MUTEP_CTL1_MUTEALL (0xdf) 253*4882a593Smuzhiyun #define CS53L30_MUTEP_CTL1_DEFAULT (0) 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun /* R32 (0x20) CS53L30_MUTEP_CTL2 - MUTE Pin Control 2 */ 256*4882a593Smuzhiyun #define CS53L30_MUTE_PIN_POLARITY_SHIFT 7 257*4882a593Smuzhiyun #define CS53L30_MUTE_PIN_POLARITY_MASK (1 << CS53L30_MUTE_PIN_POLARITY_SHIFT) 258*4882a593Smuzhiyun #define CS53L30_MUTE_PIN_POLARITY (1 << CS53L30_MUTE_PIN_POLARITY_SHIFT) 259*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_TDM_PDN_SHIFT 6 260*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_TDM_PDN_MASK (1 << CS53L30_MUTE_ASP_TDM_PDN_SHIFT) 261*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_TDM_PDN (1 << CS53L30_MUTE_ASP_TDM_PDN_SHIFT) 262*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT 5 263*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_SDOUT2_PDN_MASK (1 << CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT) 264*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_SDOUT2_PDN (1 << CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT) 265*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT 4 266*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_SDOUT1_PDN_MASK (1 << CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT) 267*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_SDOUT1_PDN (1 << CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT) 268*4882a593Smuzhiyun /* Note: be careful - x starts from 0 */ 269*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x) ((x) + CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT) 270*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_SDOUTx_PDN_MASK(x) (1 << CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x)) 271*4882a593Smuzhiyun #define CS53L30_MUTE_ASP_SDOUTx_PDN (1 << CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x)) 272*4882a593Smuzhiyun #define CS53L30_MUTE_ADC2B_PDN_SHIFT 3 273*4882a593Smuzhiyun #define CS53L30_MUTE_ADC2B_PDN_MASK (1 << CS53L30_MUTE_ADC2B_PDN_SHIFT) 274*4882a593Smuzhiyun #define CS53L30_MUTE_ADC2B_PDN (1 << CS53L30_MUTE_ADC2B_PDN_SHIFT) 275*4882a593Smuzhiyun #define CS53L30_MUTE_ADC2A_PDN_SHIFT 2 276*4882a593Smuzhiyun #define CS53L30_MUTE_ADC2A_PDN_MASK (1 << CS53L30_MUTE_ADC2A_PDN_SHIFT) 277*4882a593Smuzhiyun #define CS53L30_MUTE_ADC2A_PDN (1 << CS53L30_MUTE_ADC2A_PDN_SHIFT) 278*4882a593Smuzhiyun #define CS53L30_MUTE_ADC1B_PDN_SHIFT 1 279*4882a593Smuzhiyun #define CS53L30_MUTE_ADC1B_PDN_MASK (1 << CS53L30_MUTE_ADC1B_PDN_SHIFT) 280*4882a593Smuzhiyun #define CS53L30_MUTE_ADC1B_PDN (1 << CS53L30_MUTE_ADC1B_PDN_SHIFT) 281*4882a593Smuzhiyun #define CS53L30_MUTE_ADC1A_PDN_SHIFT 0 282*4882a593Smuzhiyun #define CS53L30_MUTE_ADC1A_PDN_MASK (1 << CS53L30_MUTE_ADC1A_PDN_SHIFT) 283*4882a593Smuzhiyun #define CS53L30_MUTE_ADC1A_PDN (1 << CS53L30_MUTE_ADC1A_PDN_SHIFT) 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun #define CS53L30_MUTEP_CTL2_DEFAULT (CS53L30_MUTE_PIN_POLARITY) 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* R33 (0x21) CS53L30_INBIAS_CTL1 - Input Bias Control 1 */ 288*4882a593Smuzhiyun #define CS53L30_IN4M_BIAS_SHIFT 6 289*4882a593Smuzhiyun #define CS53L30_IN4M_BIAS_WIDTH 2 290*4882a593Smuzhiyun #define CS53L30_IN4M_BIAS_MASK (((1 << CS53L30_IN4M_BIAS_WIDTH) - 1) << CS53L30_IN4M_BIAS_SHIFT) 291*4882a593Smuzhiyun #define CS53L30_IN4M_BIAS_OPEN (0 << CS53L30_IN4M_BIAS_SHIFT) 292*4882a593Smuzhiyun #define CS53L30_IN4M_BIAS_PULL_DOWN (1 << CS53L30_IN4M_BIAS_SHIFT) 293*4882a593Smuzhiyun #define CS53L30_IN4M_BIAS_VCM (2 << CS53L30_IN4M_BIAS_SHIFT) 294*4882a593Smuzhiyun #define CS53L30_IN4P_BIAS_SHIFT 4 295*4882a593Smuzhiyun #define CS53L30_IN4P_BIAS_WIDTH 2 296*4882a593Smuzhiyun #define CS53L30_IN4P_BIAS_MASK (((1 << CS53L30_IN4P_BIAS_WIDTH) - 1) << CS53L30_IN4P_BIAS_SHIFT) 297*4882a593Smuzhiyun #define CS53L30_IN4P_BIAS_OPEN (0 << CS53L30_IN4P_BIAS_SHIFT) 298*4882a593Smuzhiyun #define CS53L30_IN4P_BIAS_PULL_DOWN (1 << CS53L30_IN4P_BIAS_SHIFT) 299*4882a593Smuzhiyun #define CS53L30_IN4P_BIAS_VCM (2 << CS53L30_IN4P_BIAS_SHIFT) 300*4882a593Smuzhiyun #define CS53L30_IN3M_BIAS_SHIFT 2 301*4882a593Smuzhiyun #define CS53L30_IN3M_BIAS_WIDTH 2 302*4882a593Smuzhiyun #define CS53L30_IN3M_BIAS_MASK (((1 << CS53L30_IN3M_BIAS_WIDTH) - 1) << CS53L30_IN4M_BIAS_SHIFT) 303*4882a593Smuzhiyun #define CS53L30_IN3M_BIAS_OPEN (0 << CS53L30_IN3M_BIAS_SHIFT) 304*4882a593Smuzhiyun #define CS53L30_IN3M_BIAS_PULL_DOWN (1 << CS53L30_IN3M_BIAS_SHIFT) 305*4882a593Smuzhiyun #define CS53L30_IN3M_BIAS_VCM (2 << CS53L30_IN3M_BIAS_SHIFT) 306*4882a593Smuzhiyun #define CS53L30_IN3P_BIAS_SHIFT 0 307*4882a593Smuzhiyun #define CS53L30_IN3P_BIAS_WIDTH 2 308*4882a593Smuzhiyun #define CS53L30_IN3P_BIAS_MASK (((1 << CS53L30_IN3P_BIAS_WIDTH) - 1) << CS53L30_IN3P_BIAS_SHIFT) 309*4882a593Smuzhiyun #define CS53L30_IN3P_BIAS_OPEN (0 << CS53L30_IN3P_BIAS_SHIFT) 310*4882a593Smuzhiyun #define CS53L30_IN3P_BIAS_PULL_DOWN (1 << CS53L30_IN3P_BIAS_SHIFT) 311*4882a593Smuzhiyun #define CS53L30_IN3P_BIAS_VCM (2 << CS53L30_IN3P_BIAS_SHIFT) 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun #define CS53L30_INBIAS_CTL1_DEFAULT (CS53L30_IN4M_BIAS_VCM | CS53L30_IN4P_BIAS_VCM |\ 314*4882a593Smuzhiyun CS53L30_IN3M_BIAS_VCM | CS53L30_IN3P_BIAS_VCM) 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* R34 (0x22) CS53L30_INBIAS_CTL2 - Input Bias Control 2 */ 317*4882a593Smuzhiyun #define CS53L30_IN2M_BIAS_SHIFT 6 318*4882a593Smuzhiyun #define CS53L30_IN2M_BIAS_WIDTH 2 319*4882a593Smuzhiyun #define CS53L30_IN2M_BIAS_MASK (((1 << CS53L30_IN2M_BIAS_WIDTH) - 1) << CS53L30_IN2M_BIAS_SHIFT) 320*4882a593Smuzhiyun #define CS53L30_IN2M_BIAS_OPEN (0 << CS53L30_IN2M_BIAS_SHIFT) 321*4882a593Smuzhiyun #define CS53L30_IN2M_BIAS_PULL_DOWN (1 << CS53L30_IN2M_BIAS_SHIFT) 322*4882a593Smuzhiyun #define CS53L30_IN2M_BIAS_VCM (2 << CS53L30_IN2M_BIAS_SHIFT) 323*4882a593Smuzhiyun #define CS53L30_IN2P_BIAS_SHIFT 4 324*4882a593Smuzhiyun #define CS53L30_IN2P_BIAS_WIDTH 2 325*4882a593Smuzhiyun #define CS53L30_IN2P_BIAS_MASK (((1 << CS53L30_IN2P_BIAS_WIDTH) - 1) << CS53L30_IN2P_BIAS_SHIFT) 326*4882a593Smuzhiyun #define CS53L30_IN2P_BIAS_OPEN (0 << CS53L30_IN2P_BIAS_SHIFT) 327*4882a593Smuzhiyun #define CS53L30_IN2P_BIAS_PULL_DOWN (1 << CS53L30_IN2P_BIAS_SHIFT) 328*4882a593Smuzhiyun #define CS53L30_IN2P_BIAS_VCM (2 << CS53L30_IN2P_BIAS_SHIFT) 329*4882a593Smuzhiyun #define CS53L30_IN1M_BIAS_SHIFT 2 330*4882a593Smuzhiyun #define CS53L30_IN1M_BIAS_WIDTH 2 331*4882a593Smuzhiyun #define CS53L30_IN1M_BIAS_MASK (((1 << CS53L30_IN1M_BIAS_WIDTH) - 1) << CS53L30_IN1M_BIAS_SHIFT) 332*4882a593Smuzhiyun #define CS53L30_IN1M_BIAS_OPEN (0 << CS53L30_IN1M_BIAS_SHIFT) 333*4882a593Smuzhiyun #define CS53L30_IN1M_BIAS_PULL_DOWN (1 << CS53L30_IN1M_BIAS_SHIFT) 334*4882a593Smuzhiyun #define CS53L30_IN1M_BIAS_VCM (2 << CS53L30_IN1M_BIAS_SHIFT) 335*4882a593Smuzhiyun #define CS53L30_IN1P_BIAS_SHIFT 0 336*4882a593Smuzhiyun #define CS53L30_IN1P_BIAS_WIDTH 2 337*4882a593Smuzhiyun #define CS53L30_IN1P_BIAS_MASK (((1 << CS53L30_IN1P_BIAS_WIDTH) - 1) << CS53L30_IN1P_BIAS_SHIFT) 338*4882a593Smuzhiyun #define CS53L30_IN1P_BIAS_OPEN (0 << CS53L30_IN1P_BIAS_SHIFT) 339*4882a593Smuzhiyun #define CS53L30_IN1P_BIAS_PULL_DOWN (1 << CS53L30_IN1P_BIAS_SHIFT) 340*4882a593Smuzhiyun #define CS53L30_IN1P_BIAS_VCM (2 << CS53L30_IN1P_BIAS_SHIFT) 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun #define CS53L30_INBIAS_CTL2_DEFAULT (CS53L30_IN2M_BIAS_VCM | CS53L30_IN2P_BIAS_VCM |\ 343*4882a593Smuzhiyun CS53L30_IN1M_BIAS_VCM | CS53L30_IN1P_BIAS_VCM) 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun /* R35 (0x23) & R36 (0x24) CS53L30_DMICx_STR_CTL - DMIC1 & DMIC2 Stereo Control */ 346*4882a593Smuzhiyun #define CS53L30_DMICx_STEREO_ENB_SHIFT 5 347*4882a593Smuzhiyun #define CS53L30_DMICx_STEREO_ENB_MASK (1 << CS53L30_DMICx_STEREO_ENB_SHIFT) 348*4882a593Smuzhiyun #define CS53L30_DMICx_STEREO_ENB (1 << CS53L30_DMICx_STEREO_ENB_SHIFT) 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun /* 0x88 and 0xCC are reserved bits */ 351*4882a593Smuzhiyun #define CS53L30_DMIC1_STR_CTL_DEFAULT (CS53L30_DMICx_STEREO_ENB | 0x88) 352*4882a593Smuzhiyun #define CS53L30_DMIC2_STR_CTL_DEFAULT (CS53L30_DMICx_STEREO_ENB | 0xCC) 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun /* R37/R45 (0x25/0x2D) CS53L30_ADCDMICx_CTL1 - ADC1/DMIC1 & ADC2/DMIC2 Control 1 */ 355*4882a593Smuzhiyun #define CS53L30_ADCxB_PDN_SHIFT 7 356*4882a593Smuzhiyun #define CS53L30_ADCxB_PDN_MASK (1 << CS53L30_ADCxB_PDN_SHIFT) 357*4882a593Smuzhiyun #define CS53L30_ADCxB_PDN (1 << CS53L30_ADCxB_PDN_SHIFT) 358*4882a593Smuzhiyun #define CS53L30_ADCxA_PDN_SHIFT 6 359*4882a593Smuzhiyun #define CS53L30_ADCxA_PDN_MASK (1 << CS53L30_ADCxA_PDN_SHIFT) 360*4882a593Smuzhiyun #define CS53L30_ADCxA_PDN (1 << CS53L30_ADCxA_PDN_SHIFT) 361*4882a593Smuzhiyun #define CS53L30_DMICx_PDN_SHIFT 2 362*4882a593Smuzhiyun #define CS53L30_DMICx_PDN_MASK (1 << CS53L30_DMICx_PDN_SHIFT) 363*4882a593Smuzhiyun #define CS53L30_DMICx_PDN (1 << CS53L30_DMICx_PDN_SHIFT) 364*4882a593Smuzhiyun #define CS53L30_DMICx_SCLK_DIV_SHIFT 1 365*4882a593Smuzhiyun #define CS53L30_DMICx_SCLK_DIV_MASK (1 << CS53L30_DMICx_SCLK_DIV_SHIFT) 366*4882a593Smuzhiyun #define CS53L30_DMICx_SCLK_DIV (1 << CS53L30_DMICx_SCLK_DIV_SHIFT) 367*4882a593Smuzhiyun #define CS53L30_CH_TYPE_SHIFT 0 368*4882a593Smuzhiyun #define CS53L30_CH_TYPE_MASK (1 << CS53L30_CH_TYPE_SHIFT) 369*4882a593Smuzhiyun #define CS53L30_CH_TYPE (1 << CS53L30_CH_TYPE_SHIFT) 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun #define CS53L30_ADCDMICx_PDN_MASK 0xFF 372*4882a593Smuzhiyun #define CS53L30_ADCDMICx_CTL1_DEFAULT (CS53L30_DMICx_PDN) 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun /* R38/R46 (0x26/0x2E) CS53L30_ADCDMICx_CTL2 - ADC1/DMIC1 & ADC2/DMIC2 Control 2 */ 375*4882a593Smuzhiyun #define CS53L30_ADCx_NOTCH_DIS_SHIFT 7 376*4882a593Smuzhiyun #define CS53L30_ADCx_NOTCH_DIS_MASK (1 << CS53L30_ADCx_NOTCH_DIS_SHIFT) 377*4882a593Smuzhiyun #define CS53L30_ADCx_NOTCH_DIS (1 << CS53L30_ADCx_NOTCH_DIS_SHIFT) 378*4882a593Smuzhiyun #define CS53L30_ADCxB_INV_SHIFT 5 379*4882a593Smuzhiyun #define CS53L30_ADCxB_INV_MASK (1 << CS53L30_ADCxB_INV_SHIFT) 380*4882a593Smuzhiyun #define CS53L30_ADCxB_INV (1 << CS53L30_ADCxB_INV_SHIFT) 381*4882a593Smuzhiyun #define CS53L30_ADCxA_INV_SHIFT 4 382*4882a593Smuzhiyun #define CS53L30_ADCxA_INV_MASK (1 << CS53L30_ADCxA_INV_SHIFT) 383*4882a593Smuzhiyun #define CS53L30_ADCxA_INV (1 << CS53L30_ADCxA_INV_SHIFT) 384*4882a593Smuzhiyun #define CS53L30_ADCxB_DIG_BOOST_SHIFT 1 385*4882a593Smuzhiyun #define CS53L30_ADCxB_DIG_BOOST_MASK (1 << CS53L30_ADCxB_DIG_BOOST_SHIFT) 386*4882a593Smuzhiyun #define CS53L30_ADCxB_DIG_BOOST (1 << CS53L30_ADCxB_DIG_BOOST_SHIFT) 387*4882a593Smuzhiyun #define CS53L30_ADCxA_DIG_BOOST_SHIFT 0 388*4882a593Smuzhiyun #define CS53L30_ADCxA_DIG_BOOST_MASK (1 << CS53L30_ADCxA_DIG_BOOST_SHIFT) 389*4882a593Smuzhiyun #define CS53L30_ADCxA_DIG_BOOST (1 << CS53L30_ADCxA_DIG_BOOST_SHIFT) 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun #define CS53L30_ADCDMIC1_CTL2_DEFAULT (0) 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun /* R39/R47 (0x27/0x2F) CS53L30_ADCx_CTL3 - ADC1/ADC2 Control 3 */ 394*4882a593Smuzhiyun #define CS53L30_ADCx_HPF_EN_SHIFT 3 395*4882a593Smuzhiyun #define CS53L30_ADCx_HPF_EN_MASK (1 << CS53L30_ADCx_HPF_EN_SHIFT) 396*4882a593Smuzhiyun #define CS53L30_ADCx_HPF_EN (1 << CS53L30_ADCx_HPF_EN_SHIFT) 397*4882a593Smuzhiyun #define CS53L30_ADCx_HPF_CF_SHIFT 1 398*4882a593Smuzhiyun #define CS53L30_ADCx_HPF_CF_WIDTH 2 399*4882a593Smuzhiyun #define CS53L30_ADCx_HPF_CF_MASK (((1 << CS53L30_ADCx_HPF_CF_WIDTH) - 1) << CS53L30_ADCx_HPF_CF_SHIFT) 400*4882a593Smuzhiyun #define CS53L30_ADCx_HPF_CF_1HZ86 (0 << CS53L30_ADCx_HPF_CF_SHIFT) 401*4882a593Smuzhiyun #define CS53L30_ADCx_HPF_CF_120HZ (1 << CS53L30_ADCx_HPF_CF_SHIFT) 402*4882a593Smuzhiyun #define CS53L30_ADCx_HPF_CF_235HZ (2 << CS53L30_ADCx_HPF_CF_SHIFT) 403*4882a593Smuzhiyun #define CS53L30_ADCx_HPF_CF_466HZ (3 << CS53L30_ADCx_HPF_CF_SHIFT) 404*4882a593Smuzhiyun #define CS53L30_ADCx_NG_ALL_SHIFT 0 405*4882a593Smuzhiyun #define CS53L30_ADCx_NG_ALL_MASK (1 << CS53L30_ADCx_NG_ALL_SHIFT) 406*4882a593Smuzhiyun #define CS53L30_ADCx_NG_ALL (1 << CS53L30_ADCx_NG_ALL_SHIFT) 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun #define CS53L30_ADCx_CTL3_DEFAULT (CS53L30_ADCx_HPF_EN) 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun /* R40/R48 (0x28/0x30) CS53L30_ADCx_NG_CTL - ADC1/ADC2 Noise Gate Control */ 411*4882a593Smuzhiyun #define CS53L30_ADCxB_NG_SHIFT 7 412*4882a593Smuzhiyun #define CS53L30_ADCxB_NG_MASK (1 << CS53L30_ADCxB_NG_SHIFT) 413*4882a593Smuzhiyun #define CS53L30_ADCxB_NG (1 << CS53L30_ADCxB_NG_SHIFT) 414*4882a593Smuzhiyun #define CS53L30_ADCxA_NG_SHIFT 6 415*4882a593Smuzhiyun #define CS53L30_ADCxA_NG_MASK (1 << CS53L30_ADCxA_NG_SHIFT) 416*4882a593Smuzhiyun #define CS53L30_ADCxA_NG (1 << CS53L30_ADCxA_NG_SHIFT) 417*4882a593Smuzhiyun #define CS53L30_ADCx_NG_BOOST_SHIFT 5 418*4882a593Smuzhiyun #define CS53L30_ADCx_NG_BOOST_MASK (1 << CS53L30_ADCx_NG_BOOST_SHIFT) 419*4882a593Smuzhiyun #define CS53L30_ADCx_NG_BOOST (1 << CS53L30_ADCx_NG_BOOST_SHIFT) 420*4882a593Smuzhiyun #define CS53L30_ADCx_NG_THRESH_SHIFT 2 421*4882a593Smuzhiyun #define CS53L30_ADCx_NG_THRESH_WIDTH 3 422*4882a593Smuzhiyun #define CS53L30_ADCx_NG_THRESH_MASK (((1 << CS53L30_ADCx_NG_THRESH_WIDTH) - 1) << CS53L30_ADCx_NG_THRESH_SHIFT) 423*4882a593Smuzhiyun #define CS53L30_ADCx_NG_DELAY_SHIFT 0 424*4882a593Smuzhiyun #define CS53L30_ADCx_NG_DELAY_WIDTH 2 425*4882a593Smuzhiyun #define CS53L30_ADCx_NG_DELAY_MASK (((1 << CS53L30_ADCx_NG_DELAY_WIDTH) - 1) << CS53L30_ADCx_NG_DELAY_SHIFT) 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun #define CS53L30_ADCx_NG_CTL_DEFAULT (0) 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun /* R41/R42/R49/R50 (0x29/0x2A/0x31/0x32) CS53L30_ADCxy_AFE_CTL - ADC1A/1B/2A/2B AFE Control */ 430*4882a593Smuzhiyun #define CS53L30_ADCxy_PREAMP_SHIFT 6 431*4882a593Smuzhiyun #define CS53L30_ADCxy_PREAMP_WIDTH 2 432*4882a593Smuzhiyun #define CS53L30_ADCxy_PREAMP_MASK (((1 << CS53L30_ADCxy_PREAMP_WIDTH) - 1) << CS53L30_ADCxy_PREAMP_SHIFT) 433*4882a593Smuzhiyun #define CS53L30_ADCxy_PGA_VOL_SHIFT 0 434*4882a593Smuzhiyun #define CS53L30_ADCxy_PGA_VOL_WIDTH 6 435*4882a593Smuzhiyun #define CS53L30_ADCxy_PGA_VOL_MASK (((1 << CS53L30_ADCxy_PGA_VOL_WIDTH) - 1) << CS53L30_ADCxy_PGA_VOL_SHIFT) 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun #define CS53L30_ADCxy_AFE_CTL_DEFAULT (0) 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun /* R43/R44/R51/R52 (0x2B/0x2C/0x33/0x34) CS53L30_ADCxy_DIG_VOL - ADC1A/1B/2A/2B Digital Volume */ 440*4882a593Smuzhiyun #define CS53L30_ADCxy_VOL_MUTE (0x80) 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun #define CS53L30_ADCxy_DIG_VOL_DEFAULT (0x0) 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun /* CS53L30_INT */ 445*4882a593Smuzhiyun #define CS53L30_PDN_DONE (1 << 7) 446*4882a593Smuzhiyun #define CS53L30_THMS_TRIP (1 << 6) 447*4882a593Smuzhiyun #define CS53L30_SYNC_DONE (1 << 5) 448*4882a593Smuzhiyun #define CS53L30_ADC2B_OVFL (1 << 4) 449*4882a593Smuzhiyun #define CS53L30_ADC2A_OVFL (1 << 3) 450*4882a593Smuzhiyun #define CS53L30_ADC1B_OVFL (1 << 2) 451*4882a593Smuzhiyun #define CS53L30_ADC1A_OVFL (1 << 1) 452*4882a593Smuzhiyun #define CS53L30_MUTE_PIN (1 << 0) 453*4882a593Smuzhiyun #define CS53L30_DEVICE_INT_MASK 0xFF 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun #endif /* __CS53L30_H__ */ 456