1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // ALSA SoC Audio driver for CS47L92 codec
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2016-2019 Cirrus Logic, Inc. and
6*4882a593Smuzhiyun // Cirrus Logic International Semiconductor Ltd.
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/moduleparam.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/pm.h>
15*4882a593Smuzhiyun #include <linux/pm_runtime.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <sound/core.h>
18*4882a593Smuzhiyun #include <sound/pcm.h>
19*4882a593Smuzhiyun #include <sound/pcm_params.h>
20*4882a593Smuzhiyun #include <sound/soc.h>
21*4882a593Smuzhiyun #include <sound/tlv.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <linux/irqchip/irq-madera.h>
24*4882a593Smuzhiyun #include <linux/mfd/madera/core.h>
25*4882a593Smuzhiyun #include <linux/mfd/madera/registers.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "madera.h"
28*4882a593Smuzhiyun #include "wm_adsp.h"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define CS47L92_NUM_ADSP 1
31*4882a593Smuzhiyun #define CS47L92_MONO_OUTPUTS 3
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define DRV_NAME "cs47l92-codec"
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct cs47l92 {
36*4882a593Smuzhiyun struct madera_priv core;
37*4882a593Smuzhiyun struct madera_fll fll[2];
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static const struct wm_adsp_region cs47l92_dsp1_regions[] = {
41*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x080000 },
42*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static const char * const cs47l92_outdemux_texts[] = {
48*4882a593Smuzhiyun "HPOUT3",
49*4882a593Smuzhiyun "HPOUT4",
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
cs47l92_put_demux(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)52*4882a593Smuzhiyun static int cs47l92_put_demux(struct snd_kcontrol *kcontrol,
53*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct snd_soc_component *component =
56*4882a593Smuzhiyun snd_soc_dapm_kcontrol_component(kcontrol);
57*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm =
58*4882a593Smuzhiyun snd_soc_component_get_dapm(component);
59*4882a593Smuzhiyun struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
60*4882a593Smuzhiyun struct madera_priv *priv = &cs47l92->core;
61*4882a593Smuzhiyun struct madera *madera = priv->madera;
62*4882a593Smuzhiyun struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
63*4882a593Smuzhiyun unsigned int ep_sel, mux, change, cur;
64*4882a593Smuzhiyun bool out_mono;
65*4882a593Smuzhiyun int ret;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (ucontrol->value.enumerated.item[0] > e->items - 1)
68*4882a593Smuzhiyun return -EINVAL;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun mux = ucontrol->value.enumerated.item[0];
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun snd_soc_dapm_mutex_lock(dapm);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun ep_sel = mux << e->shift_l;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun change = snd_soc_component_test_bits(component, MADERA_OUTPUT_ENABLES_1,
77*4882a593Smuzhiyun MADERA_EP_SEL_MASK,
78*4882a593Smuzhiyun ep_sel);
79*4882a593Smuzhiyun if (!change)
80*4882a593Smuzhiyun goto end;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun ret = regmap_read(madera->regmap, MADERA_OUTPUT_ENABLES_1, &cur);
83*4882a593Smuzhiyun if (ret != 0)
84*4882a593Smuzhiyun dev_warn(madera->dev, "Failed to read outputs: %d\n", ret);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* EP_SEL should not be modified while HPOUT3 or 4 is enabled */
87*4882a593Smuzhiyun ret = regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
88*4882a593Smuzhiyun MADERA_OUT3L_ENA | MADERA_OUT3R_ENA, 0);
89*4882a593Smuzhiyun if (ret)
90*4882a593Smuzhiyun dev_warn(madera->dev, "Failed to disable outputs: %d\n", ret);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun usleep_range(2000, 3000); /* wait for wseq to complete */
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun ret = regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
95*4882a593Smuzhiyun MADERA_EP_SEL, ep_sel);
96*4882a593Smuzhiyun if (ret) {
97*4882a593Smuzhiyun dev_err(madera->dev, "Failed to set OUT3 demux: %d\n", ret);
98*4882a593Smuzhiyun } else {
99*4882a593Smuzhiyun out_mono = madera->pdata.codec.out_mono[2 + mux];
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun ret = madera_set_output_mode(component, 3, out_mono);
102*4882a593Smuzhiyun if (ret < 0)
103*4882a593Smuzhiyun dev_warn(madera->dev,
104*4882a593Smuzhiyun "Failed to set output mode: %d\n", ret);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun ret = regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
108*4882a593Smuzhiyun MADERA_OUT3L_ENA | MADERA_OUT3R_ENA, cur);
109*4882a593Smuzhiyun if (ret) {
110*4882a593Smuzhiyun dev_warn(madera->dev, "Failed to restore outputs: %d\n", ret);
111*4882a593Smuzhiyun } else {
112*4882a593Smuzhiyun /* wait for wseq */
113*4882a593Smuzhiyun if (cur & (MADERA_OUT3L_ENA | MADERA_OUT3R_ENA))
114*4882a593Smuzhiyun msleep(34); /* enable delay */
115*4882a593Smuzhiyun else
116*4882a593Smuzhiyun usleep_range(2000, 3000); /* disable delay */
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun end:
120*4882a593Smuzhiyun snd_soc_dapm_mutex_unlock(dapm);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(cs47l92_outdemux_enum,
126*4882a593Smuzhiyun MADERA_OUTPUT_ENABLES_1,
127*4882a593Smuzhiyun MADERA_EP_SEL_SHIFT,
128*4882a593Smuzhiyun cs47l92_outdemux_texts);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l92_outdemux =
131*4882a593Smuzhiyun SOC_DAPM_ENUM_EXT("OUT3 Demux", cs47l92_outdemux_enum,
132*4882a593Smuzhiyun snd_soc_dapm_get_enum_double, cs47l92_put_demux);
133*4882a593Smuzhiyun
cs47l92_adsp_power_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)134*4882a593Smuzhiyun static int cs47l92_adsp_power_ev(struct snd_soc_dapm_widget *w,
135*4882a593Smuzhiyun struct snd_kcontrol *kcontrol,
136*4882a593Smuzhiyun int event)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct snd_soc_component *component =
139*4882a593Smuzhiyun snd_soc_dapm_to_component(w->dapm);
140*4882a593Smuzhiyun struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
141*4882a593Smuzhiyun struct madera_priv *priv = &cs47l92->core;
142*4882a593Smuzhiyun struct madera *madera = priv->madera;
143*4882a593Smuzhiyun unsigned int freq;
144*4882a593Smuzhiyun int ret;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun ret = regmap_read(madera->regmap, MADERA_DSP_CLOCK_2, &freq);
147*4882a593Smuzhiyun if (ret != 0) {
148*4882a593Smuzhiyun dev_err(madera->dev,
149*4882a593Smuzhiyun "Failed to read MADERA_DSP_CLOCK_2: %d\n", ret);
150*4882a593Smuzhiyun return ret;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun switch (event) {
154*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
155*4882a593Smuzhiyun ret = madera_set_adsp_clk(&cs47l92->core, w->shift, freq);
156*4882a593Smuzhiyun if (ret)
157*4882a593Smuzhiyun return ret;
158*4882a593Smuzhiyun break;
159*4882a593Smuzhiyun default:
160*4882a593Smuzhiyun break;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun return wm_adsp_early_event(w, kcontrol, event);
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
cs47l92_outclk_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)166*4882a593Smuzhiyun static int cs47l92_outclk_ev(struct snd_soc_dapm_widget *w,
167*4882a593Smuzhiyun struct snd_kcontrol *kcontrol,
168*4882a593Smuzhiyun int event)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun struct snd_soc_component *component =
171*4882a593Smuzhiyun snd_soc_dapm_to_component(w->dapm);
172*4882a593Smuzhiyun struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
173*4882a593Smuzhiyun struct madera_priv *priv = &cs47l92->core;
174*4882a593Smuzhiyun struct madera *madera = priv->madera;
175*4882a593Smuzhiyun unsigned int val;
176*4882a593Smuzhiyun int ret;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun ret = regmap_read(madera->regmap, MADERA_OUTPUT_RATE_1, &val);
179*4882a593Smuzhiyun if (ret) {
180*4882a593Smuzhiyun dev_err(madera->dev, "Failed to read OUTCLK source: %d\n", ret);
181*4882a593Smuzhiyun return ret;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun val &= MADERA_OUT_CLK_SRC_MASK;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun switch (val) {
187*4882a593Smuzhiyun case MADERA_OUTCLK_MCLK1:
188*4882a593Smuzhiyun case MADERA_OUTCLK_MCLK2:
189*4882a593Smuzhiyun case MADERA_OUTCLK_MCLK3:
190*4882a593Smuzhiyun val -= (MADERA_OUTCLK_MCLK1 - MADERA_MCLK1);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun switch (event) {
193*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
194*4882a593Smuzhiyun ret = clk_prepare_enable(madera->mclk[val].clk);
195*4882a593Smuzhiyun if (ret)
196*4882a593Smuzhiyun return ret;
197*4882a593Smuzhiyun break;
198*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
199*4882a593Smuzhiyun clk_disable_unprepare(madera->mclk[val].clk);
200*4882a593Smuzhiyun break;
201*4882a593Smuzhiyun default:
202*4882a593Smuzhiyun break;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun default:
205*4882a593Smuzhiyun break;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun return madera_domain_clk_ev(w, kcontrol, event);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun #define CS47L92_NG_SRC(name, base) \
212*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
213*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
214*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \
215*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \
216*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \
217*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \
218*4882a593Smuzhiyun SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
219*4882a593Smuzhiyun SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0)
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l92_snd_controls[] = {
222*4882a593Smuzhiyun SOC_ENUM("IN1 OSR", madera_in_dmic_osr[0]),
223*4882a593Smuzhiyun SOC_ENUM("IN2 OSR", madera_in_dmic_osr[1]),
224*4882a593Smuzhiyun SOC_ENUM("IN3 OSR", madera_in_dmic_osr[2]),
225*4882a593Smuzhiyun SOC_ENUM("IN4 OSR", madera_in_dmic_osr[3]),
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN1L Volume", MADERA_IN1L_CONTROL,
228*4882a593Smuzhiyun MADERA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
229*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN1R Volume", MADERA_IN1R_CONTROL,
230*4882a593Smuzhiyun MADERA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
231*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN2L Volume", MADERA_IN2L_CONTROL,
232*4882a593Smuzhiyun MADERA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
233*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN2R Volume", MADERA_IN2R_CONTROL,
234*4882a593Smuzhiyun MADERA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun SOC_ENUM("IN HPF Cutoff Frequency", madera_in_hpf_cut_enum),
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun SOC_SINGLE_EXT("IN1L LP Switch", MADERA_ADC_DIGITAL_VOLUME_1L,
239*4882a593Smuzhiyun MADERA_IN1L_LP_MODE_SHIFT, 1, 0,
240*4882a593Smuzhiyun snd_soc_get_volsw, madera_lp_mode_put),
241*4882a593Smuzhiyun SOC_SINGLE_EXT("IN1R LP Switch", MADERA_ADC_DIGITAL_VOLUME_1R,
242*4882a593Smuzhiyun MADERA_IN1L_LP_MODE_SHIFT, 1, 0,
243*4882a593Smuzhiyun snd_soc_get_volsw, madera_lp_mode_put),
244*4882a593Smuzhiyun SOC_SINGLE_EXT("IN2L LP Switch", MADERA_ADC_DIGITAL_VOLUME_2L,
245*4882a593Smuzhiyun MADERA_IN1L_LP_MODE_SHIFT, 1, 0,
246*4882a593Smuzhiyun snd_soc_get_volsw, madera_lp_mode_put),
247*4882a593Smuzhiyun SOC_SINGLE_EXT("IN2R LP Switch", MADERA_ADC_DIGITAL_VOLUME_2R,
248*4882a593Smuzhiyun MADERA_IN1L_LP_MODE_SHIFT, 1, 0,
249*4882a593Smuzhiyun snd_soc_get_volsw, madera_lp_mode_put),
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun SOC_SINGLE("IN1L HPF Switch", MADERA_IN1L_CONTROL,
252*4882a593Smuzhiyun MADERA_IN1L_HPF_SHIFT, 1, 0),
253*4882a593Smuzhiyun SOC_SINGLE("IN1R HPF Switch", MADERA_IN1R_CONTROL,
254*4882a593Smuzhiyun MADERA_IN1R_HPF_SHIFT, 1, 0),
255*4882a593Smuzhiyun SOC_SINGLE("IN2L HPF Switch", MADERA_IN2L_CONTROL,
256*4882a593Smuzhiyun MADERA_IN2L_HPF_SHIFT, 1, 0),
257*4882a593Smuzhiyun SOC_SINGLE("IN2R HPF Switch", MADERA_IN2R_CONTROL,
258*4882a593Smuzhiyun MADERA_IN2R_HPF_SHIFT, 1, 0),
259*4882a593Smuzhiyun SOC_SINGLE("IN3L HPF Switch", MADERA_IN3L_CONTROL,
260*4882a593Smuzhiyun MADERA_IN3L_HPF_SHIFT, 1, 0),
261*4882a593Smuzhiyun SOC_SINGLE("IN3R HPF Switch", MADERA_IN3R_CONTROL,
262*4882a593Smuzhiyun MADERA_IN3R_HPF_SHIFT, 1, 0),
263*4882a593Smuzhiyun SOC_SINGLE("IN4L HPF Switch", MADERA_IN4L_CONTROL,
264*4882a593Smuzhiyun MADERA_IN4L_HPF_SHIFT, 1, 0),
265*4882a593Smuzhiyun SOC_SINGLE("IN4R HPF Switch", MADERA_IN4R_CONTROL,
266*4882a593Smuzhiyun MADERA_IN4R_HPF_SHIFT, 1, 0),
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1L,
269*4882a593Smuzhiyun MADERA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
270*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1R,
271*4882a593Smuzhiyun MADERA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
272*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2L,
273*4882a593Smuzhiyun MADERA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
274*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2R,
275*4882a593Smuzhiyun MADERA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
276*4882a593Smuzhiyun SOC_SINGLE_TLV("IN3L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3L,
277*4882a593Smuzhiyun MADERA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
278*4882a593Smuzhiyun SOC_SINGLE_TLV("IN3R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3R,
279*4882a593Smuzhiyun MADERA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
280*4882a593Smuzhiyun SOC_SINGLE_TLV("IN4L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4L,
281*4882a593Smuzhiyun MADERA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
282*4882a593Smuzhiyun SOC_SINGLE_TLV("IN4R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4R,
283*4882a593Smuzhiyun MADERA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun SOC_ENUM("Input Ramp Up", madera_in_vi_ramp),
286*4882a593Smuzhiyun SOC_ENUM("Input Ramp Down", madera_in_vd_ramp),
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ1", MADERA_EQ1MIX_INPUT_1_SOURCE),
289*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ2", MADERA_EQ2MIX_INPUT_1_SOURCE),
290*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ3", MADERA_EQ3MIX_INPUT_1_SOURCE),
291*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ4", MADERA_EQ4MIX_INPUT_1_SOURCE),
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ1 Coefficients", MADERA_EQ1_2),
294*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B1 Volume", MADERA_EQ1_1, MADERA_EQ1_B1_GAIN_SHIFT,
295*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
296*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B2 Volume", MADERA_EQ1_1, MADERA_EQ1_B2_GAIN_SHIFT,
297*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
298*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B3 Volume", MADERA_EQ1_1, MADERA_EQ1_B3_GAIN_SHIFT,
299*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
300*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B4 Volume", MADERA_EQ1_2, MADERA_EQ1_B4_GAIN_SHIFT,
301*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
302*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B5 Volume", MADERA_EQ1_2, MADERA_EQ1_B5_GAIN_SHIFT,
303*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ2 Coefficients", MADERA_EQ2_2),
306*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B1 Volume", MADERA_EQ2_1, MADERA_EQ2_B1_GAIN_SHIFT,
307*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
308*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B2 Volume", MADERA_EQ2_1, MADERA_EQ2_B2_GAIN_SHIFT,
309*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
310*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B3 Volume", MADERA_EQ2_1, MADERA_EQ2_B3_GAIN_SHIFT,
311*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
312*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B4 Volume", MADERA_EQ2_2, MADERA_EQ2_B4_GAIN_SHIFT,
313*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
314*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B5 Volume", MADERA_EQ2_2, MADERA_EQ2_B5_GAIN_SHIFT,
315*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ3 Coefficients", MADERA_EQ3_2),
318*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B1 Volume", MADERA_EQ3_1, MADERA_EQ3_B1_GAIN_SHIFT,
319*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
320*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B2 Volume", MADERA_EQ3_1, MADERA_EQ3_B2_GAIN_SHIFT,
321*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
322*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B3 Volume", MADERA_EQ3_1, MADERA_EQ3_B3_GAIN_SHIFT,
323*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
324*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B4 Volume", MADERA_EQ3_2, MADERA_EQ3_B4_GAIN_SHIFT,
325*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
326*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B5 Volume", MADERA_EQ3_2, MADERA_EQ3_B5_GAIN_SHIFT,
327*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ4 Coefficients", MADERA_EQ4_2),
330*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B1 Volume", MADERA_EQ4_1, MADERA_EQ4_B1_GAIN_SHIFT,
331*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
332*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B2 Volume", MADERA_EQ4_1, MADERA_EQ4_B2_GAIN_SHIFT,
333*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
334*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B3 Volume", MADERA_EQ4_1, MADERA_EQ4_B3_GAIN_SHIFT,
335*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
336*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B4 Volume", MADERA_EQ4_2, MADERA_EQ4_B4_GAIN_SHIFT,
337*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
338*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B5 Volume", MADERA_EQ4_2, MADERA_EQ4_B5_GAIN_SHIFT,
339*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun SOC_SINGLE("DAC High Performance Mode Switch", MADERA_OUTPUT_RATE_1,
342*4882a593Smuzhiyun MADERA_CP_DAC_MODE_SHIFT, 1, 0),
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC1L", MADERA_DRC1LMIX_INPUT_1_SOURCE),
345*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC1R", MADERA_DRC1RMIX_INPUT_1_SOURCE),
346*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC2L", MADERA_DRC2LMIX_INPUT_1_SOURCE),
347*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC2R", MADERA_DRC2RMIX_INPUT_1_SOURCE),
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun SND_SOC_BYTES_MASK("DRC1", MADERA_DRC1_CTRL1, 5,
350*4882a593Smuzhiyun MADERA_DRC1R_ENA | MADERA_DRC1L_ENA),
351*4882a593Smuzhiyun SND_SOC_BYTES_MASK("DRC2", MADERA_DRC2_CTRL1, 5,
352*4882a593Smuzhiyun MADERA_DRC2R_ENA | MADERA_DRC2L_ENA),
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF1", MADERA_HPLP1MIX_INPUT_1_SOURCE),
355*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF2", MADERA_HPLP2MIX_INPUT_1_SOURCE),
356*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF3", MADERA_HPLP3MIX_INPUT_1_SOURCE),
357*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF4", MADERA_HPLP4MIX_INPUT_1_SOURCE),
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF1 Coefficients", MADERA_HPLPF1_2),
360*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF2 Coefficients", MADERA_HPLPF2_2),
361*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF3 Coefficients", MADERA_HPLPF3_2),
362*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF4 Coefficients", MADERA_HPLPF4_2),
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun SOC_ENUM("LHPF1 Mode", madera_lhpf1_mode),
365*4882a593Smuzhiyun SOC_ENUM("LHPF2 Mode", madera_lhpf2_mode),
366*4882a593Smuzhiyun SOC_ENUM("LHPF3 Mode", madera_lhpf3_mode),
367*4882a593Smuzhiyun SOC_ENUM("LHPF4 Mode", madera_lhpf4_mode),
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC1 FSL", madera_isrc_fsl[0]),
370*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC2 FSL", madera_isrc_fsl[1]),
371*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC1 FSH", madera_isrc_fsh[0]),
372*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC2 FSH", madera_isrc_fsh[1]),
373*4882a593Smuzhiyun MADERA_RATE_ENUM("ASRC1 Rate 1", madera_asrc1_bidir_rate[0]),
374*4882a593Smuzhiyun MADERA_RATE_ENUM("ASRC1 Rate 2", madera_asrc1_bidir_rate[1]),
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP1L", MADERA_DSP1LMIX_INPUT_1_SOURCE),
379*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP1R", MADERA_DSP1RMIX_INPUT_1_SOURCE),
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Generator Volume", MADERA_COMFORT_NOISE_GENERATOR,
382*4882a593Smuzhiyun MADERA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, madera_noise_tlv),
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT1L", MADERA_OUT1LMIX_INPUT_1_SOURCE),
385*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT1R", MADERA_OUT1RMIX_INPUT_1_SOURCE),
386*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT2L", MADERA_OUT2LMIX_INPUT_1_SOURCE),
387*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT2R", MADERA_OUT2RMIX_INPUT_1_SOURCE),
388*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT3L", MADERA_OUT3LMIX_INPUT_1_SOURCE),
389*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT3R", MADERA_OUT3RMIX_INPUT_1_SOURCE),
390*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT1L", MADERA_OUT5LMIX_INPUT_1_SOURCE),
391*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT1R", MADERA_OUT5RMIX_INPUT_1_SOURCE),
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun SOC_SINGLE("HPOUT1 SC Protect Switch", MADERA_HP1_SHORT_CIRCUIT_CTRL,
394*4882a593Smuzhiyun MADERA_HP1_SC_ENA_SHIFT, 1, 0),
395*4882a593Smuzhiyun SOC_SINGLE("HPOUT2 SC Protect Switch", MADERA_HP2_SHORT_CIRCUIT_CTRL,
396*4882a593Smuzhiyun MADERA_HP2_SC_ENA_SHIFT, 1, 0),
397*4882a593Smuzhiyun SOC_SINGLE("HPOUT3 SC Protect Switch", MADERA_HP3_SHORT_CIRCUIT_CTRL,
398*4882a593Smuzhiyun MADERA_HP3_SC_ENA_SHIFT, 1, 0),
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun SOC_SINGLE("SPKDAT1 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_5L,
401*4882a593Smuzhiyun MADERA_OUT5_OSR_SHIFT, 1, 0),
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_1L,
404*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_MUTE_SHIFT, 1, 1),
405*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT2 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_2L,
406*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_MUTE_SHIFT, 1, 1),
407*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT3 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_3L,
408*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_MUTE_SHIFT, 1, 1),
409*4882a593Smuzhiyun SOC_DOUBLE_R("SPKDAT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_5L,
410*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_MUTE_SHIFT, 1, 1),
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_1L,
413*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_VOL_SHIFT,
414*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
415*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_2L,
416*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_VOL_SHIFT,
417*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
418*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_3L,
419*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_VOL_SHIFT,
420*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
421*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_5L,
422*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_VOL_SHIFT,
423*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun SOC_DOUBLE("SPKDAT1 Switch", MADERA_PDM_SPK1_CTRL_1, MADERA_SPK1L_MUTE_SHIFT,
426*4882a593Smuzhiyun MADERA_SPK1R_MUTE_SHIFT, 1, 1),
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun SOC_ENUM("Output Ramp Up", madera_out_vi_ramp),
429*4882a593Smuzhiyun SOC_ENUM("Output Ramp Down", madera_out_vd_ramp),
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun SOC_SINGLE("Noise Gate Switch", MADERA_NOISE_GATE_CONTROL,
432*4882a593Smuzhiyun MADERA_NGATE_ENA_SHIFT, 1, 0),
433*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Gate Threshold Volume", MADERA_NOISE_GATE_CONTROL,
434*4882a593Smuzhiyun MADERA_NGATE_THR_SHIFT, 7, 1, madera_ng_tlv),
435*4882a593Smuzhiyun SOC_ENUM("Noise Gate Hold", madera_ng_hold),
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun SOC_ENUM_EXT("DFC1RX Width", madera_dfc_width[0],
438*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
439*4882a593Smuzhiyun SOC_ENUM_EXT("DFC1RX Type", madera_dfc_type[0],
440*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
441*4882a593Smuzhiyun SOC_ENUM_EXT("DFC1TX Width", madera_dfc_width[1],
442*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
443*4882a593Smuzhiyun SOC_ENUM_EXT("DFC1TX Type", madera_dfc_type[1],
444*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
445*4882a593Smuzhiyun SOC_ENUM_EXT("DFC2RX Width", madera_dfc_width[2],
446*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
447*4882a593Smuzhiyun SOC_ENUM_EXT("DFC2RX Type", madera_dfc_type[2],
448*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
449*4882a593Smuzhiyun SOC_ENUM_EXT("DFC2TX Width", madera_dfc_width[3],
450*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
451*4882a593Smuzhiyun SOC_ENUM_EXT("DFC2TX Type", madera_dfc_type[3],
452*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
453*4882a593Smuzhiyun SOC_ENUM_EXT("DFC3RX Width", madera_dfc_width[4],
454*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
455*4882a593Smuzhiyun SOC_ENUM_EXT("DFC3RX Type", madera_dfc_type[4],
456*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
457*4882a593Smuzhiyun SOC_ENUM_EXT("DFC3TX Width", madera_dfc_width[5],
458*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
459*4882a593Smuzhiyun SOC_ENUM_EXT("DFC3TX Type", madera_dfc_type[5],
460*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
461*4882a593Smuzhiyun SOC_ENUM_EXT("DFC4RX Width", madera_dfc_width[6],
462*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
463*4882a593Smuzhiyun SOC_ENUM_EXT("DFC4RX Type", madera_dfc_type[6],
464*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
465*4882a593Smuzhiyun SOC_ENUM_EXT("DFC4TX Width", madera_dfc_width[7],
466*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
467*4882a593Smuzhiyun SOC_ENUM_EXT("DFC4TX Type", madera_dfc_type[7],
468*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
469*4882a593Smuzhiyun SOC_ENUM_EXT("DFC5RX Width", madera_dfc_width[8],
470*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
471*4882a593Smuzhiyun SOC_ENUM_EXT("DFC5RX Type", madera_dfc_type[8],
472*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
473*4882a593Smuzhiyun SOC_ENUM_EXT("DFC5TX Width", madera_dfc_width[9],
474*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
475*4882a593Smuzhiyun SOC_ENUM_EXT("DFC5TX Type", madera_dfc_type[9],
476*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
477*4882a593Smuzhiyun SOC_ENUM_EXT("DFC6RX Width", madera_dfc_width[10],
478*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
479*4882a593Smuzhiyun SOC_ENUM_EXT("DFC6RX Type", madera_dfc_type[10],
480*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
481*4882a593Smuzhiyun SOC_ENUM_EXT("DFC6TX Width", madera_dfc_width[11],
482*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
483*4882a593Smuzhiyun SOC_ENUM_EXT("DFC6TX Type", madera_dfc_type[11],
484*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
485*4882a593Smuzhiyun SOC_ENUM_EXT("DFC7RX Width", madera_dfc_width[12],
486*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
487*4882a593Smuzhiyun SOC_ENUM_EXT("DFC7RX Type", madera_dfc_type[12],
488*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
489*4882a593Smuzhiyun SOC_ENUM_EXT("DFC7TX Width", madera_dfc_width[13],
490*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
491*4882a593Smuzhiyun SOC_ENUM_EXT("DFC7TX Type", madera_dfc_type[13],
492*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
493*4882a593Smuzhiyun SOC_ENUM_EXT("DFC8RX Width", madera_dfc_width[14],
494*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
495*4882a593Smuzhiyun SOC_ENUM_EXT("DFC8RX Type", madera_dfc_type[14],
496*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
497*4882a593Smuzhiyun SOC_ENUM_EXT("DFC8TX Width", madera_dfc_width[15],
498*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
499*4882a593Smuzhiyun SOC_ENUM_EXT("DFC8TX Type", madera_dfc_type[15],
500*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun CS47L92_NG_SRC("HPOUT1L", MADERA_NOISE_GATE_SELECT_1L),
503*4882a593Smuzhiyun CS47L92_NG_SRC("HPOUT1R", MADERA_NOISE_GATE_SELECT_1R),
504*4882a593Smuzhiyun CS47L92_NG_SRC("HPOUT2L", MADERA_NOISE_GATE_SELECT_2L),
505*4882a593Smuzhiyun CS47L92_NG_SRC("HPOUT2R", MADERA_NOISE_GATE_SELECT_2R),
506*4882a593Smuzhiyun CS47L92_NG_SRC("HPOUT3L", MADERA_NOISE_GATE_SELECT_3L),
507*4882a593Smuzhiyun CS47L92_NG_SRC("HPOUT3R", MADERA_NOISE_GATE_SELECT_3R),
508*4882a593Smuzhiyun CS47L92_NG_SRC("SPKDAT1L", MADERA_NOISE_GATE_SELECT_5L),
509*4882a593Smuzhiyun CS47L92_NG_SRC("SPKDAT1R", MADERA_NOISE_GATE_SELECT_5R),
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX1", MADERA_AIF1TX1MIX_INPUT_1_SOURCE),
512*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX2", MADERA_AIF1TX2MIX_INPUT_1_SOURCE),
513*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX3", MADERA_AIF1TX3MIX_INPUT_1_SOURCE),
514*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX4", MADERA_AIF1TX4MIX_INPUT_1_SOURCE),
515*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX5", MADERA_AIF1TX5MIX_INPUT_1_SOURCE),
516*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX6", MADERA_AIF1TX6MIX_INPUT_1_SOURCE),
517*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX7", MADERA_AIF1TX7MIX_INPUT_1_SOURCE),
518*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX8", MADERA_AIF1TX8MIX_INPUT_1_SOURCE),
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX1", MADERA_AIF2TX1MIX_INPUT_1_SOURCE),
521*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX2", MADERA_AIF2TX2MIX_INPUT_1_SOURCE),
522*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX3", MADERA_AIF2TX3MIX_INPUT_1_SOURCE),
523*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX4", MADERA_AIF2TX4MIX_INPUT_1_SOURCE),
524*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX5", MADERA_AIF2TX5MIX_INPUT_1_SOURCE),
525*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX6", MADERA_AIF2TX6MIX_INPUT_1_SOURCE),
526*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX7", MADERA_AIF2TX7MIX_INPUT_1_SOURCE),
527*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX8", MADERA_AIF2TX8MIX_INPUT_1_SOURCE),
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX1", MADERA_AIF3TX1MIX_INPUT_1_SOURCE),
530*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX2", MADERA_AIF3TX2MIX_INPUT_1_SOURCE),
531*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX3", MADERA_AIF3TX3MIX_INPUT_1_SOURCE),
532*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX4", MADERA_AIF3TX4MIX_INPUT_1_SOURCE),
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX1", MADERA_SLIMTX1MIX_INPUT_1_SOURCE),
535*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX2", MADERA_SLIMTX2MIX_INPUT_1_SOURCE),
536*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX3", MADERA_SLIMTX3MIX_INPUT_1_SOURCE),
537*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX4", MADERA_SLIMTX4MIX_INPUT_1_SOURCE),
538*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX5", MADERA_SLIMTX5MIX_INPUT_1_SOURCE),
539*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX6", MADERA_SLIMTX6MIX_INPUT_1_SOURCE),
540*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX7", MADERA_SLIMTX7MIX_INPUT_1_SOURCE),
541*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX8", MADERA_SLIMTX8MIX_INPUT_1_SOURCE),
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun MADERA_GAINMUX_CONTROLS("SPDIFTX1", MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE),
544*4882a593Smuzhiyun MADERA_GAINMUX_CONTROLS("SPDIFTX2", MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE),
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP1", 0),
547*4882a593Smuzhiyun };
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ1, MADERA_EQ1MIX_INPUT_1_SOURCE);
550*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ2, MADERA_EQ2MIX_INPUT_1_SOURCE);
551*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ3, MADERA_EQ3MIX_INPUT_1_SOURCE);
552*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ4, MADERA_EQ4MIX_INPUT_1_SOURCE);
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC1L, MADERA_DRC1LMIX_INPUT_1_SOURCE);
555*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC1R, MADERA_DRC1RMIX_INPUT_1_SOURCE);
556*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC2L, MADERA_DRC2LMIX_INPUT_1_SOURCE);
557*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC2R, MADERA_DRC2RMIX_INPUT_1_SOURCE);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF1, MADERA_HPLP1MIX_INPUT_1_SOURCE);
560*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF2, MADERA_HPLP2MIX_INPUT_1_SOURCE);
561*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF3, MADERA_HPLP3MIX_INPUT_1_SOURCE);
562*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF4, MADERA_HPLP4MIX_INPUT_1_SOURCE);
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP1L, MADERA_DSP1LMIX_INPUT_1_SOURCE);
565*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP1R, MADERA_DSP1RMIX_INPUT_1_SOURCE);
566*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP1, MADERA_DSP1AUX1MIX_INPUT_1_SOURCE);
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun MADERA_MIXER_ENUMS(PWM1, MADERA_PWM1MIX_INPUT_1_SOURCE);
569*4882a593Smuzhiyun MADERA_MIXER_ENUMS(PWM2, MADERA_PWM2MIX_INPUT_1_SOURCE);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT1L, MADERA_OUT1LMIX_INPUT_1_SOURCE);
572*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT1R, MADERA_OUT1RMIX_INPUT_1_SOURCE);
573*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT2L, MADERA_OUT2LMIX_INPUT_1_SOURCE);
574*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT2R, MADERA_OUT2RMIX_INPUT_1_SOURCE);
575*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT3L, MADERA_OUT3LMIX_INPUT_1_SOURCE);
576*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT3R, MADERA_OUT3RMIX_INPUT_1_SOURCE);
577*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT1L, MADERA_OUT5LMIX_INPUT_1_SOURCE);
578*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT1R, MADERA_OUT5RMIX_INPUT_1_SOURCE);
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX1, MADERA_AIF1TX1MIX_INPUT_1_SOURCE);
581*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX2, MADERA_AIF1TX2MIX_INPUT_1_SOURCE);
582*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX3, MADERA_AIF1TX3MIX_INPUT_1_SOURCE);
583*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX4, MADERA_AIF1TX4MIX_INPUT_1_SOURCE);
584*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX5, MADERA_AIF1TX5MIX_INPUT_1_SOURCE);
585*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX6, MADERA_AIF1TX6MIX_INPUT_1_SOURCE);
586*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX7, MADERA_AIF1TX7MIX_INPUT_1_SOURCE);
587*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX8, MADERA_AIF1TX8MIX_INPUT_1_SOURCE);
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX1, MADERA_AIF2TX1MIX_INPUT_1_SOURCE);
590*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX2, MADERA_AIF2TX2MIX_INPUT_1_SOURCE);
591*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX3, MADERA_AIF2TX3MIX_INPUT_1_SOURCE);
592*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX4, MADERA_AIF2TX4MIX_INPUT_1_SOURCE);
593*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX5, MADERA_AIF2TX5MIX_INPUT_1_SOURCE);
594*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX6, MADERA_AIF2TX6MIX_INPUT_1_SOURCE);
595*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX7, MADERA_AIF2TX7MIX_INPUT_1_SOURCE);
596*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX8, MADERA_AIF2TX8MIX_INPUT_1_SOURCE);
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX1, MADERA_AIF3TX1MIX_INPUT_1_SOURCE);
599*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX2, MADERA_AIF3TX2MIX_INPUT_1_SOURCE);
600*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX3, MADERA_AIF3TX3MIX_INPUT_1_SOURCE);
601*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX4, MADERA_AIF3TX4MIX_INPUT_1_SOURCE);
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX1, MADERA_SLIMTX1MIX_INPUT_1_SOURCE);
604*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX2, MADERA_SLIMTX2MIX_INPUT_1_SOURCE);
605*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX3, MADERA_SLIMTX3MIX_INPUT_1_SOURCE);
606*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX4, MADERA_SLIMTX4MIX_INPUT_1_SOURCE);
607*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX5, MADERA_SLIMTX5MIX_INPUT_1_SOURCE);
608*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX6, MADERA_SLIMTX6MIX_INPUT_1_SOURCE);
609*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX7, MADERA_SLIMTX7MIX_INPUT_1_SOURCE);
610*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX8, MADERA_SLIMTX8MIX_INPUT_1_SOURCE);
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun MADERA_MUX_ENUMS(SPD1TX1, MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE);
613*4882a593Smuzhiyun MADERA_MUX_ENUMS(SPD1TX2, MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE);
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN1L, MADERA_ASRC1_1LMIX_INPUT_1_SOURCE);
616*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN1R, MADERA_ASRC1_1RMIX_INPUT_1_SOURCE);
617*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN2L, MADERA_ASRC1_2LMIX_INPUT_1_SOURCE);
618*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN2R, MADERA_ASRC1_2RMIX_INPUT_1_SOURCE);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT1, MADERA_ISRC1INT1MIX_INPUT_1_SOURCE);
621*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT2, MADERA_ISRC1INT2MIX_INPUT_1_SOURCE);
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC1, MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE);
624*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC2, MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE);
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT1, MADERA_ISRC2INT1MIX_INPUT_1_SOURCE);
627*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT2, MADERA_ISRC2INT2MIX_INPUT_1_SOURCE);
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC1, MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE);
630*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC2, MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE);
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC1, MADERA_DFC1MIX_INPUT_1_SOURCE);
633*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC2, MADERA_DFC2MIX_INPUT_1_SOURCE);
634*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC3, MADERA_DFC3MIX_INPUT_1_SOURCE);
635*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC4, MADERA_DFC4MIX_INPUT_1_SOURCE);
636*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC5, MADERA_DFC5MIX_INPUT_1_SOURCE);
637*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC6, MADERA_DFC6MIX_INPUT_1_SOURCE);
638*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC7, MADERA_DFC7MIX_INPUT_1_SOURCE);
639*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC8, MADERA_DFC8MIX_INPUT_1_SOURCE);
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun static const char * const cs47l92_aec_loopback_texts[] = {
642*4882a593Smuzhiyun "HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R",
643*4882a593Smuzhiyun "SPKDAT1L", "SPKDAT1R",
644*4882a593Smuzhiyun };
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun static const unsigned int cs47l92_aec_loopback_values[] = {
647*4882a593Smuzhiyun 0, 1, 2, 3, 4, 5, 8, 9
648*4882a593Smuzhiyun };
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun static const struct soc_enum cs47l92_aec_loopback =
651*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_1,
652*4882a593Smuzhiyun MADERA_AEC1_LOOPBACK_SRC_SHIFT, 0xf,
653*4882a593Smuzhiyun ARRAY_SIZE(cs47l92_aec_loopback_texts),
654*4882a593Smuzhiyun cs47l92_aec_loopback_texts,
655*4882a593Smuzhiyun cs47l92_aec_loopback_values);
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l92_aec_loopback_mux =
658*4882a593Smuzhiyun SOC_DAPM_ENUM("AEC1 Loopback", cs47l92_aec_loopback);
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun static const struct snd_soc_dapm_widget cs47l92_dapm_widgets[] = {
661*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SYSCLK", MADERA_SYSTEM_CLOCK_1, MADERA_SYSCLK_ENA_SHIFT,
662*4882a593Smuzhiyun 0, madera_sysclk_ev,
663*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
664*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
665*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASYNCCLK", MADERA_ASYNC_CLOCK_1,
666*4882a593Smuzhiyun MADERA_ASYNC_CLK_ENA_SHIFT, 0, madera_clk_ev,
667*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
668*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OPCLK", MADERA_OUTPUT_SYSTEM_CLOCK,
669*4882a593Smuzhiyun MADERA_OPCLK_ENA_SHIFT, 0, NULL, 0),
670*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", MADERA_OUTPUT_ASYNC_CLOCK,
671*4882a593Smuzhiyun MADERA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
672*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSPCLK", MADERA_DSP_CLOCK_1, MADERA_DSP_CLK_ENA_SHIFT,
673*4882a593Smuzhiyun 0, madera_clk_ev,
674*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD1", 20, 0),
677*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD2", 20, 0),
678*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1", MADERA_MIC_BIAS_CTRL_1,
681*4882a593Smuzhiyun MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
682*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2", MADERA_MIC_BIAS_CTRL_2,
683*4882a593Smuzhiyun MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1A", MADERA_MIC_BIAS_CTRL_5,
686*4882a593Smuzhiyun MADERA_MICB1A_ENA_SHIFT, 0, NULL, 0),
687*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1B", MADERA_MIC_BIAS_CTRL_5,
688*4882a593Smuzhiyun MADERA_MICB1B_ENA_SHIFT, 0, NULL, 0),
689*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1C", MADERA_MIC_BIAS_CTRL_5,
690*4882a593Smuzhiyun MADERA_MICB1C_ENA_SHIFT, 0, NULL, 0),
691*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1D", MADERA_MIC_BIAS_CTRL_5,
692*4882a593Smuzhiyun MADERA_MICB1D_ENA_SHIFT, 0, NULL, 0),
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2A", MADERA_MIC_BIAS_CTRL_6,
695*4882a593Smuzhiyun MADERA_MICB2A_ENA_SHIFT, 0, NULL, 0),
696*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2B", MADERA_MIC_BIAS_CTRL_6,
697*4882a593Smuzhiyun MADERA_MICB2B_ENA_SHIFT, 0, NULL, 0),
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("FXCLK", SND_SOC_NOPM,
700*4882a593Smuzhiyun MADERA_DOM_GRP_FX, 0,
701*4882a593Smuzhiyun madera_domain_clk_ev,
702*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
703*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASRC1CLK", SND_SOC_NOPM,
704*4882a593Smuzhiyun MADERA_DOM_GRP_ASRC1, 0,
705*4882a593Smuzhiyun madera_domain_clk_ev,
706*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
707*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC1CLK", SND_SOC_NOPM,
708*4882a593Smuzhiyun MADERA_DOM_GRP_ISRC1, 0,
709*4882a593Smuzhiyun madera_domain_clk_ev,
710*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
711*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC2CLK", SND_SOC_NOPM,
712*4882a593Smuzhiyun MADERA_DOM_GRP_ISRC2, 0,
713*4882a593Smuzhiyun madera_domain_clk_ev,
714*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
715*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OUTCLK", SND_SOC_NOPM,
716*4882a593Smuzhiyun MADERA_DOM_GRP_OUT, 0,
717*4882a593Smuzhiyun cs47l92_outclk_ev,
718*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
719*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SPDCLK", SND_SOC_NOPM,
720*4882a593Smuzhiyun MADERA_DOM_GRP_SPD, 0,
721*4882a593Smuzhiyun madera_domain_clk_ev,
722*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
723*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM,
724*4882a593Smuzhiyun MADERA_DOM_GRP_DSP1, 0,
725*4882a593Smuzhiyun madera_domain_clk_ev,
726*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
727*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF1TXCLK", SND_SOC_NOPM,
728*4882a593Smuzhiyun MADERA_DOM_GRP_AIF1, 0,
729*4882a593Smuzhiyun madera_domain_clk_ev,
730*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
731*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF2TXCLK", SND_SOC_NOPM,
732*4882a593Smuzhiyun MADERA_DOM_GRP_AIF2, 0,
733*4882a593Smuzhiyun madera_domain_clk_ev,
734*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
735*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF3TXCLK", SND_SOC_NOPM,
736*4882a593Smuzhiyun MADERA_DOM_GRP_AIF3, 0,
737*4882a593Smuzhiyun madera_domain_clk_ev,
738*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
739*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SLIMBUSCLK", SND_SOC_NOPM,
740*4882a593Smuzhiyun MADERA_DOM_GRP_SLIMBUS, 0,
741*4882a593Smuzhiyun madera_domain_clk_ev,
742*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
743*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("PWMCLK", SND_SOC_NOPM,
744*4882a593Smuzhiyun MADERA_DOM_GRP_PWM, 0,
745*4882a593Smuzhiyun madera_domain_clk_ev,
746*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
747*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DFCCLK", SND_SOC_NOPM,
748*4882a593Smuzhiyun MADERA_DOM_GRP_DFC, 0,
749*4882a593Smuzhiyun madera_domain_clk_ev,
750*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("TONE"),
753*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("NOISE"),
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ALN"),
756*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ALP"),
757*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BLN"),
758*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BLP"),
759*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ARN"),
760*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ARP"),
761*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BR"),
762*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2ALN"),
763*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2ALP"),
764*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2BL"),
765*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2ARN"),
766*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2ARP"),
767*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2BR"),
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[0]),
770*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[1]),
771*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[2]),
772*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[3]),
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
775*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
778*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun SND_SOC_DAPM_DEMUX("OUT3 Demux", SND_SOC_NOPM, 0, 0, &cs47l92_outdemux),
781*4882a593Smuzhiyun SND_SOC_DAPM_MUX("OUT3 Mono Mux", SND_SOC_NOPM, 0, 0, &cs47l92_outdemux),
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
784*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun SND_SOC_DAPM_PGA("PWM1 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM1_ENA_SHIFT,
787*4882a593Smuzhiyun 0, NULL, 0),
788*4882a593Smuzhiyun SND_SOC_DAPM_PGA("PWM2 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM2_ENA_SHIFT,
789*4882a593Smuzhiyun 0, NULL, 0),
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
792*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX1_ENA_SHIFT, 0),
793*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
794*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX2_ENA_SHIFT, 0),
795*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
796*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX3_ENA_SHIFT, 0),
797*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
798*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX4_ENA_SHIFT, 0),
799*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
800*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX5_ENA_SHIFT, 0),
801*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
802*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX6_ENA_SHIFT, 0),
803*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 6,
804*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX7_ENA_SHIFT, 0),
805*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 7,
806*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX8_ENA_SHIFT, 0),
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
809*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX1_ENA_SHIFT, 0),
810*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
811*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX2_ENA_SHIFT, 0),
812*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
813*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX3_ENA_SHIFT, 0),
814*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
815*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX4_ENA_SHIFT, 0),
816*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 4,
817*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX5_ENA_SHIFT, 0),
818*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 5,
819*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX6_ENA_SHIFT, 0),
820*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX7", NULL, 6,
821*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX7_ENA_SHIFT, 0),
822*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX8", NULL, 7,
823*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX8_ENA_SHIFT, 0),
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
826*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
827*4882a593Smuzhiyun MADERA_SLIMTX1_ENA_SHIFT, 0),
828*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
829*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
830*4882a593Smuzhiyun MADERA_SLIMTX2_ENA_SHIFT, 0),
831*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
832*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
833*4882a593Smuzhiyun MADERA_SLIMTX3_ENA_SHIFT, 0),
834*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
835*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
836*4882a593Smuzhiyun MADERA_SLIMTX4_ENA_SHIFT, 0),
837*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
838*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
839*4882a593Smuzhiyun MADERA_SLIMTX5_ENA_SHIFT, 0),
840*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
841*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
842*4882a593Smuzhiyun MADERA_SLIMTX6_ENA_SHIFT, 0),
843*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 6,
844*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
845*4882a593Smuzhiyun MADERA_SLIMTX7_ENA_SHIFT, 0),
846*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 7,
847*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
848*4882a593Smuzhiyun MADERA_SLIMTX8_ENA_SHIFT, 0),
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
851*4882a593Smuzhiyun MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX1_ENA_SHIFT, 0),
852*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
853*4882a593Smuzhiyun MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX2_ENA_SHIFT, 0),
854*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX3", NULL, 2,
855*4882a593Smuzhiyun MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX3_ENA_SHIFT, 0),
856*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX4", NULL, 3,
857*4882a593Smuzhiyun MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX4_ENA_SHIFT, 0),
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
860*4882a593Smuzhiyun MADERA_OUT1L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
861*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
862*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
863*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
864*4882a593Smuzhiyun MADERA_OUT1R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
865*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
866*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
867*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT2L", SND_SOC_NOPM,
868*4882a593Smuzhiyun MADERA_OUT2L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
869*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
870*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
871*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT2R", SND_SOC_NOPM,
872*4882a593Smuzhiyun MADERA_OUT2R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
873*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
874*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
875*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT3L", MADERA_OUTPUT_ENABLES_1,
876*4882a593Smuzhiyun MADERA_OUT3L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
877*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
878*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
879*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT3R", MADERA_OUTPUT_ENABLES_1,
880*4882a593Smuzhiyun MADERA_OUT3R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
881*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
882*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
883*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT5L", MADERA_OUTPUT_ENABLES_1,
884*4882a593Smuzhiyun MADERA_OUT5L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
885*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
886*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT5R", MADERA_OUTPUT_ENABLES_1,
887*4882a593Smuzhiyun MADERA_OUT5R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
888*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPD1TX1", MADERA_SPD1_TX_CONTROL,
891*4882a593Smuzhiyun MADERA_SPD1_VAL1_SHIFT, 0, NULL, 0),
892*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPD1TX2", MADERA_SPD1_TX_CONTROL,
893*4882a593Smuzhiyun MADERA_SPD1_VAL2_SHIFT, 0, NULL, 0),
894*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("SPD1", MADERA_SPD1_TX_CONTROL,
895*4882a593Smuzhiyun MADERA_SPD1_ENA_SHIFT, 0, NULL, 0),
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun /*
898*4882a593Smuzhiyun * mux_in widgets : arranged in the order of sources
899*4882a593Smuzhiyun * specified in MADERA_MIXER_INPUT_ROUTES
900*4882a593Smuzhiyun */
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Noise Generator", MADERA_COMFORT_NOISE_GENERATOR,
903*4882a593Smuzhiyun MADERA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator 1", MADERA_TONE_GENERATOR_1,
906*4882a593Smuzhiyun MADERA_TONE1_ENA_SHIFT, 0, NULL, 0),
907*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator 2", MADERA_TONE_GENERATOR_1,
908*4882a593Smuzhiyun MADERA_TONE2_ENA_SHIFT, 0, NULL, 0),
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("HAPTICS"),
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun SND_SOC_DAPM_MUX("AEC1 Loopback", MADERA_DAC_AEC_CONTROL_1,
913*4882a593Smuzhiyun MADERA_AEC1_LOOPBACK_ENA_SHIFT, 0,
914*4882a593Smuzhiyun &cs47l92_aec_loopback_mux),
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN1L", MADERA_INPUT_ENABLES, MADERA_IN1L_ENA_SHIFT,
917*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
918*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
919*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
920*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN1R", MADERA_INPUT_ENABLES, MADERA_IN1R_ENA_SHIFT,
921*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
922*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
923*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
924*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN2L", MADERA_INPUT_ENABLES, MADERA_IN2L_ENA_SHIFT,
925*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
926*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
927*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
928*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN2R", MADERA_INPUT_ENABLES, MADERA_IN2R_ENA_SHIFT,
929*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
930*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
931*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
932*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN3L", MADERA_INPUT_ENABLES, MADERA_IN3L_ENA_SHIFT,
933*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
934*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
935*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
936*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN3R", MADERA_INPUT_ENABLES, MADERA_IN3R_ENA_SHIFT,
937*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
938*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
939*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
940*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN4L", MADERA_INPUT_ENABLES, MADERA_IN4L_ENA_SHIFT,
941*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
942*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
943*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
944*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN4R", MADERA_INPUT_ENABLES, MADERA_IN4R_ENA_SHIFT,
945*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
946*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
947*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
950*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX1_ENA_SHIFT, 0),
951*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
952*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX2_ENA_SHIFT, 0),
953*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
954*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX3_ENA_SHIFT, 0),
955*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
956*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX4_ENA_SHIFT, 0),
957*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
958*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX5_ENA_SHIFT, 0),
959*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
960*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX6_ENA_SHIFT, 0),
961*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 6,
962*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX7_ENA_SHIFT, 0),
963*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 7,
964*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX8_ENA_SHIFT, 0),
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
967*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX1_ENA_SHIFT, 0),
968*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
969*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX2_ENA_SHIFT, 0),
970*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
971*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX3_ENA_SHIFT, 0),
972*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
973*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX4_ENA_SHIFT, 0),
974*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 4,
975*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX5_ENA_SHIFT, 0),
976*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 5,
977*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX6_ENA_SHIFT, 0),
978*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX7", NULL, 6,
979*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX7_ENA_SHIFT, 0),
980*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX8", NULL, 7,
981*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX8_ENA_SHIFT, 0),
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
984*4882a593Smuzhiyun MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX1_ENA_SHIFT, 0),
985*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
986*4882a593Smuzhiyun MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX2_ENA_SHIFT, 0),
987*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX3", NULL, 2,
988*4882a593Smuzhiyun MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX3_ENA_SHIFT, 0),
989*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX4", NULL, 3,
990*4882a593Smuzhiyun MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX4_ENA_SHIFT, 0),
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
993*4882a593Smuzhiyun MADERA_SLIMRX1_ENA_SHIFT, 0),
994*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
995*4882a593Smuzhiyun MADERA_SLIMRX2_ENA_SHIFT, 0),
996*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
997*4882a593Smuzhiyun MADERA_SLIMRX3_ENA_SHIFT, 0),
998*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
999*4882a593Smuzhiyun MADERA_SLIMRX4_ENA_SHIFT, 0),
1000*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1001*4882a593Smuzhiyun MADERA_SLIMRX5_ENA_SHIFT, 0),
1002*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1003*4882a593Smuzhiyun MADERA_SLIMRX6_ENA_SHIFT, 0),
1004*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 6, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1005*4882a593Smuzhiyun MADERA_SLIMRX7_ENA_SHIFT, 0),
1006*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 7, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1007*4882a593Smuzhiyun MADERA_SLIMRX8_ENA_SHIFT, 0),
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ1", MADERA_EQ1_1, MADERA_EQ1_ENA_SHIFT, 0, NULL, 0),
1010*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ2", MADERA_EQ2_1, MADERA_EQ2_ENA_SHIFT, 0, NULL, 0),
1011*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ3", MADERA_EQ3_1, MADERA_EQ3_ENA_SHIFT, 0, NULL, 0),
1012*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ4", MADERA_EQ4_1, MADERA_EQ4_ENA_SHIFT, 0, NULL, 0),
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC1L", MADERA_DRC1_CTRL1, MADERA_DRC1L_ENA_SHIFT, 0,
1015*4882a593Smuzhiyun NULL, 0),
1016*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC1R", MADERA_DRC1_CTRL1, MADERA_DRC1R_ENA_SHIFT, 0,
1017*4882a593Smuzhiyun NULL, 0),
1018*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC2L", MADERA_DRC2_CTRL1, MADERA_DRC2L_ENA_SHIFT, 0,
1019*4882a593Smuzhiyun NULL, 0),
1020*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC2R", MADERA_DRC2_CTRL1, MADERA_DRC2R_ENA_SHIFT, 0,
1021*4882a593Smuzhiyun NULL, 0),
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF1", MADERA_HPLPF1_1, MADERA_LHPF1_ENA_SHIFT, 0,
1024*4882a593Smuzhiyun NULL, 0),
1025*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF2", MADERA_HPLPF2_1, MADERA_LHPF2_ENA_SHIFT, 0,
1026*4882a593Smuzhiyun NULL, 0),
1027*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF3", MADERA_HPLPF3_1, MADERA_LHPF3_ENA_SHIFT, 0,
1028*4882a593Smuzhiyun NULL, 0),
1029*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF4", MADERA_HPLPF4_1, MADERA_LHPF4_ENA_SHIFT, 0,
1030*4882a593Smuzhiyun NULL, 0),
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN1L", MADERA_ASRC1_ENABLE,
1033*4882a593Smuzhiyun MADERA_ASRC1_IN1L_ENA_SHIFT, 0, NULL, 0),
1034*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN1R", MADERA_ASRC1_ENABLE,
1035*4882a593Smuzhiyun MADERA_ASRC1_IN1R_ENA_SHIFT, 0, NULL, 0),
1036*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN2L", MADERA_ASRC1_ENABLE,
1037*4882a593Smuzhiyun MADERA_ASRC1_IN2L_ENA_SHIFT, 0, NULL, 0),
1038*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN2R", MADERA_ASRC1_ENABLE,
1039*4882a593Smuzhiyun MADERA_ASRC1_IN2R_ENA_SHIFT, 0, NULL, 0),
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC1", MADERA_ISRC_1_CTRL_3,
1042*4882a593Smuzhiyun MADERA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
1043*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC2", MADERA_ISRC_1_CTRL_3,
1044*4882a593Smuzhiyun MADERA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT1", MADERA_ISRC_1_CTRL_3,
1047*4882a593Smuzhiyun MADERA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
1048*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT2", MADERA_ISRC_1_CTRL_3,
1049*4882a593Smuzhiyun MADERA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC1", MADERA_ISRC_2_CTRL_3,
1052*4882a593Smuzhiyun MADERA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
1053*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC2", MADERA_ISRC_2_CTRL_3,
1054*4882a593Smuzhiyun MADERA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT1", MADERA_ISRC_2_CTRL_3,
1057*4882a593Smuzhiyun MADERA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
1058*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT2", MADERA_ISRC_2_CTRL_3,
1059*4882a593Smuzhiyun MADERA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun WM_ADSP2("DSP1", 0, cs47l92_adsp_power_ev),
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun /* end of ordered widget list */
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC1", MADERA_DFC1_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1066*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC2", MADERA_DFC2_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1067*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC3", MADERA_DFC3_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1068*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC4", MADERA_DFC4_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1069*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC5", MADERA_DFC5_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1070*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC6", MADERA_DFC6_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1071*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC7", MADERA_DFC7_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1072*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC8", MADERA_DFC8_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ1, "EQ1"),
1075*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ2, "EQ2"),
1076*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ3, "EQ3"),
1077*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ4, "EQ4"),
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC1L, "DRC1L"),
1080*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC1R, "DRC1R"),
1081*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC2L, "DRC2L"),
1082*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC2R, "DRC2R"),
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0,
1085*4882a593Smuzhiyun &madera_drc_activity_output_mux[0]),
1086*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0,
1087*4882a593Smuzhiyun &madera_drc_activity_output_mux[1]),
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF1, "LHPF1"),
1090*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF2, "LHPF2"),
1091*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF3, "LHPF3"),
1092*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF4, "LHPF4"),
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(PWM1, "PWM1"),
1095*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(PWM2, "PWM2"),
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
1098*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
1099*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT2L, "HPOUT2L"),
1100*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT2R, "HPOUT2R"),
1101*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT3L, "HPOUT3L"),
1102*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT3R, "HPOUT3R"),
1103*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1104*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1107*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1108*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1109*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1110*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1111*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1112*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1113*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1116*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1117*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
1118*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
1119*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"),
1120*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"),
1121*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX7, "AIF2TX7"),
1122*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX8, "AIF2TX8"),
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1125*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1126*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX3, "AIF3TX3"),
1127*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX4, "AIF3TX4"),
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
1130*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
1131*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
1132*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
1133*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
1134*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
1135*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"),
1136*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"),
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun MADERA_MUX_WIDGETS(SPD1TX1, "SPDIFTX1"),
1139*4882a593Smuzhiyun MADERA_MUX_WIDGETS(SPD1TX2, "SPDIFTX2"),
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN1L, "ASRC1IN1L"),
1142*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN1R, "ASRC1IN1R"),
1143*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN2L, "ASRC1IN2L"),
1144*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN2R, "ASRC1IN2R"),
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP1, "DSP1"),
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
1149*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
1152*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
1155*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
1158*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
1159*4882a593Smuzhiyun
1160*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC1, "DFC1"),
1161*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC2, "DFC2"),
1162*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC3, "DFC3"),
1163*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC4, "DFC4"),
1164*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC5, "DFC5"),
1165*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC6, "DFC6"),
1166*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC7, "DFC7"),
1167*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC8, "DFC8"),
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1170*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1171*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1172*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1173*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1174*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1175*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT4L"),
1176*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT4R"),
1177*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
1178*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
1179*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPDIF1"),
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MICSUPP"),
1182*4882a593Smuzhiyun };
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun #define MADERA_MIXER_INPUT_ROUTES(name) \
1185*4882a593Smuzhiyun { name, "Noise Generator", "Noise Generator" }, \
1186*4882a593Smuzhiyun { name, "Tone Generator 1", "Tone Generator 1" }, \
1187*4882a593Smuzhiyun { name, "Tone Generator 2", "Tone Generator 2" }, \
1188*4882a593Smuzhiyun { name, "Haptics", "HAPTICS" }, \
1189*4882a593Smuzhiyun { name, "AEC1", "AEC1 Loopback" }, \
1190*4882a593Smuzhiyun { name, "IN1L", "IN1L" }, \
1191*4882a593Smuzhiyun { name, "IN1R", "IN1R" }, \
1192*4882a593Smuzhiyun { name, "IN2L", "IN2L" }, \
1193*4882a593Smuzhiyun { name, "IN2R", "IN2R" }, \
1194*4882a593Smuzhiyun { name, "IN3L", "IN3L" }, \
1195*4882a593Smuzhiyun { name, "IN3R", "IN3R" }, \
1196*4882a593Smuzhiyun { name, "IN4L", "IN4L" }, \
1197*4882a593Smuzhiyun { name, "IN4R", "IN4R" }, \
1198*4882a593Smuzhiyun { name, "AIF1RX1", "AIF1RX1" }, \
1199*4882a593Smuzhiyun { name, "AIF1RX2", "AIF1RX2" }, \
1200*4882a593Smuzhiyun { name, "AIF1RX3", "AIF1RX3" }, \
1201*4882a593Smuzhiyun { name, "AIF1RX4", "AIF1RX4" }, \
1202*4882a593Smuzhiyun { name, "AIF1RX5", "AIF1RX5" }, \
1203*4882a593Smuzhiyun { name, "AIF1RX6", "AIF1RX6" }, \
1204*4882a593Smuzhiyun { name, "AIF1RX7", "AIF1RX7" }, \
1205*4882a593Smuzhiyun { name, "AIF1RX8", "AIF1RX8" }, \
1206*4882a593Smuzhiyun { name, "AIF2RX1", "AIF2RX1" }, \
1207*4882a593Smuzhiyun { name, "AIF2RX2", "AIF2RX2" }, \
1208*4882a593Smuzhiyun { name, "AIF2RX3", "AIF2RX3" }, \
1209*4882a593Smuzhiyun { name, "AIF2RX4", "AIF2RX4" }, \
1210*4882a593Smuzhiyun { name, "AIF2RX5", "AIF2RX5" }, \
1211*4882a593Smuzhiyun { name, "AIF2RX6", "AIF2RX6" }, \
1212*4882a593Smuzhiyun { name, "AIF2RX7", "AIF2RX7" }, \
1213*4882a593Smuzhiyun { name, "AIF2RX8", "AIF2RX8" }, \
1214*4882a593Smuzhiyun { name, "AIF3RX1", "AIF3RX1" }, \
1215*4882a593Smuzhiyun { name, "AIF3RX2", "AIF3RX2" }, \
1216*4882a593Smuzhiyun { name, "AIF3RX3", "AIF3RX3" }, \
1217*4882a593Smuzhiyun { name, "AIF3RX4", "AIF3RX4" }, \
1218*4882a593Smuzhiyun { name, "SLIMRX1", "SLIMRX1" }, \
1219*4882a593Smuzhiyun { name, "SLIMRX2", "SLIMRX2" }, \
1220*4882a593Smuzhiyun { name, "SLIMRX3", "SLIMRX3" }, \
1221*4882a593Smuzhiyun { name, "SLIMRX4", "SLIMRX4" }, \
1222*4882a593Smuzhiyun { name, "SLIMRX5", "SLIMRX5" }, \
1223*4882a593Smuzhiyun { name, "SLIMRX6", "SLIMRX6" }, \
1224*4882a593Smuzhiyun { name, "SLIMRX7", "SLIMRX7" }, \
1225*4882a593Smuzhiyun { name, "SLIMRX8", "SLIMRX8" }, \
1226*4882a593Smuzhiyun { name, "EQ1", "EQ1" }, \
1227*4882a593Smuzhiyun { name, "EQ2", "EQ2" }, \
1228*4882a593Smuzhiyun { name, "EQ3", "EQ3" }, \
1229*4882a593Smuzhiyun { name, "EQ4", "EQ4" }, \
1230*4882a593Smuzhiyun { name, "DRC1L", "DRC1L" }, \
1231*4882a593Smuzhiyun { name, "DRC1R", "DRC1R" }, \
1232*4882a593Smuzhiyun { name, "DRC2L", "DRC2L" }, \
1233*4882a593Smuzhiyun { name, "DRC2R", "DRC2R" }, \
1234*4882a593Smuzhiyun { name, "LHPF1", "LHPF1" }, \
1235*4882a593Smuzhiyun { name, "LHPF2", "LHPF2" }, \
1236*4882a593Smuzhiyun { name, "LHPF3", "LHPF3" }, \
1237*4882a593Smuzhiyun { name, "LHPF4", "LHPF4" }, \
1238*4882a593Smuzhiyun { name, "ASRC1IN1L", "ASRC1IN1L" }, \
1239*4882a593Smuzhiyun { name, "ASRC1IN1R", "ASRC1IN1R" }, \
1240*4882a593Smuzhiyun { name, "ASRC1IN2L", "ASRC1IN2L" }, \
1241*4882a593Smuzhiyun { name, "ASRC1IN2R", "ASRC1IN2R" }, \
1242*4882a593Smuzhiyun { name, "ISRC1DEC1", "ISRC1DEC1" }, \
1243*4882a593Smuzhiyun { name, "ISRC1DEC2", "ISRC1DEC2" }, \
1244*4882a593Smuzhiyun { name, "ISRC1INT1", "ISRC1INT1" }, \
1245*4882a593Smuzhiyun { name, "ISRC1INT2", "ISRC1INT2" }, \
1246*4882a593Smuzhiyun { name, "ISRC2DEC1", "ISRC2DEC1" }, \
1247*4882a593Smuzhiyun { name, "ISRC2DEC2", "ISRC2DEC2" }, \
1248*4882a593Smuzhiyun { name, "ISRC2INT1", "ISRC2INT1" }, \
1249*4882a593Smuzhiyun { name, "ISRC2INT2", "ISRC2INT2" }, \
1250*4882a593Smuzhiyun { name, "DSP1.1", "DSP1" }, \
1251*4882a593Smuzhiyun { name, "DSP1.2", "DSP1" }, \
1252*4882a593Smuzhiyun { name, "DSP1.3", "DSP1" }, \
1253*4882a593Smuzhiyun { name, "DSP1.4", "DSP1" }, \
1254*4882a593Smuzhiyun { name, "DSP1.5", "DSP1" }, \
1255*4882a593Smuzhiyun { name, "DSP1.6", "DSP1" }, \
1256*4882a593Smuzhiyun { name, "DFC1", "DFC1" }, \
1257*4882a593Smuzhiyun { name, "DFC2", "DFC2" }, \
1258*4882a593Smuzhiyun { name, "DFC3", "DFC3" }, \
1259*4882a593Smuzhiyun { name, "DFC4", "DFC4" }, \
1260*4882a593Smuzhiyun { name, "DFC5", "DFC5" }, \
1261*4882a593Smuzhiyun { name, "DFC6", "DFC6" }, \
1262*4882a593Smuzhiyun { name, "DFC7", "DFC7" }, \
1263*4882a593Smuzhiyun { name, "DFC8", "DFC8" }
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun static const struct snd_soc_dapm_route cs47l92_dapm_routes[] = {
1266*4882a593Smuzhiyun /* Internal clock domains */
1267*4882a593Smuzhiyun { "EQ1", NULL, "FXCLK" },
1268*4882a593Smuzhiyun { "EQ2", NULL, "FXCLK" },
1269*4882a593Smuzhiyun { "EQ3", NULL, "FXCLK" },
1270*4882a593Smuzhiyun { "EQ4", NULL, "FXCLK" },
1271*4882a593Smuzhiyun { "DRC1L", NULL, "FXCLK" },
1272*4882a593Smuzhiyun { "DRC1R", NULL, "FXCLK" },
1273*4882a593Smuzhiyun { "DRC2L", NULL, "FXCLK" },
1274*4882a593Smuzhiyun { "DRC2R", NULL, "FXCLK" },
1275*4882a593Smuzhiyun { "LHPF1", NULL, "FXCLK" },
1276*4882a593Smuzhiyun { "LHPF2", NULL, "FXCLK" },
1277*4882a593Smuzhiyun { "LHPF3", NULL, "FXCLK" },
1278*4882a593Smuzhiyun { "LHPF4", NULL, "FXCLK" },
1279*4882a593Smuzhiyun { "PWM1 Mixer", NULL, "PWMCLK" },
1280*4882a593Smuzhiyun { "PWM2 Mixer", NULL, "PWMCLK" },
1281*4882a593Smuzhiyun { "OUT1L", NULL, "OUTCLK" },
1282*4882a593Smuzhiyun { "OUT1R", NULL, "OUTCLK" },
1283*4882a593Smuzhiyun { "OUT2L", NULL, "OUTCLK" },
1284*4882a593Smuzhiyun { "OUT2R", NULL, "OUTCLK" },
1285*4882a593Smuzhiyun { "OUT3L", NULL, "OUTCLK" },
1286*4882a593Smuzhiyun { "OUT3R", NULL, "OUTCLK" },
1287*4882a593Smuzhiyun { "OUT5L", NULL, "OUTCLK" },
1288*4882a593Smuzhiyun { "OUT5R", NULL, "OUTCLK" },
1289*4882a593Smuzhiyun { "AIF1TX1", NULL, "AIF1TXCLK" },
1290*4882a593Smuzhiyun { "AIF1TX2", NULL, "AIF1TXCLK" },
1291*4882a593Smuzhiyun { "AIF1TX3", NULL, "AIF1TXCLK" },
1292*4882a593Smuzhiyun { "AIF1TX4", NULL, "AIF1TXCLK" },
1293*4882a593Smuzhiyun { "AIF1TX5", NULL, "AIF1TXCLK" },
1294*4882a593Smuzhiyun { "AIF1TX6", NULL, "AIF1TXCLK" },
1295*4882a593Smuzhiyun { "AIF1TX7", NULL, "AIF1TXCLK" },
1296*4882a593Smuzhiyun { "AIF1TX8", NULL, "AIF1TXCLK" },
1297*4882a593Smuzhiyun { "AIF2TX1", NULL, "AIF2TXCLK" },
1298*4882a593Smuzhiyun { "AIF2TX2", NULL, "AIF2TXCLK" },
1299*4882a593Smuzhiyun { "AIF2TX3", NULL, "AIF2TXCLK" },
1300*4882a593Smuzhiyun { "AIF2TX4", NULL, "AIF2TXCLK" },
1301*4882a593Smuzhiyun { "AIF2TX5", NULL, "AIF2TXCLK" },
1302*4882a593Smuzhiyun { "AIF2TX6", NULL, "AIF2TXCLK" },
1303*4882a593Smuzhiyun { "AIF2TX7", NULL, "AIF2TXCLK" },
1304*4882a593Smuzhiyun { "AIF2TX8", NULL, "AIF2TXCLK" },
1305*4882a593Smuzhiyun { "AIF3TX1", NULL, "AIF3TXCLK" },
1306*4882a593Smuzhiyun { "AIF3TX2", NULL, "AIF3TXCLK" },
1307*4882a593Smuzhiyun { "AIF3TX3", NULL, "AIF3TXCLK" },
1308*4882a593Smuzhiyun { "AIF3TX4", NULL, "AIF3TXCLK" },
1309*4882a593Smuzhiyun { "SLIMTX1", NULL, "SLIMBUSCLK" },
1310*4882a593Smuzhiyun { "SLIMTX2", NULL, "SLIMBUSCLK" },
1311*4882a593Smuzhiyun { "SLIMTX3", NULL, "SLIMBUSCLK" },
1312*4882a593Smuzhiyun { "SLIMTX4", NULL, "SLIMBUSCLK" },
1313*4882a593Smuzhiyun { "SLIMTX5", NULL, "SLIMBUSCLK" },
1314*4882a593Smuzhiyun { "SLIMTX6", NULL, "SLIMBUSCLK" },
1315*4882a593Smuzhiyun { "SLIMTX7", NULL, "SLIMBUSCLK" },
1316*4882a593Smuzhiyun { "SLIMTX8", NULL, "SLIMBUSCLK" },
1317*4882a593Smuzhiyun { "SPD1TX1", NULL, "SPDCLK" },
1318*4882a593Smuzhiyun { "SPD1TX2", NULL, "SPDCLK" },
1319*4882a593Smuzhiyun { "DSP1", NULL, "DSP1CLK" },
1320*4882a593Smuzhiyun { "ISRC1DEC1", NULL, "ISRC1CLK" },
1321*4882a593Smuzhiyun { "ISRC1DEC2", NULL, "ISRC1CLK" },
1322*4882a593Smuzhiyun { "ISRC1INT1", NULL, "ISRC1CLK" },
1323*4882a593Smuzhiyun { "ISRC1INT2", NULL, "ISRC1CLK" },
1324*4882a593Smuzhiyun { "ISRC2DEC1", NULL, "ISRC2CLK" },
1325*4882a593Smuzhiyun { "ISRC2DEC2", NULL, "ISRC2CLK" },
1326*4882a593Smuzhiyun { "ISRC2INT1", NULL, "ISRC2CLK" },
1327*4882a593Smuzhiyun { "ISRC2INT2", NULL, "ISRC2CLK" },
1328*4882a593Smuzhiyun { "ASRC1IN1L", NULL, "ASRC1CLK" },
1329*4882a593Smuzhiyun { "ASRC1IN1R", NULL, "ASRC1CLK" },
1330*4882a593Smuzhiyun { "ASRC1IN2L", NULL, "ASRC1CLK" },
1331*4882a593Smuzhiyun { "ASRC1IN2R", NULL, "ASRC1CLK" },
1332*4882a593Smuzhiyun { "DFC1", NULL, "DFCCLK" },
1333*4882a593Smuzhiyun { "DFC2", NULL, "DFCCLK" },
1334*4882a593Smuzhiyun { "DFC3", NULL, "DFCCLK" },
1335*4882a593Smuzhiyun { "DFC4", NULL, "DFCCLK" },
1336*4882a593Smuzhiyun { "DFC5", NULL, "DFCCLK" },
1337*4882a593Smuzhiyun { "DFC6", NULL, "DFCCLK" },
1338*4882a593Smuzhiyun { "DFC7", NULL, "DFCCLK" },
1339*4882a593Smuzhiyun { "DFC8", NULL, "DFCCLK" },
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun { "OUT1L", NULL, "CPVDD1" },
1342*4882a593Smuzhiyun { "OUT1L", NULL, "CPVDD2" },
1343*4882a593Smuzhiyun { "OUT1R", NULL, "CPVDD1" },
1344*4882a593Smuzhiyun { "OUT1R", NULL, "CPVDD2" },
1345*4882a593Smuzhiyun { "OUT2L", NULL, "CPVDD1" },
1346*4882a593Smuzhiyun { "OUT2L", NULL, "CPVDD2" },
1347*4882a593Smuzhiyun { "OUT2R", NULL, "CPVDD1" },
1348*4882a593Smuzhiyun { "OUT2R", NULL, "CPVDD2" },
1349*4882a593Smuzhiyun { "OUT3L", NULL, "CPVDD1" },
1350*4882a593Smuzhiyun { "OUT3L", NULL, "CPVDD2" },
1351*4882a593Smuzhiyun { "OUT3R", NULL, "CPVDD1" },
1352*4882a593Smuzhiyun { "OUT3R", NULL, "CPVDD2" },
1353*4882a593Smuzhiyun
1354*4882a593Smuzhiyun { "OUT1L", NULL, "SYSCLK" },
1355*4882a593Smuzhiyun { "OUT1R", NULL, "SYSCLK" },
1356*4882a593Smuzhiyun { "OUT2L", NULL, "SYSCLK" },
1357*4882a593Smuzhiyun { "OUT2R", NULL, "SYSCLK" },
1358*4882a593Smuzhiyun { "OUT3L", NULL, "SYSCLK" },
1359*4882a593Smuzhiyun { "OUT3R", NULL, "SYSCLK" },
1360*4882a593Smuzhiyun { "OUT5L", NULL, "SYSCLK" },
1361*4882a593Smuzhiyun { "OUT5R", NULL, "SYSCLK" },
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun { "SPD1", NULL, "SYSCLK" },
1364*4882a593Smuzhiyun { "SPD1", NULL, "SPD1TX1" },
1365*4882a593Smuzhiyun { "SPD1", NULL, "SPD1TX2" },
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun { "IN1L", NULL, "SYSCLK" },
1368*4882a593Smuzhiyun { "IN1R", NULL, "SYSCLK" },
1369*4882a593Smuzhiyun { "IN2L", NULL, "SYSCLK" },
1370*4882a593Smuzhiyun { "IN2R", NULL, "SYSCLK" },
1371*4882a593Smuzhiyun { "IN3L", NULL, "SYSCLK" },
1372*4882a593Smuzhiyun { "IN3R", NULL, "SYSCLK" },
1373*4882a593Smuzhiyun { "IN4L", NULL, "SYSCLK" },
1374*4882a593Smuzhiyun { "IN4R", NULL, "SYSCLK" },
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun { "ASRC1IN1L", NULL, "SYSCLK" },
1377*4882a593Smuzhiyun { "ASRC1IN1R", NULL, "SYSCLK" },
1378*4882a593Smuzhiyun { "ASRC1IN2L", NULL, "SYSCLK" },
1379*4882a593Smuzhiyun { "ASRC1IN2R", NULL, "SYSCLK" },
1380*4882a593Smuzhiyun
1381*4882a593Smuzhiyun { "ASRC1IN1L", NULL, "ASYNCCLK" },
1382*4882a593Smuzhiyun { "ASRC1IN1R", NULL, "ASYNCCLK" },
1383*4882a593Smuzhiyun { "ASRC1IN2L", NULL, "ASYNCCLK" },
1384*4882a593Smuzhiyun { "ASRC1IN2R", NULL, "ASYNCCLK" },
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun { "MICBIAS1", NULL, "MICVDD" },
1387*4882a593Smuzhiyun { "MICBIAS2", NULL, "MICVDD" },
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun { "MICBIAS1A", NULL, "MICBIAS1" },
1390*4882a593Smuzhiyun { "MICBIAS1B", NULL, "MICBIAS1" },
1391*4882a593Smuzhiyun { "MICBIAS1C", NULL, "MICBIAS1" },
1392*4882a593Smuzhiyun { "MICBIAS1D", NULL, "MICBIAS1" },
1393*4882a593Smuzhiyun
1394*4882a593Smuzhiyun { "MICBIAS2A", NULL, "MICBIAS2" },
1395*4882a593Smuzhiyun { "MICBIAS2B", NULL, "MICBIAS2" },
1396*4882a593Smuzhiyun
1397*4882a593Smuzhiyun { "Noise Generator", NULL, "SYSCLK" },
1398*4882a593Smuzhiyun { "Tone Generator 1", NULL, "SYSCLK" },
1399*4882a593Smuzhiyun { "Tone Generator 2", NULL, "SYSCLK" },
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun { "Noise Generator", NULL, "NOISE" },
1402*4882a593Smuzhiyun { "Tone Generator 1", NULL, "TONE" },
1403*4882a593Smuzhiyun { "Tone Generator 2", NULL, "TONE" },
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX1" },
1406*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX2" },
1407*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX3" },
1408*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX4" },
1409*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX5" },
1410*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX6" },
1411*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX7" },
1412*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX8" },
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun { "AIF1RX1", NULL, "AIF1 Playback" },
1415*4882a593Smuzhiyun { "AIF1RX2", NULL, "AIF1 Playback" },
1416*4882a593Smuzhiyun { "AIF1RX3", NULL, "AIF1 Playback" },
1417*4882a593Smuzhiyun { "AIF1RX4", NULL, "AIF1 Playback" },
1418*4882a593Smuzhiyun { "AIF1RX5", NULL, "AIF1 Playback" },
1419*4882a593Smuzhiyun { "AIF1RX6", NULL, "AIF1 Playback" },
1420*4882a593Smuzhiyun { "AIF1RX7", NULL, "AIF1 Playback" },
1421*4882a593Smuzhiyun { "AIF1RX8", NULL, "AIF1 Playback" },
1422*4882a593Smuzhiyun
1423*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX1" },
1424*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX2" },
1425*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX3" },
1426*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX4" },
1427*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX5" },
1428*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX6" },
1429*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX7" },
1430*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX8" },
1431*4882a593Smuzhiyun
1432*4882a593Smuzhiyun { "AIF2RX1", NULL, "AIF2 Playback" },
1433*4882a593Smuzhiyun { "AIF2RX2", NULL, "AIF2 Playback" },
1434*4882a593Smuzhiyun { "AIF2RX3", NULL, "AIF2 Playback" },
1435*4882a593Smuzhiyun { "AIF2RX4", NULL, "AIF2 Playback" },
1436*4882a593Smuzhiyun { "AIF2RX5", NULL, "AIF2 Playback" },
1437*4882a593Smuzhiyun { "AIF2RX6", NULL, "AIF2 Playback" },
1438*4882a593Smuzhiyun { "AIF2RX7", NULL, "AIF2 Playback" },
1439*4882a593Smuzhiyun { "AIF2RX8", NULL, "AIF2 Playback" },
1440*4882a593Smuzhiyun
1441*4882a593Smuzhiyun { "AIF3 Capture", NULL, "AIF3TX1" },
1442*4882a593Smuzhiyun { "AIF3 Capture", NULL, "AIF3TX2" },
1443*4882a593Smuzhiyun { "AIF3 Capture", NULL, "AIF3TX3" },
1444*4882a593Smuzhiyun { "AIF3 Capture", NULL, "AIF3TX4" },
1445*4882a593Smuzhiyun
1446*4882a593Smuzhiyun { "AIF3RX1", NULL, "AIF3 Playback" },
1447*4882a593Smuzhiyun { "AIF3RX2", NULL, "AIF3 Playback" },
1448*4882a593Smuzhiyun { "AIF3RX3", NULL, "AIF3 Playback" },
1449*4882a593Smuzhiyun { "AIF3RX4", NULL, "AIF3 Playback" },
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX1" },
1452*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX2" },
1453*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX3" },
1454*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX4" },
1455*4882a593Smuzhiyun
1456*4882a593Smuzhiyun { "SLIMRX1", NULL, "Slim1 Playback" },
1457*4882a593Smuzhiyun { "SLIMRX2", NULL, "Slim1 Playback" },
1458*4882a593Smuzhiyun { "SLIMRX3", NULL, "Slim1 Playback" },
1459*4882a593Smuzhiyun { "SLIMRX4", NULL, "Slim1 Playback" },
1460*4882a593Smuzhiyun
1461*4882a593Smuzhiyun { "Slim2 Capture", NULL, "SLIMTX5" },
1462*4882a593Smuzhiyun { "Slim2 Capture", NULL, "SLIMTX6" },
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun { "SLIMRX5", NULL, "Slim2 Playback" },
1465*4882a593Smuzhiyun { "SLIMRX6", NULL, "Slim2 Playback" },
1466*4882a593Smuzhiyun
1467*4882a593Smuzhiyun { "Slim3 Capture", NULL, "SLIMTX7" },
1468*4882a593Smuzhiyun { "Slim3 Capture", NULL, "SLIMTX8" },
1469*4882a593Smuzhiyun
1470*4882a593Smuzhiyun { "SLIMRX7", NULL, "Slim3 Playback" },
1471*4882a593Smuzhiyun { "SLIMRX8", NULL, "Slim3 Playback" },
1472*4882a593Smuzhiyun
1473*4882a593Smuzhiyun { "AIF1 Playback", NULL, "SYSCLK" },
1474*4882a593Smuzhiyun { "AIF2 Playback", NULL, "SYSCLK" },
1475*4882a593Smuzhiyun { "AIF3 Playback", NULL, "SYSCLK" },
1476*4882a593Smuzhiyun { "Slim1 Playback", NULL, "SYSCLK" },
1477*4882a593Smuzhiyun { "Slim2 Playback", NULL, "SYSCLK" },
1478*4882a593Smuzhiyun { "Slim3 Playback", NULL, "SYSCLK" },
1479*4882a593Smuzhiyun
1480*4882a593Smuzhiyun { "AIF1 Capture", NULL, "SYSCLK" },
1481*4882a593Smuzhiyun { "AIF2 Capture", NULL, "SYSCLK" },
1482*4882a593Smuzhiyun { "AIF3 Capture", NULL, "SYSCLK" },
1483*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SYSCLK" },
1484*4882a593Smuzhiyun { "Slim2 Capture", NULL, "SYSCLK" },
1485*4882a593Smuzhiyun { "Slim3 Capture", NULL, "SYSCLK" },
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun { "Audio Trace DSP", NULL, "DSP1" },
1488*4882a593Smuzhiyun
1489*4882a593Smuzhiyun { "IN1L Analog Mux", "A", "IN1ALN" },
1490*4882a593Smuzhiyun { "IN1L Analog Mux", "A", "IN1ALP" },
1491*4882a593Smuzhiyun { "IN1L Analog Mux", "B", "IN1BLN" },
1492*4882a593Smuzhiyun { "IN1L Analog Mux", "B", "IN1BLP" },
1493*4882a593Smuzhiyun { "IN1R Analog Mux", "A", "IN1ARN" },
1494*4882a593Smuzhiyun { "IN1R Analog Mux", "A", "IN1ARP" },
1495*4882a593Smuzhiyun { "IN1R Analog Mux", "B", "IN1BR" },
1496*4882a593Smuzhiyun { "IN1R Analog Mux", "B", "IN1ALN" },
1497*4882a593Smuzhiyun
1498*4882a593Smuzhiyun { "IN1L Mode", "Analog", "IN1L Analog Mux" },
1499*4882a593Smuzhiyun { "IN1R Mode", "Analog", "IN1R Analog Mux" },
1500*4882a593Smuzhiyun
1501*4882a593Smuzhiyun { "IN1L Mode", "Digital", "IN1ALN" },
1502*4882a593Smuzhiyun { "IN1L Mode", "Digital", "IN1ALP" },
1503*4882a593Smuzhiyun { "IN1R Mode", "Digital", "IN1ALN" },
1504*4882a593Smuzhiyun { "IN1R Mode", "Digital", "IN1ALP" },
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun { "IN1L", NULL, "IN1L Mode" },
1507*4882a593Smuzhiyun { "IN1R", NULL, "IN1R Mode" },
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun { "IN2L Analog Mux", "A", "IN2ALN" },
1510*4882a593Smuzhiyun { "IN2L Analog Mux", "A", "IN2ALP" },
1511*4882a593Smuzhiyun { "IN2L Analog Mux", "B", "IN2ALN" },
1512*4882a593Smuzhiyun { "IN2L Analog Mux", "B", "IN2BL" },
1513*4882a593Smuzhiyun { "IN2R Analog Mux", "A", "IN2ARN" },
1514*4882a593Smuzhiyun { "IN2R Analog Mux", "A", "IN2ARP" },
1515*4882a593Smuzhiyun { "IN2R Analog Mux", "B", "IN2ARN" },
1516*4882a593Smuzhiyun { "IN2R Analog Mux", "B", "IN2BR" },
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun { "IN2L Mode", "Analog", "IN2L Analog Mux" },
1519*4882a593Smuzhiyun { "IN2R Mode", "Analog", "IN2R Analog Mux" },
1520*4882a593Smuzhiyun
1521*4882a593Smuzhiyun { "IN2L Mode", "Digital", "IN2ALN" },
1522*4882a593Smuzhiyun { "IN2L Mode", "Digital", "IN2ALP" },
1523*4882a593Smuzhiyun { "IN2R Mode", "Digital", "IN2ALN" },
1524*4882a593Smuzhiyun { "IN2R Mode", "Digital", "IN2ALP" },
1525*4882a593Smuzhiyun
1526*4882a593Smuzhiyun { "IN2L", NULL, "IN2L Mode" },
1527*4882a593Smuzhiyun { "IN2R", NULL, "IN2R Mode" },
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun { "IN3L", NULL, "IN1ARN" },
1530*4882a593Smuzhiyun { "IN3L", NULL, "IN1ARP" },
1531*4882a593Smuzhiyun { "IN3R", NULL, "IN1ARN" },
1532*4882a593Smuzhiyun { "IN3R", NULL, "IN1ARP" },
1533*4882a593Smuzhiyun
1534*4882a593Smuzhiyun { "IN4L", NULL, "IN2ARN" },
1535*4882a593Smuzhiyun { "IN4L", NULL, "IN2ARP" },
1536*4882a593Smuzhiyun { "IN4R", NULL, "IN2ARN" },
1537*4882a593Smuzhiyun { "IN4R", NULL, "IN2ARP" },
1538*4882a593Smuzhiyun
1539*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1540*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1541*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1542*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1543*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1544*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1545*4882a593Smuzhiyun
1546*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1547*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1548*4882a593Smuzhiyun
1549*4882a593Smuzhiyun MADERA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1550*4882a593Smuzhiyun MADERA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1551*4882a593Smuzhiyun
1552*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1553*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1554*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1555*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1556*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1557*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1558*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1559*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1560*4882a593Smuzhiyun
1561*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1562*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1563*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
1564*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
1565*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"),
1566*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"),
1567*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX7", "AIF2TX7"),
1568*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX8", "AIF2TX8"),
1569*4882a593Smuzhiyun
1570*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1571*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1572*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF3TX3", "AIF3TX3"),
1573*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF3TX4", "AIF3TX4"),
1574*4882a593Smuzhiyun
1575*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
1576*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
1577*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
1578*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
1579*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
1580*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
1581*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"),
1582*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"),
1583*4882a593Smuzhiyun
1584*4882a593Smuzhiyun MADERA_MUX_ROUTES("SPD1TX1", "SPDIFTX1"),
1585*4882a593Smuzhiyun MADERA_MUX_ROUTES("SPD1TX2", "SPDIFTX2"),
1586*4882a593Smuzhiyun
1587*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ1", "EQ1"),
1588*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ2", "EQ2"),
1589*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ3", "EQ3"),
1590*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ4", "EQ4"),
1591*4882a593Smuzhiyun
1592*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC1L", "DRC1L"),
1593*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC1R", "DRC1R"),
1594*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC2L", "DRC2L"),
1595*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC2R", "DRC2R"),
1596*4882a593Smuzhiyun
1597*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF1", "LHPF1"),
1598*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF2", "LHPF2"),
1599*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF3", "LHPF3"),
1600*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF4", "LHPF4"),
1601*4882a593Smuzhiyun
1602*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN1L", "ASRC1IN1L"),
1603*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN1R", "ASRC1IN1R"),
1604*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN2L", "ASRC1IN2L"),
1605*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN2R", "ASRC1IN2R"),
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP1"),
1608*4882a593Smuzhiyun
1609*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
1610*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
1613*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
1614*4882a593Smuzhiyun
1615*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
1616*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
1617*4882a593Smuzhiyun
1618*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
1619*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
1620*4882a593Smuzhiyun
1621*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT1L", "OUT1L" },
1622*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT1R", "OUT1R" },
1623*4882a593Smuzhiyun { "HPOUT1L", NULL, "OUT1L" },
1624*4882a593Smuzhiyun { "HPOUT1R", NULL, "OUT1R" },
1625*4882a593Smuzhiyun
1626*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT2L", "OUT2L" },
1627*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT2R", "OUT2R" },
1628*4882a593Smuzhiyun { "HPOUT2L", NULL, "OUT2L" },
1629*4882a593Smuzhiyun { "HPOUT2R", NULL, "OUT2R" },
1630*4882a593Smuzhiyun
1631*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT3L", "OUT3L" },
1632*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT3R", "OUT3R" },
1633*4882a593Smuzhiyun { "OUT3 Demux", NULL, "OUT3L" },
1634*4882a593Smuzhiyun { "OUT3 Demux", NULL, "OUT3R" },
1635*4882a593Smuzhiyun
1636*4882a593Smuzhiyun { "OUT3R", NULL, "OUT3 Mono Mux" },
1637*4882a593Smuzhiyun
1638*4882a593Smuzhiyun { "HPOUT3L", "HPOUT3", "OUT3 Demux" },
1639*4882a593Smuzhiyun { "HPOUT3R", "HPOUT3", "OUT3 Demux" },
1640*4882a593Smuzhiyun { "HPOUT4L", "HPOUT4", "OUT3 Demux" },
1641*4882a593Smuzhiyun { "HPOUT4R", "HPOUT4", "OUT3 Demux" },
1642*4882a593Smuzhiyun
1643*4882a593Smuzhiyun { "AEC1 Loopback", "SPKDAT1L", "OUT5L" },
1644*4882a593Smuzhiyun { "AEC1 Loopback", "SPKDAT1R", "OUT5R" },
1645*4882a593Smuzhiyun { "SPKDAT1L", NULL, "OUT5L" },
1646*4882a593Smuzhiyun { "SPKDAT1R", NULL, "OUT5R" },
1647*4882a593Smuzhiyun
1648*4882a593Smuzhiyun { "SPDIF1", NULL, "SPD1" },
1649*4882a593Smuzhiyun
1650*4882a593Smuzhiyun { "MICSUPP", NULL, "SYSCLK" },
1651*4882a593Smuzhiyun
1652*4882a593Smuzhiyun { "DRC1 Signal Activity", NULL, "DRC1 Activity Output" },
1653*4882a593Smuzhiyun { "DRC2 Signal Activity", NULL, "DRC2 Activity Output" },
1654*4882a593Smuzhiyun { "DRC1 Activity Output", "Switch", "DRC1L" },
1655*4882a593Smuzhiyun { "DRC1 Activity Output", "Switch", "DRC1R" },
1656*4882a593Smuzhiyun { "DRC2 Activity Output", "Switch", "DRC2L" },
1657*4882a593Smuzhiyun { "DRC2 Activity Output", "Switch", "DRC2R" },
1658*4882a593Smuzhiyun
1659*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC1", "DFC1"),
1660*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC2", "DFC2"),
1661*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC3", "DFC3"),
1662*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC4", "DFC4"),
1663*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC5", "DFC5"),
1664*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC6", "DFC6"),
1665*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC7", "DFC7"),
1666*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC8", "DFC8"),
1667*4882a593Smuzhiyun };
1668*4882a593Smuzhiyun
cs47l92_set_fll(struct snd_soc_component * component,int fll_id,int source,unsigned int fref,unsigned int fout)1669*4882a593Smuzhiyun static int cs47l92_set_fll(struct snd_soc_component *component, int fll_id,
1670*4882a593Smuzhiyun int source, unsigned int fref, unsigned int fout)
1671*4882a593Smuzhiyun {
1672*4882a593Smuzhiyun struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
1673*4882a593Smuzhiyun
1674*4882a593Smuzhiyun switch (fll_id) {
1675*4882a593Smuzhiyun case MADERA_FLL1_REFCLK:
1676*4882a593Smuzhiyun return madera_fllhj_set_refclk(&cs47l92->fll[0], source, fref,
1677*4882a593Smuzhiyun fout);
1678*4882a593Smuzhiyun case MADERA_FLL2_REFCLK:
1679*4882a593Smuzhiyun return madera_fllhj_set_refclk(&cs47l92->fll[1], source, fref,
1680*4882a593Smuzhiyun fout);
1681*4882a593Smuzhiyun default:
1682*4882a593Smuzhiyun return -EINVAL;
1683*4882a593Smuzhiyun }
1684*4882a593Smuzhiyun }
1685*4882a593Smuzhiyun
1686*4882a593Smuzhiyun static struct snd_soc_dai_driver cs47l92_dai[] = {
1687*4882a593Smuzhiyun {
1688*4882a593Smuzhiyun .name = "cs47l92-aif1",
1689*4882a593Smuzhiyun .id = 1,
1690*4882a593Smuzhiyun .base = MADERA_AIF1_BCLK_CTRL,
1691*4882a593Smuzhiyun .playback = {
1692*4882a593Smuzhiyun .stream_name = "AIF1 Playback",
1693*4882a593Smuzhiyun .channels_min = 1,
1694*4882a593Smuzhiyun .channels_max = 8,
1695*4882a593Smuzhiyun .rates = MADERA_RATES,
1696*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1697*4882a593Smuzhiyun },
1698*4882a593Smuzhiyun .capture = {
1699*4882a593Smuzhiyun .stream_name = "AIF1 Capture",
1700*4882a593Smuzhiyun .channels_min = 1,
1701*4882a593Smuzhiyun .channels_max = 8,
1702*4882a593Smuzhiyun .rates = MADERA_RATES,
1703*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1704*4882a593Smuzhiyun },
1705*4882a593Smuzhiyun .ops = &madera_dai_ops,
1706*4882a593Smuzhiyun .symmetric_rates = 1,
1707*4882a593Smuzhiyun .symmetric_samplebits = 1,
1708*4882a593Smuzhiyun },
1709*4882a593Smuzhiyun {
1710*4882a593Smuzhiyun .name = "cs47l92-aif2",
1711*4882a593Smuzhiyun .id = 2,
1712*4882a593Smuzhiyun .base = MADERA_AIF2_BCLK_CTRL,
1713*4882a593Smuzhiyun .playback = {
1714*4882a593Smuzhiyun .stream_name = "AIF2 Playback",
1715*4882a593Smuzhiyun .channels_min = 1,
1716*4882a593Smuzhiyun .channels_max = 8,
1717*4882a593Smuzhiyun .rates = MADERA_RATES,
1718*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1719*4882a593Smuzhiyun },
1720*4882a593Smuzhiyun .capture = {
1721*4882a593Smuzhiyun .stream_name = "AIF2 Capture",
1722*4882a593Smuzhiyun .channels_min = 1,
1723*4882a593Smuzhiyun .channels_max = 8,
1724*4882a593Smuzhiyun .rates = MADERA_RATES,
1725*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1726*4882a593Smuzhiyun },
1727*4882a593Smuzhiyun .ops = &madera_dai_ops,
1728*4882a593Smuzhiyun .symmetric_rates = 1,
1729*4882a593Smuzhiyun .symmetric_samplebits = 1,
1730*4882a593Smuzhiyun },
1731*4882a593Smuzhiyun {
1732*4882a593Smuzhiyun .name = "cs47l92-aif3",
1733*4882a593Smuzhiyun .id = 3,
1734*4882a593Smuzhiyun .base = MADERA_AIF3_BCLK_CTRL,
1735*4882a593Smuzhiyun .playback = {
1736*4882a593Smuzhiyun .stream_name = "AIF3 Playback",
1737*4882a593Smuzhiyun .channels_min = 1,
1738*4882a593Smuzhiyun .channels_max = 4,
1739*4882a593Smuzhiyun .rates = MADERA_RATES,
1740*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1741*4882a593Smuzhiyun },
1742*4882a593Smuzhiyun .capture = {
1743*4882a593Smuzhiyun .stream_name = "AIF3 Capture",
1744*4882a593Smuzhiyun .channels_min = 1,
1745*4882a593Smuzhiyun .channels_max = 4,
1746*4882a593Smuzhiyun .rates = MADERA_RATES,
1747*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1748*4882a593Smuzhiyun },
1749*4882a593Smuzhiyun .ops = &madera_dai_ops,
1750*4882a593Smuzhiyun .symmetric_rates = 1,
1751*4882a593Smuzhiyun .symmetric_samplebits = 1,
1752*4882a593Smuzhiyun },
1753*4882a593Smuzhiyun {
1754*4882a593Smuzhiyun .name = "cs47l92-slim1",
1755*4882a593Smuzhiyun .id = 5,
1756*4882a593Smuzhiyun .playback = {
1757*4882a593Smuzhiyun .stream_name = "Slim1 Playback",
1758*4882a593Smuzhiyun .channels_min = 1,
1759*4882a593Smuzhiyun .channels_max = 4,
1760*4882a593Smuzhiyun .rates = MADERA_RATES,
1761*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1762*4882a593Smuzhiyun },
1763*4882a593Smuzhiyun .capture = {
1764*4882a593Smuzhiyun .stream_name = "Slim1 Capture",
1765*4882a593Smuzhiyun .channels_min = 1,
1766*4882a593Smuzhiyun .channels_max = 4,
1767*4882a593Smuzhiyun .rates = MADERA_RATES,
1768*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1769*4882a593Smuzhiyun },
1770*4882a593Smuzhiyun .ops = &madera_simple_dai_ops,
1771*4882a593Smuzhiyun },
1772*4882a593Smuzhiyun {
1773*4882a593Smuzhiyun .name = "cs47l92-slim2",
1774*4882a593Smuzhiyun .id = 6,
1775*4882a593Smuzhiyun .playback = {
1776*4882a593Smuzhiyun .stream_name = "Slim2 Playback",
1777*4882a593Smuzhiyun .channels_min = 1,
1778*4882a593Smuzhiyun .channels_max = 2,
1779*4882a593Smuzhiyun .rates = MADERA_RATES,
1780*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1781*4882a593Smuzhiyun },
1782*4882a593Smuzhiyun .capture = {
1783*4882a593Smuzhiyun .stream_name = "Slim2 Capture",
1784*4882a593Smuzhiyun .channels_min = 1,
1785*4882a593Smuzhiyun .channels_max = 2,
1786*4882a593Smuzhiyun .rates = MADERA_RATES,
1787*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1788*4882a593Smuzhiyun },
1789*4882a593Smuzhiyun .ops = &madera_simple_dai_ops,
1790*4882a593Smuzhiyun },
1791*4882a593Smuzhiyun {
1792*4882a593Smuzhiyun .name = "cs47l92-slim3",
1793*4882a593Smuzhiyun .id = 7,
1794*4882a593Smuzhiyun .playback = {
1795*4882a593Smuzhiyun .stream_name = "Slim3 Playback",
1796*4882a593Smuzhiyun .channels_min = 1,
1797*4882a593Smuzhiyun .channels_max = 2,
1798*4882a593Smuzhiyun .rates = MADERA_RATES,
1799*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1800*4882a593Smuzhiyun },
1801*4882a593Smuzhiyun .capture = {
1802*4882a593Smuzhiyun .stream_name = "Slim3 Capture",
1803*4882a593Smuzhiyun .channels_min = 1,
1804*4882a593Smuzhiyun .channels_max = 2,
1805*4882a593Smuzhiyun .rates = MADERA_RATES,
1806*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1807*4882a593Smuzhiyun },
1808*4882a593Smuzhiyun .ops = &madera_simple_dai_ops,
1809*4882a593Smuzhiyun },
1810*4882a593Smuzhiyun {
1811*4882a593Smuzhiyun .name = "cs47l92-cpu-trace",
1812*4882a593Smuzhiyun .capture = {
1813*4882a593Smuzhiyun .stream_name = "Audio Trace CPU",
1814*4882a593Smuzhiyun .channels_min = 1,
1815*4882a593Smuzhiyun .channels_max = 2,
1816*4882a593Smuzhiyun .rates = MADERA_RATES,
1817*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1818*4882a593Smuzhiyun },
1819*4882a593Smuzhiyun .compress_new = snd_soc_new_compress,
1820*4882a593Smuzhiyun },
1821*4882a593Smuzhiyun {
1822*4882a593Smuzhiyun .name = "cs47l92-dsp-trace",
1823*4882a593Smuzhiyun .capture = {
1824*4882a593Smuzhiyun .stream_name = "Audio Trace DSP",
1825*4882a593Smuzhiyun .channels_min = 1,
1826*4882a593Smuzhiyun .channels_max = 2,
1827*4882a593Smuzhiyun .rates = MADERA_RATES,
1828*4882a593Smuzhiyun .formats = MADERA_FORMATS,
1829*4882a593Smuzhiyun },
1830*4882a593Smuzhiyun },
1831*4882a593Smuzhiyun };
1832*4882a593Smuzhiyun
cs47l92_open(struct snd_soc_component * component,struct snd_compr_stream * stream)1833*4882a593Smuzhiyun static int cs47l92_open(struct snd_soc_component *component,
1834*4882a593Smuzhiyun struct snd_compr_stream *stream)
1835*4882a593Smuzhiyun {
1836*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = stream->private_data;
1837*4882a593Smuzhiyun struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
1838*4882a593Smuzhiyun struct madera_priv *priv = &cs47l92->core;
1839*4882a593Smuzhiyun struct madera *madera = priv->madera;
1840*4882a593Smuzhiyun int n_adsp;
1841*4882a593Smuzhiyun
1842*4882a593Smuzhiyun if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l92-dsp-trace") == 0) {
1843*4882a593Smuzhiyun n_adsp = 0;
1844*4882a593Smuzhiyun } else {
1845*4882a593Smuzhiyun dev_err(madera->dev,
1846*4882a593Smuzhiyun "No suitable compressed stream for DAI '%s'\n",
1847*4882a593Smuzhiyun asoc_rtd_to_codec(rtd, 0)->name);
1848*4882a593Smuzhiyun return -EINVAL;
1849*4882a593Smuzhiyun }
1850*4882a593Smuzhiyun
1851*4882a593Smuzhiyun return wm_adsp_compr_open(&priv->adsp[n_adsp], stream);
1852*4882a593Smuzhiyun }
1853*4882a593Smuzhiyun
cs47l92_adsp2_irq(int irq,void * data)1854*4882a593Smuzhiyun static irqreturn_t cs47l92_adsp2_irq(int irq, void *data)
1855*4882a593Smuzhiyun {
1856*4882a593Smuzhiyun struct cs47l92 *cs47l92 = data;
1857*4882a593Smuzhiyun struct madera_priv *priv = &cs47l92->core;
1858*4882a593Smuzhiyun struct madera *madera = priv->madera;
1859*4882a593Smuzhiyun int ret;
1860*4882a593Smuzhiyun
1861*4882a593Smuzhiyun ret = wm_adsp_compr_handle_irq(&priv->adsp[0]);
1862*4882a593Smuzhiyun if (ret == -ENODEV) {
1863*4882a593Smuzhiyun dev_err(madera->dev, "Spurious compressed data IRQ\n");
1864*4882a593Smuzhiyun return IRQ_NONE;
1865*4882a593Smuzhiyun }
1866*4882a593Smuzhiyun
1867*4882a593Smuzhiyun return IRQ_HANDLED;
1868*4882a593Smuzhiyun }
1869*4882a593Smuzhiyun
1870*4882a593Smuzhiyun static const struct snd_soc_dapm_route cs47l92_mono_routes[] = {
1871*4882a593Smuzhiyun { "OUT1R", NULL, "OUT1L" },
1872*4882a593Smuzhiyun { "OUT2R", NULL, "OUT2L" },
1873*4882a593Smuzhiyun { "OUT3 Mono Mux", "HPOUT3", "OUT3L" },
1874*4882a593Smuzhiyun { "OUT3 Mono Mux", "HPOUT4", "OUT3L" },
1875*4882a593Smuzhiyun };
1876*4882a593Smuzhiyun
cs47l92_component_probe(struct snd_soc_component * component)1877*4882a593Smuzhiyun static int cs47l92_component_probe(struct snd_soc_component *component)
1878*4882a593Smuzhiyun {
1879*4882a593Smuzhiyun struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
1880*4882a593Smuzhiyun struct madera *madera = cs47l92->core.madera;
1881*4882a593Smuzhiyun int ret;
1882*4882a593Smuzhiyun
1883*4882a593Smuzhiyun snd_soc_component_init_regmap(component, madera->regmap);
1884*4882a593Smuzhiyun
1885*4882a593Smuzhiyun mutex_lock(&madera->dapm_ptr_lock);
1886*4882a593Smuzhiyun madera->dapm = snd_soc_component_get_dapm(component);
1887*4882a593Smuzhiyun mutex_unlock(&madera->dapm_ptr_lock);
1888*4882a593Smuzhiyun
1889*4882a593Smuzhiyun ret = madera_init_inputs(component);
1890*4882a593Smuzhiyun if (ret)
1891*4882a593Smuzhiyun return ret;
1892*4882a593Smuzhiyun
1893*4882a593Smuzhiyun ret = madera_init_outputs(component, cs47l92_mono_routes,
1894*4882a593Smuzhiyun ARRAY_SIZE(cs47l92_mono_routes),
1895*4882a593Smuzhiyun CS47L92_MONO_OUTPUTS);
1896*4882a593Smuzhiyun if (ret)
1897*4882a593Smuzhiyun return ret;
1898*4882a593Smuzhiyun
1899*4882a593Smuzhiyun snd_soc_component_disable_pin(component, "HAPTICS");
1900*4882a593Smuzhiyun
1901*4882a593Smuzhiyun ret = snd_soc_add_component_controls(component,
1902*4882a593Smuzhiyun madera_adsp_rate_controls,
1903*4882a593Smuzhiyun CS47L92_NUM_ADSP);
1904*4882a593Smuzhiyun if (ret)
1905*4882a593Smuzhiyun return ret;
1906*4882a593Smuzhiyun
1907*4882a593Smuzhiyun return wm_adsp2_component_probe(&cs47l92->core.adsp[0], component);
1908*4882a593Smuzhiyun }
1909*4882a593Smuzhiyun
cs47l92_component_remove(struct snd_soc_component * component)1910*4882a593Smuzhiyun static void cs47l92_component_remove(struct snd_soc_component *component)
1911*4882a593Smuzhiyun {
1912*4882a593Smuzhiyun struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
1913*4882a593Smuzhiyun struct madera *madera = cs47l92->core.madera;
1914*4882a593Smuzhiyun
1915*4882a593Smuzhiyun mutex_lock(&madera->dapm_ptr_lock);
1916*4882a593Smuzhiyun madera->dapm = NULL;
1917*4882a593Smuzhiyun mutex_unlock(&madera->dapm_ptr_lock);
1918*4882a593Smuzhiyun
1919*4882a593Smuzhiyun wm_adsp2_component_remove(&cs47l92->core.adsp[0], component);
1920*4882a593Smuzhiyun }
1921*4882a593Smuzhiyun
1922*4882a593Smuzhiyun #define CS47L92_DIG_VU 0x0200
1923*4882a593Smuzhiyun
1924*4882a593Smuzhiyun static unsigned int cs47l92_digital_vu[] = {
1925*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1L,
1926*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1R,
1927*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2L,
1928*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2R,
1929*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3L,
1930*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3R,
1931*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5L,
1932*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5R,
1933*4882a593Smuzhiyun };
1934*4882a593Smuzhiyun
1935*4882a593Smuzhiyun static const struct snd_compress_ops cs47l92_compress_ops = {
1936*4882a593Smuzhiyun .open = &cs47l92_open,
1937*4882a593Smuzhiyun .free = &wm_adsp_compr_free,
1938*4882a593Smuzhiyun .set_params = &wm_adsp_compr_set_params,
1939*4882a593Smuzhiyun .get_caps = &wm_adsp_compr_get_caps,
1940*4882a593Smuzhiyun .trigger = &wm_adsp_compr_trigger,
1941*4882a593Smuzhiyun .pointer = &wm_adsp_compr_pointer,
1942*4882a593Smuzhiyun .copy = &wm_adsp_compr_copy,
1943*4882a593Smuzhiyun };
1944*4882a593Smuzhiyun
1945*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_cs47l92 = {
1946*4882a593Smuzhiyun .probe = &cs47l92_component_probe,
1947*4882a593Smuzhiyun .remove = &cs47l92_component_remove,
1948*4882a593Smuzhiyun .set_sysclk = &madera_set_sysclk,
1949*4882a593Smuzhiyun .set_pll = &cs47l92_set_fll,
1950*4882a593Smuzhiyun .name = DRV_NAME,
1951*4882a593Smuzhiyun .compress_ops = &cs47l92_compress_ops,
1952*4882a593Smuzhiyun .controls = cs47l92_snd_controls,
1953*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(cs47l92_snd_controls),
1954*4882a593Smuzhiyun .dapm_widgets = cs47l92_dapm_widgets,
1955*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(cs47l92_dapm_widgets),
1956*4882a593Smuzhiyun .dapm_routes = cs47l92_dapm_routes,
1957*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(cs47l92_dapm_routes),
1958*4882a593Smuzhiyun .use_pmdown_time = 1,
1959*4882a593Smuzhiyun .endianness = 1,
1960*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
1961*4882a593Smuzhiyun };
1962*4882a593Smuzhiyun
cs47l92_probe(struct platform_device * pdev)1963*4882a593Smuzhiyun static int cs47l92_probe(struct platform_device *pdev)
1964*4882a593Smuzhiyun {
1965*4882a593Smuzhiyun struct madera *madera = dev_get_drvdata(pdev->dev.parent);
1966*4882a593Smuzhiyun struct cs47l92 *cs47l92;
1967*4882a593Smuzhiyun int i, ret;
1968*4882a593Smuzhiyun
1969*4882a593Smuzhiyun BUILD_BUG_ON(ARRAY_SIZE(cs47l92_dai) > MADERA_MAX_DAI);
1970*4882a593Smuzhiyun
1971*4882a593Smuzhiyun /* quick exit if Madera irqchip driver hasn't completed probe */
1972*4882a593Smuzhiyun if (!madera->irq_dev) {
1973*4882a593Smuzhiyun dev_dbg(&pdev->dev, "irqchip driver not ready\n");
1974*4882a593Smuzhiyun return -EPROBE_DEFER;
1975*4882a593Smuzhiyun }
1976*4882a593Smuzhiyun
1977*4882a593Smuzhiyun cs47l92 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l92), GFP_KERNEL);
1978*4882a593Smuzhiyun if (!cs47l92)
1979*4882a593Smuzhiyun return -ENOMEM;
1980*4882a593Smuzhiyun
1981*4882a593Smuzhiyun platform_set_drvdata(pdev, cs47l92);
1982*4882a593Smuzhiyun
1983*4882a593Smuzhiyun cs47l92->core.madera = madera;
1984*4882a593Smuzhiyun cs47l92->core.dev = &pdev->dev;
1985*4882a593Smuzhiyun cs47l92->core.num_inputs = 8;
1986*4882a593Smuzhiyun
1987*4882a593Smuzhiyun ret = madera_core_init(&cs47l92->core);
1988*4882a593Smuzhiyun if (ret)
1989*4882a593Smuzhiyun return ret;
1990*4882a593Smuzhiyun
1991*4882a593Smuzhiyun ret = madera_request_irq(madera, MADERA_IRQ_DSP_IRQ1,
1992*4882a593Smuzhiyun "ADSP2 Compressed IRQ", cs47l92_adsp2_irq,
1993*4882a593Smuzhiyun cs47l92);
1994*4882a593Smuzhiyun if (ret != 0) {
1995*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
1996*4882a593Smuzhiyun goto error_core;
1997*4882a593Smuzhiyun }
1998*4882a593Smuzhiyun
1999*4882a593Smuzhiyun ret = madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 1);
2000*4882a593Smuzhiyun if (ret)
2001*4882a593Smuzhiyun dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
2002*4882a593Smuzhiyun
2003*4882a593Smuzhiyun cs47l92->core.adsp[0].part = "cs47l92";
2004*4882a593Smuzhiyun cs47l92->core.adsp[0].num = 1;
2005*4882a593Smuzhiyun cs47l92->core.adsp[0].type = WMFW_ADSP2;
2006*4882a593Smuzhiyun cs47l92->core.adsp[0].rev = 2;
2007*4882a593Smuzhiyun cs47l92->core.adsp[0].dev = madera->dev;
2008*4882a593Smuzhiyun cs47l92->core.adsp[0].regmap = madera->regmap_32bit;
2009*4882a593Smuzhiyun
2010*4882a593Smuzhiyun cs47l92->core.adsp[0].base = MADERA_DSP1_CONFIG_1;
2011*4882a593Smuzhiyun cs47l92->core.adsp[0].mem = cs47l92_dsp1_regions;
2012*4882a593Smuzhiyun cs47l92->core.adsp[0].num_mems = ARRAY_SIZE(cs47l92_dsp1_regions);
2013*4882a593Smuzhiyun
2014*4882a593Smuzhiyun cs47l92->core.adsp[0].lock_regions = WM_ADSP2_REGION_1_9;
2015*4882a593Smuzhiyun
2016*4882a593Smuzhiyun ret = wm_adsp2_init(&cs47l92->core.adsp[0]);
2017*4882a593Smuzhiyun if (ret != 0)
2018*4882a593Smuzhiyun goto error_dsp_irq;
2019*4882a593Smuzhiyun
2020*4882a593Smuzhiyun ret = madera_init_bus_error_irq(&cs47l92->core, 0, wm_adsp2_bus_error);
2021*4882a593Smuzhiyun if (ret != 0)
2022*4882a593Smuzhiyun goto error_adsp;
2023*4882a593Smuzhiyun
2024*4882a593Smuzhiyun madera_init_fll(madera, 1, MADERA_FLL1_CONTROL_1 - 1,
2025*4882a593Smuzhiyun &cs47l92->fll[0]);
2026*4882a593Smuzhiyun madera_init_fll(madera, 2, MADERA_FLL2_CONTROL_1 - 1,
2027*4882a593Smuzhiyun &cs47l92->fll[1]);
2028*4882a593Smuzhiyun
2029*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cs47l92_dai); i++)
2030*4882a593Smuzhiyun madera_init_dai(&cs47l92->core, i);
2031*4882a593Smuzhiyun
2032*4882a593Smuzhiyun /* Latch volume update bits */
2033*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cs47l92_digital_vu); i++)
2034*4882a593Smuzhiyun regmap_update_bits(madera->regmap, cs47l92_digital_vu[i],
2035*4882a593Smuzhiyun CS47L92_DIG_VU, CS47L92_DIG_VU);
2036*4882a593Smuzhiyun
2037*4882a593Smuzhiyun pm_runtime_enable(&pdev->dev);
2038*4882a593Smuzhiyun pm_runtime_idle(&pdev->dev);
2039*4882a593Smuzhiyun
2040*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&pdev->dev,
2041*4882a593Smuzhiyun &soc_component_dev_cs47l92,
2042*4882a593Smuzhiyun cs47l92_dai,
2043*4882a593Smuzhiyun ARRAY_SIZE(cs47l92_dai));
2044*4882a593Smuzhiyun if (ret < 0) {
2045*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
2046*4882a593Smuzhiyun goto error_pm_runtime;
2047*4882a593Smuzhiyun }
2048*4882a593Smuzhiyun
2049*4882a593Smuzhiyun return ret;
2050*4882a593Smuzhiyun
2051*4882a593Smuzhiyun error_pm_runtime:
2052*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
2053*4882a593Smuzhiyun madera_free_bus_error_irq(&cs47l92->core, 0);
2054*4882a593Smuzhiyun error_adsp:
2055*4882a593Smuzhiyun wm_adsp2_remove(&cs47l92->core.adsp[0]);
2056*4882a593Smuzhiyun error_dsp_irq:
2057*4882a593Smuzhiyun madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 0);
2058*4882a593Smuzhiyun madera_free_irq(madera, MADERA_IRQ_DSP_IRQ1, cs47l92);
2059*4882a593Smuzhiyun error_core:
2060*4882a593Smuzhiyun madera_core_free(&cs47l92->core);
2061*4882a593Smuzhiyun
2062*4882a593Smuzhiyun return ret;
2063*4882a593Smuzhiyun }
2064*4882a593Smuzhiyun
cs47l92_remove(struct platform_device * pdev)2065*4882a593Smuzhiyun static int cs47l92_remove(struct platform_device *pdev)
2066*4882a593Smuzhiyun {
2067*4882a593Smuzhiyun struct cs47l92 *cs47l92 = platform_get_drvdata(pdev);
2068*4882a593Smuzhiyun
2069*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
2070*4882a593Smuzhiyun
2071*4882a593Smuzhiyun madera_free_bus_error_irq(&cs47l92->core, 0);
2072*4882a593Smuzhiyun wm_adsp2_remove(&cs47l92->core.adsp[0]);
2073*4882a593Smuzhiyun
2074*4882a593Smuzhiyun madera_set_irq_wake(cs47l92->core.madera, MADERA_IRQ_DSP_IRQ1, 0);
2075*4882a593Smuzhiyun madera_free_irq(cs47l92->core.madera, MADERA_IRQ_DSP_IRQ1, cs47l92);
2076*4882a593Smuzhiyun
2077*4882a593Smuzhiyun madera_core_free(&cs47l92->core);
2078*4882a593Smuzhiyun
2079*4882a593Smuzhiyun return 0;
2080*4882a593Smuzhiyun }
2081*4882a593Smuzhiyun
2082*4882a593Smuzhiyun static struct platform_driver cs47l92_codec_driver = {
2083*4882a593Smuzhiyun .driver = {
2084*4882a593Smuzhiyun .name = "cs47l92-codec",
2085*4882a593Smuzhiyun },
2086*4882a593Smuzhiyun .probe = &cs47l92_probe,
2087*4882a593Smuzhiyun .remove = &cs47l92_remove,
2088*4882a593Smuzhiyun };
2089*4882a593Smuzhiyun
2090*4882a593Smuzhiyun module_platform_driver(cs47l92_codec_driver);
2091*4882a593Smuzhiyun
2092*4882a593Smuzhiyun MODULE_SOFTDEP("pre: madera irq-madera arizona-micsupp");
2093*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC CS47L92 driver");
2094*4882a593Smuzhiyun MODULE_AUTHOR("Stuart Henderson <stuarth@opensource.cirrus.com>");
2095*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
2096*4882a593Smuzhiyun MODULE_ALIAS("platform:cs47l92-codec");
2097