1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // ALSA SoC Audio driver for CS47L90 codec
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
6*4882a593Smuzhiyun // Cirrus Logic International Semiconductor Ltd.
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/moduleparam.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/pm.h>
15*4882a593Smuzhiyun #include <linux/pm_runtime.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <sound/core.h>
18*4882a593Smuzhiyun #include <sound/pcm.h>
19*4882a593Smuzhiyun #include <sound/pcm_params.h>
20*4882a593Smuzhiyun #include <sound/soc.h>
21*4882a593Smuzhiyun #include <sound/tlv.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <linux/irqchip/irq-madera.h>
24*4882a593Smuzhiyun #include <linux/mfd/madera/core.h>
25*4882a593Smuzhiyun #include <linux/mfd/madera/registers.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "madera.h"
28*4882a593Smuzhiyun #include "wm_adsp.h"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define DRV_NAME "cs47l90-codec"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define CS47L90_NUM_ADSP 7
33*4882a593Smuzhiyun #define CS47L90_MONO_OUTPUTS 3
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct cs47l90 {
36*4882a593Smuzhiyun struct madera_priv core;
37*4882a593Smuzhiyun struct madera_fll fll[3];
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static const struct wm_adsp_region cs47l90_dsp1_regions[] = {
41*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x080000 },
42*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static const struct wm_adsp_region cs47l90_dsp2_regions[] = {
48*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x160000 },
50*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x120000 },
51*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x140000 },
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static const struct wm_adsp_region cs47l90_dsp3_regions[] = {
55*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x180000 },
56*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
57*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x1a0000 },
58*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x1c0000 },
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static const struct wm_adsp_region cs47l90_dsp4_regions[] = {
62*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x200000 },
63*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x260000 },
64*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x220000 },
65*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x240000 },
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static const struct wm_adsp_region cs47l90_dsp5_regions[] = {
69*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x280000 },
70*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x2e0000 },
71*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x2a0000 },
72*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x2c0000 },
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static const struct wm_adsp_region cs47l90_dsp6_regions[] = {
76*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x300000 },
77*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x360000 },
78*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x320000 },
79*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x340000 },
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const struct wm_adsp_region cs47l90_dsp7_regions[] = {
83*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x380000 },
84*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x3e0000 },
85*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x3a0000 },
86*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x3c0000 },
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static const struct wm_adsp_region *cs47l90_dsp_regions[] = {
90*4882a593Smuzhiyun cs47l90_dsp1_regions,
91*4882a593Smuzhiyun cs47l90_dsp2_regions,
92*4882a593Smuzhiyun cs47l90_dsp3_regions,
93*4882a593Smuzhiyun cs47l90_dsp4_regions,
94*4882a593Smuzhiyun cs47l90_dsp5_regions,
95*4882a593Smuzhiyun cs47l90_dsp6_regions,
96*4882a593Smuzhiyun cs47l90_dsp7_regions,
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const int cs47l90_dsp_control_bases[] = {
100*4882a593Smuzhiyun MADERA_DSP1_CONFIG_1,
101*4882a593Smuzhiyun MADERA_DSP2_CONFIG_1,
102*4882a593Smuzhiyun MADERA_DSP3_CONFIG_1,
103*4882a593Smuzhiyun MADERA_DSP4_CONFIG_1,
104*4882a593Smuzhiyun MADERA_DSP5_CONFIG_1,
105*4882a593Smuzhiyun MADERA_DSP6_CONFIG_1,
106*4882a593Smuzhiyun MADERA_DSP7_CONFIG_1,
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
cs47l90_adsp_power_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)109*4882a593Smuzhiyun static int cs47l90_adsp_power_ev(struct snd_soc_dapm_widget *w,
110*4882a593Smuzhiyun struct snd_kcontrol *kcontrol,
111*4882a593Smuzhiyun int event)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct snd_soc_component *component =
114*4882a593Smuzhiyun snd_soc_dapm_to_component(w->dapm);
115*4882a593Smuzhiyun struct cs47l90 *cs47l90 = snd_soc_component_get_drvdata(component);
116*4882a593Smuzhiyun struct madera_priv *priv = &cs47l90->core;
117*4882a593Smuzhiyun struct madera *madera = priv->madera;
118*4882a593Smuzhiyun unsigned int freq;
119*4882a593Smuzhiyun int ret;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun ret = regmap_read(madera->regmap, MADERA_DSP_CLOCK_2, &freq);
122*4882a593Smuzhiyun if (ret != 0) {
123*4882a593Smuzhiyun dev_err(madera->dev,
124*4882a593Smuzhiyun "Failed to read MADERA_DSP_CLOCK_2: %d\n", ret);
125*4882a593Smuzhiyun return ret;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun switch (event) {
129*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
130*4882a593Smuzhiyun ret = madera_set_adsp_clk(&cs47l90->core, w->shift, freq);
131*4882a593Smuzhiyun if (ret)
132*4882a593Smuzhiyun return ret;
133*4882a593Smuzhiyun break;
134*4882a593Smuzhiyun default:
135*4882a593Smuzhiyun break;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun return wm_adsp_early_event(w, kcontrol, event);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #define CS47L90_NG_SRC(name, base) \
142*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
143*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
144*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \
145*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \
146*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \
147*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \
148*4882a593Smuzhiyun SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
149*4882a593Smuzhiyun SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0)
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun #define CS47L90_RXANC_INPUT_ROUTES(widget, name) \
152*4882a593Smuzhiyun { widget, NULL, name " NG Mux" }, \
153*4882a593Smuzhiyun { name " NG Internal", NULL, "RXANC NG Clock" }, \
154*4882a593Smuzhiyun { name " NG Internal", NULL, name " Channel" }, \
155*4882a593Smuzhiyun { name " NG External", NULL, "RXANC NG External Clock" }, \
156*4882a593Smuzhiyun { name " NG External", NULL, name " Channel" }, \
157*4882a593Smuzhiyun { name " NG Mux", "None", name " Channel" }, \
158*4882a593Smuzhiyun { name " NG Mux", "Internal", name " NG Internal" }, \
159*4882a593Smuzhiyun { name " NG Mux", "External", name " NG External" }, \
160*4882a593Smuzhiyun { name " Channel", "Left", name " Left Input" }, \
161*4882a593Smuzhiyun { name " Channel", "Combine", name " Left Input" }, \
162*4882a593Smuzhiyun { name " Channel", "Right", name " Right Input" }, \
163*4882a593Smuzhiyun { name " Channel", "Combine", name " Right Input" }, \
164*4882a593Smuzhiyun { name " Left Input", "IN1", "IN1L" }, \
165*4882a593Smuzhiyun { name " Right Input", "IN1", "IN1R" }, \
166*4882a593Smuzhiyun { name " Left Input", "IN2", "IN2L" }, \
167*4882a593Smuzhiyun { name " Right Input", "IN2", "IN2R" }, \
168*4882a593Smuzhiyun { name " Left Input", "IN3", "IN3L" }, \
169*4882a593Smuzhiyun { name " Right Input", "IN3", "IN3R" }, \
170*4882a593Smuzhiyun { name " Left Input", "IN4", "IN4L" }, \
171*4882a593Smuzhiyun { name " Right Input", "IN4", "IN4R" }, \
172*4882a593Smuzhiyun { name " Left Input", "IN5", "IN5L" }, \
173*4882a593Smuzhiyun { name " Right Input", "IN5", "IN5R" }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun #define CS47L90_RXANC_OUTPUT_ROUTES(widget, name) \
176*4882a593Smuzhiyun { widget, NULL, name " ANC Source" }, \
177*4882a593Smuzhiyun { name " ANC Source", "RXANCL", "RXANCL" }, \
178*4882a593Smuzhiyun { name " ANC Source", "RXANCR", "RXANCR" }
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l90_snd_controls[] = {
181*4882a593Smuzhiyun SOC_ENUM("IN1 OSR", madera_in_dmic_osr[0]),
182*4882a593Smuzhiyun SOC_ENUM("IN2 OSR", madera_in_dmic_osr[1]),
183*4882a593Smuzhiyun SOC_ENUM("IN3 OSR", madera_in_dmic_osr[2]),
184*4882a593Smuzhiyun SOC_ENUM("IN4 OSR", madera_in_dmic_osr[3]),
185*4882a593Smuzhiyun SOC_ENUM("IN5 OSR", madera_in_dmic_osr[4]),
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN1L Volume", MADERA_IN1L_CONTROL,
188*4882a593Smuzhiyun MADERA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
189*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN1R Volume", MADERA_IN1R_CONTROL,
190*4882a593Smuzhiyun MADERA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
191*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN2L Volume", MADERA_IN2L_CONTROL,
192*4882a593Smuzhiyun MADERA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
193*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN2R Volume", MADERA_IN2R_CONTROL,
194*4882a593Smuzhiyun MADERA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun SOC_ENUM("IN HPF Cutoff Frequency", madera_in_hpf_cut_enum),
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun SOC_SINGLE_EXT("IN1L LP Switch", MADERA_ADC_DIGITAL_VOLUME_1L,
199*4882a593Smuzhiyun MADERA_IN1L_LP_MODE_SHIFT, 1, 0,
200*4882a593Smuzhiyun snd_soc_get_volsw, madera_lp_mode_put),
201*4882a593Smuzhiyun SOC_SINGLE_EXT("IN1R LP Switch", MADERA_ADC_DIGITAL_VOLUME_1R,
202*4882a593Smuzhiyun MADERA_IN1R_LP_MODE_SHIFT, 1, 0,
203*4882a593Smuzhiyun snd_soc_get_volsw, madera_lp_mode_put),
204*4882a593Smuzhiyun SOC_SINGLE_EXT("IN2L LP Switch", MADERA_ADC_DIGITAL_VOLUME_2L,
205*4882a593Smuzhiyun MADERA_IN2L_LP_MODE_SHIFT, 1, 0,
206*4882a593Smuzhiyun snd_soc_get_volsw, madera_lp_mode_put),
207*4882a593Smuzhiyun SOC_SINGLE_EXT("IN2R LP Switch", MADERA_ADC_DIGITAL_VOLUME_2R,
208*4882a593Smuzhiyun MADERA_IN2R_LP_MODE_SHIFT, 1, 0,
209*4882a593Smuzhiyun snd_soc_get_volsw, madera_lp_mode_put),
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun SOC_SINGLE("IN1L HPF Switch", MADERA_IN1L_CONTROL,
212*4882a593Smuzhiyun MADERA_IN1L_HPF_SHIFT, 1, 0),
213*4882a593Smuzhiyun SOC_SINGLE("IN1R HPF Switch", MADERA_IN1R_CONTROL,
214*4882a593Smuzhiyun MADERA_IN1R_HPF_SHIFT, 1, 0),
215*4882a593Smuzhiyun SOC_SINGLE("IN2L HPF Switch", MADERA_IN2L_CONTROL,
216*4882a593Smuzhiyun MADERA_IN2L_HPF_SHIFT, 1, 0),
217*4882a593Smuzhiyun SOC_SINGLE("IN2R HPF Switch", MADERA_IN2R_CONTROL,
218*4882a593Smuzhiyun MADERA_IN2R_HPF_SHIFT, 1, 0),
219*4882a593Smuzhiyun SOC_SINGLE("IN3L HPF Switch", MADERA_IN3L_CONTROL,
220*4882a593Smuzhiyun MADERA_IN3L_HPF_SHIFT, 1, 0),
221*4882a593Smuzhiyun SOC_SINGLE("IN3R HPF Switch", MADERA_IN3R_CONTROL,
222*4882a593Smuzhiyun MADERA_IN3R_HPF_SHIFT, 1, 0),
223*4882a593Smuzhiyun SOC_SINGLE("IN4L HPF Switch", MADERA_IN4L_CONTROL,
224*4882a593Smuzhiyun MADERA_IN4L_HPF_SHIFT, 1, 0),
225*4882a593Smuzhiyun SOC_SINGLE("IN4R HPF Switch", MADERA_IN4R_CONTROL,
226*4882a593Smuzhiyun MADERA_IN4R_HPF_SHIFT, 1, 0),
227*4882a593Smuzhiyun SOC_SINGLE("IN5L HPF Switch", MADERA_IN5L_CONTROL,
228*4882a593Smuzhiyun MADERA_IN5L_HPF_SHIFT, 1, 0),
229*4882a593Smuzhiyun SOC_SINGLE("IN5R HPF Switch", MADERA_IN5R_CONTROL,
230*4882a593Smuzhiyun MADERA_IN5R_HPF_SHIFT, 1, 0),
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1L,
233*4882a593Smuzhiyun MADERA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
234*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1R,
235*4882a593Smuzhiyun MADERA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
236*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2L,
237*4882a593Smuzhiyun MADERA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
238*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2R,
239*4882a593Smuzhiyun MADERA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
240*4882a593Smuzhiyun SOC_SINGLE_TLV("IN3L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3L,
241*4882a593Smuzhiyun MADERA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
242*4882a593Smuzhiyun SOC_SINGLE_TLV("IN3R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3R,
243*4882a593Smuzhiyun MADERA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
244*4882a593Smuzhiyun SOC_SINGLE_TLV("IN4L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4L,
245*4882a593Smuzhiyun MADERA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
246*4882a593Smuzhiyun SOC_SINGLE_TLV("IN4R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4R,
247*4882a593Smuzhiyun MADERA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
248*4882a593Smuzhiyun SOC_SINGLE_TLV("IN5L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_5L,
249*4882a593Smuzhiyun MADERA_IN5L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
250*4882a593Smuzhiyun SOC_SINGLE_TLV("IN5R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_5R,
251*4882a593Smuzhiyun MADERA_IN5R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun SOC_ENUM("Input Ramp Up", madera_in_vi_ramp),
254*4882a593Smuzhiyun SOC_ENUM("Input Ramp Down", madera_in_vd_ramp),
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun SND_SOC_BYTES("RXANC Coefficients", MADERA_ANC_COEFF_START,
257*4882a593Smuzhiyun MADERA_ANC_COEFF_END - MADERA_ANC_COEFF_START + 1),
258*4882a593Smuzhiyun SND_SOC_BYTES("RXANCL Config", MADERA_FCL_FILTER_CONTROL, 1),
259*4882a593Smuzhiyun SND_SOC_BYTES("RXANCL Coefficients", MADERA_FCL_COEFF_START,
260*4882a593Smuzhiyun MADERA_FCL_COEFF_END - MADERA_FCL_COEFF_START + 1),
261*4882a593Smuzhiyun SND_SOC_BYTES("RXANCR Config", MADERA_FCR_FILTER_CONTROL, 1),
262*4882a593Smuzhiyun SND_SOC_BYTES("RXANCR Coefficients", MADERA_FCR_COEFF_START,
263*4882a593Smuzhiyun MADERA_FCR_COEFF_END - MADERA_FCR_COEFF_START + 1),
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ1", MADERA_EQ1MIX_INPUT_1_SOURCE),
266*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ2", MADERA_EQ2MIX_INPUT_1_SOURCE),
267*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ3", MADERA_EQ3MIX_INPUT_1_SOURCE),
268*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ4", MADERA_EQ4MIX_INPUT_1_SOURCE),
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ1 Coefficients", MADERA_EQ1_2),
271*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B1 Volume", MADERA_EQ1_1, MADERA_EQ1_B1_GAIN_SHIFT,
272*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
273*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B2 Volume", MADERA_EQ1_1, MADERA_EQ1_B2_GAIN_SHIFT,
274*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
275*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B3 Volume", MADERA_EQ1_1, MADERA_EQ1_B3_GAIN_SHIFT,
276*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
277*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B4 Volume", MADERA_EQ1_2, MADERA_EQ1_B4_GAIN_SHIFT,
278*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
279*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B5 Volume", MADERA_EQ1_2, MADERA_EQ1_B5_GAIN_SHIFT,
280*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ2 Coefficients", MADERA_EQ2_2),
283*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B1 Volume", MADERA_EQ2_1, MADERA_EQ2_B1_GAIN_SHIFT,
284*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
285*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B2 Volume", MADERA_EQ2_1, MADERA_EQ2_B2_GAIN_SHIFT,
286*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
287*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B3 Volume", MADERA_EQ2_1, MADERA_EQ2_B3_GAIN_SHIFT,
288*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
289*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B4 Volume", MADERA_EQ2_2, MADERA_EQ2_B4_GAIN_SHIFT,
290*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
291*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B5 Volume", MADERA_EQ2_2, MADERA_EQ2_B5_GAIN_SHIFT,
292*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ3 Coefficients", MADERA_EQ3_2),
295*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B1 Volume", MADERA_EQ3_1, MADERA_EQ3_B1_GAIN_SHIFT,
296*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
297*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B2 Volume", MADERA_EQ3_1, MADERA_EQ3_B2_GAIN_SHIFT,
298*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
299*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B3 Volume", MADERA_EQ3_1, MADERA_EQ3_B3_GAIN_SHIFT,
300*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
301*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B4 Volume", MADERA_EQ3_2, MADERA_EQ3_B4_GAIN_SHIFT,
302*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
303*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B5 Volume", MADERA_EQ3_2, MADERA_EQ3_B5_GAIN_SHIFT,
304*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ4 Coefficients", MADERA_EQ4_2),
307*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B1 Volume", MADERA_EQ4_1, MADERA_EQ4_B1_GAIN_SHIFT,
308*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
309*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B2 Volume", MADERA_EQ4_1, MADERA_EQ4_B2_GAIN_SHIFT,
310*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
311*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B3 Volume", MADERA_EQ4_1, MADERA_EQ4_B3_GAIN_SHIFT,
312*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
313*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B4 Volume", MADERA_EQ4_2, MADERA_EQ4_B4_GAIN_SHIFT,
314*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
315*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B5 Volume", MADERA_EQ4_2, MADERA_EQ4_B5_GAIN_SHIFT,
316*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC1L", MADERA_DRC1LMIX_INPUT_1_SOURCE),
319*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC1R", MADERA_DRC1RMIX_INPUT_1_SOURCE),
320*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC2L", MADERA_DRC2LMIX_INPUT_1_SOURCE),
321*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC2R", MADERA_DRC2RMIX_INPUT_1_SOURCE),
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun SND_SOC_BYTES_MASK("DRC1", MADERA_DRC1_CTRL1, 5,
324*4882a593Smuzhiyun MADERA_DRC1R_ENA | MADERA_DRC1L_ENA),
325*4882a593Smuzhiyun SND_SOC_BYTES_MASK("DRC2", MADERA_DRC2_CTRL1, 5,
326*4882a593Smuzhiyun MADERA_DRC2R_ENA | MADERA_DRC2L_ENA),
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF1", MADERA_HPLP1MIX_INPUT_1_SOURCE),
329*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF2", MADERA_HPLP2MIX_INPUT_1_SOURCE),
330*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF3", MADERA_HPLP3MIX_INPUT_1_SOURCE),
331*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF4", MADERA_HPLP4MIX_INPUT_1_SOURCE),
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF1 Coefficients", MADERA_HPLPF1_2),
334*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF2 Coefficients", MADERA_HPLPF2_2),
335*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF3 Coefficients", MADERA_HPLPF3_2),
336*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF4 Coefficients", MADERA_HPLPF4_2),
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun SOC_ENUM("LHPF1 Mode", madera_lhpf1_mode),
339*4882a593Smuzhiyun SOC_ENUM("LHPF2 Mode", madera_lhpf2_mode),
340*4882a593Smuzhiyun SOC_ENUM("LHPF3 Mode", madera_lhpf3_mode),
341*4882a593Smuzhiyun SOC_ENUM("LHPF4 Mode", madera_lhpf4_mode),
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC1 FSL", madera_isrc_fsl[0]),
344*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC2 FSL", madera_isrc_fsl[1]),
345*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC3 FSL", madera_isrc_fsl[2]),
346*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC4 FSL", madera_isrc_fsl[3]),
347*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC1 FSH", madera_isrc_fsh[0]),
348*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC2 FSH", madera_isrc_fsh[1]),
349*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC3 FSH", madera_isrc_fsh[2]),
350*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC4 FSH", madera_isrc_fsh[3]),
351*4882a593Smuzhiyun MADERA_RATE_ENUM("ASRC1 Rate 1", madera_asrc1_rate[0]),
352*4882a593Smuzhiyun MADERA_RATE_ENUM("ASRC1 Rate 2", madera_asrc1_rate[1]),
353*4882a593Smuzhiyun MADERA_RATE_ENUM("ASRC2 Rate 1", madera_asrc2_rate[0]),
354*4882a593Smuzhiyun MADERA_RATE_ENUM("ASRC2 Rate 2", madera_asrc2_rate[1]),
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
357*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP2", 2),
358*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP3", 3),
359*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP4", 4),
360*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP5", 5),
361*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP6", 6),
362*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP7", 7),
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP1L", MADERA_DSP1LMIX_INPUT_1_SOURCE),
365*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP1R", MADERA_DSP1RMIX_INPUT_1_SOURCE),
366*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP2L", MADERA_DSP2LMIX_INPUT_1_SOURCE),
367*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP2R", MADERA_DSP2RMIX_INPUT_1_SOURCE),
368*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP3L", MADERA_DSP3LMIX_INPUT_1_SOURCE),
369*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP3R", MADERA_DSP3RMIX_INPUT_1_SOURCE),
370*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP4L", MADERA_DSP4LMIX_INPUT_1_SOURCE),
371*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP4R", MADERA_DSP4RMIX_INPUT_1_SOURCE),
372*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP5L", MADERA_DSP5LMIX_INPUT_1_SOURCE),
373*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP5R", MADERA_DSP5RMIX_INPUT_1_SOURCE),
374*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP6L", MADERA_DSP6LMIX_INPUT_1_SOURCE),
375*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP6R", MADERA_DSP6RMIX_INPUT_1_SOURCE),
376*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP7L", MADERA_DSP7LMIX_INPUT_1_SOURCE),
377*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP7R", MADERA_DSP7RMIX_INPUT_1_SOURCE),
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Generator Volume", MADERA_COMFORT_NOISE_GENERATOR,
380*4882a593Smuzhiyun MADERA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, madera_noise_tlv),
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT1L", MADERA_OUT1LMIX_INPUT_1_SOURCE),
383*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT1R", MADERA_OUT1RMIX_INPUT_1_SOURCE),
384*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT2L", MADERA_OUT2LMIX_INPUT_1_SOURCE),
385*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT2R", MADERA_OUT2RMIX_INPUT_1_SOURCE),
386*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT3L", MADERA_OUT3LMIX_INPUT_1_SOURCE),
387*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT3R", MADERA_OUT3RMIX_INPUT_1_SOURCE),
388*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT1L", MADERA_OUT5LMIX_INPUT_1_SOURCE),
389*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT1R", MADERA_OUT5RMIX_INPUT_1_SOURCE),
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun SOC_SINGLE("HPOUT1 SC Protect Switch", MADERA_HP1_SHORT_CIRCUIT_CTRL,
392*4882a593Smuzhiyun MADERA_HP1_SC_ENA_SHIFT, 1, 0),
393*4882a593Smuzhiyun SOC_SINGLE("HPOUT2 SC Protect Switch", MADERA_HP2_SHORT_CIRCUIT_CTRL,
394*4882a593Smuzhiyun MADERA_HP2_SC_ENA_SHIFT, 1, 0),
395*4882a593Smuzhiyun SOC_SINGLE("HPOUT3 SC Protect Switch", MADERA_HP3_SHORT_CIRCUIT_CTRL,
396*4882a593Smuzhiyun MADERA_HP3_SC_ENA_SHIFT, 1, 0),
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun SOC_SINGLE("SPKDAT1 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_5L,
399*4882a593Smuzhiyun MADERA_OUT5_OSR_SHIFT, 1, 0),
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_1L,
402*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_MUTE_SHIFT, 1, 1),
403*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT2 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_2L,
404*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_MUTE_SHIFT, 1, 1),
405*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT3 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_3L,
406*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_MUTE_SHIFT, 1, 1),
407*4882a593Smuzhiyun SOC_DOUBLE_R("SPKDAT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_5L,
408*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_MUTE_SHIFT, 1, 1),
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_1L,
411*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_VOL_SHIFT,
412*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
413*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_2L,
414*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_VOL_SHIFT,
415*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
416*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_3L,
417*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_VOL_SHIFT,
418*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
419*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_5L,
420*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_VOL_SHIFT,
421*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun SOC_DOUBLE("SPKDAT1 Switch", MADERA_PDM_SPK1_CTRL_1, MADERA_SPK1L_MUTE_SHIFT,
424*4882a593Smuzhiyun MADERA_SPK1R_MUTE_SHIFT, 1, 1),
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun SOC_ENUM("Output Ramp Up", madera_out_vi_ramp),
427*4882a593Smuzhiyun SOC_ENUM("Output Ramp Down", madera_out_vd_ramp),
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun SOC_SINGLE("Noise Gate Switch", MADERA_NOISE_GATE_CONTROL,
430*4882a593Smuzhiyun MADERA_NGATE_ENA_SHIFT, 1, 0),
431*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Gate Threshold Volume", MADERA_NOISE_GATE_CONTROL,
432*4882a593Smuzhiyun MADERA_NGATE_THR_SHIFT, 7, 1, madera_ng_tlv),
433*4882a593Smuzhiyun SOC_ENUM("Noise Gate Hold", madera_ng_hold),
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun SOC_ENUM_EXT("DFC1RX Width", madera_dfc_width[0],
436*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
437*4882a593Smuzhiyun SOC_ENUM_EXT("DFC1RX Type", madera_dfc_type[0],
438*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
439*4882a593Smuzhiyun SOC_ENUM_EXT("DFC1TX Width", madera_dfc_width[1],
440*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
441*4882a593Smuzhiyun SOC_ENUM_EXT("DFC1TX Type", madera_dfc_type[1],
442*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
443*4882a593Smuzhiyun SOC_ENUM_EXT("DFC2RX Width", madera_dfc_width[2],
444*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
445*4882a593Smuzhiyun SOC_ENUM_EXT("DFC2RX Type", madera_dfc_type[2],
446*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
447*4882a593Smuzhiyun SOC_ENUM_EXT("DFC2TX Width", madera_dfc_width[3],
448*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
449*4882a593Smuzhiyun SOC_ENUM_EXT("DFC2TX Type", madera_dfc_type[3],
450*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
451*4882a593Smuzhiyun SOC_ENUM_EXT("DFC3RX Width", madera_dfc_width[4],
452*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
453*4882a593Smuzhiyun SOC_ENUM_EXT("DFC3RX Type", madera_dfc_type[4],
454*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
455*4882a593Smuzhiyun SOC_ENUM_EXT("DFC3TX Width", madera_dfc_width[5],
456*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
457*4882a593Smuzhiyun SOC_ENUM_EXT("DFC3TX Type", madera_dfc_type[5],
458*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
459*4882a593Smuzhiyun SOC_ENUM_EXT("DFC4RX Width", madera_dfc_width[6],
460*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
461*4882a593Smuzhiyun SOC_ENUM_EXT("DFC4RX Type", madera_dfc_type[6],
462*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
463*4882a593Smuzhiyun SOC_ENUM_EXT("DFC4TX Width", madera_dfc_width[7],
464*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
465*4882a593Smuzhiyun SOC_ENUM_EXT("DFC4TX Type", madera_dfc_type[7],
466*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
467*4882a593Smuzhiyun SOC_ENUM_EXT("DFC5RX Width", madera_dfc_width[8],
468*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
469*4882a593Smuzhiyun SOC_ENUM_EXT("DFC5RX Type", madera_dfc_type[8],
470*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
471*4882a593Smuzhiyun SOC_ENUM_EXT("DFC5TX Width", madera_dfc_width[9],
472*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
473*4882a593Smuzhiyun SOC_ENUM_EXT("DFC5TX Type", madera_dfc_type[9],
474*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
475*4882a593Smuzhiyun SOC_ENUM_EXT("DFC6RX Width", madera_dfc_width[10],
476*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
477*4882a593Smuzhiyun SOC_ENUM_EXT("DFC6RX Type", madera_dfc_type[10],
478*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
479*4882a593Smuzhiyun SOC_ENUM_EXT("DFC6TX Width", madera_dfc_width[11],
480*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
481*4882a593Smuzhiyun SOC_ENUM_EXT("DFC6TX Type", madera_dfc_type[11],
482*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
483*4882a593Smuzhiyun SOC_ENUM_EXT("DFC7RX Width", madera_dfc_width[12],
484*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
485*4882a593Smuzhiyun SOC_ENUM_EXT("DFC7RX Type", madera_dfc_type[12],
486*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
487*4882a593Smuzhiyun SOC_ENUM_EXT("DFC7TX Width", madera_dfc_width[13],
488*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
489*4882a593Smuzhiyun SOC_ENUM_EXT("DFC7TX Type", madera_dfc_type[13],
490*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
491*4882a593Smuzhiyun SOC_ENUM_EXT("DFC8RX Width", madera_dfc_width[14],
492*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
493*4882a593Smuzhiyun SOC_ENUM_EXT("DFC8RX Type", madera_dfc_type[14],
494*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
495*4882a593Smuzhiyun SOC_ENUM_EXT("DFC8TX Width", madera_dfc_width[15],
496*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
497*4882a593Smuzhiyun SOC_ENUM_EXT("DFC8TX Type", madera_dfc_type[15],
498*4882a593Smuzhiyun snd_soc_get_enum_double, madera_dfc_put),
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun CS47L90_NG_SRC("HPOUT1L", MADERA_NOISE_GATE_SELECT_1L),
501*4882a593Smuzhiyun CS47L90_NG_SRC("HPOUT1R", MADERA_NOISE_GATE_SELECT_1R),
502*4882a593Smuzhiyun CS47L90_NG_SRC("HPOUT2L", MADERA_NOISE_GATE_SELECT_2L),
503*4882a593Smuzhiyun CS47L90_NG_SRC("HPOUT2R", MADERA_NOISE_GATE_SELECT_2R),
504*4882a593Smuzhiyun CS47L90_NG_SRC("HPOUT3L", MADERA_NOISE_GATE_SELECT_3L),
505*4882a593Smuzhiyun CS47L90_NG_SRC("HPOUT3R", MADERA_NOISE_GATE_SELECT_3R),
506*4882a593Smuzhiyun CS47L90_NG_SRC("SPKDAT1L", MADERA_NOISE_GATE_SELECT_5L),
507*4882a593Smuzhiyun CS47L90_NG_SRC("SPKDAT1R", MADERA_NOISE_GATE_SELECT_5R),
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX1", MADERA_AIF1TX1MIX_INPUT_1_SOURCE),
510*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX2", MADERA_AIF1TX2MIX_INPUT_1_SOURCE),
511*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX3", MADERA_AIF1TX3MIX_INPUT_1_SOURCE),
512*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX4", MADERA_AIF1TX4MIX_INPUT_1_SOURCE),
513*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX5", MADERA_AIF1TX5MIX_INPUT_1_SOURCE),
514*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX6", MADERA_AIF1TX6MIX_INPUT_1_SOURCE),
515*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX7", MADERA_AIF1TX7MIX_INPUT_1_SOURCE),
516*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX8", MADERA_AIF1TX8MIX_INPUT_1_SOURCE),
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX1", MADERA_AIF2TX1MIX_INPUT_1_SOURCE),
519*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX2", MADERA_AIF2TX2MIX_INPUT_1_SOURCE),
520*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX3", MADERA_AIF2TX3MIX_INPUT_1_SOURCE),
521*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX4", MADERA_AIF2TX4MIX_INPUT_1_SOURCE),
522*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX5", MADERA_AIF2TX5MIX_INPUT_1_SOURCE),
523*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX6", MADERA_AIF2TX6MIX_INPUT_1_SOURCE),
524*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX7", MADERA_AIF2TX7MIX_INPUT_1_SOURCE),
525*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX8", MADERA_AIF2TX8MIX_INPUT_1_SOURCE),
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX1", MADERA_AIF3TX1MIX_INPUT_1_SOURCE),
528*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX2", MADERA_AIF3TX2MIX_INPUT_1_SOURCE),
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF4TX1", MADERA_AIF4TX1MIX_INPUT_1_SOURCE),
531*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF4TX2", MADERA_AIF4TX2MIX_INPUT_1_SOURCE),
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX1", MADERA_SLIMTX1MIX_INPUT_1_SOURCE),
534*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX2", MADERA_SLIMTX2MIX_INPUT_1_SOURCE),
535*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX3", MADERA_SLIMTX3MIX_INPUT_1_SOURCE),
536*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX4", MADERA_SLIMTX4MIX_INPUT_1_SOURCE),
537*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX5", MADERA_SLIMTX5MIX_INPUT_1_SOURCE),
538*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX6", MADERA_SLIMTX6MIX_INPUT_1_SOURCE),
539*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX7", MADERA_SLIMTX7MIX_INPUT_1_SOURCE),
540*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX8", MADERA_SLIMTX8MIX_INPUT_1_SOURCE),
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun MADERA_GAINMUX_CONTROLS("SPDIF1TX1", MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE),
543*4882a593Smuzhiyun MADERA_GAINMUX_CONTROLS("SPDIF1TX2", MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE),
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP1", 0),
546*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP2", 1),
547*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP3", 2),
548*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP4", 3),
549*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP5", 4),
550*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP6", 5),
551*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP7", 6),
552*4882a593Smuzhiyun };
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ1, MADERA_EQ1MIX_INPUT_1_SOURCE);
555*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ2, MADERA_EQ2MIX_INPUT_1_SOURCE);
556*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ3, MADERA_EQ3MIX_INPUT_1_SOURCE);
557*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ4, MADERA_EQ4MIX_INPUT_1_SOURCE);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC1L, MADERA_DRC1LMIX_INPUT_1_SOURCE);
560*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC1R, MADERA_DRC1RMIX_INPUT_1_SOURCE);
561*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC2L, MADERA_DRC2LMIX_INPUT_1_SOURCE);
562*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC2R, MADERA_DRC2RMIX_INPUT_1_SOURCE);
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF1, MADERA_HPLP1MIX_INPUT_1_SOURCE);
565*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF2, MADERA_HPLP2MIX_INPUT_1_SOURCE);
566*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF3, MADERA_HPLP3MIX_INPUT_1_SOURCE);
567*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF4, MADERA_HPLP4MIX_INPUT_1_SOURCE);
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP1L, MADERA_DSP1LMIX_INPUT_1_SOURCE);
570*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP1R, MADERA_DSP1RMIX_INPUT_1_SOURCE);
571*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP1, MADERA_DSP1AUX1MIX_INPUT_1_SOURCE);
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP2L, MADERA_DSP2LMIX_INPUT_1_SOURCE);
574*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP2R, MADERA_DSP2RMIX_INPUT_1_SOURCE);
575*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP2, MADERA_DSP2AUX1MIX_INPUT_1_SOURCE);
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP3L, MADERA_DSP3LMIX_INPUT_1_SOURCE);
578*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP3R, MADERA_DSP3RMIX_INPUT_1_SOURCE);
579*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP3, MADERA_DSP3AUX1MIX_INPUT_1_SOURCE);
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP4L, MADERA_DSP4LMIX_INPUT_1_SOURCE);
582*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP4R, MADERA_DSP4RMIX_INPUT_1_SOURCE);
583*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP4, MADERA_DSP4AUX1MIX_INPUT_1_SOURCE);
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP5L, MADERA_DSP5LMIX_INPUT_1_SOURCE);
586*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP5R, MADERA_DSP5RMIX_INPUT_1_SOURCE);
587*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP5, MADERA_DSP5AUX1MIX_INPUT_1_SOURCE);
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP6L, MADERA_DSP6LMIX_INPUT_1_SOURCE);
590*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP6R, MADERA_DSP6RMIX_INPUT_1_SOURCE);
591*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP6, MADERA_DSP6AUX1MIX_INPUT_1_SOURCE);
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP7L, MADERA_DSP7LMIX_INPUT_1_SOURCE);
594*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP7R, MADERA_DSP7RMIX_INPUT_1_SOURCE);
595*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP7, MADERA_DSP7AUX1MIX_INPUT_1_SOURCE);
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun MADERA_MIXER_ENUMS(PWM1, MADERA_PWM1MIX_INPUT_1_SOURCE);
598*4882a593Smuzhiyun MADERA_MIXER_ENUMS(PWM2, MADERA_PWM2MIX_INPUT_1_SOURCE);
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT1L, MADERA_OUT1LMIX_INPUT_1_SOURCE);
601*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT1R, MADERA_OUT1RMIX_INPUT_1_SOURCE);
602*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT2L, MADERA_OUT2LMIX_INPUT_1_SOURCE);
603*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT2R, MADERA_OUT2RMIX_INPUT_1_SOURCE);
604*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT3L, MADERA_OUT3LMIX_INPUT_1_SOURCE);
605*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT3R, MADERA_OUT3RMIX_INPUT_1_SOURCE);
606*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT1L, MADERA_OUT5LMIX_INPUT_1_SOURCE);
607*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT1R, MADERA_OUT5RMIX_INPUT_1_SOURCE);
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX1, MADERA_AIF1TX1MIX_INPUT_1_SOURCE);
610*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX2, MADERA_AIF1TX2MIX_INPUT_1_SOURCE);
611*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX3, MADERA_AIF1TX3MIX_INPUT_1_SOURCE);
612*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX4, MADERA_AIF1TX4MIX_INPUT_1_SOURCE);
613*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX5, MADERA_AIF1TX5MIX_INPUT_1_SOURCE);
614*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX6, MADERA_AIF1TX6MIX_INPUT_1_SOURCE);
615*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX7, MADERA_AIF1TX7MIX_INPUT_1_SOURCE);
616*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX8, MADERA_AIF1TX8MIX_INPUT_1_SOURCE);
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX1, MADERA_AIF2TX1MIX_INPUT_1_SOURCE);
619*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX2, MADERA_AIF2TX2MIX_INPUT_1_SOURCE);
620*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX3, MADERA_AIF2TX3MIX_INPUT_1_SOURCE);
621*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX4, MADERA_AIF2TX4MIX_INPUT_1_SOURCE);
622*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX5, MADERA_AIF2TX5MIX_INPUT_1_SOURCE);
623*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX6, MADERA_AIF2TX6MIX_INPUT_1_SOURCE);
624*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX7, MADERA_AIF2TX7MIX_INPUT_1_SOURCE);
625*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX8, MADERA_AIF2TX8MIX_INPUT_1_SOURCE);
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX1, MADERA_AIF3TX1MIX_INPUT_1_SOURCE);
628*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX2, MADERA_AIF3TX2MIX_INPUT_1_SOURCE);
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF4TX1, MADERA_AIF4TX1MIX_INPUT_1_SOURCE);
631*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF4TX2, MADERA_AIF4TX2MIX_INPUT_1_SOURCE);
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX1, MADERA_SLIMTX1MIX_INPUT_1_SOURCE);
634*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX2, MADERA_SLIMTX2MIX_INPUT_1_SOURCE);
635*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX3, MADERA_SLIMTX3MIX_INPUT_1_SOURCE);
636*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX4, MADERA_SLIMTX4MIX_INPUT_1_SOURCE);
637*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX5, MADERA_SLIMTX5MIX_INPUT_1_SOURCE);
638*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX6, MADERA_SLIMTX6MIX_INPUT_1_SOURCE);
639*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX7, MADERA_SLIMTX7MIX_INPUT_1_SOURCE);
640*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX8, MADERA_SLIMTX8MIX_INPUT_1_SOURCE);
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun MADERA_MUX_ENUMS(SPD1TX1, MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE);
643*4882a593Smuzhiyun MADERA_MUX_ENUMS(SPD1TX2, MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE);
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN1L, MADERA_ASRC1_1LMIX_INPUT_1_SOURCE);
646*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN1R, MADERA_ASRC1_1RMIX_INPUT_1_SOURCE);
647*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN2L, MADERA_ASRC1_2LMIX_INPUT_1_SOURCE);
648*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN2R, MADERA_ASRC1_2RMIX_INPUT_1_SOURCE);
649*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC2IN1L, MADERA_ASRC2_1LMIX_INPUT_1_SOURCE);
650*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC2IN1R, MADERA_ASRC2_1RMIX_INPUT_1_SOURCE);
651*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC2IN2L, MADERA_ASRC2_2LMIX_INPUT_1_SOURCE);
652*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC2IN2R, MADERA_ASRC2_2RMIX_INPUT_1_SOURCE);
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT1, MADERA_ISRC1INT1MIX_INPUT_1_SOURCE);
655*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT2, MADERA_ISRC1INT2MIX_INPUT_1_SOURCE);
656*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT3, MADERA_ISRC1INT3MIX_INPUT_1_SOURCE);
657*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT4, MADERA_ISRC1INT4MIX_INPUT_1_SOURCE);
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC1, MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE);
660*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC2, MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE);
661*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC3, MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE);
662*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC4, MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE);
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT1, MADERA_ISRC2INT1MIX_INPUT_1_SOURCE);
665*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT2, MADERA_ISRC2INT2MIX_INPUT_1_SOURCE);
666*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT3, MADERA_ISRC2INT3MIX_INPUT_1_SOURCE);
667*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT4, MADERA_ISRC2INT4MIX_INPUT_1_SOURCE);
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC1, MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE);
670*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC2, MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE);
671*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC3, MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE);
672*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC4, MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE);
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC3INT1, MADERA_ISRC3INT1MIX_INPUT_1_SOURCE);
675*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC3INT2, MADERA_ISRC3INT2MIX_INPUT_1_SOURCE);
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC3DEC1, MADERA_ISRC3DEC1MIX_INPUT_1_SOURCE);
678*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC3DEC2, MADERA_ISRC3DEC2MIX_INPUT_1_SOURCE);
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC4INT1, MADERA_ISRC4INT1MIX_INPUT_1_SOURCE);
681*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC4INT2, MADERA_ISRC4INT2MIX_INPUT_1_SOURCE);
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC4DEC1, MADERA_ISRC4DEC1MIX_INPUT_1_SOURCE);
684*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC4DEC2, MADERA_ISRC4DEC2MIX_INPUT_1_SOURCE);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC1, MADERA_DFC1MIX_INPUT_1_SOURCE);
687*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC2, MADERA_DFC2MIX_INPUT_1_SOURCE);
688*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC3, MADERA_DFC3MIX_INPUT_1_SOURCE);
689*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC4, MADERA_DFC4MIX_INPUT_1_SOURCE);
690*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC5, MADERA_DFC5MIX_INPUT_1_SOURCE);
691*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC6, MADERA_DFC6MIX_INPUT_1_SOURCE);
692*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC7, MADERA_DFC7MIX_INPUT_1_SOURCE);
693*4882a593Smuzhiyun MADERA_MUX_ENUMS(DFC8, MADERA_DFC8MIX_INPUT_1_SOURCE);
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun static const char * const cs47l90_aec_loopback_texts[] = {
696*4882a593Smuzhiyun "HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R",
697*4882a593Smuzhiyun "SPKDAT1L", "SPKDAT1R",
698*4882a593Smuzhiyun };
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun static const unsigned int cs47l90_aec_loopback_values[] = {
701*4882a593Smuzhiyun 0, 1, 2, 3, 4, 5, 8, 9,
702*4882a593Smuzhiyun };
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun static const struct soc_enum cs47l90_aec1_loopback =
705*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_1,
706*4882a593Smuzhiyun MADERA_AEC1_LOOPBACK_SRC_SHIFT, 0xf,
707*4882a593Smuzhiyun ARRAY_SIZE(cs47l90_aec_loopback_texts),
708*4882a593Smuzhiyun cs47l90_aec_loopback_texts,
709*4882a593Smuzhiyun cs47l90_aec_loopback_values);
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun static const struct soc_enum cs47l90_aec2_loopback =
712*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_2,
713*4882a593Smuzhiyun MADERA_AEC2_LOOPBACK_SRC_SHIFT, 0xf,
714*4882a593Smuzhiyun ARRAY_SIZE(cs47l90_aec_loopback_texts),
715*4882a593Smuzhiyun cs47l90_aec_loopback_texts,
716*4882a593Smuzhiyun cs47l90_aec_loopback_values);
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l90_aec_loopback_mux[] = {
719*4882a593Smuzhiyun SOC_DAPM_ENUM("AEC1 Loopback", cs47l90_aec1_loopback),
720*4882a593Smuzhiyun SOC_DAPM_ENUM("AEC2 Loopback", cs47l90_aec2_loopback),
721*4882a593Smuzhiyun };
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l90_anc_input_mux[] = {
724*4882a593Smuzhiyun SOC_DAPM_ENUM("RXANCL Input", madera_anc_input_src[0]),
725*4882a593Smuzhiyun SOC_DAPM_ENUM("RXANCL Channel", madera_anc_input_src[1]),
726*4882a593Smuzhiyun SOC_DAPM_ENUM("RXANCR Input", madera_anc_input_src[2]),
727*4882a593Smuzhiyun SOC_DAPM_ENUM("RXANCR Channel", madera_anc_input_src[3]),
728*4882a593Smuzhiyun };
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l90_anc_ng_mux =
731*4882a593Smuzhiyun SOC_DAPM_ENUM("RXANC NG Source", madera_anc_ng_enum);
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l90_output_anc_src[] = {
734*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT1L ANC Source", madera_output_anc_src[0]),
735*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT1R ANC Source", madera_output_anc_src[1]),
736*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT2L ANC Source", madera_output_anc_src[2]),
737*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT2R ANC Source", madera_output_anc_src[3]),
738*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT3L ANC Source", madera_output_anc_src[4]),
739*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT3R ANC Source", madera_output_anc_src[0]),
740*4882a593Smuzhiyun SOC_DAPM_ENUM("SPKDAT1L ANC Source", madera_output_anc_src[8]),
741*4882a593Smuzhiyun SOC_DAPM_ENUM("SPKDAT1R ANC Source", madera_output_anc_src[9]),
742*4882a593Smuzhiyun };
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun static const struct snd_soc_dapm_widget cs47l90_dapm_widgets[] = {
745*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SYSCLK", MADERA_SYSTEM_CLOCK_1, MADERA_SYSCLK_ENA_SHIFT,
746*4882a593Smuzhiyun 0, madera_sysclk_ev,
747*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
748*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
749*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASYNCCLK", MADERA_ASYNC_CLOCK_1,
750*4882a593Smuzhiyun MADERA_ASYNC_CLK_ENA_SHIFT, 0, madera_clk_ev,
751*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
752*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OPCLK", MADERA_OUTPUT_SYSTEM_CLOCK,
753*4882a593Smuzhiyun MADERA_OPCLK_ENA_SHIFT, 0, NULL, 0),
754*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", MADERA_OUTPUT_ASYNC_CLOCK,
755*4882a593Smuzhiyun MADERA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
756*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSPCLK", MADERA_DSP_CLOCK_1, MADERA_DSP_CLK_ENA_SHIFT,
757*4882a593Smuzhiyun 0, madera_clk_ev,
758*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
761*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
762*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD4", 0, 0),
763*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD1", 20, 0),
764*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD2", 20, 0),
765*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1", MADERA_MIC_BIAS_CTRL_1,
768*4882a593Smuzhiyun MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
769*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2", MADERA_MIC_BIAS_CTRL_2,
770*4882a593Smuzhiyun MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1A", MADERA_MIC_BIAS_CTRL_5,
773*4882a593Smuzhiyun MADERA_MICB1A_ENA_SHIFT, 0, NULL, 0),
774*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1B", MADERA_MIC_BIAS_CTRL_5,
775*4882a593Smuzhiyun MADERA_MICB1B_ENA_SHIFT, 0, NULL, 0),
776*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1C", MADERA_MIC_BIAS_CTRL_5,
777*4882a593Smuzhiyun MADERA_MICB1C_ENA_SHIFT, 0, NULL, 0),
778*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1D", MADERA_MIC_BIAS_CTRL_5,
779*4882a593Smuzhiyun MADERA_MICB1D_ENA_SHIFT, 0, NULL, 0),
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2A", MADERA_MIC_BIAS_CTRL_6,
782*4882a593Smuzhiyun MADERA_MICB2A_ENA_SHIFT, 0, NULL, 0),
783*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2B", MADERA_MIC_BIAS_CTRL_6,
784*4882a593Smuzhiyun MADERA_MICB2B_ENA_SHIFT, 0, NULL, 0),
785*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2C", MADERA_MIC_BIAS_CTRL_6,
786*4882a593Smuzhiyun MADERA_MICB2C_ENA_SHIFT, 0, NULL, 0),
787*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2D", MADERA_MIC_BIAS_CTRL_6,
788*4882a593Smuzhiyun MADERA_MICB2D_ENA_SHIFT, 0, NULL, 0),
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("FXCLK", SND_SOC_NOPM,
791*4882a593Smuzhiyun MADERA_DOM_GRP_FX, 0,
792*4882a593Smuzhiyun madera_domain_clk_ev,
793*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
794*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASRC1CLK", SND_SOC_NOPM,
795*4882a593Smuzhiyun MADERA_DOM_GRP_ASRC1, 0,
796*4882a593Smuzhiyun madera_domain_clk_ev,
797*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
798*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASRC2CLK", SND_SOC_NOPM,
799*4882a593Smuzhiyun MADERA_DOM_GRP_ASRC2, 0,
800*4882a593Smuzhiyun madera_domain_clk_ev,
801*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
802*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC1CLK", SND_SOC_NOPM,
803*4882a593Smuzhiyun MADERA_DOM_GRP_ISRC1, 0,
804*4882a593Smuzhiyun madera_domain_clk_ev,
805*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
806*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC2CLK", SND_SOC_NOPM,
807*4882a593Smuzhiyun MADERA_DOM_GRP_ISRC2, 0,
808*4882a593Smuzhiyun madera_domain_clk_ev,
809*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
810*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC3CLK", SND_SOC_NOPM,
811*4882a593Smuzhiyun MADERA_DOM_GRP_ISRC3, 0,
812*4882a593Smuzhiyun madera_domain_clk_ev,
813*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
814*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC4CLK", SND_SOC_NOPM,
815*4882a593Smuzhiyun MADERA_DOM_GRP_ISRC4, 0,
816*4882a593Smuzhiyun madera_domain_clk_ev,
817*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
818*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OUTCLK", SND_SOC_NOPM,
819*4882a593Smuzhiyun MADERA_DOM_GRP_OUT, 0,
820*4882a593Smuzhiyun madera_domain_clk_ev,
821*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
822*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SPDCLK", SND_SOC_NOPM,
823*4882a593Smuzhiyun MADERA_DOM_GRP_SPD, 0,
824*4882a593Smuzhiyun madera_domain_clk_ev,
825*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
826*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM,
827*4882a593Smuzhiyun MADERA_DOM_GRP_DSP1, 0,
828*4882a593Smuzhiyun madera_domain_clk_ev,
829*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
830*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM,
831*4882a593Smuzhiyun MADERA_DOM_GRP_DSP2, 0,
832*4882a593Smuzhiyun madera_domain_clk_ev,
833*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
834*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP3CLK", SND_SOC_NOPM,
835*4882a593Smuzhiyun MADERA_DOM_GRP_DSP3, 0,
836*4882a593Smuzhiyun madera_domain_clk_ev,
837*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
838*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP4CLK", SND_SOC_NOPM,
839*4882a593Smuzhiyun MADERA_DOM_GRP_DSP4, 0,
840*4882a593Smuzhiyun madera_domain_clk_ev,
841*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
842*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP5CLK", SND_SOC_NOPM,
843*4882a593Smuzhiyun MADERA_DOM_GRP_DSP5, 0,
844*4882a593Smuzhiyun madera_domain_clk_ev,
845*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
846*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP6CLK", SND_SOC_NOPM,
847*4882a593Smuzhiyun MADERA_DOM_GRP_DSP6, 0,
848*4882a593Smuzhiyun madera_domain_clk_ev,
849*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
850*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP7CLK", SND_SOC_NOPM,
851*4882a593Smuzhiyun MADERA_DOM_GRP_DSP7, 0,
852*4882a593Smuzhiyun madera_domain_clk_ev,
853*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
854*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF1TXCLK", SND_SOC_NOPM,
855*4882a593Smuzhiyun MADERA_DOM_GRP_AIF1, 0,
856*4882a593Smuzhiyun madera_domain_clk_ev,
857*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
858*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF2TXCLK", SND_SOC_NOPM,
859*4882a593Smuzhiyun MADERA_DOM_GRP_AIF2, 0,
860*4882a593Smuzhiyun madera_domain_clk_ev,
861*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
862*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF3TXCLK", SND_SOC_NOPM,
863*4882a593Smuzhiyun MADERA_DOM_GRP_AIF3, 0,
864*4882a593Smuzhiyun madera_domain_clk_ev,
865*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
866*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF4TXCLK", SND_SOC_NOPM,
867*4882a593Smuzhiyun MADERA_DOM_GRP_AIF4, 0,
868*4882a593Smuzhiyun madera_domain_clk_ev,
869*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
870*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SLIMBUSCLK", SND_SOC_NOPM,
871*4882a593Smuzhiyun MADERA_DOM_GRP_SLIMBUS, 0,
872*4882a593Smuzhiyun madera_domain_clk_ev,
873*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
874*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("PWMCLK", SND_SOC_NOPM,
875*4882a593Smuzhiyun MADERA_DOM_GRP_PWM, 0,
876*4882a593Smuzhiyun madera_domain_clk_ev,
877*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
878*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DFCCLK", SND_SOC_NOPM,
879*4882a593Smuzhiyun MADERA_DOM_GRP_DFC, 0,
880*4882a593Smuzhiyun madera_domain_clk_ev,
881*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("TONE"),
884*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("NOISE"),
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ALN"),
887*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ALP"),
888*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BLN"),
889*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BLP"),
890*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ARN"),
891*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ARP"),
892*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BRN"),
893*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BRP"),
894*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2ALN"),
895*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2ALP"),
896*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2BLN"),
897*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2BLP"),
898*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2RN"),
899*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2RP"),
900*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICCLK3"),
901*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICDAT3"),
902*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICCLK4"),
903*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICDAT4"),
904*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICCLK5"),
905*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICDAT5"),
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[0]),
908*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[1]),
909*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[2]),
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
912*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
915*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
918*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DSP Trigger Out"),
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun SND_SOC_DAPM_PGA("PWM1 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM1_ENA_SHIFT,
923*4882a593Smuzhiyun 0, NULL, 0),
924*4882a593Smuzhiyun SND_SOC_DAPM_PGA("PWM2 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM2_ENA_SHIFT,
925*4882a593Smuzhiyun 0, NULL, 0),
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("RXANC NG External Clock", SND_SOC_NOPM,
928*4882a593Smuzhiyun MADERA_EXT_NG_SEL_SET_SHIFT, 0, madera_anc_ev,
929*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
930*4882a593Smuzhiyun SND_SOC_DAPM_PGA("RXANCL NG External", SND_SOC_NOPM, 0, 0, NULL, 0),
931*4882a593Smuzhiyun SND_SOC_DAPM_PGA("RXANCR NG External", SND_SOC_NOPM, 0, 0, NULL, 0),
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("RXANC NG Clock", SND_SOC_NOPM,
934*4882a593Smuzhiyun MADERA_CLK_NG_ENA_SET_SHIFT, 0, madera_anc_ev,
935*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
936*4882a593Smuzhiyun SND_SOC_DAPM_PGA("RXANCL NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0),
937*4882a593Smuzhiyun SND_SOC_DAPM_PGA("RXANCR NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0),
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCL Left Input", SND_SOC_NOPM, 0, 0,
940*4882a593Smuzhiyun &cs47l90_anc_input_mux[0]),
941*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCL Right Input", SND_SOC_NOPM, 0, 0,
942*4882a593Smuzhiyun &cs47l90_anc_input_mux[0]),
943*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCL Channel", SND_SOC_NOPM, 0, 0,
944*4882a593Smuzhiyun &cs47l90_anc_input_mux[1]),
945*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCL NG Mux", SND_SOC_NOPM, 0, 0, &cs47l90_anc_ng_mux),
946*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCR Left Input", SND_SOC_NOPM, 0, 0,
947*4882a593Smuzhiyun &cs47l90_anc_input_mux[2]),
948*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCR Right Input", SND_SOC_NOPM, 0, 0,
949*4882a593Smuzhiyun &cs47l90_anc_input_mux[2]),
950*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCR Channel", SND_SOC_NOPM, 0, 0,
951*4882a593Smuzhiyun &cs47l90_anc_input_mux[3]),
952*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCR NG Mux", SND_SOC_NOPM, 0, 0, &cs47l90_anc_ng_mux),
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("RXANCL", SND_SOC_NOPM, MADERA_CLK_L_ENA_SET_SHIFT,
955*4882a593Smuzhiyun 0, NULL, 0, madera_anc_ev,
956*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
957*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("RXANCR", SND_SOC_NOPM, MADERA_CLK_R_ENA_SET_SHIFT,
958*4882a593Smuzhiyun 0, NULL, 0, madera_anc_ev,
959*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT1L ANC Source", SND_SOC_NOPM, 0, 0,
962*4882a593Smuzhiyun &cs47l90_output_anc_src[0]),
963*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT1R ANC Source", SND_SOC_NOPM, 0, 0,
964*4882a593Smuzhiyun &cs47l90_output_anc_src[1]),
965*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT2L ANC Source", SND_SOC_NOPM, 0, 0,
966*4882a593Smuzhiyun &cs47l90_output_anc_src[2]),
967*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT2R ANC Source", SND_SOC_NOPM, 0, 0,
968*4882a593Smuzhiyun &cs47l90_output_anc_src[3]),
969*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT3L ANC Source", SND_SOC_NOPM, 0, 0,
970*4882a593Smuzhiyun &cs47l90_output_anc_src[4]),
971*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT3R ANC Source", SND_SOC_NOPM, 0, 0,
972*4882a593Smuzhiyun &cs47l90_output_anc_src[5]),
973*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPKDAT1L ANC Source", SND_SOC_NOPM, 0, 0,
974*4882a593Smuzhiyun &cs47l90_output_anc_src[6]),
975*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPKDAT1R ANC Source", SND_SOC_NOPM, 0, 0,
976*4882a593Smuzhiyun &cs47l90_output_anc_src[7]),
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
979*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX1_ENA_SHIFT, 0),
980*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
981*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX2_ENA_SHIFT, 0),
982*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
983*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX3_ENA_SHIFT, 0),
984*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
985*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX4_ENA_SHIFT, 0),
986*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
987*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX5_ENA_SHIFT, 0),
988*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
989*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX6_ENA_SHIFT, 0),
990*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 6,
991*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX7_ENA_SHIFT, 0),
992*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 7,
993*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX8_ENA_SHIFT, 0),
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
996*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX1_ENA_SHIFT, 0),
997*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
998*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX2_ENA_SHIFT, 0),
999*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
1000*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX3_ENA_SHIFT, 0),
1001*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
1002*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX4_ENA_SHIFT, 0),
1003*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 4,
1004*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX5_ENA_SHIFT, 0),
1005*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 5,
1006*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX6_ENA_SHIFT, 0),
1007*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX7", NULL, 6,
1008*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX7_ENA_SHIFT, 0),
1009*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX8", NULL, 7,
1010*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX8_ENA_SHIFT, 0),
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
1013*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1014*4882a593Smuzhiyun MADERA_SLIMTX1_ENA_SHIFT, 0),
1015*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
1016*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1017*4882a593Smuzhiyun MADERA_SLIMTX2_ENA_SHIFT, 0),
1018*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
1019*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1020*4882a593Smuzhiyun MADERA_SLIMTX3_ENA_SHIFT, 0),
1021*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
1022*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1023*4882a593Smuzhiyun MADERA_SLIMTX4_ENA_SHIFT, 0),
1024*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
1025*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1026*4882a593Smuzhiyun MADERA_SLIMTX5_ENA_SHIFT, 0),
1027*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
1028*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1029*4882a593Smuzhiyun MADERA_SLIMTX6_ENA_SHIFT, 0),
1030*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 6,
1031*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1032*4882a593Smuzhiyun MADERA_SLIMTX7_ENA_SHIFT, 0),
1033*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 7,
1034*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1035*4882a593Smuzhiyun MADERA_SLIMTX8_ENA_SHIFT, 0),
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
1038*4882a593Smuzhiyun MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX1_ENA_SHIFT, 0),
1039*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
1040*4882a593Smuzhiyun MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX2_ENA_SHIFT, 0),
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF4TX1", NULL, 0,
1043*4882a593Smuzhiyun MADERA_AIF4_TX_ENABLES, MADERA_AIF4TX1_ENA_SHIFT, 0),
1044*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF4TX2", NULL, 1,
1045*4882a593Smuzhiyun MADERA_AIF4_TX_ENABLES, MADERA_AIF4TX2_ENA_SHIFT, 0),
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
1048*4882a593Smuzhiyun MADERA_OUT1L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
1049*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1050*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1051*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
1052*4882a593Smuzhiyun MADERA_OUT1R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
1053*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1054*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1055*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT2L", SND_SOC_NOPM,
1056*4882a593Smuzhiyun MADERA_OUT2L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
1057*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1058*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1059*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT2R", SND_SOC_NOPM,
1060*4882a593Smuzhiyun MADERA_OUT2R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
1061*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1062*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1063*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT3L", SND_SOC_NOPM,
1064*4882a593Smuzhiyun MADERA_OUT3L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
1065*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1066*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1067*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT3R", SND_SOC_NOPM,
1068*4882a593Smuzhiyun MADERA_OUT3R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
1069*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1070*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1071*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT5L", MADERA_OUTPUT_ENABLES_1,
1072*4882a593Smuzhiyun MADERA_OUT5L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
1073*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1074*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT5R", MADERA_OUTPUT_ENABLES_1,
1075*4882a593Smuzhiyun MADERA_OUT5R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
1076*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPD1TX1", MADERA_SPD1_TX_CONTROL,
1079*4882a593Smuzhiyun MADERA_SPD1_VAL1_SHIFT, 0, NULL, 0),
1080*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPD1TX2", MADERA_SPD1_TX_CONTROL,
1081*4882a593Smuzhiyun MADERA_SPD1_VAL2_SHIFT, 0, NULL, 0),
1082*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("SPD1", MADERA_SPD1_TX_CONTROL,
1083*4882a593Smuzhiyun MADERA_SPD1_ENA_SHIFT, 0, NULL, 0),
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun /*
1086*4882a593Smuzhiyun * mux_in widgets : arranged in the order of sources
1087*4882a593Smuzhiyun * specified in MADERA_MIXER_INPUT_ROUTES
1088*4882a593Smuzhiyun */
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Noise Generator", MADERA_COMFORT_NOISE_GENERATOR,
1091*4882a593Smuzhiyun MADERA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator 1", MADERA_TONE_GENERATOR_1,
1094*4882a593Smuzhiyun MADERA_TONE1_ENA_SHIFT, 0, NULL, 0),
1095*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator 2", MADERA_TONE_GENERATOR_1,
1096*4882a593Smuzhiyun MADERA_TONE2_ENA_SHIFT, 0, NULL, 0),
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("HAPTICS"),
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun SND_SOC_DAPM_MUX("AEC1 Loopback", MADERA_DAC_AEC_CONTROL_1,
1101*4882a593Smuzhiyun MADERA_AEC1_LOOPBACK_ENA_SHIFT, 0,
1102*4882a593Smuzhiyun &cs47l90_aec_loopback_mux[0]),
1103*4882a593Smuzhiyun SND_SOC_DAPM_MUX("AEC2 Loopback", MADERA_DAC_AEC_CONTROL_2,
1104*4882a593Smuzhiyun MADERA_AEC2_LOOPBACK_ENA_SHIFT, 0,
1105*4882a593Smuzhiyun &cs47l90_aec_loopback_mux[1]),
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN1L", MADERA_INPUT_ENABLES, MADERA_IN1L_ENA_SHIFT,
1108*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1109*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1110*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1111*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN1R", MADERA_INPUT_ENABLES, MADERA_IN1R_ENA_SHIFT,
1112*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1113*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1114*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1115*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN2L", MADERA_INPUT_ENABLES, MADERA_IN2L_ENA_SHIFT,
1116*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1117*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1118*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1119*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN2R", MADERA_INPUT_ENABLES, MADERA_IN2R_ENA_SHIFT,
1120*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1121*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1122*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1123*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN3L", MADERA_INPUT_ENABLES, MADERA_IN3L_ENA_SHIFT,
1124*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1125*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1126*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1127*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN3R", MADERA_INPUT_ENABLES, MADERA_IN3R_ENA_SHIFT,
1128*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1129*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1130*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1131*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN4L", MADERA_INPUT_ENABLES, MADERA_IN4L_ENA_SHIFT,
1132*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1133*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1134*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1135*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN4R", MADERA_INPUT_ENABLES, MADERA_IN4R_ENA_SHIFT,
1136*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1137*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1138*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1139*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN5L", MADERA_INPUT_ENABLES, MADERA_IN5L_ENA_SHIFT,
1140*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1141*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1142*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1143*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN5R", MADERA_INPUT_ENABLES, MADERA_IN5R_ENA_SHIFT,
1144*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1145*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1146*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
1149*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX1_ENA_SHIFT, 0),
1150*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
1151*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX2_ENA_SHIFT, 0),
1152*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
1153*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX3_ENA_SHIFT, 0),
1154*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
1155*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX4_ENA_SHIFT, 0),
1156*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
1157*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX5_ENA_SHIFT, 0),
1158*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
1159*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX6_ENA_SHIFT, 0),
1160*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 6,
1161*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX7_ENA_SHIFT, 0),
1162*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 7,
1163*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX8_ENA_SHIFT, 0),
1164*4882a593Smuzhiyun
1165*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
1166*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX1_ENA_SHIFT, 0),
1167*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
1168*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX2_ENA_SHIFT, 0),
1169*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
1170*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX3_ENA_SHIFT, 0),
1171*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
1172*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX4_ENA_SHIFT, 0),
1173*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 4,
1174*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX5_ENA_SHIFT, 0),
1175*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 5,
1176*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX6_ENA_SHIFT, 0),
1177*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX7", NULL, 6,
1178*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX7_ENA_SHIFT, 0),
1179*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX8", NULL, 7,
1180*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX8_ENA_SHIFT, 0),
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
1183*4882a593Smuzhiyun MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX1_ENA_SHIFT, 0),
1184*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
1185*4882a593Smuzhiyun MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX2_ENA_SHIFT, 0),
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF4RX1", NULL, 0,
1188*4882a593Smuzhiyun MADERA_AIF4_RX_ENABLES, MADERA_AIF4RX1_ENA_SHIFT, 0),
1189*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF4RX2", NULL, 1,
1190*4882a593Smuzhiyun MADERA_AIF4_RX_ENABLES, MADERA_AIF4RX2_ENA_SHIFT, 0),
1191*4882a593Smuzhiyun
1192*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1193*4882a593Smuzhiyun MADERA_SLIMRX1_ENA_SHIFT, 0),
1194*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1195*4882a593Smuzhiyun MADERA_SLIMRX2_ENA_SHIFT, 0),
1196*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1197*4882a593Smuzhiyun MADERA_SLIMRX3_ENA_SHIFT, 0),
1198*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1199*4882a593Smuzhiyun MADERA_SLIMRX4_ENA_SHIFT, 0),
1200*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1201*4882a593Smuzhiyun MADERA_SLIMRX5_ENA_SHIFT, 0),
1202*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1203*4882a593Smuzhiyun MADERA_SLIMRX6_ENA_SHIFT, 0),
1204*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 6, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1205*4882a593Smuzhiyun MADERA_SLIMRX7_ENA_SHIFT, 0),
1206*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 7, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1207*4882a593Smuzhiyun MADERA_SLIMRX8_ENA_SHIFT, 0),
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ1", MADERA_EQ1_1, MADERA_EQ1_ENA_SHIFT, 0, NULL, 0),
1210*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ2", MADERA_EQ2_1, MADERA_EQ2_ENA_SHIFT, 0, NULL, 0),
1211*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ3", MADERA_EQ3_1, MADERA_EQ3_ENA_SHIFT, 0, NULL, 0),
1212*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ4", MADERA_EQ4_1, MADERA_EQ4_ENA_SHIFT, 0, NULL, 0),
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC1L", MADERA_DRC1_CTRL1, MADERA_DRC1L_ENA_SHIFT, 0,
1215*4882a593Smuzhiyun NULL, 0),
1216*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC1R", MADERA_DRC1_CTRL1, MADERA_DRC1R_ENA_SHIFT, 0,
1217*4882a593Smuzhiyun NULL, 0),
1218*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC2L", MADERA_DRC2_CTRL1, MADERA_DRC2L_ENA_SHIFT, 0,
1219*4882a593Smuzhiyun NULL, 0),
1220*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC2R", MADERA_DRC2_CTRL1, MADERA_DRC2R_ENA_SHIFT, 0,
1221*4882a593Smuzhiyun NULL, 0),
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF1", MADERA_HPLPF1_1, MADERA_LHPF1_ENA_SHIFT, 0,
1224*4882a593Smuzhiyun NULL, 0),
1225*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF2", MADERA_HPLPF2_1, MADERA_LHPF2_ENA_SHIFT, 0,
1226*4882a593Smuzhiyun NULL, 0),
1227*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF3", MADERA_HPLPF3_1, MADERA_LHPF3_ENA_SHIFT, 0,
1228*4882a593Smuzhiyun NULL, 0),
1229*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF4", MADERA_HPLPF4_1, MADERA_LHPF4_ENA_SHIFT, 0,
1230*4882a593Smuzhiyun NULL, 0),
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN1L", MADERA_ASRC1_ENABLE,
1233*4882a593Smuzhiyun MADERA_ASRC1_IN1L_ENA_SHIFT, 0, NULL, 0),
1234*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN1R", MADERA_ASRC1_ENABLE,
1235*4882a593Smuzhiyun MADERA_ASRC1_IN1R_ENA_SHIFT, 0, NULL, 0),
1236*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN2L", MADERA_ASRC1_ENABLE,
1237*4882a593Smuzhiyun MADERA_ASRC1_IN2L_ENA_SHIFT, 0, NULL, 0),
1238*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN2R", MADERA_ASRC1_ENABLE,
1239*4882a593Smuzhiyun MADERA_ASRC1_IN2R_ENA_SHIFT, 0, NULL, 0),
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC2IN1L", MADERA_ASRC2_ENABLE,
1242*4882a593Smuzhiyun MADERA_ASRC2_IN1L_ENA_SHIFT, 0, NULL, 0),
1243*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC2IN1R", MADERA_ASRC2_ENABLE,
1244*4882a593Smuzhiyun MADERA_ASRC2_IN1R_ENA_SHIFT, 0, NULL, 0),
1245*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC2IN2L", MADERA_ASRC2_ENABLE,
1246*4882a593Smuzhiyun MADERA_ASRC2_IN2L_ENA_SHIFT, 0, NULL, 0),
1247*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC2IN2R", MADERA_ASRC2_ENABLE,
1248*4882a593Smuzhiyun MADERA_ASRC2_IN2R_ENA_SHIFT, 0, NULL, 0),
1249*4882a593Smuzhiyun
1250*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC1", MADERA_ISRC_1_CTRL_3,
1251*4882a593Smuzhiyun MADERA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
1252*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC2", MADERA_ISRC_1_CTRL_3,
1253*4882a593Smuzhiyun MADERA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
1254*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC3", MADERA_ISRC_1_CTRL_3,
1255*4882a593Smuzhiyun MADERA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
1256*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC4", MADERA_ISRC_1_CTRL_3,
1257*4882a593Smuzhiyun MADERA_ISRC1_DEC4_ENA_SHIFT, 0, NULL, 0),
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT1", MADERA_ISRC_1_CTRL_3,
1260*4882a593Smuzhiyun MADERA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
1261*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT2", MADERA_ISRC_1_CTRL_3,
1262*4882a593Smuzhiyun MADERA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
1263*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT3", MADERA_ISRC_1_CTRL_3,
1264*4882a593Smuzhiyun MADERA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
1265*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT4", MADERA_ISRC_1_CTRL_3,
1266*4882a593Smuzhiyun MADERA_ISRC1_INT4_ENA_SHIFT, 0, NULL, 0),
1267*4882a593Smuzhiyun
1268*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC1", MADERA_ISRC_2_CTRL_3,
1269*4882a593Smuzhiyun MADERA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
1270*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC2", MADERA_ISRC_2_CTRL_3,
1271*4882a593Smuzhiyun MADERA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
1272*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC3", MADERA_ISRC_2_CTRL_3,
1273*4882a593Smuzhiyun MADERA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0),
1274*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC4", MADERA_ISRC_2_CTRL_3,
1275*4882a593Smuzhiyun MADERA_ISRC2_DEC4_ENA_SHIFT, 0, NULL, 0),
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT1", MADERA_ISRC_2_CTRL_3,
1278*4882a593Smuzhiyun MADERA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
1279*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT2", MADERA_ISRC_2_CTRL_3,
1280*4882a593Smuzhiyun MADERA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
1281*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT3", MADERA_ISRC_2_CTRL_3,
1282*4882a593Smuzhiyun MADERA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0),
1283*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT4", MADERA_ISRC_2_CTRL_3,
1284*4882a593Smuzhiyun MADERA_ISRC2_INT4_ENA_SHIFT, 0, NULL, 0),
1285*4882a593Smuzhiyun
1286*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC3DEC1", MADERA_ISRC_3_CTRL_3,
1287*4882a593Smuzhiyun MADERA_ISRC3_DEC1_ENA_SHIFT, 0, NULL, 0),
1288*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC3DEC2", MADERA_ISRC_3_CTRL_3,
1289*4882a593Smuzhiyun MADERA_ISRC3_DEC2_ENA_SHIFT, 0, NULL, 0),
1290*4882a593Smuzhiyun
1291*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC3INT1", MADERA_ISRC_3_CTRL_3,
1292*4882a593Smuzhiyun MADERA_ISRC3_INT1_ENA_SHIFT, 0, NULL, 0),
1293*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC3INT2", MADERA_ISRC_3_CTRL_3,
1294*4882a593Smuzhiyun MADERA_ISRC3_INT2_ENA_SHIFT, 0, NULL, 0),
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC4DEC1", MADERA_ISRC_4_CTRL_3,
1297*4882a593Smuzhiyun MADERA_ISRC4_DEC1_ENA_SHIFT, 0, NULL, 0),
1298*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC4DEC2", MADERA_ISRC_4_CTRL_3,
1299*4882a593Smuzhiyun MADERA_ISRC4_DEC2_ENA_SHIFT, 0, NULL, 0),
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC4INT1", MADERA_ISRC_4_CTRL_3,
1302*4882a593Smuzhiyun MADERA_ISRC4_INT1_ENA_SHIFT, 0, NULL, 0),
1303*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC4INT2", MADERA_ISRC_4_CTRL_3,
1304*4882a593Smuzhiyun MADERA_ISRC4_INT2_ENA_SHIFT, 0, NULL, 0),
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun WM_ADSP2("DSP1", 0, cs47l90_adsp_power_ev),
1307*4882a593Smuzhiyun WM_ADSP2("DSP2", 1, cs47l90_adsp_power_ev),
1308*4882a593Smuzhiyun WM_ADSP2("DSP3", 2, cs47l90_adsp_power_ev),
1309*4882a593Smuzhiyun WM_ADSP2("DSP4", 3, cs47l90_adsp_power_ev),
1310*4882a593Smuzhiyun WM_ADSP2("DSP5", 4, cs47l90_adsp_power_ev),
1311*4882a593Smuzhiyun WM_ADSP2("DSP6", 5, cs47l90_adsp_power_ev),
1312*4882a593Smuzhiyun WM_ADSP2("DSP7", 6, cs47l90_adsp_power_ev),
1313*4882a593Smuzhiyun
1314*4882a593Smuzhiyun /* end of ordered widget list */
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC1", MADERA_DFC1_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1317*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC2", MADERA_DFC2_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1318*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC3", MADERA_DFC3_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1319*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC4", MADERA_DFC4_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1320*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC5", MADERA_DFC5_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1321*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC6", MADERA_DFC6_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1322*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC7", MADERA_DFC7_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1323*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DFC8", MADERA_DFC8_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
1324*4882a593Smuzhiyun
1325*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ1, "EQ1"),
1326*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ2, "EQ2"),
1327*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ3, "EQ3"),
1328*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ4, "EQ4"),
1329*4882a593Smuzhiyun
1330*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC1L, "DRC1L"),
1331*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC1R, "DRC1R"),
1332*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC2L, "DRC2L"),
1333*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC2R, "DRC2R"),
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0,
1336*4882a593Smuzhiyun &madera_drc_activity_output_mux[0]),
1337*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0,
1338*4882a593Smuzhiyun &madera_drc_activity_output_mux[1]),
1339*4882a593Smuzhiyun
1340*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF1, "LHPF1"),
1341*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF2, "LHPF2"),
1342*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF3, "LHPF3"),
1343*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF4, "LHPF4"),
1344*4882a593Smuzhiyun
1345*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(PWM1, "PWM1"),
1346*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(PWM2, "PWM2"),
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
1349*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
1350*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT2L, "HPOUT2L"),
1351*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT2R, "HPOUT2R"),
1352*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT3L, "HPOUT3L"),
1353*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT3R, "HPOUT3R"),
1354*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1355*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1358*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1359*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1360*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1361*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1362*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1363*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1364*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1365*4882a593Smuzhiyun
1366*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1367*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1368*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
1369*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
1370*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"),
1371*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"),
1372*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX7, "AIF2TX7"),
1373*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX8, "AIF2TX8"),
1374*4882a593Smuzhiyun
1375*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1376*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1377*4882a593Smuzhiyun
1378*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF4TX1, "AIF4TX1"),
1379*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF4TX2, "AIF4TX2"),
1380*4882a593Smuzhiyun
1381*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
1382*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
1383*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
1384*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
1385*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
1386*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
1387*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"),
1388*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"),
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun MADERA_MUX_WIDGETS(SPD1TX1, "SPDIF1TX1"),
1391*4882a593Smuzhiyun MADERA_MUX_WIDGETS(SPD1TX2, "SPDIF1TX2"),
1392*4882a593Smuzhiyun
1393*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN1L, "ASRC1IN1L"),
1394*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN1R, "ASRC1IN1R"),
1395*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN2L, "ASRC1IN2L"),
1396*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN2R, "ASRC1IN2R"),
1397*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC2IN1L, "ASRC2IN1L"),
1398*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC2IN1R, "ASRC2IN1R"),
1399*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC2IN2L, "ASRC2IN2L"),
1400*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC2IN2R, "ASRC2IN2R"),
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP1, "DSP1"),
1403*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP2, "DSP2"),
1404*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP3, "DSP3"),
1405*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP4, "DSP4"),
1406*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP5, "DSP5"),
1407*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP6, "DSP6"),
1408*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP7, "DSP7"),
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0,
1411*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[0]),
1412*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP2 Trigger Output", SND_SOC_NOPM, 0, 0,
1413*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[1]),
1414*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP3 Trigger Output", SND_SOC_NOPM, 0, 0,
1415*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[2]),
1416*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP4 Trigger Output", SND_SOC_NOPM, 0, 0,
1417*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[3]),
1418*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP5 Trigger Output", SND_SOC_NOPM, 0, 0,
1419*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[4]),
1420*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP6 Trigger Output", SND_SOC_NOPM, 0, 0,
1421*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[5]),
1422*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP7 Trigger Output", SND_SOC_NOPM, 0, 0,
1423*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[6]),
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
1426*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
1427*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
1428*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
1431*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
1432*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
1433*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
1434*4882a593Smuzhiyun
1435*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
1436*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
1437*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"),
1438*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"),
1439*4882a593Smuzhiyun
1440*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
1441*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
1442*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"),
1443*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"),
1444*4882a593Smuzhiyun
1445*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"),
1446*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"),
1447*4882a593Smuzhiyun
1448*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"),
1449*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"),
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC4DEC1, "ISRC4DEC1"),
1452*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC4DEC2, "ISRC4DEC2"),
1453*4882a593Smuzhiyun
1454*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC4INT1, "ISRC4INT1"),
1455*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC4INT2, "ISRC4INT2"),
1456*4882a593Smuzhiyun
1457*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC1, "DFC1"),
1458*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC2, "DFC2"),
1459*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC3, "DFC3"),
1460*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC4, "DFC4"),
1461*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC5, "DFC5"),
1462*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC6, "DFC6"),
1463*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC7, "DFC7"),
1464*4882a593Smuzhiyun MADERA_MUX_WIDGETS(DFC8, "DFC8"),
1465*4882a593Smuzhiyun
1466*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1467*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1468*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1469*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1470*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1471*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1472*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
1473*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
1474*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPDIF1"),
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MICSUPP"),
1477*4882a593Smuzhiyun };
1478*4882a593Smuzhiyun
1479*4882a593Smuzhiyun #define MADERA_MIXER_INPUT_ROUTES(name) \
1480*4882a593Smuzhiyun { name, "Noise Generator", "Noise Generator" }, \
1481*4882a593Smuzhiyun { name, "Tone Generator 1", "Tone Generator 1" }, \
1482*4882a593Smuzhiyun { name, "Tone Generator 2", "Tone Generator 2" }, \
1483*4882a593Smuzhiyun { name, "Haptics", "HAPTICS" }, \
1484*4882a593Smuzhiyun { name, "AEC1", "AEC1 Loopback" }, \
1485*4882a593Smuzhiyun { name, "AEC2", "AEC2 Loopback" }, \
1486*4882a593Smuzhiyun { name, "IN1L", "IN1L" }, \
1487*4882a593Smuzhiyun { name, "IN1R", "IN1R" }, \
1488*4882a593Smuzhiyun { name, "IN2L", "IN2L" }, \
1489*4882a593Smuzhiyun { name, "IN2R", "IN2R" }, \
1490*4882a593Smuzhiyun { name, "IN3L", "IN3L" }, \
1491*4882a593Smuzhiyun { name, "IN3R", "IN3R" }, \
1492*4882a593Smuzhiyun { name, "IN4L", "IN4L" }, \
1493*4882a593Smuzhiyun { name, "IN4R", "IN4R" }, \
1494*4882a593Smuzhiyun { name, "IN5L", "IN5L" }, \
1495*4882a593Smuzhiyun { name, "IN5R", "IN5R" }, \
1496*4882a593Smuzhiyun { name, "AIF1RX1", "AIF1RX1" }, \
1497*4882a593Smuzhiyun { name, "AIF1RX2", "AIF1RX2" }, \
1498*4882a593Smuzhiyun { name, "AIF1RX3", "AIF1RX3" }, \
1499*4882a593Smuzhiyun { name, "AIF1RX4", "AIF1RX4" }, \
1500*4882a593Smuzhiyun { name, "AIF1RX5", "AIF1RX5" }, \
1501*4882a593Smuzhiyun { name, "AIF1RX6", "AIF1RX6" }, \
1502*4882a593Smuzhiyun { name, "AIF1RX7", "AIF1RX7" }, \
1503*4882a593Smuzhiyun { name, "AIF1RX8", "AIF1RX8" }, \
1504*4882a593Smuzhiyun { name, "AIF2RX1", "AIF2RX1" }, \
1505*4882a593Smuzhiyun { name, "AIF2RX2", "AIF2RX2" }, \
1506*4882a593Smuzhiyun { name, "AIF2RX3", "AIF2RX3" }, \
1507*4882a593Smuzhiyun { name, "AIF2RX4", "AIF2RX4" }, \
1508*4882a593Smuzhiyun { name, "AIF2RX5", "AIF2RX5" }, \
1509*4882a593Smuzhiyun { name, "AIF2RX6", "AIF2RX6" }, \
1510*4882a593Smuzhiyun { name, "AIF2RX7", "AIF2RX7" }, \
1511*4882a593Smuzhiyun { name, "AIF2RX8", "AIF2RX8" }, \
1512*4882a593Smuzhiyun { name, "AIF3RX1", "AIF3RX1" }, \
1513*4882a593Smuzhiyun { name, "AIF3RX2", "AIF3RX2" }, \
1514*4882a593Smuzhiyun { name, "AIF4RX1", "AIF4RX1" }, \
1515*4882a593Smuzhiyun { name, "AIF4RX2", "AIF4RX2" }, \
1516*4882a593Smuzhiyun { name, "SLIMRX1", "SLIMRX1" }, \
1517*4882a593Smuzhiyun { name, "SLIMRX2", "SLIMRX2" }, \
1518*4882a593Smuzhiyun { name, "SLIMRX3", "SLIMRX3" }, \
1519*4882a593Smuzhiyun { name, "SLIMRX4", "SLIMRX4" }, \
1520*4882a593Smuzhiyun { name, "SLIMRX5", "SLIMRX5" }, \
1521*4882a593Smuzhiyun { name, "SLIMRX6", "SLIMRX6" }, \
1522*4882a593Smuzhiyun { name, "SLIMRX7", "SLIMRX7" }, \
1523*4882a593Smuzhiyun { name, "SLIMRX8", "SLIMRX8" }, \
1524*4882a593Smuzhiyun { name, "EQ1", "EQ1" }, \
1525*4882a593Smuzhiyun { name, "EQ2", "EQ2" }, \
1526*4882a593Smuzhiyun { name, "EQ3", "EQ3" }, \
1527*4882a593Smuzhiyun { name, "EQ4", "EQ4" }, \
1528*4882a593Smuzhiyun { name, "DRC1L", "DRC1L" }, \
1529*4882a593Smuzhiyun { name, "DRC1R", "DRC1R" }, \
1530*4882a593Smuzhiyun { name, "DRC2L", "DRC2L" }, \
1531*4882a593Smuzhiyun { name, "DRC2R", "DRC2R" }, \
1532*4882a593Smuzhiyun { name, "LHPF1", "LHPF1" }, \
1533*4882a593Smuzhiyun { name, "LHPF2", "LHPF2" }, \
1534*4882a593Smuzhiyun { name, "LHPF3", "LHPF3" }, \
1535*4882a593Smuzhiyun { name, "LHPF4", "LHPF4" }, \
1536*4882a593Smuzhiyun { name, "ASRC1IN1L", "ASRC1IN1L" }, \
1537*4882a593Smuzhiyun { name, "ASRC1IN1R", "ASRC1IN1R" }, \
1538*4882a593Smuzhiyun { name, "ASRC1IN2L", "ASRC1IN2L" }, \
1539*4882a593Smuzhiyun { name, "ASRC1IN2R", "ASRC1IN2R" }, \
1540*4882a593Smuzhiyun { name, "ASRC2IN1L", "ASRC2IN1L" }, \
1541*4882a593Smuzhiyun { name, "ASRC2IN1R", "ASRC2IN1R" }, \
1542*4882a593Smuzhiyun { name, "ASRC2IN2L", "ASRC2IN2L" }, \
1543*4882a593Smuzhiyun { name, "ASRC2IN2R", "ASRC2IN2R" }, \
1544*4882a593Smuzhiyun { name, "ISRC1DEC1", "ISRC1DEC1" }, \
1545*4882a593Smuzhiyun { name, "ISRC1DEC2", "ISRC1DEC2" }, \
1546*4882a593Smuzhiyun { name, "ISRC1DEC3", "ISRC1DEC3" }, \
1547*4882a593Smuzhiyun { name, "ISRC1DEC4", "ISRC1DEC4" }, \
1548*4882a593Smuzhiyun { name, "ISRC1INT1", "ISRC1INT1" }, \
1549*4882a593Smuzhiyun { name, "ISRC1INT2", "ISRC1INT2" }, \
1550*4882a593Smuzhiyun { name, "ISRC1INT3", "ISRC1INT3" }, \
1551*4882a593Smuzhiyun { name, "ISRC1INT4", "ISRC1INT4" }, \
1552*4882a593Smuzhiyun { name, "ISRC2DEC1", "ISRC2DEC1" }, \
1553*4882a593Smuzhiyun { name, "ISRC2DEC2", "ISRC2DEC2" }, \
1554*4882a593Smuzhiyun { name, "ISRC2DEC3", "ISRC2DEC3" }, \
1555*4882a593Smuzhiyun { name, "ISRC2DEC4", "ISRC2DEC4" }, \
1556*4882a593Smuzhiyun { name, "ISRC2INT1", "ISRC2INT1" }, \
1557*4882a593Smuzhiyun { name, "ISRC2INT2", "ISRC2INT2" }, \
1558*4882a593Smuzhiyun { name, "ISRC2INT3", "ISRC2INT3" }, \
1559*4882a593Smuzhiyun { name, "ISRC2INT4", "ISRC2INT4" }, \
1560*4882a593Smuzhiyun { name, "ISRC3DEC1", "ISRC3DEC1" }, \
1561*4882a593Smuzhiyun { name, "ISRC3DEC2", "ISRC3DEC2" }, \
1562*4882a593Smuzhiyun { name, "ISRC3INT1", "ISRC3INT1" }, \
1563*4882a593Smuzhiyun { name, "ISRC3INT2", "ISRC3INT2" }, \
1564*4882a593Smuzhiyun { name, "ISRC4DEC1", "ISRC4DEC1" }, \
1565*4882a593Smuzhiyun { name, "ISRC4DEC2", "ISRC4DEC2" }, \
1566*4882a593Smuzhiyun { name, "ISRC4INT1", "ISRC4INT1" }, \
1567*4882a593Smuzhiyun { name, "ISRC4INT2", "ISRC4INT2" }, \
1568*4882a593Smuzhiyun { name, "DSP1.1", "DSP1" }, \
1569*4882a593Smuzhiyun { name, "DSP1.2", "DSP1" }, \
1570*4882a593Smuzhiyun { name, "DSP1.3", "DSP1" }, \
1571*4882a593Smuzhiyun { name, "DSP1.4", "DSP1" }, \
1572*4882a593Smuzhiyun { name, "DSP1.5", "DSP1" }, \
1573*4882a593Smuzhiyun { name, "DSP1.6", "DSP1" }, \
1574*4882a593Smuzhiyun { name, "DSP2.1", "DSP2" }, \
1575*4882a593Smuzhiyun { name, "DSP2.2", "DSP2" }, \
1576*4882a593Smuzhiyun { name, "DSP2.3", "DSP2" }, \
1577*4882a593Smuzhiyun { name, "DSP2.4", "DSP2" }, \
1578*4882a593Smuzhiyun { name, "DSP2.5", "DSP2" }, \
1579*4882a593Smuzhiyun { name, "DSP2.6", "DSP2" }, \
1580*4882a593Smuzhiyun { name, "DSP3.1", "DSP3" }, \
1581*4882a593Smuzhiyun { name, "DSP3.2", "DSP3" }, \
1582*4882a593Smuzhiyun { name, "DSP3.3", "DSP3" }, \
1583*4882a593Smuzhiyun { name, "DSP3.4", "DSP3" }, \
1584*4882a593Smuzhiyun { name, "DSP3.5", "DSP3" }, \
1585*4882a593Smuzhiyun { name, "DSP3.6", "DSP3" }, \
1586*4882a593Smuzhiyun { name, "DSP4.1", "DSP4" }, \
1587*4882a593Smuzhiyun { name, "DSP4.2", "DSP4" }, \
1588*4882a593Smuzhiyun { name, "DSP4.3", "DSP4" }, \
1589*4882a593Smuzhiyun { name, "DSP4.4", "DSP4" }, \
1590*4882a593Smuzhiyun { name, "DSP4.5", "DSP4" }, \
1591*4882a593Smuzhiyun { name, "DSP4.6", "DSP4" }, \
1592*4882a593Smuzhiyun { name, "DSP5.1", "DSP5" }, \
1593*4882a593Smuzhiyun { name, "DSP5.2", "DSP5" }, \
1594*4882a593Smuzhiyun { name, "DSP5.3", "DSP5" }, \
1595*4882a593Smuzhiyun { name, "DSP5.4", "DSP5" }, \
1596*4882a593Smuzhiyun { name, "DSP5.5", "DSP5" }, \
1597*4882a593Smuzhiyun { name, "DSP5.6", "DSP5" }, \
1598*4882a593Smuzhiyun { name, "DSP6.1", "DSP6" }, \
1599*4882a593Smuzhiyun { name, "DSP6.2", "DSP6" }, \
1600*4882a593Smuzhiyun { name, "DSP6.3", "DSP6" }, \
1601*4882a593Smuzhiyun { name, "DSP6.4", "DSP6" }, \
1602*4882a593Smuzhiyun { name, "DSP6.5", "DSP6" }, \
1603*4882a593Smuzhiyun { name, "DSP6.6", "DSP6" }, \
1604*4882a593Smuzhiyun { name, "DSP7.1", "DSP7" }, \
1605*4882a593Smuzhiyun { name, "DSP7.2", "DSP7" }, \
1606*4882a593Smuzhiyun { name, "DSP7.3", "DSP7" }, \
1607*4882a593Smuzhiyun { name, "DSP7.4", "DSP7" }, \
1608*4882a593Smuzhiyun { name, "DSP7.5", "DSP7" }, \
1609*4882a593Smuzhiyun { name, "DSP7.6", "DSP7" }, \
1610*4882a593Smuzhiyun { name, "DFC1", "DFC1" }, \
1611*4882a593Smuzhiyun { name, "DFC2", "DFC2" }, \
1612*4882a593Smuzhiyun { name, "DFC3", "DFC3" }, \
1613*4882a593Smuzhiyun { name, "DFC4", "DFC4" }, \
1614*4882a593Smuzhiyun { name, "DFC5", "DFC5" }, \
1615*4882a593Smuzhiyun { name, "DFC6", "DFC6" }, \
1616*4882a593Smuzhiyun { name, "DFC7", "DFC7" }, \
1617*4882a593Smuzhiyun { name, "DFC8", "DFC8" }
1618*4882a593Smuzhiyun
1619*4882a593Smuzhiyun static const struct snd_soc_dapm_route cs47l90_dapm_routes[] = {
1620*4882a593Smuzhiyun /* Internal clock domains */
1621*4882a593Smuzhiyun { "EQ1", NULL, "FXCLK" },
1622*4882a593Smuzhiyun { "EQ2", NULL, "FXCLK" },
1623*4882a593Smuzhiyun { "EQ3", NULL, "FXCLK" },
1624*4882a593Smuzhiyun { "EQ4", NULL, "FXCLK" },
1625*4882a593Smuzhiyun { "DRC1L", NULL, "FXCLK" },
1626*4882a593Smuzhiyun { "DRC1R", NULL, "FXCLK" },
1627*4882a593Smuzhiyun { "DRC2L", NULL, "FXCLK" },
1628*4882a593Smuzhiyun { "DRC2R", NULL, "FXCLK" },
1629*4882a593Smuzhiyun { "LHPF1", NULL, "FXCLK" },
1630*4882a593Smuzhiyun { "LHPF2", NULL, "FXCLK" },
1631*4882a593Smuzhiyun { "LHPF3", NULL, "FXCLK" },
1632*4882a593Smuzhiyun { "LHPF4", NULL, "FXCLK" },
1633*4882a593Smuzhiyun { "PWM1 Mixer", NULL, "PWMCLK" },
1634*4882a593Smuzhiyun { "PWM2 Mixer", NULL, "PWMCLK" },
1635*4882a593Smuzhiyun { "OUT1L", NULL, "OUTCLK" },
1636*4882a593Smuzhiyun { "OUT1R", NULL, "OUTCLK" },
1637*4882a593Smuzhiyun { "OUT2L", NULL, "OUTCLK" },
1638*4882a593Smuzhiyun { "OUT2R", NULL, "OUTCLK" },
1639*4882a593Smuzhiyun { "OUT3L", NULL, "OUTCLK" },
1640*4882a593Smuzhiyun { "OUT3R", NULL, "OUTCLK" },
1641*4882a593Smuzhiyun { "OUT5L", NULL, "OUTCLK" },
1642*4882a593Smuzhiyun { "OUT5R", NULL, "OUTCLK" },
1643*4882a593Smuzhiyun { "AIF1TX1", NULL, "AIF1TXCLK" },
1644*4882a593Smuzhiyun { "AIF1TX2", NULL, "AIF1TXCLK" },
1645*4882a593Smuzhiyun { "AIF1TX3", NULL, "AIF1TXCLK" },
1646*4882a593Smuzhiyun { "AIF1TX4", NULL, "AIF1TXCLK" },
1647*4882a593Smuzhiyun { "AIF1TX5", NULL, "AIF1TXCLK" },
1648*4882a593Smuzhiyun { "AIF1TX6", NULL, "AIF1TXCLK" },
1649*4882a593Smuzhiyun { "AIF1TX7", NULL, "AIF1TXCLK" },
1650*4882a593Smuzhiyun { "AIF1TX8", NULL, "AIF1TXCLK" },
1651*4882a593Smuzhiyun { "AIF2TX1", NULL, "AIF2TXCLK" },
1652*4882a593Smuzhiyun { "AIF2TX2", NULL, "AIF2TXCLK" },
1653*4882a593Smuzhiyun { "AIF2TX3", NULL, "AIF2TXCLK" },
1654*4882a593Smuzhiyun { "AIF2TX4", NULL, "AIF2TXCLK" },
1655*4882a593Smuzhiyun { "AIF2TX5", NULL, "AIF2TXCLK" },
1656*4882a593Smuzhiyun { "AIF2TX6", NULL, "AIF2TXCLK" },
1657*4882a593Smuzhiyun { "AIF2TX7", NULL, "AIF2TXCLK" },
1658*4882a593Smuzhiyun { "AIF2TX8", NULL, "AIF2TXCLK" },
1659*4882a593Smuzhiyun { "AIF3TX1", NULL, "AIF3TXCLK" },
1660*4882a593Smuzhiyun { "AIF3TX2", NULL, "AIF3TXCLK" },
1661*4882a593Smuzhiyun { "AIF4TX1", NULL, "AIF4TXCLK" },
1662*4882a593Smuzhiyun { "AIF4TX2", NULL, "AIF4TXCLK" },
1663*4882a593Smuzhiyun { "SLIMTX1", NULL, "SLIMBUSCLK" },
1664*4882a593Smuzhiyun { "SLIMTX2", NULL, "SLIMBUSCLK" },
1665*4882a593Smuzhiyun { "SLIMTX3", NULL, "SLIMBUSCLK" },
1666*4882a593Smuzhiyun { "SLIMTX4", NULL, "SLIMBUSCLK" },
1667*4882a593Smuzhiyun { "SLIMTX5", NULL, "SLIMBUSCLK" },
1668*4882a593Smuzhiyun { "SLIMTX6", NULL, "SLIMBUSCLK" },
1669*4882a593Smuzhiyun { "SLIMTX7", NULL, "SLIMBUSCLK" },
1670*4882a593Smuzhiyun { "SLIMTX8", NULL, "SLIMBUSCLK" },
1671*4882a593Smuzhiyun { "SPD1TX1", NULL, "SPDCLK" },
1672*4882a593Smuzhiyun { "SPD1TX2", NULL, "SPDCLK" },
1673*4882a593Smuzhiyun { "DSP1", NULL, "DSP1CLK" },
1674*4882a593Smuzhiyun { "DSP2", NULL, "DSP2CLK" },
1675*4882a593Smuzhiyun { "DSP3", NULL, "DSP3CLK" },
1676*4882a593Smuzhiyun { "DSP4", NULL, "DSP4CLK" },
1677*4882a593Smuzhiyun { "DSP5", NULL, "DSP5CLK" },
1678*4882a593Smuzhiyun { "DSP6", NULL, "DSP6CLK" },
1679*4882a593Smuzhiyun { "DSP7", NULL, "DSP7CLK" },
1680*4882a593Smuzhiyun { "ISRC1DEC1", NULL, "ISRC1CLK" },
1681*4882a593Smuzhiyun { "ISRC1DEC2", NULL, "ISRC1CLK" },
1682*4882a593Smuzhiyun { "ISRC1DEC3", NULL, "ISRC1CLK" },
1683*4882a593Smuzhiyun { "ISRC1DEC4", NULL, "ISRC1CLK" },
1684*4882a593Smuzhiyun { "ISRC1INT1", NULL, "ISRC1CLK" },
1685*4882a593Smuzhiyun { "ISRC1INT2", NULL, "ISRC1CLK" },
1686*4882a593Smuzhiyun { "ISRC1INT3", NULL, "ISRC1CLK" },
1687*4882a593Smuzhiyun { "ISRC1INT4", NULL, "ISRC1CLK" },
1688*4882a593Smuzhiyun { "ISRC2DEC1", NULL, "ISRC2CLK" },
1689*4882a593Smuzhiyun { "ISRC2DEC2", NULL, "ISRC2CLK" },
1690*4882a593Smuzhiyun { "ISRC2DEC3", NULL, "ISRC2CLK" },
1691*4882a593Smuzhiyun { "ISRC2DEC4", NULL, "ISRC2CLK" },
1692*4882a593Smuzhiyun { "ISRC2INT1", NULL, "ISRC2CLK" },
1693*4882a593Smuzhiyun { "ISRC2INT2", NULL, "ISRC2CLK" },
1694*4882a593Smuzhiyun { "ISRC2INT3", NULL, "ISRC2CLK" },
1695*4882a593Smuzhiyun { "ISRC2INT4", NULL, "ISRC2CLK" },
1696*4882a593Smuzhiyun { "ISRC3DEC1", NULL, "ISRC3CLK" },
1697*4882a593Smuzhiyun { "ISRC3DEC2", NULL, "ISRC3CLK" },
1698*4882a593Smuzhiyun { "ISRC3INT1", NULL, "ISRC3CLK" },
1699*4882a593Smuzhiyun { "ISRC3INT2", NULL, "ISRC3CLK" },
1700*4882a593Smuzhiyun { "ISRC4DEC1", NULL, "ISRC4CLK" },
1701*4882a593Smuzhiyun { "ISRC4DEC2", NULL, "ISRC4CLK" },
1702*4882a593Smuzhiyun { "ISRC4INT1", NULL, "ISRC4CLK" },
1703*4882a593Smuzhiyun { "ISRC4INT2", NULL, "ISRC4CLK" },
1704*4882a593Smuzhiyun { "ASRC1IN1L", NULL, "ASRC1CLK" },
1705*4882a593Smuzhiyun { "ASRC1IN1R", NULL, "ASRC1CLK" },
1706*4882a593Smuzhiyun { "ASRC1IN2L", NULL, "ASRC1CLK" },
1707*4882a593Smuzhiyun { "ASRC1IN2R", NULL, "ASRC1CLK" },
1708*4882a593Smuzhiyun { "ASRC2IN1L", NULL, "ASRC2CLK" },
1709*4882a593Smuzhiyun { "ASRC2IN1R", NULL, "ASRC2CLK" },
1710*4882a593Smuzhiyun { "ASRC2IN2L", NULL, "ASRC2CLK" },
1711*4882a593Smuzhiyun { "ASRC2IN2R", NULL, "ASRC2CLK" },
1712*4882a593Smuzhiyun { "DFC1", NULL, "DFCCLK" },
1713*4882a593Smuzhiyun { "DFC2", NULL, "DFCCLK" },
1714*4882a593Smuzhiyun { "DFC3", NULL, "DFCCLK" },
1715*4882a593Smuzhiyun { "DFC4", NULL, "DFCCLK" },
1716*4882a593Smuzhiyun { "DFC5", NULL, "DFCCLK" },
1717*4882a593Smuzhiyun { "DFC6", NULL, "DFCCLK" },
1718*4882a593Smuzhiyun { "DFC7", NULL, "DFCCLK" },
1719*4882a593Smuzhiyun { "DFC8", NULL, "DFCCLK" },
1720*4882a593Smuzhiyun
1721*4882a593Smuzhiyun { "AIF2 Capture", NULL, "DBVDD2" },
1722*4882a593Smuzhiyun { "AIF2 Playback", NULL, "DBVDD2" },
1723*4882a593Smuzhiyun
1724*4882a593Smuzhiyun { "AIF3 Capture", NULL, "DBVDD3" },
1725*4882a593Smuzhiyun { "AIF3 Playback", NULL, "DBVDD3" },
1726*4882a593Smuzhiyun
1727*4882a593Smuzhiyun { "AIF4 Capture", NULL, "DBVDD3" },
1728*4882a593Smuzhiyun { "AIF4 Playback", NULL, "DBVDD3" },
1729*4882a593Smuzhiyun
1730*4882a593Smuzhiyun { "OUT1L", NULL, "CPVDD1" },
1731*4882a593Smuzhiyun { "OUT1L", NULL, "CPVDD2" },
1732*4882a593Smuzhiyun { "OUT1R", NULL, "CPVDD1" },
1733*4882a593Smuzhiyun { "OUT1R", NULL, "CPVDD2" },
1734*4882a593Smuzhiyun { "OUT2L", NULL, "CPVDD1" },
1735*4882a593Smuzhiyun { "OUT2L", NULL, "CPVDD2" },
1736*4882a593Smuzhiyun { "OUT2R", NULL, "CPVDD1" },
1737*4882a593Smuzhiyun { "OUT2R", NULL, "CPVDD2" },
1738*4882a593Smuzhiyun { "OUT3L", NULL, "CPVDD1" },
1739*4882a593Smuzhiyun { "OUT3L", NULL, "CPVDD2" },
1740*4882a593Smuzhiyun { "OUT3R", NULL, "CPVDD1" },
1741*4882a593Smuzhiyun { "OUT3R", NULL, "CPVDD2" },
1742*4882a593Smuzhiyun
1743*4882a593Smuzhiyun { "OUT1L", NULL, "SYSCLK" },
1744*4882a593Smuzhiyun { "OUT1R", NULL, "SYSCLK" },
1745*4882a593Smuzhiyun { "OUT2L", NULL, "SYSCLK" },
1746*4882a593Smuzhiyun { "OUT2R", NULL, "SYSCLK" },
1747*4882a593Smuzhiyun { "OUT3L", NULL, "SYSCLK" },
1748*4882a593Smuzhiyun { "OUT3R", NULL, "SYSCLK" },
1749*4882a593Smuzhiyun { "OUT5L", NULL, "SYSCLK" },
1750*4882a593Smuzhiyun { "OUT5R", NULL, "SYSCLK" },
1751*4882a593Smuzhiyun
1752*4882a593Smuzhiyun { "SPD1", NULL, "SYSCLK" },
1753*4882a593Smuzhiyun { "SPD1", NULL, "SPD1TX1" },
1754*4882a593Smuzhiyun { "SPD1", NULL, "SPD1TX2" },
1755*4882a593Smuzhiyun
1756*4882a593Smuzhiyun { "IN1L", NULL, "SYSCLK" },
1757*4882a593Smuzhiyun { "IN1R", NULL, "SYSCLK" },
1758*4882a593Smuzhiyun { "IN2L", NULL, "SYSCLK" },
1759*4882a593Smuzhiyun { "IN2R", NULL, "SYSCLK" },
1760*4882a593Smuzhiyun { "IN3L", NULL, "SYSCLK" },
1761*4882a593Smuzhiyun { "IN3R", NULL, "SYSCLK" },
1762*4882a593Smuzhiyun { "IN4L", NULL, "SYSCLK" },
1763*4882a593Smuzhiyun { "IN4R", NULL, "SYSCLK" },
1764*4882a593Smuzhiyun { "IN5L", NULL, "SYSCLK" },
1765*4882a593Smuzhiyun { "IN5R", NULL, "SYSCLK" },
1766*4882a593Smuzhiyun
1767*4882a593Smuzhiyun { "IN3L", NULL, "DBVDD4" },
1768*4882a593Smuzhiyun { "IN3R", NULL, "DBVDD4" },
1769*4882a593Smuzhiyun { "IN4L", NULL, "DBVDD4" },
1770*4882a593Smuzhiyun { "IN4R", NULL, "DBVDD4" },
1771*4882a593Smuzhiyun { "IN5L", NULL, "DBVDD4" },
1772*4882a593Smuzhiyun { "IN5R", NULL, "DBVDD4" },
1773*4882a593Smuzhiyun
1774*4882a593Smuzhiyun { "ASRC1IN1L", NULL, "SYSCLK" },
1775*4882a593Smuzhiyun { "ASRC1IN1R", NULL, "SYSCLK" },
1776*4882a593Smuzhiyun { "ASRC1IN2L", NULL, "SYSCLK" },
1777*4882a593Smuzhiyun { "ASRC1IN2R", NULL, "SYSCLK" },
1778*4882a593Smuzhiyun { "ASRC2IN1L", NULL, "SYSCLK" },
1779*4882a593Smuzhiyun { "ASRC2IN1R", NULL, "SYSCLK" },
1780*4882a593Smuzhiyun { "ASRC2IN2L", NULL, "SYSCLK" },
1781*4882a593Smuzhiyun { "ASRC2IN2R", NULL, "SYSCLK" },
1782*4882a593Smuzhiyun
1783*4882a593Smuzhiyun { "ASRC1IN1L", NULL, "ASYNCCLK" },
1784*4882a593Smuzhiyun { "ASRC1IN1R", NULL, "ASYNCCLK" },
1785*4882a593Smuzhiyun { "ASRC1IN2L", NULL, "ASYNCCLK" },
1786*4882a593Smuzhiyun { "ASRC1IN2R", NULL, "ASYNCCLK" },
1787*4882a593Smuzhiyun { "ASRC2IN1L", NULL, "ASYNCCLK" },
1788*4882a593Smuzhiyun { "ASRC2IN1R", NULL, "ASYNCCLK" },
1789*4882a593Smuzhiyun { "ASRC2IN2L", NULL, "ASYNCCLK" },
1790*4882a593Smuzhiyun { "ASRC2IN2R", NULL, "ASYNCCLK" },
1791*4882a593Smuzhiyun
1792*4882a593Smuzhiyun { "MICBIAS1", NULL, "MICVDD" },
1793*4882a593Smuzhiyun { "MICBIAS2", NULL, "MICVDD" },
1794*4882a593Smuzhiyun
1795*4882a593Smuzhiyun { "MICBIAS1A", NULL, "MICBIAS1" },
1796*4882a593Smuzhiyun { "MICBIAS1B", NULL, "MICBIAS1" },
1797*4882a593Smuzhiyun { "MICBIAS1C", NULL, "MICBIAS1" },
1798*4882a593Smuzhiyun { "MICBIAS1D", NULL, "MICBIAS1" },
1799*4882a593Smuzhiyun
1800*4882a593Smuzhiyun { "MICBIAS2A", NULL, "MICBIAS2" },
1801*4882a593Smuzhiyun { "MICBIAS2B", NULL, "MICBIAS2" },
1802*4882a593Smuzhiyun { "MICBIAS2C", NULL, "MICBIAS2" },
1803*4882a593Smuzhiyun { "MICBIAS2D", NULL, "MICBIAS2" },
1804*4882a593Smuzhiyun
1805*4882a593Smuzhiyun { "Noise Generator", NULL, "SYSCLK" },
1806*4882a593Smuzhiyun { "Tone Generator 1", NULL, "SYSCLK" },
1807*4882a593Smuzhiyun { "Tone Generator 2", NULL, "SYSCLK" },
1808*4882a593Smuzhiyun
1809*4882a593Smuzhiyun { "Noise Generator", NULL, "NOISE" },
1810*4882a593Smuzhiyun { "Tone Generator 1", NULL, "TONE" },
1811*4882a593Smuzhiyun { "Tone Generator 2", NULL, "TONE" },
1812*4882a593Smuzhiyun
1813*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX1" },
1814*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX2" },
1815*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX3" },
1816*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX4" },
1817*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX5" },
1818*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX6" },
1819*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX7" },
1820*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX8" },
1821*4882a593Smuzhiyun
1822*4882a593Smuzhiyun { "AIF1RX1", NULL, "AIF1 Playback" },
1823*4882a593Smuzhiyun { "AIF1RX2", NULL, "AIF1 Playback" },
1824*4882a593Smuzhiyun { "AIF1RX3", NULL, "AIF1 Playback" },
1825*4882a593Smuzhiyun { "AIF1RX4", NULL, "AIF1 Playback" },
1826*4882a593Smuzhiyun { "AIF1RX5", NULL, "AIF1 Playback" },
1827*4882a593Smuzhiyun { "AIF1RX6", NULL, "AIF1 Playback" },
1828*4882a593Smuzhiyun { "AIF1RX7", NULL, "AIF1 Playback" },
1829*4882a593Smuzhiyun { "AIF1RX8", NULL, "AIF1 Playback" },
1830*4882a593Smuzhiyun
1831*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX1" },
1832*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX2" },
1833*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX3" },
1834*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX4" },
1835*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX5" },
1836*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX6" },
1837*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX7" },
1838*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX8" },
1839*4882a593Smuzhiyun
1840*4882a593Smuzhiyun { "AIF2RX1", NULL, "AIF2 Playback" },
1841*4882a593Smuzhiyun { "AIF2RX2", NULL, "AIF2 Playback" },
1842*4882a593Smuzhiyun { "AIF2RX3", NULL, "AIF2 Playback" },
1843*4882a593Smuzhiyun { "AIF2RX4", NULL, "AIF2 Playback" },
1844*4882a593Smuzhiyun { "AIF2RX5", NULL, "AIF2 Playback" },
1845*4882a593Smuzhiyun { "AIF2RX6", NULL, "AIF2 Playback" },
1846*4882a593Smuzhiyun { "AIF2RX7", NULL, "AIF2 Playback" },
1847*4882a593Smuzhiyun { "AIF2RX8", NULL, "AIF2 Playback" },
1848*4882a593Smuzhiyun
1849*4882a593Smuzhiyun { "AIF3 Capture", NULL, "AIF3TX1" },
1850*4882a593Smuzhiyun { "AIF3 Capture", NULL, "AIF3TX2" },
1851*4882a593Smuzhiyun
1852*4882a593Smuzhiyun { "AIF3RX1", NULL, "AIF3 Playback" },
1853*4882a593Smuzhiyun { "AIF3RX2", NULL, "AIF3 Playback" },
1854*4882a593Smuzhiyun
1855*4882a593Smuzhiyun { "AIF4 Capture", NULL, "AIF4TX1" },
1856*4882a593Smuzhiyun { "AIF4 Capture", NULL, "AIF4TX2" },
1857*4882a593Smuzhiyun
1858*4882a593Smuzhiyun { "AIF4RX1", NULL, "AIF4 Playback" },
1859*4882a593Smuzhiyun { "AIF4RX2", NULL, "AIF4 Playback" },
1860*4882a593Smuzhiyun
1861*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX1" },
1862*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX2" },
1863*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX3" },
1864*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX4" },
1865*4882a593Smuzhiyun
1866*4882a593Smuzhiyun { "SLIMRX1", NULL, "Slim1 Playback" },
1867*4882a593Smuzhiyun { "SLIMRX2", NULL, "Slim1 Playback" },
1868*4882a593Smuzhiyun { "SLIMRX3", NULL, "Slim1 Playback" },
1869*4882a593Smuzhiyun { "SLIMRX4", NULL, "Slim1 Playback" },
1870*4882a593Smuzhiyun
1871*4882a593Smuzhiyun { "Slim2 Capture", NULL, "SLIMTX5" },
1872*4882a593Smuzhiyun { "Slim2 Capture", NULL, "SLIMTX6" },
1873*4882a593Smuzhiyun
1874*4882a593Smuzhiyun { "SLIMRX5", NULL, "Slim2 Playback" },
1875*4882a593Smuzhiyun { "SLIMRX6", NULL, "Slim2 Playback" },
1876*4882a593Smuzhiyun
1877*4882a593Smuzhiyun { "Slim3 Capture", NULL, "SLIMTX7" },
1878*4882a593Smuzhiyun { "Slim3 Capture", NULL, "SLIMTX8" },
1879*4882a593Smuzhiyun
1880*4882a593Smuzhiyun { "SLIMRX7", NULL, "Slim3 Playback" },
1881*4882a593Smuzhiyun { "SLIMRX8", NULL, "Slim3 Playback" },
1882*4882a593Smuzhiyun
1883*4882a593Smuzhiyun { "AIF1 Playback", NULL, "SYSCLK" },
1884*4882a593Smuzhiyun { "AIF2 Playback", NULL, "SYSCLK" },
1885*4882a593Smuzhiyun { "AIF3 Playback", NULL, "SYSCLK" },
1886*4882a593Smuzhiyun { "AIF4 Playback", NULL, "SYSCLK" },
1887*4882a593Smuzhiyun { "Slim1 Playback", NULL, "SYSCLK" },
1888*4882a593Smuzhiyun { "Slim2 Playback", NULL, "SYSCLK" },
1889*4882a593Smuzhiyun { "Slim3 Playback", NULL, "SYSCLK" },
1890*4882a593Smuzhiyun
1891*4882a593Smuzhiyun { "AIF1 Capture", NULL, "SYSCLK" },
1892*4882a593Smuzhiyun { "AIF2 Capture", NULL, "SYSCLK" },
1893*4882a593Smuzhiyun { "AIF3 Capture", NULL, "SYSCLK" },
1894*4882a593Smuzhiyun { "AIF4 Capture", NULL, "SYSCLK" },
1895*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SYSCLK" },
1896*4882a593Smuzhiyun { "Slim2 Capture", NULL, "SYSCLK" },
1897*4882a593Smuzhiyun { "Slim3 Capture", NULL, "SYSCLK" },
1898*4882a593Smuzhiyun
1899*4882a593Smuzhiyun { "Voice Control DSP", NULL, "DSP6" },
1900*4882a593Smuzhiyun
1901*4882a593Smuzhiyun { "Audio Trace DSP", NULL, "DSP1" },
1902*4882a593Smuzhiyun
1903*4882a593Smuzhiyun { "IN1L Analog Mux", "A", "IN1ALN" },
1904*4882a593Smuzhiyun { "IN1L Analog Mux", "A", "IN1ALP" },
1905*4882a593Smuzhiyun { "IN1L Analog Mux", "B", "IN1BLN" },
1906*4882a593Smuzhiyun { "IN1L Analog Mux", "B", "IN1BLP" },
1907*4882a593Smuzhiyun { "IN1R Analog Mux", "A", "IN1ARN" },
1908*4882a593Smuzhiyun { "IN1R Analog Mux", "A", "IN1ARP" },
1909*4882a593Smuzhiyun { "IN1R Analog Mux", "B", "IN1BRN" },
1910*4882a593Smuzhiyun { "IN1R Analog Mux", "B", "IN1BRP" },
1911*4882a593Smuzhiyun
1912*4882a593Smuzhiyun { "IN1L Mode", "Analog", "IN1L Analog Mux" },
1913*4882a593Smuzhiyun { "IN1R Mode", "Analog", "IN1R Analog Mux" },
1914*4882a593Smuzhiyun
1915*4882a593Smuzhiyun { "IN1L Mode", "Digital", "IN1ARN" },
1916*4882a593Smuzhiyun { "IN1L Mode", "Digital", "IN1ARP" },
1917*4882a593Smuzhiyun { "IN1R Mode", "Digital", "IN1ARN" },
1918*4882a593Smuzhiyun { "IN1R Mode", "Digital", "IN1ARP" },
1919*4882a593Smuzhiyun
1920*4882a593Smuzhiyun { "IN1L", NULL, "IN1L Mode" },
1921*4882a593Smuzhiyun { "IN1R", NULL, "IN1R Mode" },
1922*4882a593Smuzhiyun
1923*4882a593Smuzhiyun { "IN2L Analog Mux", "A", "IN2ALN" },
1924*4882a593Smuzhiyun { "IN2L Analog Mux", "A", "IN2ALP" },
1925*4882a593Smuzhiyun { "IN2L Analog Mux", "B", "IN2BLN" },
1926*4882a593Smuzhiyun { "IN2L Analog Mux", "B", "IN2BLP" },
1927*4882a593Smuzhiyun
1928*4882a593Smuzhiyun { "IN2L Mode", "Analog", "IN2L Analog Mux" },
1929*4882a593Smuzhiyun { "IN2R Mode", "Analog", "IN2RN" },
1930*4882a593Smuzhiyun { "IN2R Mode", "Analog", "IN2RP" },
1931*4882a593Smuzhiyun
1932*4882a593Smuzhiyun { "IN2L Mode", "Digital", "IN2ALN" },
1933*4882a593Smuzhiyun { "IN2L Mode", "Digital", "IN2ALP" },
1934*4882a593Smuzhiyun { "IN2R Mode", "Digital", "IN2ALN" },
1935*4882a593Smuzhiyun { "IN2R Mode", "Digital", "IN2ALP" },
1936*4882a593Smuzhiyun
1937*4882a593Smuzhiyun { "IN2L", NULL, "IN2L Mode" },
1938*4882a593Smuzhiyun { "IN2R", NULL, "IN2R Mode" },
1939*4882a593Smuzhiyun
1940*4882a593Smuzhiyun { "IN3L", NULL, "DMICCLK3" },
1941*4882a593Smuzhiyun { "IN3L", NULL, "DMICDAT3" },
1942*4882a593Smuzhiyun { "IN3R", NULL, "DMICCLK3" },
1943*4882a593Smuzhiyun { "IN3R", NULL, "DMICDAT3" },
1944*4882a593Smuzhiyun
1945*4882a593Smuzhiyun { "IN4L", NULL, "DMICCLK4" },
1946*4882a593Smuzhiyun { "IN4L", NULL, "DMICDAT4" },
1947*4882a593Smuzhiyun { "IN4R", NULL, "DMICCLK4" },
1948*4882a593Smuzhiyun { "IN4R", NULL, "DMICDAT4" },
1949*4882a593Smuzhiyun
1950*4882a593Smuzhiyun { "IN5L", NULL, "DMICCLK5" },
1951*4882a593Smuzhiyun { "IN5L", NULL, "DMICDAT5" },
1952*4882a593Smuzhiyun { "IN5R", NULL, "DMICCLK5" },
1953*4882a593Smuzhiyun { "IN5R", NULL, "DMICDAT5" },
1954*4882a593Smuzhiyun
1955*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1956*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1957*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1958*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1959*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1960*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1961*4882a593Smuzhiyun
1962*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1963*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1964*4882a593Smuzhiyun
1965*4882a593Smuzhiyun MADERA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1966*4882a593Smuzhiyun MADERA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1967*4882a593Smuzhiyun
1968*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1969*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1970*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1971*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1972*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1973*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1974*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1975*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1976*4882a593Smuzhiyun
1977*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1978*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1979*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
1980*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
1981*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"),
1982*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"),
1983*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX7", "AIF2TX7"),
1984*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX8", "AIF2TX8"),
1985*4882a593Smuzhiyun
1986*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1987*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1988*4882a593Smuzhiyun
1989*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF4TX1", "AIF4TX1"),
1990*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF4TX2", "AIF4TX2"),
1991*4882a593Smuzhiyun
1992*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
1993*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
1994*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
1995*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
1996*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
1997*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
1998*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"),
1999*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"),
2000*4882a593Smuzhiyun
2001*4882a593Smuzhiyun MADERA_MUX_ROUTES("SPD1TX1", "SPDIF1TX1"),
2002*4882a593Smuzhiyun MADERA_MUX_ROUTES("SPD1TX2", "SPDIF1TX2"),
2003*4882a593Smuzhiyun
2004*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ1", "EQ1"),
2005*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ2", "EQ2"),
2006*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ3", "EQ3"),
2007*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ4", "EQ4"),
2008*4882a593Smuzhiyun
2009*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC1L", "DRC1L"),
2010*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC1R", "DRC1R"),
2011*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC2L", "DRC2L"),
2012*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC2R", "DRC2R"),
2013*4882a593Smuzhiyun
2014*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF1", "LHPF1"),
2015*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF2", "LHPF2"),
2016*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF3", "LHPF3"),
2017*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF4", "LHPF4"),
2018*4882a593Smuzhiyun
2019*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN1L", "ASRC1IN1L"),
2020*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN1R", "ASRC1IN1R"),
2021*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN2L", "ASRC1IN2L"),
2022*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN2R", "ASRC1IN2R"),
2023*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC2IN1L", "ASRC2IN1L"),
2024*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC2IN1R", "ASRC2IN1R"),
2025*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC2IN2L", "ASRC2IN2L"),
2026*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC2IN2R", "ASRC2IN2R"),
2027*4882a593Smuzhiyun
2028*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP1"),
2029*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP2"),
2030*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP3"),
2031*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP4"),
2032*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP5"),
2033*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP6"),
2034*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP7"),
2035*4882a593Smuzhiyun
2036*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP1 Trigger Output" },
2037*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP2 Trigger Output" },
2038*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP3 Trigger Output" },
2039*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP4 Trigger Output" },
2040*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP5 Trigger Output" },
2041*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP6 Trigger Output" },
2042*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP7 Trigger Output" },
2043*4882a593Smuzhiyun
2044*4882a593Smuzhiyun { "DSP1 Trigger Output", "Switch", "DSP1" },
2045*4882a593Smuzhiyun { "DSP2 Trigger Output", "Switch", "DSP2" },
2046*4882a593Smuzhiyun { "DSP3 Trigger Output", "Switch", "DSP3" },
2047*4882a593Smuzhiyun { "DSP4 Trigger Output", "Switch", "DSP4" },
2048*4882a593Smuzhiyun { "DSP5 Trigger Output", "Switch", "DSP5" },
2049*4882a593Smuzhiyun { "DSP6 Trigger Output", "Switch", "DSP6" },
2050*4882a593Smuzhiyun { "DSP7 Trigger Output", "Switch", "DSP7" },
2051*4882a593Smuzhiyun
2052*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
2053*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
2054*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
2055*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
2056*4882a593Smuzhiyun
2057*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
2058*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
2059*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
2060*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
2061*4882a593Smuzhiyun
2062*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
2063*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
2064*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"),
2065*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"),
2066*4882a593Smuzhiyun
2067*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
2068*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
2069*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
2070*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
2071*4882a593Smuzhiyun
2072*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"),
2073*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"),
2074*4882a593Smuzhiyun
2075*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"),
2076*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"),
2077*4882a593Smuzhiyun
2078*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC4INT1", "ISRC4INT1"),
2079*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC4INT2", "ISRC4INT2"),
2080*4882a593Smuzhiyun
2081*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC4DEC1", "ISRC4DEC1"),
2082*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC4DEC2", "ISRC4DEC2"),
2083*4882a593Smuzhiyun
2084*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT1L", "OUT1L" },
2085*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT1R", "OUT1R" },
2086*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT1L", "OUT1L" },
2087*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT1R", "OUT1R" },
2088*4882a593Smuzhiyun { "HPOUT1L", NULL, "OUT1L" },
2089*4882a593Smuzhiyun { "HPOUT1R", NULL, "OUT1R" },
2090*4882a593Smuzhiyun
2091*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT2L", "OUT2L" },
2092*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT2R", "OUT2R" },
2093*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT2L", "OUT2L" },
2094*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT2R", "OUT2R" },
2095*4882a593Smuzhiyun { "HPOUT2L", NULL, "OUT2L" },
2096*4882a593Smuzhiyun { "HPOUT2R", NULL, "OUT2R" },
2097*4882a593Smuzhiyun
2098*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT3L", "OUT3L" },
2099*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT3R", "OUT3R" },
2100*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT3L", "OUT3L" },
2101*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT3R", "OUT3R" },
2102*4882a593Smuzhiyun { "HPOUT3L", NULL, "OUT3L" },
2103*4882a593Smuzhiyun { "HPOUT3R", NULL, "OUT3R" },
2104*4882a593Smuzhiyun
2105*4882a593Smuzhiyun { "AEC1 Loopback", "SPKDAT1L", "OUT5L" },
2106*4882a593Smuzhiyun { "AEC1 Loopback", "SPKDAT1R", "OUT5R" },
2107*4882a593Smuzhiyun { "AEC2 Loopback", "SPKDAT1L", "OUT5L" },
2108*4882a593Smuzhiyun { "AEC2 Loopback", "SPKDAT1R", "OUT5R" },
2109*4882a593Smuzhiyun { "SPKDAT1L", NULL, "OUT5L" },
2110*4882a593Smuzhiyun { "SPKDAT1R", NULL, "OUT5R" },
2111*4882a593Smuzhiyun
2112*4882a593Smuzhiyun CS47L90_RXANC_INPUT_ROUTES("RXANCL", "RXANCL"),
2113*4882a593Smuzhiyun CS47L90_RXANC_INPUT_ROUTES("RXANCR", "RXANCR"),
2114*4882a593Smuzhiyun
2115*4882a593Smuzhiyun CS47L90_RXANC_OUTPUT_ROUTES("OUT1L", "HPOUT1L"),
2116*4882a593Smuzhiyun CS47L90_RXANC_OUTPUT_ROUTES("OUT1R", "HPOUT1R"),
2117*4882a593Smuzhiyun CS47L90_RXANC_OUTPUT_ROUTES("OUT2L", "HPOUT2L"),
2118*4882a593Smuzhiyun CS47L90_RXANC_OUTPUT_ROUTES("OUT2R", "HPOUT2R"),
2119*4882a593Smuzhiyun CS47L90_RXANC_OUTPUT_ROUTES("OUT3L", "HPOUT3L"),
2120*4882a593Smuzhiyun CS47L90_RXANC_OUTPUT_ROUTES("OUT3R", "HPOUT3R"),
2121*4882a593Smuzhiyun CS47L90_RXANC_OUTPUT_ROUTES("OUT5L", "SPKDAT1L"),
2122*4882a593Smuzhiyun CS47L90_RXANC_OUTPUT_ROUTES("OUT5R", "SPKDAT1R"),
2123*4882a593Smuzhiyun
2124*4882a593Smuzhiyun { "SPDIF1", NULL, "SPD1" },
2125*4882a593Smuzhiyun
2126*4882a593Smuzhiyun { "MICSUPP", NULL, "SYSCLK" },
2127*4882a593Smuzhiyun
2128*4882a593Smuzhiyun { "DRC1 Signal Activity", NULL, "DRC1 Activity Output" },
2129*4882a593Smuzhiyun { "DRC2 Signal Activity", NULL, "DRC2 Activity Output" },
2130*4882a593Smuzhiyun { "DRC1 Activity Output", "Switch", "DRC1L" },
2131*4882a593Smuzhiyun { "DRC1 Activity Output", "Switch", "DRC1R" },
2132*4882a593Smuzhiyun { "DRC2 Activity Output", "Switch", "DRC2L" },
2133*4882a593Smuzhiyun { "DRC2 Activity Output", "Switch", "DRC2R" },
2134*4882a593Smuzhiyun
2135*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC1", "DFC1"),
2136*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC2", "DFC2"),
2137*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC3", "DFC3"),
2138*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC4", "DFC4"),
2139*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC5", "DFC5"),
2140*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC6", "DFC6"),
2141*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC7", "DFC7"),
2142*4882a593Smuzhiyun MADERA_MUX_ROUTES("DFC8", "DFC8"),
2143*4882a593Smuzhiyun };
2144*4882a593Smuzhiyun
cs47l90_set_fll(struct snd_soc_component * component,int fll_id,int source,unsigned int fref,unsigned int fout)2145*4882a593Smuzhiyun static int cs47l90_set_fll(struct snd_soc_component *component, int fll_id,
2146*4882a593Smuzhiyun int source, unsigned int fref, unsigned int fout)
2147*4882a593Smuzhiyun {
2148*4882a593Smuzhiyun struct cs47l90 *cs47l90 = snd_soc_component_get_drvdata(component);
2149*4882a593Smuzhiyun
2150*4882a593Smuzhiyun switch (fll_id) {
2151*4882a593Smuzhiyun case MADERA_FLL1_REFCLK:
2152*4882a593Smuzhiyun return madera_set_fll_refclk(&cs47l90->fll[0], source, fref,
2153*4882a593Smuzhiyun fout);
2154*4882a593Smuzhiyun case MADERA_FLL2_REFCLK:
2155*4882a593Smuzhiyun return madera_set_fll_refclk(&cs47l90->fll[1], source, fref,
2156*4882a593Smuzhiyun fout);
2157*4882a593Smuzhiyun case MADERA_FLLAO_REFCLK:
2158*4882a593Smuzhiyun return madera_set_fll_ao_refclk(&cs47l90->fll[2], source, fref,
2159*4882a593Smuzhiyun fout);
2160*4882a593Smuzhiyun case MADERA_FLL1_SYNCCLK:
2161*4882a593Smuzhiyun return madera_set_fll_syncclk(&cs47l90->fll[0], source, fref,
2162*4882a593Smuzhiyun fout);
2163*4882a593Smuzhiyun case MADERA_FLL2_SYNCCLK:
2164*4882a593Smuzhiyun return madera_set_fll_syncclk(&cs47l90->fll[1], source, fref,
2165*4882a593Smuzhiyun fout);
2166*4882a593Smuzhiyun default:
2167*4882a593Smuzhiyun return -EINVAL;
2168*4882a593Smuzhiyun }
2169*4882a593Smuzhiyun }
2170*4882a593Smuzhiyun
2171*4882a593Smuzhiyun static struct snd_soc_dai_driver cs47l90_dai[] = {
2172*4882a593Smuzhiyun {
2173*4882a593Smuzhiyun .name = "cs47l90-aif1",
2174*4882a593Smuzhiyun .id = 1,
2175*4882a593Smuzhiyun .base = MADERA_AIF1_BCLK_CTRL,
2176*4882a593Smuzhiyun .playback = {
2177*4882a593Smuzhiyun .stream_name = "AIF1 Playback",
2178*4882a593Smuzhiyun .channels_min = 1,
2179*4882a593Smuzhiyun .channels_max = 8,
2180*4882a593Smuzhiyun .rates = MADERA_RATES,
2181*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2182*4882a593Smuzhiyun },
2183*4882a593Smuzhiyun .capture = {
2184*4882a593Smuzhiyun .stream_name = "AIF1 Capture",
2185*4882a593Smuzhiyun .channels_min = 1,
2186*4882a593Smuzhiyun .channels_max = 8,
2187*4882a593Smuzhiyun .rates = MADERA_RATES,
2188*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2189*4882a593Smuzhiyun },
2190*4882a593Smuzhiyun .ops = &madera_dai_ops,
2191*4882a593Smuzhiyun .symmetric_rates = 1,
2192*4882a593Smuzhiyun .symmetric_samplebits = 1,
2193*4882a593Smuzhiyun },
2194*4882a593Smuzhiyun {
2195*4882a593Smuzhiyun .name = "cs47l90-aif2",
2196*4882a593Smuzhiyun .id = 2,
2197*4882a593Smuzhiyun .base = MADERA_AIF2_BCLK_CTRL,
2198*4882a593Smuzhiyun .playback = {
2199*4882a593Smuzhiyun .stream_name = "AIF2 Playback",
2200*4882a593Smuzhiyun .channels_min = 1,
2201*4882a593Smuzhiyun .channels_max = 8,
2202*4882a593Smuzhiyun .rates = MADERA_RATES,
2203*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2204*4882a593Smuzhiyun },
2205*4882a593Smuzhiyun .capture = {
2206*4882a593Smuzhiyun .stream_name = "AIF2 Capture",
2207*4882a593Smuzhiyun .channels_min = 1,
2208*4882a593Smuzhiyun .channels_max = 8,
2209*4882a593Smuzhiyun .rates = MADERA_RATES,
2210*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2211*4882a593Smuzhiyun },
2212*4882a593Smuzhiyun .ops = &madera_dai_ops,
2213*4882a593Smuzhiyun .symmetric_rates = 1,
2214*4882a593Smuzhiyun .symmetric_samplebits = 1,
2215*4882a593Smuzhiyun },
2216*4882a593Smuzhiyun {
2217*4882a593Smuzhiyun .name = "cs47l90-aif3",
2218*4882a593Smuzhiyun .id = 3,
2219*4882a593Smuzhiyun .base = MADERA_AIF3_BCLK_CTRL,
2220*4882a593Smuzhiyun .playback = {
2221*4882a593Smuzhiyun .stream_name = "AIF3 Playback",
2222*4882a593Smuzhiyun .channels_min = 1,
2223*4882a593Smuzhiyun .channels_max = 2,
2224*4882a593Smuzhiyun .rates = MADERA_RATES,
2225*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2226*4882a593Smuzhiyun },
2227*4882a593Smuzhiyun .capture = {
2228*4882a593Smuzhiyun .stream_name = "AIF3 Capture",
2229*4882a593Smuzhiyun .channels_min = 1,
2230*4882a593Smuzhiyun .channels_max = 2,
2231*4882a593Smuzhiyun .rates = MADERA_RATES,
2232*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2233*4882a593Smuzhiyun },
2234*4882a593Smuzhiyun .ops = &madera_dai_ops,
2235*4882a593Smuzhiyun .symmetric_rates = 1,
2236*4882a593Smuzhiyun .symmetric_samplebits = 1,
2237*4882a593Smuzhiyun },
2238*4882a593Smuzhiyun {
2239*4882a593Smuzhiyun .name = "cs47l90-aif4",
2240*4882a593Smuzhiyun .id = 4,
2241*4882a593Smuzhiyun .base = MADERA_AIF4_BCLK_CTRL,
2242*4882a593Smuzhiyun .playback = {
2243*4882a593Smuzhiyun .stream_name = "AIF4 Playback",
2244*4882a593Smuzhiyun .channels_min = 1,
2245*4882a593Smuzhiyun .channels_max = 2,
2246*4882a593Smuzhiyun .rates = MADERA_RATES,
2247*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2248*4882a593Smuzhiyun },
2249*4882a593Smuzhiyun .capture = {
2250*4882a593Smuzhiyun .stream_name = "AIF4 Capture",
2251*4882a593Smuzhiyun .channels_min = 1,
2252*4882a593Smuzhiyun .channels_max = 2,
2253*4882a593Smuzhiyun .rates = MADERA_RATES,
2254*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2255*4882a593Smuzhiyun },
2256*4882a593Smuzhiyun .ops = &madera_dai_ops,
2257*4882a593Smuzhiyun .symmetric_rates = 1,
2258*4882a593Smuzhiyun .symmetric_samplebits = 1,
2259*4882a593Smuzhiyun },
2260*4882a593Smuzhiyun {
2261*4882a593Smuzhiyun .name = "cs47l90-slim1",
2262*4882a593Smuzhiyun .id = 5,
2263*4882a593Smuzhiyun .playback = {
2264*4882a593Smuzhiyun .stream_name = "Slim1 Playback",
2265*4882a593Smuzhiyun .channels_min = 1,
2266*4882a593Smuzhiyun .channels_max = 4,
2267*4882a593Smuzhiyun .rates = MADERA_RATES,
2268*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2269*4882a593Smuzhiyun },
2270*4882a593Smuzhiyun .capture = {
2271*4882a593Smuzhiyun .stream_name = "Slim1 Capture",
2272*4882a593Smuzhiyun .channels_min = 1,
2273*4882a593Smuzhiyun .channels_max = 4,
2274*4882a593Smuzhiyun .rates = MADERA_RATES,
2275*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2276*4882a593Smuzhiyun },
2277*4882a593Smuzhiyun .ops = &madera_simple_dai_ops,
2278*4882a593Smuzhiyun },
2279*4882a593Smuzhiyun {
2280*4882a593Smuzhiyun .name = "cs47l90-slim2",
2281*4882a593Smuzhiyun .id = 6,
2282*4882a593Smuzhiyun .playback = {
2283*4882a593Smuzhiyun .stream_name = "Slim2 Playback",
2284*4882a593Smuzhiyun .channels_min = 1,
2285*4882a593Smuzhiyun .channels_max = 2,
2286*4882a593Smuzhiyun .rates = MADERA_RATES,
2287*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2288*4882a593Smuzhiyun },
2289*4882a593Smuzhiyun .capture = {
2290*4882a593Smuzhiyun .stream_name = "Slim2 Capture",
2291*4882a593Smuzhiyun .channels_min = 1,
2292*4882a593Smuzhiyun .channels_max = 2,
2293*4882a593Smuzhiyun .rates = MADERA_RATES,
2294*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2295*4882a593Smuzhiyun },
2296*4882a593Smuzhiyun .ops = &madera_simple_dai_ops,
2297*4882a593Smuzhiyun },
2298*4882a593Smuzhiyun {
2299*4882a593Smuzhiyun .name = "cs47l90-slim3",
2300*4882a593Smuzhiyun .id = 7,
2301*4882a593Smuzhiyun .playback = {
2302*4882a593Smuzhiyun .stream_name = "Slim3 Playback",
2303*4882a593Smuzhiyun .channels_min = 1,
2304*4882a593Smuzhiyun .channels_max = 2,
2305*4882a593Smuzhiyun .rates = MADERA_RATES,
2306*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2307*4882a593Smuzhiyun },
2308*4882a593Smuzhiyun .capture = {
2309*4882a593Smuzhiyun .stream_name = "Slim3 Capture",
2310*4882a593Smuzhiyun .channels_min = 1,
2311*4882a593Smuzhiyun .channels_max = 2,
2312*4882a593Smuzhiyun .rates = MADERA_RATES,
2313*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2314*4882a593Smuzhiyun },
2315*4882a593Smuzhiyun .ops = &madera_simple_dai_ops,
2316*4882a593Smuzhiyun },
2317*4882a593Smuzhiyun {
2318*4882a593Smuzhiyun .name = "cs47l90-cpu-voicectrl",
2319*4882a593Smuzhiyun .capture = {
2320*4882a593Smuzhiyun .stream_name = "Voice Control CPU",
2321*4882a593Smuzhiyun .channels_min = 1,
2322*4882a593Smuzhiyun .channels_max = 1,
2323*4882a593Smuzhiyun .rates = MADERA_RATES,
2324*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2325*4882a593Smuzhiyun },
2326*4882a593Smuzhiyun .compress_new = &snd_soc_new_compress,
2327*4882a593Smuzhiyun },
2328*4882a593Smuzhiyun {
2329*4882a593Smuzhiyun .name = "cs47l90-dsp-voicectrl",
2330*4882a593Smuzhiyun .capture = {
2331*4882a593Smuzhiyun .stream_name = "Voice Control DSP",
2332*4882a593Smuzhiyun .channels_min = 1,
2333*4882a593Smuzhiyun .channels_max = 1,
2334*4882a593Smuzhiyun .rates = MADERA_RATES,
2335*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2336*4882a593Smuzhiyun },
2337*4882a593Smuzhiyun },
2338*4882a593Smuzhiyun {
2339*4882a593Smuzhiyun .name = "cs47l90-cpu-trace",
2340*4882a593Smuzhiyun .capture = {
2341*4882a593Smuzhiyun .stream_name = "Audio Trace CPU",
2342*4882a593Smuzhiyun .channels_min = 1,
2343*4882a593Smuzhiyun .channels_max = 6,
2344*4882a593Smuzhiyun .rates = MADERA_RATES,
2345*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2346*4882a593Smuzhiyun },
2347*4882a593Smuzhiyun .compress_new = &snd_soc_new_compress,
2348*4882a593Smuzhiyun },
2349*4882a593Smuzhiyun {
2350*4882a593Smuzhiyun .name = "cs47l90-dsp-trace",
2351*4882a593Smuzhiyun .capture = {
2352*4882a593Smuzhiyun .stream_name = "Audio Trace DSP",
2353*4882a593Smuzhiyun .channels_min = 1,
2354*4882a593Smuzhiyun .channels_max = 6,
2355*4882a593Smuzhiyun .rates = MADERA_RATES,
2356*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2357*4882a593Smuzhiyun },
2358*4882a593Smuzhiyun },
2359*4882a593Smuzhiyun };
2360*4882a593Smuzhiyun
cs47l90_open(struct snd_soc_component * component,struct snd_compr_stream * stream)2361*4882a593Smuzhiyun static int cs47l90_open(struct snd_soc_component *component,
2362*4882a593Smuzhiyun struct snd_compr_stream *stream)
2363*4882a593Smuzhiyun {
2364*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = stream->private_data;
2365*4882a593Smuzhiyun struct cs47l90 *cs47l90 = snd_soc_component_get_drvdata(component);
2366*4882a593Smuzhiyun struct madera_priv *priv = &cs47l90->core;
2367*4882a593Smuzhiyun struct madera *madera = priv->madera;
2368*4882a593Smuzhiyun int n_adsp;
2369*4882a593Smuzhiyun
2370*4882a593Smuzhiyun if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l90-dsp-voicectrl") == 0) {
2371*4882a593Smuzhiyun n_adsp = 5;
2372*4882a593Smuzhiyun } else if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l90-dsp-trace") == 0) {
2373*4882a593Smuzhiyun n_adsp = 0;
2374*4882a593Smuzhiyun } else {
2375*4882a593Smuzhiyun dev_err(madera->dev,
2376*4882a593Smuzhiyun "No suitable compressed stream for DAI '%s'\n",
2377*4882a593Smuzhiyun asoc_rtd_to_codec(rtd, 0)->name);
2378*4882a593Smuzhiyun return -EINVAL;
2379*4882a593Smuzhiyun }
2380*4882a593Smuzhiyun
2381*4882a593Smuzhiyun return wm_adsp_compr_open(&priv->adsp[n_adsp], stream);
2382*4882a593Smuzhiyun }
2383*4882a593Smuzhiyun
cs47l90_adsp2_irq(int irq,void * data)2384*4882a593Smuzhiyun static irqreturn_t cs47l90_adsp2_irq(int irq, void *data)
2385*4882a593Smuzhiyun {
2386*4882a593Smuzhiyun struct cs47l90 *cs47l90 = data;
2387*4882a593Smuzhiyun struct madera_priv *priv = &cs47l90->core;
2388*4882a593Smuzhiyun struct madera *madera = priv->madera;
2389*4882a593Smuzhiyun struct madera_voice_trigger_info trig_info;
2390*4882a593Smuzhiyun int serviced = 0;
2391*4882a593Smuzhiyun int i, ret;
2392*4882a593Smuzhiyun
2393*4882a593Smuzhiyun for (i = 0; i < CS47L90_NUM_ADSP; ++i) {
2394*4882a593Smuzhiyun ret = wm_adsp_compr_handle_irq(&priv->adsp[i]);
2395*4882a593Smuzhiyun if (ret != -ENODEV)
2396*4882a593Smuzhiyun serviced++;
2397*4882a593Smuzhiyun if (ret == WM_ADSP_COMPR_VOICE_TRIGGER) {
2398*4882a593Smuzhiyun trig_info.core_num = i + 1;
2399*4882a593Smuzhiyun blocking_notifier_call_chain(&madera->notifier,
2400*4882a593Smuzhiyun MADERA_NOTIFY_VOICE_TRIGGER,
2401*4882a593Smuzhiyun &trig_info);
2402*4882a593Smuzhiyun }
2403*4882a593Smuzhiyun }
2404*4882a593Smuzhiyun
2405*4882a593Smuzhiyun if (!serviced) {
2406*4882a593Smuzhiyun dev_err(madera->dev, "Spurious compressed data IRQ\n");
2407*4882a593Smuzhiyun return IRQ_NONE;
2408*4882a593Smuzhiyun }
2409*4882a593Smuzhiyun
2410*4882a593Smuzhiyun return IRQ_HANDLED;
2411*4882a593Smuzhiyun }
2412*4882a593Smuzhiyun
cs47l90_component_probe(struct snd_soc_component * component)2413*4882a593Smuzhiyun static int cs47l90_component_probe(struct snd_soc_component *component)
2414*4882a593Smuzhiyun {
2415*4882a593Smuzhiyun struct cs47l90 *cs47l90 = snd_soc_component_get_drvdata(component);
2416*4882a593Smuzhiyun struct madera *madera = cs47l90->core.madera;
2417*4882a593Smuzhiyun int ret, i;
2418*4882a593Smuzhiyun
2419*4882a593Smuzhiyun snd_soc_component_init_regmap(component, madera->regmap);
2420*4882a593Smuzhiyun
2421*4882a593Smuzhiyun mutex_lock(&madera->dapm_ptr_lock);
2422*4882a593Smuzhiyun madera->dapm = snd_soc_component_get_dapm(component);
2423*4882a593Smuzhiyun mutex_unlock(&madera->dapm_ptr_lock);
2424*4882a593Smuzhiyun
2425*4882a593Smuzhiyun ret = madera_init_inputs(component);
2426*4882a593Smuzhiyun if (ret)
2427*4882a593Smuzhiyun return ret;
2428*4882a593Smuzhiyun
2429*4882a593Smuzhiyun ret = madera_init_outputs(component, NULL, CS47L90_MONO_OUTPUTS,
2430*4882a593Smuzhiyun CS47L90_MONO_OUTPUTS);
2431*4882a593Smuzhiyun if (ret)
2432*4882a593Smuzhiyun return ret;
2433*4882a593Smuzhiyun
2434*4882a593Smuzhiyun snd_soc_component_disable_pin(component, "HAPTICS");
2435*4882a593Smuzhiyun
2436*4882a593Smuzhiyun ret = snd_soc_add_component_controls(component,
2437*4882a593Smuzhiyun madera_adsp_rate_controls,
2438*4882a593Smuzhiyun CS47L90_NUM_ADSP);
2439*4882a593Smuzhiyun if (ret)
2440*4882a593Smuzhiyun return ret;
2441*4882a593Smuzhiyun
2442*4882a593Smuzhiyun for (i = 0; i < CS47L90_NUM_ADSP; i++)
2443*4882a593Smuzhiyun wm_adsp2_component_probe(&cs47l90->core.adsp[i], component);
2444*4882a593Smuzhiyun
2445*4882a593Smuzhiyun return 0;
2446*4882a593Smuzhiyun }
2447*4882a593Smuzhiyun
cs47l90_component_remove(struct snd_soc_component * component)2448*4882a593Smuzhiyun static void cs47l90_component_remove(struct snd_soc_component *component)
2449*4882a593Smuzhiyun {
2450*4882a593Smuzhiyun struct cs47l90 *cs47l90 = snd_soc_component_get_drvdata(component);
2451*4882a593Smuzhiyun struct madera *madera = cs47l90->core.madera;
2452*4882a593Smuzhiyun int i;
2453*4882a593Smuzhiyun
2454*4882a593Smuzhiyun mutex_lock(&madera->dapm_ptr_lock);
2455*4882a593Smuzhiyun madera->dapm = NULL;
2456*4882a593Smuzhiyun mutex_unlock(&madera->dapm_ptr_lock);
2457*4882a593Smuzhiyun
2458*4882a593Smuzhiyun for (i = 0; i < CS47L90_NUM_ADSP; i++)
2459*4882a593Smuzhiyun wm_adsp2_component_remove(&cs47l90->core.adsp[i], component);
2460*4882a593Smuzhiyun }
2461*4882a593Smuzhiyun
2462*4882a593Smuzhiyun #define CS47L90_DIG_VU 0x0200
2463*4882a593Smuzhiyun
2464*4882a593Smuzhiyun static unsigned int cs47l90_digital_vu[] = {
2465*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1L,
2466*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1R,
2467*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2L,
2468*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2R,
2469*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3L,
2470*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3R,
2471*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5L,
2472*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5R,
2473*4882a593Smuzhiyun };
2474*4882a593Smuzhiyun
2475*4882a593Smuzhiyun static const struct snd_compress_ops cs47l90_compress_ops = {
2476*4882a593Smuzhiyun .open = &cs47l90_open,
2477*4882a593Smuzhiyun .free = &wm_adsp_compr_free,
2478*4882a593Smuzhiyun .set_params = &wm_adsp_compr_set_params,
2479*4882a593Smuzhiyun .get_caps = &wm_adsp_compr_get_caps,
2480*4882a593Smuzhiyun .trigger = &wm_adsp_compr_trigger,
2481*4882a593Smuzhiyun .pointer = &wm_adsp_compr_pointer,
2482*4882a593Smuzhiyun .copy = &wm_adsp_compr_copy,
2483*4882a593Smuzhiyun };
2484*4882a593Smuzhiyun
2485*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_cs47l90 = {
2486*4882a593Smuzhiyun .probe = &cs47l90_component_probe,
2487*4882a593Smuzhiyun .remove = &cs47l90_component_remove,
2488*4882a593Smuzhiyun .set_sysclk = &madera_set_sysclk,
2489*4882a593Smuzhiyun .set_pll = &cs47l90_set_fll,
2490*4882a593Smuzhiyun .name = DRV_NAME,
2491*4882a593Smuzhiyun .compress_ops = &cs47l90_compress_ops,
2492*4882a593Smuzhiyun .controls = cs47l90_snd_controls,
2493*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(cs47l90_snd_controls),
2494*4882a593Smuzhiyun .dapm_widgets = cs47l90_dapm_widgets,
2495*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(cs47l90_dapm_widgets),
2496*4882a593Smuzhiyun .dapm_routes = cs47l90_dapm_routes,
2497*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(cs47l90_dapm_routes),
2498*4882a593Smuzhiyun .use_pmdown_time = 1,
2499*4882a593Smuzhiyun .endianness = 1,
2500*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
2501*4882a593Smuzhiyun };
2502*4882a593Smuzhiyun
cs47l90_probe(struct platform_device * pdev)2503*4882a593Smuzhiyun static int cs47l90_probe(struct platform_device *pdev)
2504*4882a593Smuzhiyun {
2505*4882a593Smuzhiyun struct madera *madera = dev_get_drvdata(pdev->dev.parent);
2506*4882a593Smuzhiyun struct cs47l90 *cs47l90;
2507*4882a593Smuzhiyun int i, ret;
2508*4882a593Smuzhiyun
2509*4882a593Smuzhiyun BUILD_BUG_ON(ARRAY_SIZE(cs47l90_dai) > MADERA_MAX_DAI);
2510*4882a593Smuzhiyun
2511*4882a593Smuzhiyun /* quick exit if Madera irqchip driver hasn't completed probe */
2512*4882a593Smuzhiyun if (!madera->irq_dev) {
2513*4882a593Smuzhiyun dev_dbg(&pdev->dev, "irqchip driver not ready\n");
2514*4882a593Smuzhiyun return -EPROBE_DEFER;
2515*4882a593Smuzhiyun }
2516*4882a593Smuzhiyun
2517*4882a593Smuzhiyun cs47l90 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l90),
2518*4882a593Smuzhiyun GFP_KERNEL);
2519*4882a593Smuzhiyun if (!cs47l90)
2520*4882a593Smuzhiyun return -ENOMEM;
2521*4882a593Smuzhiyun
2522*4882a593Smuzhiyun platform_set_drvdata(pdev, cs47l90);
2523*4882a593Smuzhiyun
2524*4882a593Smuzhiyun cs47l90->core.madera = madera;
2525*4882a593Smuzhiyun cs47l90->core.dev = &pdev->dev;
2526*4882a593Smuzhiyun cs47l90->core.num_inputs = 10;
2527*4882a593Smuzhiyun
2528*4882a593Smuzhiyun ret = madera_core_init(&cs47l90->core);
2529*4882a593Smuzhiyun if (ret)
2530*4882a593Smuzhiyun return ret;
2531*4882a593Smuzhiyun
2532*4882a593Smuzhiyun ret = madera_request_irq(madera, MADERA_IRQ_DSP_IRQ1,
2533*4882a593Smuzhiyun "ADSP2 Compressed IRQ", cs47l90_adsp2_irq,
2534*4882a593Smuzhiyun cs47l90);
2535*4882a593Smuzhiyun if (ret != 0) {
2536*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
2537*4882a593Smuzhiyun goto error_core;
2538*4882a593Smuzhiyun }
2539*4882a593Smuzhiyun
2540*4882a593Smuzhiyun ret = madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 1);
2541*4882a593Smuzhiyun if (ret)
2542*4882a593Smuzhiyun dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
2543*4882a593Smuzhiyun
2544*4882a593Smuzhiyun for (i = 0; i < CS47L90_NUM_ADSP; i++) {
2545*4882a593Smuzhiyun cs47l90->core.adsp[i].part = "cs47l90";
2546*4882a593Smuzhiyun cs47l90->core.adsp[i].num = i + 1;
2547*4882a593Smuzhiyun cs47l90->core.adsp[i].type = WMFW_ADSP2;
2548*4882a593Smuzhiyun cs47l90->core.adsp[i].rev = 2;
2549*4882a593Smuzhiyun cs47l90->core.adsp[i].dev = madera->dev;
2550*4882a593Smuzhiyun cs47l90->core.adsp[i].regmap = madera->regmap_32bit;
2551*4882a593Smuzhiyun
2552*4882a593Smuzhiyun cs47l90->core.adsp[i].base = cs47l90_dsp_control_bases[i];
2553*4882a593Smuzhiyun cs47l90->core.adsp[i].mem = cs47l90_dsp_regions[i];
2554*4882a593Smuzhiyun cs47l90->core.adsp[i].num_mems =
2555*4882a593Smuzhiyun ARRAY_SIZE(cs47l90_dsp1_regions);
2556*4882a593Smuzhiyun
2557*4882a593Smuzhiyun cs47l90->core.adsp[i].lock_regions = WM_ADSP2_REGION_1_9;
2558*4882a593Smuzhiyun
2559*4882a593Smuzhiyun ret = wm_adsp2_init(&cs47l90->core.adsp[i]);
2560*4882a593Smuzhiyun
2561*4882a593Smuzhiyun if (ret == 0) {
2562*4882a593Smuzhiyun ret = madera_init_bus_error_irq(&cs47l90->core, i,
2563*4882a593Smuzhiyun wm_adsp2_bus_error);
2564*4882a593Smuzhiyun if (ret != 0)
2565*4882a593Smuzhiyun wm_adsp2_remove(&cs47l90->core.adsp[i]);
2566*4882a593Smuzhiyun }
2567*4882a593Smuzhiyun
2568*4882a593Smuzhiyun if (ret) {
2569*4882a593Smuzhiyun for (--i; i >= 0; --i) {
2570*4882a593Smuzhiyun madera_free_bus_error_irq(&cs47l90->core, i);
2571*4882a593Smuzhiyun wm_adsp2_remove(&cs47l90->core.adsp[i]);
2572*4882a593Smuzhiyun }
2573*4882a593Smuzhiyun goto error_dsp_irq;
2574*4882a593Smuzhiyun }
2575*4882a593Smuzhiyun }
2576*4882a593Smuzhiyun
2577*4882a593Smuzhiyun madera_init_fll(madera, 1, MADERA_FLL1_CONTROL_1 - 1,
2578*4882a593Smuzhiyun &cs47l90->fll[0]);
2579*4882a593Smuzhiyun madera_init_fll(madera, 2, MADERA_FLL2_CONTROL_1 - 1,
2580*4882a593Smuzhiyun &cs47l90->fll[1]);
2581*4882a593Smuzhiyun madera_init_fll(madera, 4, MADERA_FLLAO_CONTROL_1 - 1,
2582*4882a593Smuzhiyun &cs47l90->fll[2]);
2583*4882a593Smuzhiyun
2584*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cs47l90_dai); i++)
2585*4882a593Smuzhiyun madera_init_dai(&cs47l90->core, i);
2586*4882a593Smuzhiyun
2587*4882a593Smuzhiyun /* Latch volume update bits */
2588*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cs47l90_digital_vu); i++)
2589*4882a593Smuzhiyun regmap_update_bits(madera->regmap, cs47l90_digital_vu[i],
2590*4882a593Smuzhiyun CS47L90_DIG_VU, CS47L90_DIG_VU);
2591*4882a593Smuzhiyun
2592*4882a593Smuzhiyun pm_runtime_enable(&pdev->dev);
2593*4882a593Smuzhiyun pm_runtime_idle(&pdev->dev);
2594*4882a593Smuzhiyun
2595*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&pdev->dev,
2596*4882a593Smuzhiyun &soc_component_dev_cs47l90,
2597*4882a593Smuzhiyun cs47l90_dai,
2598*4882a593Smuzhiyun ARRAY_SIZE(cs47l90_dai));
2599*4882a593Smuzhiyun if (ret < 0) {
2600*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
2601*4882a593Smuzhiyun goto error_pm_runtime;
2602*4882a593Smuzhiyun }
2603*4882a593Smuzhiyun
2604*4882a593Smuzhiyun return ret;
2605*4882a593Smuzhiyun
2606*4882a593Smuzhiyun error_pm_runtime:
2607*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
2608*4882a593Smuzhiyun
2609*4882a593Smuzhiyun for (i = 0; i < CS47L90_NUM_ADSP; i++) {
2610*4882a593Smuzhiyun madera_free_bus_error_irq(&cs47l90->core, i);
2611*4882a593Smuzhiyun wm_adsp2_remove(&cs47l90->core.adsp[i]);
2612*4882a593Smuzhiyun }
2613*4882a593Smuzhiyun error_dsp_irq:
2614*4882a593Smuzhiyun madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 0);
2615*4882a593Smuzhiyun madera_free_irq(madera, MADERA_IRQ_DSP_IRQ1, cs47l90);
2616*4882a593Smuzhiyun error_core:
2617*4882a593Smuzhiyun madera_core_free(&cs47l90->core);
2618*4882a593Smuzhiyun
2619*4882a593Smuzhiyun return ret;
2620*4882a593Smuzhiyun }
2621*4882a593Smuzhiyun
cs47l90_remove(struct platform_device * pdev)2622*4882a593Smuzhiyun static int cs47l90_remove(struct platform_device *pdev)
2623*4882a593Smuzhiyun {
2624*4882a593Smuzhiyun struct cs47l90 *cs47l90 = platform_get_drvdata(pdev);
2625*4882a593Smuzhiyun int i;
2626*4882a593Smuzhiyun
2627*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
2628*4882a593Smuzhiyun
2629*4882a593Smuzhiyun for (i = 0; i < CS47L90_NUM_ADSP; i++) {
2630*4882a593Smuzhiyun madera_free_bus_error_irq(&cs47l90->core, i);
2631*4882a593Smuzhiyun wm_adsp2_remove(&cs47l90->core.adsp[i]);
2632*4882a593Smuzhiyun }
2633*4882a593Smuzhiyun
2634*4882a593Smuzhiyun madera_set_irq_wake(cs47l90->core.madera, MADERA_IRQ_DSP_IRQ1, 0);
2635*4882a593Smuzhiyun madera_free_irq(cs47l90->core.madera, MADERA_IRQ_DSP_IRQ1, cs47l90);
2636*4882a593Smuzhiyun madera_core_free(&cs47l90->core);
2637*4882a593Smuzhiyun
2638*4882a593Smuzhiyun return 0;
2639*4882a593Smuzhiyun }
2640*4882a593Smuzhiyun
2641*4882a593Smuzhiyun static struct platform_driver cs47l90_codec_driver = {
2642*4882a593Smuzhiyun .driver = {
2643*4882a593Smuzhiyun .name = "cs47l90-codec",
2644*4882a593Smuzhiyun },
2645*4882a593Smuzhiyun .probe = &cs47l90_probe,
2646*4882a593Smuzhiyun .remove = &cs47l90_remove,
2647*4882a593Smuzhiyun };
2648*4882a593Smuzhiyun
2649*4882a593Smuzhiyun module_platform_driver(cs47l90_codec_driver);
2650*4882a593Smuzhiyun
2651*4882a593Smuzhiyun MODULE_SOFTDEP("pre: madera irq-madera arizona-micsupp");
2652*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC CS47L90 driver");
2653*4882a593Smuzhiyun MODULE_AUTHOR("Nikesh Oswal <nikesh@opensource.cirrus.com>");
2654*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
2655*4882a593Smuzhiyun MODULE_ALIAS("platform:cs47l90-codec");
2656