1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // ALSA SoC Audio driver for CS47L85 codec
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
6*4882a593Smuzhiyun // Cirrus Logic International Semiconductor Ltd.
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/moduleparam.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/pm.h>
15*4882a593Smuzhiyun #include <linux/pm_runtime.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <sound/core.h>
18*4882a593Smuzhiyun #include <sound/pcm.h>
19*4882a593Smuzhiyun #include <sound/pcm_params.h>
20*4882a593Smuzhiyun #include <sound/soc.h>
21*4882a593Smuzhiyun #include <sound/tlv.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <linux/irqchip/irq-madera.h>
24*4882a593Smuzhiyun #include <linux/mfd/madera/core.h>
25*4882a593Smuzhiyun #include <linux/mfd/madera/registers.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "madera.h"
28*4882a593Smuzhiyun #include "wm_adsp.h"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define DRV_NAME "cs47l85-codec"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define CS47L85_NUM_ADSP 7
33*4882a593Smuzhiyun #define CS47L85_MONO_OUTPUTS 4
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct cs47l85 {
36*4882a593Smuzhiyun struct madera_priv core;
37*4882a593Smuzhiyun struct madera_fll fll[3];
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static const struct wm_adsp_region cs47l85_dsp1_regions[] = {
41*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x080000 },
42*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static const struct wm_adsp_region cs47l85_dsp2_regions[] = {
48*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x160000 },
50*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x120000 },
51*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x140000 },
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static const struct wm_adsp_region cs47l85_dsp3_regions[] = {
55*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x180000 },
56*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
57*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x1a0000 },
58*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x1c0000 },
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static const struct wm_adsp_region cs47l85_dsp4_regions[] = {
62*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x200000 },
63*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x260000 },
64*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x220000 },
65*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x240000 },
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static const struct wm_adsp_region cs47l85_dsp5_regions[] = {
69*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x280000 },
70*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x2e0000 },
71*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x2a0000 },
72*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x2c0000 },
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static const struct wm_adsp_region cs47l85_dsp6_regions[] = {
76*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x300000 },
77*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x360000 },
78*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x320000 },
79*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x340000 },
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const struct wm_adsp_region cs47l85_dsp7_regions[] = {
83*4882a593Smuzhiyun { .type = WMFW_ADSP2_PM, .base = 0x380000 },
84*4882a593Smuzhiyun { .type = WMFW_ADSP2_ZM, .base = 0x3e0000 },
85*4882a593Smuzhiyun { .type = WMFW_ADSP2_XM, .base = 0x3a0000 },
86*4882a593Smuzhiyun { .type = WMFW_ADSP2_YM, .base = 0x3c0000 },
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static const struct wm_adsp_region *cs47l85_dsp_regions[] = {
90*4882a593Smuzhiyun cs47l85_dsp1_regions,
91*4882a593Smuzhiyun cs47l85_dsp2_regions,
92*4882a593Smuzhiyun cs47l85_dsp3_regions,
93*4882a593Smuzhiyun cs47l85_dsp4_regions,
94*4882a593Smuzhiyun cs47l85_dsp5_regions,
95*4882a593Smuzhiyun cs47l85_dsp6_regions,
96*4882a593Smuzhiyun cs47l85_dsp7_regions,
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const unsigned int wm_adsp2_control_bases[] = {
100*4882a593Smuzhiyun MADERA_DSP1_CONFIG_1,
101*4882a593Smuzhiyun MADERA_DSP2_CONFIG_1,
102*4882a593Smuzhiyun MADERA_DSP3_CONFIG_1,
103*4882a593Smuzhiyun MADERA_DSP4_CONFIG_1,
104*4882a593Smuzhiyun MADERA_DSP5_CONFIG_1,
105*4882a593Smuzhiyun MADERA_DSP6_CONFIG_1,
106*4882a593Smuzhiyun MADERA_DSP7_CONFIG_1,
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
cs47l85_adsp_power_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)109*4882a593Smuzhiyun static int cs47l85_adsp_power_ev(struct snd_soc_dapm_widget *w,
110*4882a593Smuzhiyun struct snd_kcontrol *kcontrol,
111*4882a593Smuzhiyun int event)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct snd_soc_component *component =
114*4882a593Smuzhiyun snd_soc_dapm_to_component(w->dapm);
115*4882a593Smuzhiyun struct cs47l85 *cs47l85 = snd_soc_component_get_drvdata(component);
116*4882a593Smuzhiyun struct madera_priv *priv = &cs47l85->core;
117*4882a593Smuzhiyun struct madera *madera = priv->madera;
118*4882a593Smuzhiyun unsigned int freq;
119*4882a593Smuzhiyun int ret;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun ret = regmap_read(madera->regmap, MADERA_DSP_CLOCK_1, &freq);
122*4882a593Smuzhiyun if (ret != 0) {
123*4882a593Smuzhiyun dev_err(madera->dev,
124*4882a593Smuzhiyun "Failed to read MADERA_DSP_CLOCK_1: %d\n", ret);
125*4882a593Smuzhiyun return ret;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun freq &= MADERA_DSP_CLK_FREQ_LEGACY_MASK;
129*4882a593Smuzhiyun freq >>= MADERA_DSP_CLK_FREQ_LEGACY_SHIFT;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun switch (event) {
132*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
133*4882a593Smuzhiyun ret = madera_set_adsp_clk(&cs47l85->core, w->shift, freq);
134*4882a593Smuzhiyun if (ret)
135*4882a593Smuzhiyun return ret;
136*4882a593Smuzhiyun break;
137*4882a593Smuzhiyun default:
138*4882a593Smuzhiyun break;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun return wm_adsp_early_event(w, kcontrol, event);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun #define CS47L85_NG_SRC(name, base) \
145*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
146*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
147*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \
148*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \
149*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \
150*4882a593Smuzhiyun SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \
151*4882a593Smuzhiyun SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \
152*4882a593Smuzhiyun SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \
153*4882a593Smuzhiyun SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
154*4882a593Smuzhiyun SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0), \
155*4882a593Smuzhiyun SOC_SINGLE(name " NG SPKDAT2L Switch", base, 10, 1, 0), \
156*4882a593Smuzhiyun SOC_SINGLE(name " NG SPKDAT2R Switch", base, 11, 1, 0)
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #define CS47L85_RXANC_INPUT_ROUTES(widget, name) \
159*4882a593Smuzhiyun { widget, NULL, name " NG Mux" }, \
160*4882a593Smuzhiyun { name " NG Internal", NULL, "RXANC NG Clock" }, \
161*4882a593Smuzhiyun { name " NG Internal", NULL, name " Channel" }, \
162*4882a593Smuzhiyun { name " NG External", NULL, "RXANC NG External Clock" }, \
163*4882a593Smuzhiyun { name " NG External", NULL, name " Channel" }, \
164*4882a593Smuzhiyun { name " NG Mux", "None", name " Channel" }, \
165*4882a593Smuzhiyun { name " NG Mux", "Internal", name " NG Internal" }, \
166*4882a593Smuzhiyun { name " NG Mux", "External", name " NG External" }, \
167*4882a593Smuzhiyun { name " Channel", "Left", name " Left Input" }, \
168*4882a593Smuzhiyun { name " Channel", "Combine", name " Left Input" }, \
169*4882a593Smuzhiyun { name " Channel", "Right", name " Right Input" }, \
170*4882a593Smuzhiyun { name " Channel", "Combine", name " Right Input" }, \
171*4882a593Smuzhiyun { name " Left Input", "IN1", "IN1L" }, \
172*4882a593Smuzhiyun { name " Right Input", "IN1", "IN1R" }, \
173*4882a593Smuzhiyun { name " Left Input", "IN2", "IN2L" }, \
174*4882a593Smuzhiyun { name " Right Input", "IN2", "IN2R" }, \
175*4882a593Smuzhiyun { name " Left Input", "IN3", "IN3L" }, \
176*4882a593Smuzhiyun { name " Right Input", "IN3", "IN3R" }, \
177*4882a593Smuzhiyun { name " Left Input", "IN4", "IN4L" }, \
178*4882a593Smuzhiyun { name " Right Input", "IN4", "IN4R" }, \
179*4882a593Smuzhiyun { name " Left Input", "IN5", "IN5L" }, \
180*4882a593Smuzhiyun { name " Right Input", "IN5", "IN5R" }, \
181*4882a593Smuzhiyun { name " Left Input", "IN6", "IN6L" }, \
182*4882a593Smuzhiyun { name " Right Input", "IN6", "IN6R" }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun #define CS47L85_RXANC_OUTPUT_ROUTES(widget, name) \
185*4882a593Smuzhiyun { widget, NULL, name " ANC Source" }, \
186*4882a593Smuzhiyun { name " ANC Source", "RXANCL", "RXANCL" }, \
187*4882a593Smuzhiyun { name " ANC Source", "RXANCR", "RXANCR" }
188*4882a593Smuzhiyun
cs47l85_hp_post_enable(struct snd_soc_dapm_widget * w)189*4882a593Smuzhiyun static void cs47l85_hp_post_enable(struct snd_soc_dapm_widget *w)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun struct snd_soc_component *component =
192*4882a593Smuzhiyun snd_soc_dapm_to_component(w->dapm);
193*4882a593Smuzhiyun unsigned int val;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun switch (w->shift) {
196*4882a593Smuzhiyun case MADERA_OUT1L_ENA_SHIFT:
197*4882a593Smuzhiyun case MADERA_OUT1R_ENA_SHIFT:
198*4882a593Smuzhiyun val = snd_soc_component_read(component, MADERA_OUTPUT_ENABLES_1);
199*4882a593Smuzhiyun val &= (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun if (val != (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA))
202*4882a593Smuzhiyun break;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun snd_soc_component_update_bits(component,
205*4882a593Smuzhiyun MADERA_EDRE_HP_STEREO_CONTROL,
206*4882a593Smuzhiyun 0x0001, 1);
207*4882a593Smuzhiyun break;
208*4882a593Smuzhiyun default:
209*4882a593Smuzhiyun break;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
cs47l85_hp_post_disable(struct snd_soc_dapm_widget * w)213*4882a593Smuzhiyun static void cs47l85_hp_post_disable(struct snd_soc_dapm_widget *w)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun struct snd_soc_component *component =
216*4882a593Smuzhiyun snd_soc_dapm_to_component(w->dapm);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun switch (w->shift) {
219*4882a593Smuzhiyun case MADERA_OUT1L_ENA_SHIFT:
220*4882a593Smuzhiyun snd_soc_component_write(component, MADERA_DCS_HP1L_CONTROL,
221*4882a593Smuzhiyun 0x2006);
222*4882a593Smuzhiyun break;
223*4882a593Smuzhiyun case MADERA_OUT1R_ENA_SHIFT:
224*4882a593Smuzhiyun snd_soc_component_write(component, MADERA_DCS_HP1R_CONTROL,
225*4882a593Smuzhiyun 0x2006);
226*4882a593Smuzhiyun break;
227*4882a593Smuzhiyun default:
228*4882a593Smuzhiyun return;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /* Only get to here for OUT1L and OUT1R */
232*4882a593Smuzhiyun snd_soc_component_update_bits(component,
233*4882a593Smuzhiyun MADERA_EDRE_HP_STEREO_CONTROL,
234*4882a593Smuzhiyun 0x0001, 0);
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
cs47l85_hp_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)237*4882a593Smuzhiyun static int cs47l85_hp_ev(struct snd_soc_dapm_widget *w,
238*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun int ret;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun switch (event) {
243*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
244*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
245*4882a593Smuzhiyun return madera_hp_ev(w, kcontrol, event);
246*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
247*4882a593Smuzhiyun ret = madera_hp_ev(w, kcontrol, event);
248*4882a593Smuzhiyun if (ret < 0)
249*4882a593Smuzhiyun return ret;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun cs47l85_hp_post_enable(w);
252*4882a593Smuzhiyun return 0;
253*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
254*4882a593Smuzhiyun ret = madera_hp_ev(w, kcontrol, event);
255*4882a593Smuzhiyun cs47l85_hp_post_disable(w);
256*4882a593Smuzhiyun return ret;
257*4882a593Smuzhiyun default:
258*4882a593Smuzhiyun return -EINVAL;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l85_snd_controls[] = {
263*4882a593Smuzhiyun SOC_ENUM("IN1 OSR", madera_in_dmic_osr[0]),
264*4882a593Smuzhiyun SOC_ENUM("IN2 OSR", madera_in_dmic_osr[1]),
265*4882a593Smuzhiyun SOC_ENUM("IN3 OSR", madera_in_dmic_osr[2]),
266*4882a593Smuzhiyun SOC_ENUM("IN4 OSR", madera_in_dmic_osr[3]),
267*4882a593Smuzhiyun SOC_ENUM("IN5 OSR", madera_in_dmic_osr[4]),
268*4882a593Smuzhiyun SOC_ENUM("IN6 OSR", madera_in_dmic_osr[5]),
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN1L Volume", MADERA_IN1L_CONTROL,
271*4882a593Smuzhiyun MADERA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
272*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN1R Volume", MADERA_IN1R_CONTROL,
273*4882a593Smuzhiyun MADERA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
274*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN2L Volume", MADERA_IN2L_CONTROL,
275*4882a593Smuzhiyun MADERA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
276*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN2R Volume", MADERA_IN2R_CONTROL,
277*4882a593Smuzhiyun MADERA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
278*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN3L Volume", MADERA_IN3L_CONTROL,
279*4882a593Smuzhiyun MADERA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
280*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN3R Volume", MADERA_IN3R_CONTROL,
281*4882a593Smuzhiyun MADERA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun SOC_ENUM("IN HPF Cutoff Frequency", madera_in_hpf_cut_enum),
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun SOC_SINGLE("IN1L HPF Switch", MADERA_IN1L_CONTROL,
286*4882a593Smuzhiyun MADERA_IN1L_HPF_SHIFT, 1, 0),
287*4882a593Smuzhiyun SOC_SINGLE("IN1R HPF Switch", MADERA_IN1R_CONTROL,
288*4882a593Smuzhiyun MADERA_IN1R_HPF_SHIFT, 1, 0),
289*4882a593Smuzhiyun SOC_SINGLE("IN2L HPF Switch", MADERA_IN2L_CONTROL,
290*4882a593Smuzhiyun MADERA_IN2L_HPF_SHIFT, 1, 0),
291*4882a593Smuzhiyun SOC_SINGLE("IN2R HPF Switch", MADERA_IN2R_CONTROL,
292*4882a593Smuzhiyun MADERA_IN2R_HPF_SHIFT, 1, 0),
293*4882a593Smuzhiyun SOC_SINGLE("IN3L HPF Switch", MADERA_IN3L_CONTROL,
294*4882a593Smuzhiyun MADERA_IN3L_HPF_SHIFT, 1, 0),
295*4882a593Smuzhiyun SOC_SINGLE("IN3R HPF Switch", MADERA_IN3R_CONTROL,
296*4882a593Smuzhiyun MADERA_IN3R_HPF_SHIFT, 1, 0),
297*4882a593Smuzhiyun SOC_SINGLE("IN4L HPF Switch", MADERA_IN4L_CONTROL,
298*4882a593Smuzhiyun MADERA_IN4L_HPF_SHIFT, 1, 0),
299*4882a593Smuzhiyun SOC_SINGLE("IN4R HPF Switch", MADERA_IN4R_CONTROL,
300*4882a593Smuzhiyun MADERA_IN4R_HPF_SHIFT, 1, 0),
301*4882a593Smuzhiyun SOC_SINGLE("IN5L HPF Switch", MADERA_IN5L_CONTROL,
302*4882a593Smuzhiyun MADERA_IN5L_HPF_SHIFT, 1, 0),
303*4882a593Smuzhiyun SOC_SINGLE("IN5R HPF Switch", MADERA_IN5R_CONTROL,
304*4882a593Smuzhiyun MADERA_IN5R_HPF_SHIFT, 1, 0),
305*4882a593Smuzhiyun SOC_SINGLE("IN6L HPF Switch", MADERA_IN6L_CONTROL,
306*4882a593Smuzhiyun MADERA_IN6L_HPF_SHIFT, 1, 0),
307*4882a593Smuzhiyun SOC_SINGLE("IN6R HPF Switch", MADERA_IN6R_CONTROL,
308*4882a593Smuzhiyun MADERA_IN6R_HPF_SHIFT, 1, 0),
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1L,
311*4882a593Smuzhiyun MADERA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
312*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1R,
313*4882a593Smuzhiyun MADERA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
314*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2L,
315*4882a593Smuzhiyun MADERA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
316*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2R,
317*4882a593Smuzhiyun MADERA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
318*4882a593Smuzhiyun SOC_SINGLE_TLV("IN3L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3L,
319*4882a593Smuzhiyun MADERA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
320*4882a593Smuzhiyun SOC_SINGLE_TLV("IN3R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3R,
321*4882a593Smuzhiyun MADERA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
322*4882a593Smuzhiyun SOC_SINGLE_TLV("IN4L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4L,
323*4882a593Smuzhiyun MADERA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
324*4882a593Smuzhiyun SOC_SINGLE_TLV("IN4R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4R,
325*4882a593Smuzhiyun MADERA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
326*4882a593Smuzhiyun SOC_SINGLE_TLV("IN5L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_5L,
327*4882a593Smuzhiyun MADERA_IN5L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
328*4882a593Smuzhiyun SOC_SINGLE_TLV("IN5R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_5R,
329*4882a593Smuzhiyun MADERA_IN5R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
330*4882a593Smuzhiyun SOC_SINGLE_TLV("IN6L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_6L,
331*4882a593Smuzhiyun MADERA_IN6L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
332*4882a593Smuzhiyun SOC_SINGLE_TLV("IN6R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_6R,
333*4882a593Smuzhiyun MADERA_IN6R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun SOC_ENUM("Input Ramp Up", madera_in_vi_ramp),
336*4882a593Smuzhiyun SOC_ENUM("Input Ramp Down", madera_in_vd_ramp),
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun SND_SOC_BYTES("RXANC Coefficients", MADERA_ANC_COEFF_START,
339*4882a593Smuzhiyun MADERA_ANC_COEFF_END - MADERA_ANC_COEFF_START + 1),
340*4882a593Smuzhiyun SND_SOC_BYTES("RXANCL Config", MADERA_FCL_FILTER_CONTROL, 1),
341*4882a593Smuzhiyun SND_SOC_BYTES("RXANCL Coefficients", MADERA_FCL_COEFF_START,
342*4882a593Smuzhiyun MADERA_FCL_COEFF_END - MADERA_FCL_COEFF_START + 1),
343*4882a593Smuzhiyun SND_SOC_BYTES("RXANCR Config", MADERA_FCR_FILTER_CONTROL, 1),
344*4882a593Smuzhiyun SND_SOC_BYTES("RXANCR Coefficients", MADERA_FCR_COEFF_START,
345*4882a593Smuzhiyun MADERA_FCR_COEFF_END - MADERA_FCR_COEFF_START + 1),
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ1", MADERA_EQ1MIX_INPUT_1_SOURCE),
348*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ2", MADERA_EQ2MIX_INPUT_1_SOURCE),
349*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ3", MADERA_EQ3MIX_INPUT_1_SOURCE),
350*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ4", MADERA_EQ4MIX_INPUT_1_SOURCE),
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ1 Coefficients", MADERA_EQ1_2),
353*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B1 Volume", MADERA_EQ1_1, MADERA_EQ1_B1_GAIN_SHIFT,
354*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
355*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B2 Volume", MADERA_EQ1_1, MADERA_EQ1_B2_GAIN_SHIFT,
356*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
357*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B3 Volume", MADERA_EQ1_1, MADERA_EQ1_B3_GAIN_SHIFT,
358*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
359*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B4 Volume", MADERA_EQ1_2, MADERA_EQ1_B4_GAIN_SHIFT,
360*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
361*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B5 Volume", MADERA_EQ1_2, MADERA_EQ1_B5_GAIN_SHIFT,
362*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ2 Coefficients", MADERA_EQ2_2),
365*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B1 Volume", MADERA_EQ2_1, MADERA_EQ2_B1_GAIN_SHIFT,
366*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
367*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B2 Volume", MADERA_EQ2_1, MADERA_EQ2_B2_GAIN_SHIFT,
368*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
369*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B3 Volume", MADERA_EQ2_1, MADERA_EQ2_B3_GAIN_SHIFT,
370*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
371*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B4 Volume", MADERA_EQ2_2, MADERA_EQ2_B4_GAIN_SHIFT,
372*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
373*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B5 Volume", MADERA_EQ2_2, MADERA_EQ2_B5_GAIN_SHIFT,
374*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ3 Coefficients", MADERA_EQ3_2),
377*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B1 Volume", MADERA_EQ3_1, MADERA_EQ3_B1_GAIN_SHIFT,
378*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
379*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B2 Volume", MADERA_EQ3_1, MADERA_EQ3_B2_GAIN_SHIFT,
380*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
381*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B3 Volume", MADERA_EQ3_1, MADERA_EQ3_B3_GAIN_SHIFT,
382*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
383*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B4 Volume", MADERA_EQ3_2, MADERA_EQ3_B4_GAIN_SHIFT,
384*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
385*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B5 Volume", MADERA_EQ3_2, MADERA_EQ3_B5_GAIN_SHIFT,
386*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ4 Coefficients", MADERA_EQ4_2),
389*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B1 Volume", MADERA_EQ4_1, MADERA_EQ4_B1_GAIN_SHIFT,
390*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
391*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B2 Volume", MADERA_EQ4_1, MADERA_EQ4_B2_GAIN_SHIFT,
392*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
393*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B3 Volume", MADERA_EQ4_1, MADERA_EQ4_B3_GAIN_SHIFT,
394*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
395*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B4 Volume", MADERA_EQ4_2, MADERA_EQ4_B4_GAIN_SHIFT,
396*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
397*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B5 Volume", MADERA_EQ4_2, MADERA_EQ4_B5_GAIN_SHIFT,
398*4882a593Smuzhiyun 24, 0, madera_eq_tlv),
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC1L", MADERA_DRC1LMIX_INPUT_1_SOURCE),
401*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC1R", MADERA_DRC1RMIX_INPUT_1_SOURCE),
402*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC2L", MADERA_DRC2LMIX_INPUT_1_SOURCE),
403*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC2R", MADERA_DRC2RMIX_INPUT_1_SOURCE),
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun SND_SOC_BYTES_MASK("DRC1", MADERA_DRC1_CTRL1, 5,
406*4882a593Smuzhiyun MADERA_DRC1R_ENA | MADERA_DRC1L_ENA),
407*4882a593Smuzhiyun SND_SOC_BYTES_MASK("DRC2", MADERA_DRC2_CTRL1, 5,
408*4882a593Smuzhiyun MADERA_DRC2R_ENA | MADERA_DRC2L_ENA),
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF1", MADERA_HPLP1MIX_INPUT_1_SOURCE),
411*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF2", MADERA_HPLP2MIX_INPUT_1_SOURCE),
412*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF3", MADERA_HPLP3MIX_INPUT_1_SOURCE),
413*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF4", MADERA_HPLP4MIX_INPUT_1_SOURCE),
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF1 Coefficients", MADERA_HPLPF1_2),
416*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF2 Coefficients", MADERA_HPLPF2_2),
417*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF3 Coefficients", MADERA_HPLPF3_2),
418*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF4 Coefficients", MADERA_HPLPF4_2),
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun SOC_ENUM("LHPF1 Mode", madera_lhpf1_mode),
421*4882a593Smuzhiyun SOC_ENUM("LHPF2 Mode", madera_lhpf2_mode),
422*4882a593Smuzhiyun SOC_ENUM("LHPF3 Mode", madera_lhpf3_mode),
423*4882a593Smuzhiyun SOC_ENUM("LHPF4 Mode", madera_lhpf4_mode),
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC1 FSL", madera_isrc_fsl[0]),
426*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC2 FSL", madera_isrc_fsl[1]),
427*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC3 FSL", madera_isrc_fsl[2]),
428*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC4 FSL", madera_isrc_fsl[3]),
429*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC1 FSH", madera_isrc_fsh[0]),
430*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC2 FSH", madera_isrc_fsh[1]),
431*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC3 FSH", madera_isrc_fsh[2]),
432*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC4 FSH", madera_isrc_fsh[3]),
433*4882a593Smuzhiyun MADERA_RATE_ENUM("ASRC1 Rate 1", madera_asrc1_rate[0]),
434*4882a593Smuzhiyun MADERA_RATE_ENUM("ASRC1 Rate 2", madera_asrc1_rate[1]),
435*4882a593Smuzhiyun MADERA_RATE_ENUM("ASRC2 Rate 1", madera_asrc2_rate[0]),
436*4882a593Smuzhiyun MADERA_RATE_ENUM("ASRC2 Rate 2", madera_asrc2_rate[1]),
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
439*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP2", 2),
440*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP3", 3),
441*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP4", 4),
442*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP5", 5),
443*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP6", 6),
444*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP7", 7),
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP1L", MADERA_DSP1LMIX_INPUT_1_SOURCE),
447*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP1R", MADERA_DSP1RMIX_INPUT_1_SOURCE),
448*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP2L", MADERA_DSP2LMIX_INPUT_1_SOURCE),
449*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP2R", MADERA_DSP2RMIX_INPUT_1_SOURCE),
450*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP3L", MADERA_DSP3LMIX_INPUT_1_SOURCE),
451*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP3R", MADERA_DSP3RMIX_INPUT_1_SOURCE),
452*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP4L", MADERA_DSP4LMIX_INPUT_1_SOURCE),
453*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP4R", MADERA_DSP4RMIX_INPUT_1_SOURCE),
454*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP5L", MADERA_DSP5LMIX_INPUT_1_SOURCE),
455*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP5R", MADERA_DSP5RMIX_INPUT_1_SOURCE),
456*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP6L", MADERA_DSP6LMIX_INPUT_1_SOURCE),
457*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP6R", MADERA_DSP6RMIX_INPUT_1_SOURCE),
458*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP7L", MADERA_DSP7LMIX_INPUT_1_SOURCE),
459*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP7R", MADERA_DSP7RMIX_INPUT_1_SOURCE),
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Generator Volume", MADERA_COMFORT_NOISE_GENERATOR,
462*4882a593Smuzhiyun MADERA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, madera_noise_tlv),
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT1L", MADERA_OUT1LMIX_INPUT_1_SOURCE),
465*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT1R", MADERA_OUT1RMIX_INPUT_1_SOURCE),
466*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT2L", MADERA_OUT2LMIX_INPUT_1_SOURCE),
467*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT2R", MADERA_OUT2RMIX_INPUT_1_SOURCE),
468*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT3L", MADERA_OUT3LMIX_INPUT_1_SOURCE),
469*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT3R", MADERA_OUT3RMIX_INPUT_1_SOURCE),
470*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKOUTL", MADERA_OUT4LMIX_INPUT_1_SOURCE),
471*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKOUTR", MADERA_OUT4RMIX_INPUT_1_SOURCE),
472*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT1L", MADERA_OUT5LMIX_INPUT_1_SOURCE),
473*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT1R", MADERA_OUT5RMIX_INPUT_1_SOURCE),
474*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT2L", MADERA_OUT6LMIX_INPUT_1_SOURCE),
475*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT2R", MADERA_OUT6RMIX_INPUT_1_SOURCE),
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun SOC_SINGLE("HPOUT1 SC Protect Switch", MADERA_HP1_SHORT_CIRCUIT_CTRL,
478*4882a593Smuzhiyun MADERA_HP1_SC_ENA_SHIFT, 1, 0),
479*4882a593Smuzhiyun SOC_SINGLE("HPOUT2 SC Protect Switch", MADERA_HP2_SHORT_CIRCUIT_CTRL,
480*4882a593Smuzhiyun MADERA_HP2_SC_ENA_SHIFT, 1, 0),
481*4882a593Smuzhiyun SOC_SINGLE("HPOUT3 SC Protect Switch", MADERA_HP3_SHORT_CIRCUIT_CTRL,
482*4882a593Smuzhiyun MADERA_HP3_SC_ENA_SHIFT, 1, 0),
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun SOC_SINGLE("SPKDAT1 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_5L,
485*4882a593Smuzhiyun MADERA_OUT5_OSR_SHIFT, 1, 0),
486*4882a593Smuzhiyun SOC_SINGLE("SPKDAT2 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_6L,
487*4882a593Smuzhiyun MADERA_OUT6_OSR_SHIFT, 1, 0),
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_1L,
490*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_MUTE_SHIFT, 1, 1),
491*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT2 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_2L,
492*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_MUTE_SHIFT, 1, 1),
493*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT3 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_3L,
494*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_MUTE_SHIFT, 1, 1),
495*4882a593Smuzhiyun SOC_DOUBLE_R("Speaker Digital Switch", MADERA_DAC_DIGITAL_VOLUME_4L,
496*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_4R, MADERA_OUT4L_MUTE_SHIFT, 1, 1),
497*4882a593Smuzhiyun SOC_DOUBLE_R("SPKDAT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_5L,
498*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_MUTE_SHIFT, 1, 1),
499*4882a593Smuzhiyun SOC_DOUBLE_R("SPKDAT2 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_6L,
500*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_6R, MADERA_OUT6L_MUTE_SHIFT, 1, 1),
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_1L,
503*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_VOL_SHIFT,
504*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
505*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_2L,
506*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_VOL_SHIFT,
507*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
508*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_3L,
509*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_VOL_SHIFT,
510*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
511*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Speaker Digital Volume", MADERA_DAC_DIGITAL_VOLUME_4L,
512*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_4R, MADERA_OUT4L_VOL_SHIFT,
513*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
514*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_5L,
515*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_VOL_SHIFT,
516*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
517*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_6L,
518*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_6R, MADERA_OUT6L_VOL_SHIFT,
519*4882a593Smuzhiyun 0xbf, 0, madera_digital_tlv),
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun SOC_DOUBLE("SPKDAT1 Switch", MADERA_PDM_SPK1_CTRL_1, MADERA_SPK1L_MUTE_SHIFT,
522*4882a593Smuzhiyun MADERA_SPK1R_MUTE_SHIFT, 1, 1),
523*4882a593Smuzhiyun SOC_DOUBLE("SPKDAT2 Switch", MADERA_PDM_SPK2_CTRL_1, MADERA_SPK2L_MUTE_SHIFT,
524*4882a593Smuzhiyun MADERA_SPK2R_MUTE_SHIFT, 1, 1),
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun SOC_ENUM("Output Ramp Up", madera_out_vi_ramp),
527*4882a593Smuzhiyun SOC_ENUM("Output Ramp Down", madera_out_vd_ramp),
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun SOC_SINGLE("Noise Gate Switch", MADERA_NOISE_GATE_CONTROL,
530*4882a593Smuzhiyun MADERA_NGATE_ENA_SHIFT, 1, 0),
531*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Gate Threshold Volume", MADERA_NOISE_GATE_CONTROL,
532*4882a593Smuzhiyun MADERA_NGATE_THR_SHIFT, 7, 1, madera_ng_tlv),
533*4882a593Smuzhiyun SOC_ENUM("Noise Gate Hold", madera_ng_hold),
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun CS47L85_NG_SRC("HPOUT1L", MADERA_NOISE_GATE_SELECT_1L),
536*4882a593Smuzhiyun CS47L85_NG_SRC("HPOUT1R", MADERA_NOISE_GATE_SELECT_1R),
537*4882a593Smuzhiyun CS47L85_NG_SRC("HPOUT2L", MADERA_NOISE_GATE_SELECT_2L),
538*4882a593Smuzhiyun CS47L85_NG_SRC("HPOUT2R", MADERA_NOISE_GATE_SELECT_2R),
539*4882a593Smuzhiyun CS47L85_NG_SRC("HPOUT3L", MADERA_NOISE_GATE_SELECT_3L),
540*4882a593Smuzhiyun CS47L85_NG_SRC("HPOUT3R", MADERA_NOISE_GATE_SELECT_3R),
541*4882a593Smuzhiyun CS47L85_NG_SRC("SPKOUTL", MADERA_NOISE_GATE_SELECT_4L),
542*4882a593Smuzhiyun CS47L85_NG_SRC("SPKOUTR", MADERA_NOISE_GATE_SELECT_4R),
543*4882a593Smuzhiyun CS47L85_NG_SRC("SPKDAT1L", MADERA_NOISE_GATE_SELECT_5L),
544*4882a593Smuzhiyun CS47L85_NG_SRC("SPKDAT1R", MADERA_NOISE_GATE_SELECT_5R),
545*4882a593Smuzhiyun CS47L85_NG_SRC("SPKDAT2L", MADERA_NOISE_GATE_SELECT_6L),
546*4882a593Smuzhiyun CS47L85_NG_SRC("SPKDAT2R", MADERA_NOISE_GATE_SELECT_6R),
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX1", MADERA_AIF1TX1MIX_INPUT_1_SOURCE),
549*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX2", MADERA_AIF1TX2MIX_INPUT_1_SOURCE),
550*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX3", MADERA_AIF1TX3MIX_INPUT_1_SOURCE),
551*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX4", MADERA_AIF1TX4MIX_INPUT_1_SOURCE),
552*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX5", MADERA_AIF1TX5MIX_INPUT_1_SOURCE),
553*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX6", MADERA_AIF1TX6MIX_INPUT_1_SOURCE),
554*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX7", MADERA_AIF1TX7MIX_INPUT_1_SOURCE),
555*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX8", MADERA_AIF1TX8MIX_INPUT_1_SOURCE),
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX1", MADERA_AIF2TX1MIX_INPUT_1_SOURCE),
558*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX2", MADERA_AIF2TX2MIX_INPUT_1_SOURCE),
559*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX3", MADERA_AIF2TX3MIX_INPUT_1_SOURCE),
560*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX4", MADERA_AIF2TX4MIX_INPUT_1_SOURCE),
561*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX5", MADERA_AIF2TX5MIX_INPUT_1_SOURCE),
562*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX6", MADERA_AIF2TX6MIX_INPUT_1_SOURCE),
563*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX7", MADERA_AIF2TX7MIX_INPUT_1_SOURCE),
564*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX8", MADERA_AIF2TX8MIX_INPUT_1_SOURCE),
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX1", MADERA_AIF3TX1MIX_INPUT_1_SOURCE),
567*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX2", MADERA_AIF3TX2MIX_INPUT_1_SOURCE),
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF4TX1", MADERA_AIF4TX1MIX_INPUT_1_SOURCE),
570*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF4TX2", MADERA_AIF4TX2MIX_INPUT_1_SOURCE),
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX1", MADERA_SLIMTX1MIX_INPUT_1_SOURCE),
573*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX2", MADERA_SLIMTX2MIX_INPUT_1_SOURCE),
574*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX3", MADERA_SLIMTX3MIX_INPUT_1_SOURCE),
575*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX4", MADERA_SLIMTX4MIX_INPUT_1_SOURCE),
576*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX5", MADERA_SLIMTX5MIX_INPUT_1_SOURCE),
577*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX6", MADERA_SLIMTX6MIX_INPUT_1_SOURCE),
578*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX7", MADERA_SLIMTX7MIX_INPUT_1_SOURCE),
579*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX8", MADERA_SLIMTX8MIX_INPUT_1_SOURCE),
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun MADERA_GAINMUX_CONTROLS("SPDIF1TX1", MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE),
582*4882a593Smuzhiyun MADERA_GAINMUX_CONTROLS("SPDIF1TX2", MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE),
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP1", 0),
585*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP2", 1),
586*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP3", 2),
587*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP4", 3),
588*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP5", 4),
589*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP6", 5),
590*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP7", 6),
591*4882a593Smuzhiyun };
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ1, MADERA_EQ1MIX_INPUT_1_SOURCE);
594*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ2, MADERA_EQ2MIX_INPUT_1_SOURCE);
595*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ3, MADERA_EQ3MIX_INPUT_1_SOURCE);
596*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ4, MADERA_EQ4MIX_INPUT_1_SOURCE);
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC1L, MADERA_DRC1LMIX_INPUT_1_SOURCE);
599*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC1R, MADERA_DRC1RMIX_INPUT_1_SOURCE);
600*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC2L, MADERA_DRC2LMIX_INPUT_1_SOURCE);
601*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC2R, MADERA_DRC2RMIX_INPUT_1_SOURCE);
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF1, MADERA_HPLP1MIX_INPUT_1_SOURCE);
604*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF2, MADERA_HPLP2MIX_INPUT_1_SOURCE);
605*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF3, MADERA_HPLP3MIX_INPUT_1_SOURCE);
606*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF4, MADERA_HPLP4MIX_INPUT_1_SOURCE);
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP1L, MADERA_DSP1LMIX_INPUT_1_SOURCE);
609*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP1R, MADERA_DSP1RMIX_INPUT_1_SOURCE);
610*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP1, MADERA_DSP1AUX1MIX_INPUT_1_SOURCE);
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP2L, MADERA_DSP2LMIX_INPUT_1_SOURCE);
613*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP2R, MADERA_DSP2RMIX_INPUT_1_SOURCE);
614*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP2, MADERA_DSP2AUX1MIX_INPUT_1_SOURCE);
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP3L, MADERA_DSP3LMIX_INPUT_1_SOURCE);
617*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP3R, MADERA_DSP3RMIX_INPUT_1_SOURCE);
618*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP3, MADERA_DSP3AUX1MIX_INPUT_1_SOURCE);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP4L, MADERA_DSP4LMIX_INPUT_1_SOURCE);
621*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP4R, MADERA_DSP4RMIX_INPUT_1_SOURCE);
622*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP4, MADERA_DSP4AUX1MIX_INPUT_1_SOURCE);
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP5L, MADERA_DSP5LMIX_INPUT_1_SOURCE);
625*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP5R, MADERA_DSP5RMIX_INPUT_1_SOURCE);
626*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP5, MADERA_DSP5AUX1MIX_INPUT_1_SOURCE);
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP6L, MADERA_DSP6LMIX_INPUT_1_SOURCE);
629*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP6R, MADERA_DSP6RMIX_INPUT_1_SOURCE);
630*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP6, MADERA_DSP6AUX1MIX_INPUT_1_SOURCE);
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP7L, MADERA_DSP7LMIX_INPUT_1_SOURCE);
633*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP7R, MADERA_DSP7RMIX_INPUT_1_SOURCE);
634*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP7, MADERA_DSP7AUX1MIX_INPUT_1_SOURCE);
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun MADERA_MIXER_ENUMS(PWM1, MADERA_PWM1MIX_INPUT_1_SOURCE);
637*4882a593Smuzhiyun MADERA_MIXER_ENUMS(PWM2, MADERA_PWM2MIX_INPUT_1_SOURCE);
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT1L, MADERA_OUT1LMIX_INPUT_1_SOURCE);
640*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT1R, MADERA_OUT1RMIX_INPUT_1_SOURCE);
641*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT2L, MADERA_OUT2LMIX_INPUT_1_SOURCE);
642*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT2R, MADERA_OUT2RMIX_INPUT_1_SOURCE);
643*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT3L, MADERA_OUT3LMIX_INPUT_1_SOURCE);
644*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT3R, MADERA_OUT3RMIX_INPUT_1_SOURCE);
645*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKOUTL, MADERA_OUT4LMIX_INPUT_1_SOURCE);
646*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKOUTR, MADERA_OUT4RMIX_INPUT_1_SOURCE);
647*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT1L, MADERA_OUT5LMIX_INPUT_1_SOURCE);
648*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT1R, MADERA_OUT5RMIX_INPUT_1_SOURCE);
649*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT2L, MADERA_OUT6LMIX_INPUT_1_SOURCE);
650*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT2R, MADERA_OUT6RMIX_INPUT_1_SOURCE);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX1, MADERA_AIF1TX1MIX_INPUT_1_SOURCE);
653*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX2, MADERA_AIF1TX2MIX_INPUT_1_SOURCE);
654*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX3, MADERA_AIF1TX3MIX_INPUT_1_SOURCE);
655*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX4, MADERA_AIF1TX4MIX_INPUT_1_SOURCE);
656*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX5, MADERA_AIF1TX5MIX_INPUT_1_SOURCE);
657*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX6, MADERA_AIF1TX6MIX_INPUT_1_SOURCE);
658*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX7, MADERA_AIF1TX7MIX_INPUT_1_SOURCE);
659*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX8, MADERA_AIF1TX8MIX_INPUT_1_SOURCE);
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX1, MADERA_AIF2TX1MIX_INPUT_1_SOURCE);
662*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX2, MADERA_AIF2TX2MIX_INPUT_1_SOURCE);
663*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX3, MADERA_AIF2TX3MIX_INPUT_1_SOURCE);
664*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX4, MADERA_AIF2TX4MIX_INPUT_1_SOURCE);
665*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX5, MADERA_AIF2TX5MIX_INPUT_1_SOURCE);
666*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX6, MADERA_AIF2TX6MIX_INPUT_1_SOURCE);
667*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX7, MADERA_AIF2TX7MIX_INPUT_1_SOURCE);
668*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX8, MADERA_AIF2TX8MIX_INPUT_1_SOURCE);
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX1, MADERA_AIF3TX1MIX_INPUT_1_SOURCE);
671*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX2, MADERA_AIF3TX2MIX_INPUT_1_SOURCE);
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF4TX1, MADERA_AIF4TX1MIX_INPUT_1_SOURCE);
674*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF4TX2, MADERA_AIF4TX2MIX_INPUT_1_SOURCE);
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX1, MADERA_SLIMTX1MIX_INPUT_1_SOURCE);
677*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX2, MADERA_SLIMTX2MIX_INPUT_1_SOURCE);
678*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX3, MADERA_SLIMTX3MIX_INPUT_1_SOURCE);
679*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX4, MADERA_SLIMTX4MIX_INPUT_1_SOURCE);
680*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX5, MADERA_SLIMTX5MIX_INPUT_1_SOURCE);
681*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX6, MADERA_SLIMTX6MIX_INPUT_1_SOURCE);
682*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX7, MADERA_SLIMTX7MIX_INPUT_1_SOURCE);
683*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX8, MADERA_SLIMTX8MIX_INPUT_1_SOURCE);
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun MADERA_MUX_ENUMS(SPD1TX1, MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE);
686*4882a593Smuzhiyun MADERA_MUX_ENUMS(SPD1TX2, MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE);
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN1L, MADERA_ASRC1_1LMIX_INPUT_1_SOURCE);
689*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN1R, MADERA_ASRC1_1RMIX_INPUT_1_SOURCE);
690*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN2L, MADERA_ASRC1_2LMIX_INPUT_1_SOURCE);
691*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC1IN2R, MADERA_ASRC1_2RMIX_INPUT_1_SOURCE);
692*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC2IN1L, MADERA_ASRC2_1LMIX_INPUT_1_SOURCE);
693*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC2IN1R, MADERA_ASRC2_1RMIX_INPUT_1_SOURCE);
694*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC2IN2L, MADERA_ASRC2_2LMIX_INPUT_1_SOURCE);
695*4882a593Smuzhiyun MADERA_MUX_ENUMS(ASRC2IN2R, MADERA_ASRC2_2RMIX_INPUT_1_SOURCE);
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT1, MADERA_ISRC1INT1MIX_INPUT_1_SOURCE);
698*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT2, MADERA_ISRC1INT2MIX_INPUT_1_SOURCE);
699*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT3, MADERA_ISRC1INT3MIX_INPUT_1_SOURCE);
700*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT4, MADERA_ISRC1INT4MIX_INPUT_1_SOURCE);
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC1, MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE);
703*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC2, MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE);
704*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC3, MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE);
705*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC4, MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE);
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT1, MADERA_ISRC2INT1MIX_INPUT_1_SOURCE);
708*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT2, MADERA_ISRC2INT2MIX_INPUT_1_SOURCE);
709*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT3, MADERA_ISRC2INT3MIX_INPUT_1_SOURCE);
710*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT4, MADERA_ISRC2INT4MIX_INPUT_1_SOURCE);
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC1, MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE);
713*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC2, MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE);
714*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC3, MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE);
715*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC4, MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE);
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC3INT1, MADERA_ISRC3INT1MIX_INPUT_1_SOURCE);
718*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC3INT2, MADERA_ISRC3INT2MIX_INPUT_1_SOURCE);
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC3DEC1, MADERA_ISRC3DEC1MIX_INPUT_1_SOURCE);
721*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC3DEC2, MADERA_ISRC3DEC2MIX_INPUT_1_SOURCE);
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC4INT1, MADERA_ISRC4INT1MIX_INPUT_1_SOURCE);
724*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC4INT2, MADERA_ISRC4INT2MIX_INPUT_1_SOURCE);
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC4DEC1, MADERA_ISRC4DEC1MIX_INPUT_1_SOURCE);
727*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC4DEC2, MADERA_ISRC4DEC2MIX_INPUT_1_SOURCE);
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun static const char * const cs47l85_aec_loopback_texts[] = {
730*4882a593Smuzhiyun "HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R",
731*4882a593Smuzhiyun "SPKOUTL", "SPKOUTR", "SPKDAT1L", "SPKDAT1R", "SPKDAT2L", "SPKDAT2R",
732*4882a593Smuzhiyun };
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun static const unsigned int cs47l85_aec_loopback_values[] = {
735*4882a593Smuzhiyun 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
736*4882a593Smuzhiyun };
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun static const struct soc_enum cs47l85_aec1_loopback =
739*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_1,
740*4882a593Smuzhiyun MADERA_AEC1_LOOPBACK_SRC_SHIFT, 0xf,
741*4882a593Smuzhiyun ARRAY_SIZE(cs47l85_aec_loopback_texts),
742*4882a593Smuzhiyun cs47l85_aec_loopback_texts,
743*4882a593Smuzhiyun cs47l85_aec_loopback_values);
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun static const struct soc_enum cs47l85_aec2_loopback =
746*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_2,
747*4882a593Smuzhiyun MADERA_AEC2_LOOPBACK_SRC_SHIFT, 0xf,
748*4882a593Smuzhiyun ARRAY_SIZE(cs47l85_aec_loopback_texts),
749*4882a593Smuzhiyun cs47l85_aec_loopback_texts,
750*4882a593Smuzhiyun cs47l85_aec_loopback_values);
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l85_aec_loopback_mux[] = {
753*4882a593Smuzhiyun SOC_DAPM_ENUM("AEC1 Loopback", cs47l85_aec1_loopback),
754*4882a593Smuzhiyun SOC_DAPM_ENUM("AEC2 Loopback", cs47l85_aec2_loopback),
755*4882a593Smuzhiyun };
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l85_anc_input_mux[] = {
758*4882a593Smuzhiyun SOC_DAPM_ENUM("RXANCL Input", madera_anc_input_src[0]),
759*4882a593Smuzhiyun SOC_DAPM_ENUM("RXANCL Channel", madera_anc_input_src[1]),
760*4882a593Smuzhiyun SOC_DAPM_ENUM("RXANCR Input", madera_anc_input_src[2]),
761*4882a593Smuzhiyun SOC_DAPM_ENUM("RXANCR Channel", madera_anc_input_src[3]),
762*4882a593Smuzhiyun };
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l85_anc_ng_mux =
765*4882a593Smuzhiyun SOC_DAPM_ENUM("RXANC NG Source", madera_anc_ng_enum);
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l85_output_anc_src[] = {
768*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT1L ANC Source", madera_output_anc_src[0]),
769*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT1R ANC Source", madera_output_anc_src[1]),
770*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT2L ANC Source", madera_output_anc_src[2]),
771*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT2R ANC Source", madera_output_anc_src[3]),
772*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT3L ANC Source", madera_output_anc_src[4]),
773*4882a593Smuzhiyun SOC_DAPM_ENUM("HPOUT3R ANC Source", madera_output_anc_src[5]),
774*4882a593Smuzhiyun SOC_DAPM_ENUM("SPKOUTL ANC Source", madera_output_anc_src[6]),
775*4882a593Smuzhiyun SOC_DAPM_ENUM("SPKOUTR ANC Source", madera_output_anc_src[7]),
776*4882a593Smuzhiyun SOC_DAPM_ENUM("SPKDAT1L ANC Source", madera_output_anc_src[8]),
777*4882a593Smuzhiyun SOC_DAPM_ENUM("SPKDAT1R ANC Source", madera_output_anc_src[9]),
778*4882a593Smuzhiyun SOC_DAPM_ENUM("SPKDAT2L ANC Source", madera_output_anc_src[10]),
779*4882a593Smuzhiyun SOC_DAPM_ENUM("SPKDAT2R ANC Source", madera_output_anc_src[11]),
780*4882a593Smuzhiyun };
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun static const struct snd_soc_dapm_widget cs47l85_dapm_widgets[] = {
783*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SYSCLK", MADERA_SYSTEM_CLOCK_1, MADERA_SYSCLK_ENA_SHIFT,
784*4882a593Smuzhiyun 0, madera_sysclk_ev,
785*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
786*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
787*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASYNCCLK", MADERA_ASYNC_CLOCK_1,
788*4882a593Smuzhiyun MADERA_ASYNC_CLK_ENA_SHIFT, 0, madera_clk_ev,
789*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
790*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OPCLK", MADERA_OUTPUT_SYSTEM_CLOCK,
791*4882a593Smuzhiyun MADERA_OPCLK_ENA_SHIFT, 0, NULL, 0),
792*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", MADERA_OUTPUT_ASYNC_CLOCK,
793*4882a593Smuzhiyun MADERA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
794*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSPCLK", MADERA_DSP_CLOCK_1, MADERA_DSP_CLK_ENA_SHIFT,
795*4882a593Smuzhiyun 0, madera_clk_ev,
796*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
799*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
800*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD4", 0, 0),
801*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD1", 20, 0),
802*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD2", 20, 0),
803*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
804*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDL", 0, 0),
805*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDR", 0, 0),
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1", MADERA_MIC_BIAS_CTRL_1,
808*4882a593Smuzhiyun MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
809*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2", MADERA_MIC_BIAS_CTRL_2,
810*4882a593Smuzhiyun MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
811*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS3", MADERA_MIC_BIAS_CTRL_3,
812*4882a593Smuzhiyun MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
813*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS4", MADERA_MIC_BIAS_CTRL_4,
814*4882a593Smuzhiyun MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("FXCLK", SND_SOC_NOPM,
817*4882a593Smuzhiyun MADERA_DOM_GRP_FX, 0,
818*4882a593Smuzhiyun madera_domain_clk_ev,
819*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
820*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASRC1CLK", SND_SOC_NOPM,
821*4882a593Smuzhiyun MADERA_DOM_GRP_ASRC1, 0,
822*4882a593Smuzhiyun madera_domain_clk_ev,
823*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
824*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ASRC2CLK", SND_SOC_NOPM,
825*4882a593Smuzhiyun MADERA_DOM_GRP_ASRC2, 0,
826*4882a593Smuzhiyun madera_domain_clk_ev,
827*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
828*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC1CLK", SND_SOC_NOPM,
829*4882a593Smuzhiyun MADERA_DOM_GRP_ISRC1, 0,
830*4882a593Smuzhiyun madera_domain_clk_ev,
831*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
832*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC2CLK", SND_SOC_NOPM,
833*4882a593Smuzhiyun MADERA_DOM_GRP_ISRC2, 0,
834*4882a593Smuzhiyun madera_domain_clk_ev,
835*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
836*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC3CLK", SND_SOC_NOPM,
837*4882a593Smuzhiyun MADERA_DOM_GRP_ISRC3, 0,
838*4882a593Smuzhiyun madera_domain_clk_ev,
839*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
840*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC4CLK", SND_SOC_NOPM,
841*4882a593Smuzhiyun MADERA_DOM_GRP_ISRC4, 0,
842*4882a593Smuzhiyun madera_domain_clk_ev,
843*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
844*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OUTCLK", SND_SOC_NOPM,
845*4882a593Smuzhiyun MADERA_DOM_GRP_OUT, 0,
846*4882a593Smuzhiyun madera_domain_clk_ev,
847*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
848*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SPDCLK", SND_SOC_NOPM,
849*4882a593Smuzhiyun MADERA_DOM_GRP_SPD, 0,
850*4882a593Smuzhiyun madera_domain_clk_ev,
851*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
852*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM,
853*4882a593Smuzhiyun MADERA_DOM_GRP_DSP1, 0,
854*4882a593Smuzhiyun madera_domain_clk_ev,
855*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
856*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM,
857*4882a593Smuzhiyun MADERA_DOM_GRP_DSP2, 0,
858*4882a593Smuzhiyun madera_domain_clk_ev,
859*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
860*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP3CLK", SND_SOC_NOPM,
861*4882a593Smuzhiyun MADERA_DOM_GRP_DSP3, 0,
862*4882a593Smuzhiyun madera_domain_clk_ev,
863*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
864*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP4CLK", SND_SOC_NOPM,
865*4882a593Smuzhiyun MADERA_DOM_GRP_DSP4, 0,
866*4882a593Smuzhiyun madera_domain_clk_ev,
867*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
868*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP5CLK", SND_SOC_NOPM,
869*4882a593Smuzhiyun MADERA_DOM_GRP_DSP5, 0,
870*4882a593Smuzhiyun madera_domain_clk_ev,
871*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
872*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP6CLK", SND_SOC_NOPM,
873*4882a593Smuzhiyun MADERA_DOM_GRP_DSP6, 0,
874*4882a593Smuzhiyun madera_domain_clk_ev,
875*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
876*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP7CLK", SND_SOC_NOPM,
877*4882a593Smuzhiyun MADERA_DOM_GRP_DSP7, 0,
878*4882a593Smuzhiyun madera_domain_clk_ev,
879*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
880*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF1TXCLK", SND_SOC_NOPM,
881*4882a593Smuzhiyun MADERA_DOM_GRP_AIF1, 0,
882*4882a593Smuzhiyun madera_domain_clk_ev,
883*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
884*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF2TXCLK", SND_SOC_NOPM,
885*4882a593Smuzhiyun MADERA_DOM_GRP_AIF2, 0,
886*4882a593Smuzhiyun madera_domain_clk_ev,
887*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
888*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF3TXCLK", SND_SOC_NOPM,
889*4882a593Smuzhiyun MADERA_DOM_GRP_AIF3, 0,
890*4882a593Smuzhiyun madera_domain_clk_ev,
891*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
892*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF4TXCLK", SND_SOC_NOPM,
893*4882a593Smuzhiyun MADERA_DOM_GRP_AIF4, 0,
894*4882a593Smuzhiyun madera_domain_clk_ev,
895*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
896*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SLIMBUSCLK", SND_SOC_NOPM,
897*4882a593Smuzhiyun MADERA_DOM_GRP_SLIMBUS, 0,
898*4882a593Smuzhiyun madera_domain_clk_ev,
899*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
900*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("PWMCLK", SND_SOC_NOPM,
901*4882a593Smuzhiyun MADERA_DOM_GRP_PWM, 0,
902*4882a593Smuzhiyun madera_domain_clk_ev,
903*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("RXANC NG External Clock", SND_SOC_NOPM,
906*4882a593Smuzhiyun MADERA_EXT_NG_SEL_SET_SHIFT, 0, madera_anc_ev,
907*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("RXANC NG Clock", SND_SOC_NOPM,
910*4882a593Smuzhiyun MADERA_CLK_NG_ENA_SET_SHIFT, 0, madera_anc_ev,
911*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("TONE"),
914*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("NOISE"),
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ALN"),
917*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ALP"),
918*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BN"),
919*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BP"),
920*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1RN"),
921*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1RP"),
922*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2ALN"),
923*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2ALP"),
924*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2ARN"),
925*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2ARP"),
926*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2BLN"),
927*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2BLP"),
928*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2BRN"),
929*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2BRP"),
930*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN3LN"),
931*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN3LP"),
932*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN3RN"),
933*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN3RP"),
934*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICCLK4"),
935*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICDAT4"),
936*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICCLK5"),
937*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICDAT5"),
938*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICCLK6"),
939*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("DMICDAT6"),
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[0]),
942*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[2]),
943*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[3]),
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
946*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
949*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN3L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[2]),
952*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN3R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[2]),
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
955*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DSP Trigger Out"),
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun SND_SOC_DAPM_PGA("PWM1 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM1_ENA_SHIFT,
960*4882a593Smuzhiyun 0, NULL, 0),
961*4882a593Smuzhiyun SND_SOC_DAPM_PGA("PWM2 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM2_ENA_SHIFT,
962*4882a593Smuzhiyun 0, NULL, 0),
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun SND_SOC_DAPM_PGA("RXANCL NG External", SND_SOC_NOPM, 0, 0, NULL, 0),
965*4882a593Smuzhiyun SND_SOC_DAPM_PGA("RXANCR NG External", SND_SOC_NOPM, 0, 0, NULL, 0),
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun SND_SOC_DAPM_PGA("RXANCL NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0),
968*4882a593Smuzhiyun SND_SOC_DAPM_PGA("RXANCR NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0),
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCL Left Input", SND_SOC_NOPM, 0, 0,
971*4882a593Smuzhiyun &cs47l85_anc_input_mux[0]),
972*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCL Right Input", SND_SOC_NOPM, 0, 0,
973*4882a593Smuzhiyun &cs47l85_anc_input_mux[0]),
974*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCL Channel", SND_SOC_NOPM, 0, 0,
975*4882a593Smuzhiyun &cs47l85_anc_input_mux[1]),
976*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCL NG Mux", SND_SOC_NOPM, 0, 0, &cs47l85_anc_ng_mux),
977*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCR Left Input", SND_SOC_NOPM, 0, 0,
978*4882a593Smuzhiyun &cs47l85_anc_input_mux[2]),
979*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCR Right Input", SND_SOC_NOPM, 0, 0,
980*4882a593Smuzhiyun &cs47l85_anc_input_mux[2]),
981*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCR Channel", SND_SOC_NOPM, 0, 0,
982*4882a593Smuzhiyun &cs47l85_anc_input_mux[3]),
983*4882a593Smuzhiyun SND_SOC_DAPM_MUX("RXANCR NG Mux", SND_SOC_NOPM, 0, 0, &cs47l85_anc_ng_mux),
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("RXANCL", SND_SOC_NOPM, MADERA_CLK_L_ENA_SET_SHIFT,
986*4882a593Smuzhiyun 0, NULL, 0, madera_anc_ev,
987*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
988*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("RXANCR", SND_SOC_NOPM, MADERA_CLK_R_ENA_SET_SHIFT,
989*4882a593Smuzhiyun 0, NULL, 0, madera_anc_ev,
990*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT1L ANC Source", SND_SOC_NOPM, 0, 0,
993*4882a593Smuzhiyun &cs47l85_output_anc_src[0]),
994*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT1R ANC Source", SND_SOC_NOPM, 0, 0,
995*4882a593Smuzhiyun &cs47l85_output_anc_src[1]),
996*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT2L ANC Source", SND_SOC_NOPM, 0, 0,
997*4882a593Smuzhiyun &cs47l85_output_anc_src[2]),
998*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT2R ANC Source", SND_SOC_NOPM, 0, 0,
999*4882a593Smuzhiyun &cs47l85_output_anc_src[3]),
1000*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT3L ANC Source", SND_SOC_NOPM, 0, 0,
1001*4882a593Smuzhiyun &cs47l85_output_anc_src[4]),
1002*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT3R ANC Source", SND_SOC_NOPM, 0, 0,
1003*4882a593Smuzhiyun &cs47l85_output_anc_src[5]),
1004*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPKOUTL ANC Source", SND_SOC_NOPM, 0, 0,
1005*4882a593Smuzhiyun &cs47l85_output_anc_src[6]),
1006*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPKOUTR ANC Source", SND_SOC_NOPM, 0, 0,
1007*4882a593Smuzhiyun &cs47l85_output_anc_src[7]),
1008*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPKDAT1L ANC Source", SND_SOC_NOPM, 0, 0,
1009*4882a593Smuzhiyun &cs47l85_output_anc_src[8]),
1010*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPKDAT1R ANC Source", SND_SOC_NOPM, 0, 0,
1011*4882a593Smuzhiyun &cs47l85_output_anc_src[9]),
1012*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPKDAT2L ANC Source", SND_SOC_NOPM, 0, 0,
1013*4882a593Smuzhiyun &cs47l85_output_anc_src[10]),
1014*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPKDAT2R ANC Source", SND_SOC_NOPM, 0, 0,
1015*4882a593Smuzhiyun &cs47l85_output_anc_src[11]),
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
1018*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX1_ENA_SHIFT, 0),
1019*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
1020*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX2_ENA_SHIFT, 0),
1021*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
1022*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX3_ENA_SHIFT, 0),
1023*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
1024*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX4_ENA_SHIFT, 0),
1025*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
1026*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX5_ENA_SHIFT, 0),
1027*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
1028*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX6_ENA_SHIFT, 0),
1029*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 6,
1030*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX7_ENA_SHIFT, 0),
1031*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 7,
1032*4882a593Smuzhiyun MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX8_ENA_SHIFT, 0),
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
1035*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX1_ENA_SHIFT, 0),
1036*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
1037*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX2_ENA_SHIFT, 0),
1038*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
1039*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX3_ENA_SHIFT, 0),
1040*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
1041*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX4_ENA_SHIFT, 0),
1042*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 4,
1043*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX5_ENA_SHIFT, 0),
1044*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 5,
1045*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX6_ENA_SHIFT, 0),
1046*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX7", NULL, 6,
1047*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX7_ENA_SHIFT, 0),
1048*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX8", NULL, 7,
1049*4882a593Smuzhiyun MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX8_ENA_SHIFT, 0),
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
1052*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1053*4882a593Smuzhiyun MADERA_SLIMTX1_ENA_SHIFT, 0),
1054*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
1055*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1056*4882a593Smuzhiyun MADERA_SLIMTX2_ENA_SHIFT, 0),
1057*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
1058*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1059*4882a593Smuzhiyun MADERA_SLIMTX3_ENA_SHIFT, 0),
1060*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
1061*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1062*4882a593Smuzhiyun MADERA_SLIMTX4_ENA_SHIFT, 0),
1063*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
1064*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1065*4882a593Smuzhiyun MADERA_SLIMTX5_ENA_SHIFT, 0),
1066*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
1067*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1068*4882a593Smuzhiyun MADERA_SLIMTX6_ENA_SHIFT, 0),
1069*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 6,
1070*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1071*4882a593Smuzhiyun MADERA_SLIMTX7_ENA_SHIFT, 0),
1072*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 7,
1073*4882a593Smuzhiyun MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
1074*4882a593Smuzhiyun MADERA_SLIMTX8_ENA_SHIFT, 0),
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
1077*4882a593Smuzhiyun MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX1_ENA_SHIFT, 0),
1078*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
1079*4882a593Smuzhiyun MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX2_ENA_SHIFT, 0),
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF4TX1", NULL, 0,
1082*4882a593Smuzhiyun MADERA_AIF4_TX_ENABLES, MADERA_AIF4TX1_ENA_SHIFT, 0),
1083*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF4TX2", NULL, 1,
1084*4882a593Smuzhiyun MADERA_AIF4_TX_ENABLES, MADERA_AIF4TX2_ENA_SHIFT, 0),
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
1087*4882a593Smuzhiyun MADERA_OUT1L_ENA_SHIFT, 0, NULL, 0, cs47l85_hp_ev,
1088*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1089*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1090*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
1091*4882a593Smuzhiyun MADERA_OUT1R_ENA_SHIFT, 0, NULL, 0, cs47l85_hp_ev,
1092*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1093*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1094*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT2L", MADERA_OUTPUT_ENABLES_1,
1095*4882a593Smuzhiyun MADERA_OUT2L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
1096*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1097*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1098*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT2R", MADERA_OUTPUT_ENABLES_1,
1099*4882a593Smuzhiyun MADERA_OUT2R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
1100*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1101*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1102*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT3L", MADERA_OUTPUT_ENABLES_1,
1103*4882a593Smuzhiyun MADERA_OUT3L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
1104*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1105*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1106*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT3R", MADERA_OUTPUT_ENABLES_1,
1107*4882a593Smuzhiyun MADERA_OUT3R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
1108*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1109*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1110*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
1111*4882a593Smuzhiyun MADERA_OUT4L_ENA_SHIFT, 0, NULL, 0, madera_spk_ev,
1112*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1113*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
1114*4882a593Smuzhiyun MADERA_OUT4R_ENA_SHIFT, 0, NULL, 0, madera_spk_ev,
1115*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1116*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT5L", MADERA_OUTPUT_ENABLES_1,
1117*4882a593Smuzhiyun MADERA_OUT5L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
1118*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1119*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT5R", MADERA_OUTPUT_ENABLES_1,
1120*4882a593Smuzhiyun MADERA_OUT5R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
1121*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1122*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT6L", MADERA_OUTPUT_ENABLES_1,
1123*4882a593Smuzhiyun MADERA_OUT6L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
1124*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1125*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT6R", MADERA_OUTPUT_ENABLES_1,
1126*4882a593Smuzhiyun MADERA_OUT6R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
1127*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPD1TX1", MADERA_SPD1_TX_CONTROL,
1130*4882a593Smuzhiyun MADERA_SPD1_VAL1_SHIFT, 0, NULL, 0),
1131*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPD1TX2", MADERA_SPD1_TX_CONTROL,
1132*4882a593Smuzhiyun MADERA_SPD1_VAL2_SHIFT, 0, NULL, 0),
1133*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("SPD1", MADERA_SPD1_TX_CONTROL,
1134*4882a593Smuzhiyun MADERA_SPD1_ENA_SHIFT, 0, NULL, 0),
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun /*
1137*4882a593Smuzhiyun * Input mux widgets arranged in order of sources in MADERA_MIXER_INPUT_ROUTES
1138*4882a593Smuzhiyun * to take advantage of cache lookup in DAPM
1139*4882a593Smuzhiyun */
1140*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Noise Generator", MADERA_COMFORT_NOISE_GENERATOR,
1141*4882a593Smuzhiyun MADERA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator 1", MADERA_TONE_GENERATOR_1,
1144*4882a593Smuzhiyun MADERA_TONE1_ENA_SHIFT, 0, NULL, 0),
1145*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator 2", MADERA_TONE_GENERATOR_1,
1146*4882a593Smuzhiyun MADERA_TONE2_ENA_SHIFT, 0, NULL, 0),
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("HAPTICS"),
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun SND_SOC_DAPM_MUX("AEC1 Loopback", MADERA_DAC_AEC_CONTROL_1,
1151*4882a593Smuzhiyun MADERA_AEC1_LOOPBACK_ENA_SHIFT, 0,
1152*4882a593Smuzhiyun &cs47l85_aec_loopback_mux[0]),
1153*4882a593Smuzhiyun SND_SOC_DAPM_MUX("AEC2 Loopback", MADERA_DAC_AEC_CONTROL_2,
1154*4882a593Smuzhiyun MADERA_AEC2_LOOPBACK_ENA_SHIFT, 0,
1155*4882a593Smuzhiyun &cs47l85_aec_loopback_mux[1]),
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN1L", MADERA_INPUT_ENABLES, MADERA_IN1L_ENA_SHIFT,
1158*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1159*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1160*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1161*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN1R", MADERA_INPUT_ENABLES, MADERA_IN1R_ENA_SHIFT,
1162*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1163*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1164*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1165*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN2L", MADERA_INPUT_ENABLES, MADERA_IN2L_ENA_SHIFT,
1166*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1167*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1168*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1169*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN2R", MADERA_INPUT_ENABLES, MADERA_IN2R_ENA_SHIFT,
1170*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1171*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1172*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1173*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN3L", MADERA_INPUT_ENABLES, MADERA_IN3L_ENA_SHIFT,
1174*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1175*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1176*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1177*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN3R", MADERA_INPUT_ENABLES, MADERA_IN3R_ENA_SHIFT,
1178*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1179*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1180*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1181*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN4L", MADERA_INPUT_ENABLES, MADERA_IN4L_ENA_SHIFT,
1182*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1183*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1184*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1185*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN4R", MADERA_INPUT_ENABLES, MADERA_IN4R_ENA_SHIFT,
1186*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1187*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1188*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1189*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN5L", MADERA_INPUT_ENABLES, MADERA_IN5L_ENA_SHIFT,
1190*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1191*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1192*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1193*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN5R", MADERA_INPUT_ENABLES, MADERA_IN5R_ENA_SHIFT,
1194*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1195*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1196*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1197*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN6L", MADERA_INPUT_ENABLES, MADERA_IN6L_ENA_SHIFT,
1198*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1199*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1200*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1201*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN6R", MADERA_INPUT_ENABLES, MADERA_IN6R_ENA_SHIFT,
1202*4882a593Smuzhiyun 0, NULL, 0, madera_in_ev,
1203*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
1204*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
1207*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX1_ENA_SHIFT, 0),
1208*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
1209*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX2_ENA_SHIFT, 0),
1210*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
1211*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX3_ENA_SHIFT, 0),
1212*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
1213*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX4_ENA_SHIFT, 0),
1214*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
1215*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX5_ENA_SHIFT, 0),
1216*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
1217*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX6_ENA_SHIFT, 0),
1218*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 6,
1219*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX7_ENA_SHIFT, 0),
1220*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 7,
1221*4882a593Smuzhiyun MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX8_ENA_SHIFT, 0),
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
1224*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX1_ENA_SHIFT, 0),
1225*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
1226*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX2_ENA_SHIFT, 0),
1227*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
1228*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX3_ENA_SHIFT, 0),
1229*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
1230*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX4_ENA_SHIFT, 0),
1231*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 4,
1232*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX5_ENA_SHIFT, 0),
1233*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 5,
1234*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX6_ENA_SHIFT, 0),
1235*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX7", NULL, 6,
1236*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX7_ENA_SHIFT, 0),
1237*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX8", NULL, 7,
1238*4882a593Smuzhiyun MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX8_ENA_SHIFT, 0),
1239*4882a593Smuzhiyun
1240*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
1241*4882a593Smuzhiyun MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX1_ENA_SHIFT, 0),
1242*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
1243*4882a593Smuzhiyun MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX2_ENA_SHIFT, 0),
1244*4882a593Smuzhiyun
1245*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF4RX1", NULL, 0,
1246*4882a593Smuzhiyun MADERA_AIF4_RX_ENABLES, MADERA_AIF4RX1_ENA_SHIFT, 0),
1247*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF4RX2", NULL, 1,
1248*4882a593Smuzhiyun MADERA_AIF4_RX_ENABLES, MADERA_AIF4RX2_ENA_SHIFT, 0),
1249*4882a593Smuzhiyun
1250*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0,
1251*4882a593Smuzhiyun MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1252*4882a593Smuzhiyun MADERA_SLIMRX1_ENA_SHIFT, 0),
1253*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1,
1254*4882a593Smuzhiyun MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1255*4882a593Smuzhiyun MADERA_SLIMRX2_ENA_SHIFT, 0),
1256*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2,
1257*4882a593Smuzhiyun MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1258*4882a593Smuzhiyun MADERA_SLIMRX3_ENA_SHIFT, 0),
1259*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3,
1260*4882a593Smuzhiyun MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1261*4882a593Smuzhiyun MADERA_SLIMRX4_ENA_SHIFT, 0),
1262*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4,
1263*4882a593Smuzhiyun MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1264*4882a593Smuzhiyun MADERA_SLIMRX5_ENA_SHIFT, 0),
1265*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5,
1266*4882a593Smuzhiyun MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1267*4882a593Smuzhiyun MADERA_SLIMRX6_ENA_SHIFT, 0),
1268*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 6,
1269*4882a593Smuzhiyun MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1270*4882a593Smuzhiyun MADERA_SLIMRX7_ENA_SHIFT, 0),
1271*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 7,
1272*4882a593Smuzhiyun MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
1273*4882a593Smuzhiyun MADERA_SLIMRX8_ENA_SHIFT, 0),
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ1", MADERA_EQ1_1, MADERA_EQ1_ENA_SHIFT, 0, NULL, 0),
1276*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ2", MADERA_EQ2_1, MADERA_EQ2_ENA_SHIFT, 0, NULL, 0),
1277*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ3", MADERA_EQ3_1, MADERA_EQ3_ENA_SHIFT, 0, NULL, 0),
1278*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ4", MADERA_EQ4_1, MADERA_EQ4_ENA_SHIFT, 0, NULL, 0),
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC1L", MADERA_DRC1_CTRL1, MADERA_DRC1L_ENA_SHIFT, 0,
1281*4882a593Smuzhiyun NULL, 0),
1282*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC1R", MADERA_DRC1_CTRL1, MADERA_DRC1R_ENA_SHIFT, 0,
1283*4882a593Smuzhiyun NULL, 0),
1284*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC2L", MADERA_DRC2_CTRL1, MADERA_DRC2L_ENA_SHIFT, 0,
1285*4882a593Smuzhiyun NULL, 0),
1286*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC2R", MADERA_DRC2_CTRL1, MADERA_DRC2R_ENA_SHIFT, 0,
1287*4882a593Smuzhiyun NULL, 0),
1288*4882a593Smuzhiyun
1289*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF1", MADERA_HPLPF1_1, MADERA_LHPF1_ENA_SHIFT, 0,
1290*4882a593Smuzhiyun NULL, 0),
1291*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF2", MADERA_HPLPF2_1, MADERA_LHPF2_ENA_SHIFT, 0,
1292*4882a593Smuzhiyun NULL, 0),
1293*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF3", MADERA_HPLPF3_1, MADERA_LHPF3_ENA_SHIFT, 0,
1294*4882a593Smuzhiyun NULL, 0),
1295*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF4", MADERA_HPLPF4_1, MADERA_LHPF4_ENA_SHIFT, 0,
1296*4882a593Smuzhiyun NULL, 0),
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN1L", MADERA_ASRC1_ENABLE, MADERA_ASRC1_IN1L_ENA_SHIFT,
1299*4882a593Smuzhiyun 0, NULL, 0),
1300*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN1R", MADERA_ASRC1_ENABLE, MADERA_ASRC1_IN1R_ENA_SHIFT,
1301*4882a593Smuzhiyun 0, NULL, 0),
1302*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN2L", MADERA_ASRC1_ENABLE, MADERA_ASRC1_IN2L_ENA_SHIFT,
1303*4882a593Smuzhiyun 0, NULL, 0),
1304*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC1IN2R", MADERA_ASRC1_ENABLE, MADERA_ASRC1_IN2R_ENA_SHIFT,
1305*4882a593Smuzhiyun 0, NULL, 0),
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC2IN1L", MADERA_ASRC2_ENABLE, MADERA_ASRC2_IN1L_ENA_SHIFT,
1308*4882a593Smuzhiyun 0, NULL, 0),
1309*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC2IN1R", MADERA_ASRC2_ENABLE, MADERA_ASRC2_IN1R_ENA_SHIFT,
1310*4882a593Smuzhiyun 0, NULL, 0),
1311*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC2IN2L", MADERA_ASRC2_ENABLE, MADERA_ASRC2_IN2L_ENA_SHIFT,
1312*4882a593Smuzhiyun 0, NULL, 0),
1313*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ASRC2IN2R", MADERA_ASRC2_ENABLE, MADERA_ASRC2_IN2R_ENA_SHIFT,
1314*4882a593Smuzhiyun 0, NULL, 0),
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC1", MADERA_ISRC_1_CTRL_3,
1317*4882a593Smuzhiyun MADERA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
1318*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC2", MADERA_ISRC_1_CTRL_3,
1319*4882a593Smuzhiyun MADERA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
1320*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC3", MADERA_ISRC_1_CTRL_3,
1321*4882a593Smuzhiyun MADERA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
1322*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC4", MADERA_ISRC_1_CTRL_3,
1323*4882a593Smuzhiyun MADERA_ISRC1_DEC4_ENA_SHIFT, 0, NULL, 0),
1324*4882a593Smuzhiyun
1325*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT1", MADERA_ISRC_1_CTRL_3,
1326*4882a593Smuzhiyun MADERA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
1327*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT2", MADERA_ISRC_1_CTRL_3,
1328*4882a593Smuzhiyun MADERA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
1329*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT3", MADERA_ISRC_1_CTRL_3,
1330*4882a593Smuzhiyun MADERA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
1331*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT4", MADERA_ISRC_1_CTRL_3,
1332*4882a593Smuzhiyun MADERA_ISRC1_INT4_ENA_SHIFT, 0, NULL, 0),
1333*4882a593Smuzhiyun
1334*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC1", MADERA_ISRC_2_CTRL_3,
1335*4882a593Smuzhiyun MADERA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
1336*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC2", MADERA_ISRC_2_CTRL_3,
1337*4882a593Smuzhiyun MADERA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
1338*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC3", MADERA_ISRC_2_CTRL_3,
1339*4882a593Smuzhiyun MADERA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0),
1340*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC4", MADERA_ISRC_2_CTRL_3,
1341*4882a593Smuzhiyun MADERA_ISRC2_DEC4_ENA_SHIFT, 0, NULL, 0),
1342*4882a593Smuzhiyun
1343*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT1", MADERA_ISRC_2_CTRL_3,
1344*4882a593Smuzhiyun MADERA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
1345*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT2", MADERA_ISRC_2_CTRL_3,
1346*4882a593Smuzhiyun MADERA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
1347*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT3", MADERA_ISRC_2_CTRL_3,
1348*4882a593Smuzhiyun MADERA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0),
1349*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT4", MADERA_ISRC_2_CTRL_3,
1350*4882a593Smuzhiyun MADERA_ISRC2_INT4_ENA_SHIFT, 0, NULL, 0),
1351*4882a593Smuzhiyun
1352*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC3DEC1", MADERA_ISRC_3_CTRL_3,
1353*4882a593Smuzhiyun MADERA_ISRC3_DEC1_ENA_SHIFT, 0, NULL, 0),
1354*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC3DEC2", MADERA_ISRC_3_CTRL_3,
1355*4882a593Smuzhiyun MADERA_ISRC3_DEC2_ENA_SHIFT, 0, NULL, 0),
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC3INT1", MADERA_ISRC_3_CTRL_3,
1358*4882a593Smuzhiyun MADERA_ISRC3_INT1_ENA_SHIFT, 0, NULL, 0),
1359*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC3INT2", MADERA_ISRC_3_CTRL_3,
1360*4882a593Smuzhiyun MADERA_ISRC3_INT2_ENA_SHIFT, 0, NULL, 0),
1361*4882a593Smuzhiyun
1362*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC4DEC1", MADERA_ISRC_4_CTRL_3,
1363*4882a593Smuzhiyun MADERA_ISRC4_DEC1_ENA_SHIFT, 0, NULL, 0),
1364*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC4DEC2", MADERA_ISRC_4_CTRL_3,
1365*4882a593Smuzhiyun MADERA_ISRC4_DEC2_ENA_SHIFT, 0, NULL, 0),
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC4INT1", MADERA_ISRC_4_CTRL_3,
1368*4882a593Smuzhiyun MADERA_ISRC4_INT1_ENA_SHIFT, 0, NULL, 0),
1369*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC4INT2", MADERA_ISRC_4_CTRL_3,
1370*4882a593Smuzhiyun MADERA_ISRC4_INT2_ENA_SHIFT, 0, NULL, 0),
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun WM_ADSP2("DSP1", 0, cs47l85_adsp_power_ev),
1373*4882a593Smuzhiyun WM_ADSP2("DSP2", 1, cs47l85_adsp_power_ev),
1374*4882a593Smuzhiyun WM_ADSP2("DSP3", 2, cs47l85_adsp_power_ev),
1375*4882a593Smuzhiyun WM_ADSP2("DSP4", 3, cs47l85_adsp_power_ev),
1376*4882a593Smuzhiyun WM_ADSP2("DSP5", 4, cs47l85_adsp_power_ev),
1377*4882a593Smuzhiyun WM_ADSP2("DSP6", 5, cs47l85_adsp_power_ev),
1378*4882a593Smuzhiyun WM_ADSP2("DSP7", 6, cs47l85_adsp_power_ev),
1379*4882a593Smuzhiyun
1380*4882a593Smuzhiyun /* End of ordered input mux widgets */
1381*4882a593Smuzhiyun
1382*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ1, "EQ1"),
1383*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ2, "EQ2"),
1384*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ3, "EQ3"),
1385*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ4, "EQ4"),
1386*4882a593Smuzhiyun
1387*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC1L, "DRC1L"),
1388*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC1R, "DRC1R"),
1389*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC2L, "DRC2L"),
1390*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC2R, "DRC2R"),
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0,
1393*4882a593Smuzhiyun &madera_drc_activity_output_mux[0]),
1394*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0,
1395*4882a593Smuzhiyun &madera_drc_activity_output_mux[1]),
1396*4882a593Smuzhiyun
1397*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF1, "LHPF1"),
1398*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF2, "LHPF2"),
1399*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF3, "LHPF3"),
1400*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF4, "LHPF4"),
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(PWM1, "PWM1"),
1403*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(PWM2, "PWM2"),
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
1406*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
1407*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT2L, "HPOUT2L"),
1408*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT2R, "HPOUT2R"),
1409*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT3L, "HPOUT3L"),
1410*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT3R, "HPOUT3R"),
1411*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1412*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1413*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1414*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1415*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1416*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1419*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1420*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1421*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1422*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1423*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1424*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1425*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1428*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1429*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
1430*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
1431*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"),
1432*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"),
1433*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX7, "AIF2TX7"),
1434*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX8, "AIF2TX8"),
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1437*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1438*4882a593Smuzhiyun
1439*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF4TX1, "AIF4TX1"),
1440*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF4TX2, "AIF4TX2"),
1441*4882a593Smuzhiyun
1442*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
1443*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
1444*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
1445*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
1446*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
1447*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
1448*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"),
1449*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"),
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun MADERA_MUX_WIDGETS(SPD1TX1, "SPDIF1TX1"),
1452*4882a593Smuzhiyun MADERA_MUX_WIDGETS(SPD1TX2, "SPDIF1TX2"),
1453*4882a593Smuzhiyun
1454*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN1L, "ASRC1IN1L"),
1455*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN1R, "ASRC1IN1R"),
1456*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN2L, "ASRC1IN2L"),
1457*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC1IN2R, "ASRC1IN2R"),
1458*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC2IN1L, "ASRC2IN1L"),
1459*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC2IN1R, "ASRC2IN1R"),
1460*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC2IN2L, "ASRC2IN2L"),
1461*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ASRC2IN2R, "ASRC2IN2R"),
1462*4882a593Smuzhiyun
1463*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP1, "DSP1"),
1464*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP2, "DSP2"),
1465*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP3, "DSP3"),
1466*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP4, "DSP4"),
1467*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP5, "DSP5"),
1468*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP6, "DSP6"),
1469*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP7, "DSP7"),
1470*4882a593Smuzhiyun
1471*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0,
1472*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[0]),
1473*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP2 Trigger Output", SND_SOC_NOPM, 0, 0,
1474*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[1]),
1475*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP3 Trigger Output", SND_SOC_NOPM, 0, 0,
1476*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[2]),
1477*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP4 Trigger Output", SND_SOC_NOPM, 0, 0,
1478*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[3]),
1479*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP5 Trigger Output", SND_SOC_NOPM, 0, 0,
1480*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[4]),
1481*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP6 Trigger Output", SND_SOC_NOPM, 0, 0,
1482*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[5]),
1483*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP7 Trigger Output", SND_SOC_NOPM, 0, 0,
1484*4882a593Smuzhiyun &madera_dsp_trigger_output_mux[6]),
1485*4882a593Smuzhiyun
1486*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
1487*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
1488*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
1489*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
1490*4882a593Smuzhiyun
1491*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
1492*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
1493*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
1494*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
1495*4882a593Smuzhiyun
1496*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
1497*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
1498*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"),
1499*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"),
1500*4882a593Smuzhiyun
1501*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
1502*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
1503*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"),
1504*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"),
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"),
1507*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"),
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"),
1510*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"),
1511*4882a593Smuzhiyun
1512*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC4DEC1, "ISRC4DEC1"),
1513*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC4DEC2, "ISRC4DEC2"),
1514*4882a593Smuzhiyun
1515*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC4INT1, "ISRC4INT1"),
1516*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC4INT2, "ISRC4INT2"),
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1519*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1520*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1521*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1522*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1523*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1524*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
1525*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
1526*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
1527*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
1528*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
1529*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
1530*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT2L"),
1531*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT2R"),
1532*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPDIF1"),
1533*4882a593Smuzhiyun
1534*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MICSUPP"),
1535*4882a593Smuzhiyun };
1536*4882a593Smuzhiyun
1537*4882a593Smuzhiyun #define MADERA_MIXER_INPUT_ROUTES(name) \
1538*4882a593Smuzhiyun { name, "Noise Generator", "Noise Generator" }, \
1539*4882a593Smuzhiyun { name, "Tone Generator 1", "Tone Generator 1" }, \
1540*4882a593Smuzhiyun { name, "Tone Generator 2", "Tone Generator 2" }, \
1541*4882a593Smuzhiyun { name, "Haptics", "HAPTICS" }, \
1542*4882a593Smuzhiyun { name, "AEC1", "AEC1 Loopback" }, \
1543*4882a593Smuzhiyun { name, "AEC2", "AEC2 Loopback" }, \
1544*4882a593Smuzhiyun { name, "IN1L", "IN1L" }, \
1545*4882a593Smuzhiyun { name, "IN1R", "IN1R" }, \
1546*4882a593Smuzhiyun { name, "IN2L", "IN2L" }, \
1547*4882a593Smuzhiyun { name, "IN2R", "IN2R" }, \
1548*4882a593Smuzhiyun { name, "IN3L", "IN3L" }, \
1549*4882a593Smuzhiyun { name, "IN3R", "IN3R" }, \
1550*4882a593Smuzhiyun { name, "IN4L", "IN4L" }, \
1551*4882a593Smuzhiyun { name, "IN4R", "IN4R" }, \
1552*4882a593Smuzhiyun { name, "IN5L", "IN5L" }, \
1553*4882a593Smuzhiyun { name, "IN5R", "IN5R" }, \
1554*4882a593Smuzhiyun { name, "IN6L", "IN6L" }, \
1555*4882a593Smuzhiyun { name, "IN6R", "IN6R" }, \
1556*4882a593Smuzhiyun { name, "AIF1RX1", "AIF1RX1" }, \
1557*4882a593Smuzhiyun { name, "AIF1RX2", "AIF1RX2" }, \
1558*4882a593Smuzhiyun { name, "AIF1RX3", "AIF1RX3" }, \
1559*4882a593Smuzhiyun { name, "AIF1RX4", "AIF1RX4" }, \
1560*4882a593Smuzhiyun { name, "AIF1RX5", "AIF1RX5" }, \
1561*4882a593Smuzhiyun { name, "AIF1RX6", "AIF1RX6" }, \
1562*4882a593Smuzhiyun { name, "AIF1RX7", "AIF1RX7" }, \
1563*4882a593Smuzhiyun { name, "AIF1RX8", "AIF1RX8" }, \
1564*4882a593Smuzhiyun { name, "AIF2RX1", "AIF2RX1" }, \
1565*4882a593Smuzhiyun { name, "AIF2RX2", "AIF2RX2" }, \
1566*4882a593Smuzhiyun { name, "AIF2RX3", "AIF2RX3" }, \
1567*4882a593Smuzhiyun { name, "AIF2RX4", "AIF2RX4" }, \
1568*4882a593Smuzhiyun { name, "AIF2RX5", "AIF2RX5" }, \
1569*4882a593Smuzhiyun { name, "AIF2RX6", "AIF2RX6" }, \
1570*4882a593Smuzhiyun { name, "AIF2RX7", "AIF2RX7" }, \
1571*4882a593Smuzhiyun { name, "AIF2RX8", "AIF2RX8" }, \
1572*4882a593Smuzhiyun { name, "AIF3RX1", "AIF3RX1" }, \
1573*4882a593Smuzhiyun { name, "AIF3RX2", "AIF3RX2" }, \
1574*4882a593Smuzhiyun { name, "AIF4RX1", "AIF4RX1" }, \
1575*4882a593Smuzhiyun { name, "AIF4RX2", "AIF4RX2" }, \
1576*4882a593Smuzhiyun { name, "SLIMRX1", "SLIMRX1" }, \
1577*4882a593Smuzhiyun { name, "SLIMRX2", "SLIMRX2" }, \
1578*4882a593Smuzhiyun { name, "SLIMRX3", "SLIMRX3" }, \
1579*4882a593Smuzhiyun { name, "SLIMRX4", "SLIMRX4" }, \
1580*4882a593Smuzhiyun { name, "SLIMRX5", "SLIMRX5" }, \
1581*4882a593Smuzhiyun { name, "SLIMRX6", "SLIMRX6" }, \
1582*4882a593Smuzhiyun { name, "SLIMRX7", "SLIMRX7" }, \
1583*4882a593Smuzhiyun { name, "SLIMRX8", "SLIMRX8" }, \
1584*4882a593Smuzhiyun { name, "EQ1", "EQ1" }, \
1585*4882a593Smuzhiyun { name, "EQ2", "EQ2" }, \
1586*4882a593Smuzhiyun { name, "EQ3", "EQ3" }, \
1587*4882a593Smuzhiyun { name, "EQ4", "EQ4" }, \
1588*4882a593Smuzhiyun { name, "DRC1L", "DRC1L" }, \
1589*4882a593Smuzhiyun { name, "DRC1R", "DRC1R" }, \
1590*4882a593Smuzhiyun { name, "DRC2L", "DRC2L" }, \
1591*4882a593Smuzhiyun { name, "DRC2R", "DRC2R" }, \
1592*4882a593Smuzhiyun { name, "LHPF1", "LHPF1" }, \
1593*4882a593Smuzhiyun { name, "LHPF2", "LHPF2" }, \
1594*4882a593Smuzhiyun { name, "LHPF3", "LHPF3" }, \
1595*4882a593Smuzhiyun { name, "LHPF4", "LHPF4" }, \
1596*4882a593Smuzhiyun { name, "ASRC1IN1L", "ASRC1IN1L" }, \
1597*4882a593Smuzhiyun { name, "ASRC1IN1R", "ASRC1IN1R" }, \
1598*4882a593Smuzhiyun { name, "ASRC1IN2L", "ASRC1IN2L" }, \
1599*4882a593Smuzhiyun { name, "ASRC1IN2R", "ASRC1IN2R" }, \
1600*4882a593Smuzhiyun { name, "ASRC2IN1L", "ASRC2IN1L" }, \
1601*4882a593Smuzhiyun { name, "ASRC2IN1R", "ASRC2IN1R" }, \
1602*4882a593Smuzhiyun { name, "ASRC2IN2L", "ASRC2IN2L" }, \
1603*4882a593Smuzhiyun { name, "ASRC2IN2R", "ASRC2IN2R" }, \
1604*4882a593Smuzhiyun { name, "ISRC1DEC1", "ISRC1DEC1" }, \
1605*4882a593Smuzhiyun { name, "ISRC1DEC2", "ISRC1DEC2" }, \
1606*4882a593Smuzhiyun { name, "ISRC1DEC3", "ISRC1DEC3" }, \
1607*4882a593Smuzhiyun { name, "ISRC1DEC4", "ISRC1DEC4" }, \
1608*4882a593Smuzhiyun { name, "ISRC1INT1", "ISRC1INT1" }, \
1609*4882a593Smuzhiyun { name, "ISRC1INT2", "ISRC1INT2" }, \
1610*4882a593Smuzhiyun { name, "ISRC1INT3", "ISRC1INT3" }, \
1611*4882a593Smuzhiyun { name, "ISRC1INT4", "ISRC1INT4" }, \
1612*4882a593Smuzhiyun { name, "ISRC2DEC1", "ISRC2DEC1" }, \
1613*4882a593Smuzhiyun { name, "ISRC2DEC2", "ISRC2DEC2" }, \
1614*4882a593Smuzhiyun { name, "ISRC2DEC3", "ISRC2DEC3" }, \
1615*4882a593Smuzhiyun { name, "ISRC2DEC4", "ISRC2DEC4" }, \
1616*4882a593Smuzhiyun { name, "ISRC2INT1", "ISRC2INT1" }, \
1617*4882a593Smuzhiyun { name, "ISRC2INT2", "ISRC2INT2" }, \
1618*4882a593Smuzhiyun { name, "ISRC2INT3", "ISRC2INT3" }, \
1619*4882a593Smuzhiyun { name, "ISRC2INT4", "ISRC2INT4" }, \
1620*4882a593Smuzhiyun { name, "ISRC3DEC1", "ISRC3DEC1" }, \
1621*4882a593Smuzhiyun { name, "ISRC3DEC2", "ISRC3DEC2" }, \
1622*4882a593Smuzhiyun { name, "ISRC3INT1", "ISRC3INT1" }, \
1623*4882a593Smuzhiyun { name, "ISRC3INT2", "ISRC3INT2" }, \
1624*4882a593Smuzhiyun { name, "ISRC4DEC1", "ISRC4DEC1" }, \
1625*4882a593Smuzhiyun { name, "ISRC4DEC2", "ISRC4DEC2" }, \
1626*4882a593Smuzhiyun { name, "ISRC4INT1", "ISRC4INT1" }, \
1627*4882a593Smuzhiyun { name, "ISRC4INT2", "ISRC4INT2" }, \
1628*4882a593Smuzhiyun { name, "DSP1.1", "DSP1" }, \
1629*4882a593Smuzhiyun { name, "DSP1.2", "DSP1" }, \
1630*4882a593Smuzhiyun { name, "DSP1.3", "DSP1" }, \
1631*4882a593Smuzhiyun { name, "DSP1.4", "DSP1" }, \
1632*4882a593Smuzhiyun { name, "DSP1.5", "DSP1" }, \
1633*4882a593Smuzhiyun { name, "DSP1.6", "DSP1" }, \
1634*4882a593Smuzhiyun { name, "DSP2.1", "DSP2" }, \
1635*4882a593Smuzhiyun { name, "DSP2.2", "DSP2" }, \
1636*4882a593Smuzhiyun { name, "DSP2.3", "DSP2" }, \
1637*4882a593Smuzhiyun { name, "DSP2.4", "DSP2" }, \
1638*4882a593Smuzhiyun { name, "DSP2.5", "DSP2" }, \
1639*4882a593Smuzhiyun { name, "DSP2.6", "DSP2" }, \
1640*4882a593Smuzhiyun { name, "DSP3.1", "DSP3" }, \
1641*4882a593Smuzhiyun { name, "DSP3.2", "DSP3" }, \
1642*4882a593Smuzhiyun { name, "DSP3.3", "DSP3" }, \
1643*4882a593Smuzhiyun { name, "DSP3.4", "DSP3" }, \
1644*4882a593Smuzhiyun { name, "DSP3.5", "DSP3" }, \
1645*4882a593Smuzhiyun { name, "DSP3.6", "DSP3" }, \
1646*4882a593Smuzhiyun { name, "DSP4.1", "DSP4" }, \
1647*4882a593Smuzhiyun { name, "DSP4.2", "DSP4" }, \
1648*4882a593Smuzhiyun { name, "DSP4.3", "DSP4" }, \
1649*4882a593Smuzhiyun { name, "DSP4.4", "DSP4" }, \
1650*4882a593Smuzhiyun { name, "DSP4.5", "DSP4" }, \
1651*4882a593Smuzhiyun { name, "DSP4.6", "DSP4" }, \
1652*4882a593Smuzhiyun { name, "DSP5.1", "DSP5" }, \
1653*4882a593Smuzhiyun { name, "DSP5.2", "DSP5" }, \
1654*4882a593Smuzhiyun { name, "DSP5.3", "DSP5" }, \
1655*4882a593Smuzhiyun { name, "DSP5.4", "DSP5" }, \
1656*4882a593Smuzhiyun { name, "DSP5.5", "DSP5" }, \
1657*4882a593Smuzhiyun { name, "DSP5.6", "DSP5" }, \
1658*4882a593Smuzhiyun { name, "DSP6.1", "DSP6" }, \
1659*4882a593Smuzhiyun { name, "DSP6.2", "DSP6" }, \
1660*4882a593Smuzhiyun { name, "DSP6.3", "DSP6" }, \
1661*4882a593Smuzhiyun { name, "DSP6.4", "DSP6" }, \
1662*4882a593Smuzhiyun { name, "DSP6.5", "DSP6" }, \
1663*4882a593Smuzhiyun { name, "DSP6.6", "DSP6" }, \
1664*4882a593Smuzhiyun { name, "DSP7.1", "DSP7" }, \
1665*4882a593Smuzhiyun { name, "DSP7.2", "DSP7" }, \
1666*4882a593Smuzhiyun { name, "DSP7.3", "DSP7" }, \
1667*4882a593Smuzhiyun { name, "DSP7.4", "DSP7" }, \
1668*4882a593Smuzhiyun { name, "DSP7.5", "DSP7" }, \
1669*4882a593Smuzhiyun { name, "DSP7.6", "DSP7" }
1670*4882a593Smuzhiyun
1671*4882a593Smuzhiyun static const struct snd_soc_dapm_route cs47l85_dapm_routes[] = {
1672*4882a593Smuzhiyun /* Internal clock domains */
1673*4882a593Smuzhiyun { "EQ1", NULL, "FXCLK" },
1674*4882a593Smuzhiyun { "EQ2", NULL, "FXCLK" },
1675*4882a593Smuzhiyun { "EQ3", NULL, "FXCLK" },
1676*4882a593Smuzhiyun { "EQ4", NULL, "FXCLK" },
1677*4882a593Smuzhiyun { "DRC1L", NULL, "FXCLK" },
1678*4882a593Smuzhiyun { "DRC1R", NULL, "FXCLK" },
1679*4882a593Smuzhiyun { "DRC2L", NULL, "FXCLK" },
1680*4882a593Smuzhiyun { "DRC2R", NULL, "FXCLK" },
1681*4882a593Smuzhiyun { "LHPF1", NULL, "FXCLK" },
1682*4882a593Smuzhiyun { "LHPF2", NULL, "FXCLK" },
1683*4882a593Smuzhiyun { "LHPF3", NULL, "FXCLK" },
1684*4882a593Smuzhiyun { "LHPF4", NULL, "FXCLK" },
1685*4882a593Smuzhiyun { "PWM1 Mixer", NULL, "PWMCLK" },
1686*4882a593Smuzhiyun { "PWM2 Mixer", NULL, "PWMCLK" },
1687*4882a593Smuzhiyun { "OUT1L", NULL, "OUTCLK" },
1688*4882a593Smuzhiyun { "OUT1R", NULL, "OUTCLK" },
1689*4882a593Smuzhiyun { "OUT2L", NULL, "OUTCLK" },
1690*4882a593Smuzhiyun { "OUT2R", NULL, "OUTCLK" },
1691*4882a593Smuzhiyun { "OUT3L", NULL, "OUTCLK" },
1692*4882a593Smuzhiyun { "OUT3R", NULL, "OUTCLK" },
1693*4882a593Smuzhiyun { "OUT4L", NULL, "OUTCLK" },
1694*4882a593Smuzhiyun { "OUT4R", NULL, "OUTCLK" },
1695*4882a593Smuzhiyun { "OUT5L", NULL, "OUTCLK" },
1696*4882a593Smuzhiyun { "OUT5R", NULL, "OUTCLK" },
1697*4882a593Smuzhiyun { "OUT6L", NULL, "OUTCLK" },
1698*4882a593Smuzhiyun { "OUT6R", NULL, "OUTCLK" },
1699*4882a593Smuzhiyun { "AIF1TX1", NULL, "AIF1TXCLK" },
1700*4882a593Smuzhiyun { "AIF1TX2", NULL, "AIF1TXCLK" },
1701*4882a593Smuzhiyun { "AIF1TX3", NULL, "AIF1TXCLK" },
1702*4882a593Smuzhiyun { "AIF1TX4", NULL, "AIF1TXCLK" },
1703*4882a593Smuzhiyun { "AIF1TX5", NULL, "AIF1TXCLK" },
1704*4882a593Smuzhiyun { "AIF1TX6", NULL, "AIF1TXCLK" },
1705*4882a593Smuzhiyun { "AIF1TX7", NULL, "AIF1TXCLK" },
1706*4882a593Smuzhiyun { "AIF1TX8", NULL, "AIF1TXCLK" },
1707*4882a593Smuzhiyun { "AIF2TX1", NULL, "AIF2TXCLK" },
1708*4882a593Smuzhiyun { "AIF2TX2", NULL, "AIF2TXCLK" },
1709*4882a593Smuzhiyun { "AIF2TX3", NULL, "AIF2TXCLK" },
1710*4882a593Smuzhiyun { "AIF2TX4", NULL, "AIF2TXCLK" },
1711*4882a593Smuzhiyun { "AIF2TX5", NULL, "AIF2TXCLK" },
1712*4882a593Smuzhiyun { "AIF2TX6", NULL, "AIF2TXCLK" },
1713*4882a593Smuzhiyun { "AIF2TX7", NULL, "AIF2TXCLK" },
1714*4882a593Smuzhiyun { "AIF2TX8", NULL, "AIF2TXCLK" },
1715*4882a593Smuzhiyun { "AIF3TX1", NULL, "AIF3TXCLK" },
1716*4882a593Smuzhiyun { "AIF3TX2", NULL, "AIF3TXCLK" },
1717*4882a593Smuzhiyun { "AIF4TX1", NULL, "AIF4TXCLK" },
1718*4882a593Smuzhiyun { "AIF4TX2", NULL, "AIF4TXCLK" },
1719*4882a593Smuzhiyun { "SLIMTX1", NULL, "SLIMBUSCLK" },
1720*4882a593Smuzhiyun { "SLIMTX2", NULL, "SLIMBUSCLK" },
1721*4882a593Smuzhiyun { "SLIMTX3", NULL, "SLIMBUSCLK" },
1722*4882a593Smuzhiyun { "SLIMTX4", NULL, "SLIMBUSCLK" },
1723*4882a593Smuzhiyun { "SLIMTX5", NULL, "SLIMBUSCLK" },
1724*4882a593Smuzhiyun { "SLIMTX6", NULL, "SLIMBUSCLK" },
1725*4882a593Smuzhiyun { "SLIMTX7", NULL, "SLIMBUSCLK" },
1726*4882a593Smuzhiyun { "SLIMTX8", NULL, "SLIMBUSCLK" },
1727*4882a593Smuzhiyun { "SPD1TX1", NULL, "SPDCLK" },
1728*4882a593Smuzhiyun { "SPD1TX2", NULL, "SPDCLK" },
1729*4882a593Smuzhiyun { "DSP1", NULL, "DSP1CLK" },
1730*4882a593Smuzhiyun { "DSP2", NULL, "DSP2CLK" },
1731*4882a593Smuzhiyun { "DSP3", NULL, "DSP3CLK" },
1732*4882a593Smuzhiyun { "DSP4", NULL, "DSP4CLK" },
1733*4882a593Smuzhiyun { "DSP5", NULL, "DSP5CLK" },
1734*4882a593Smuzhiyun { "DSP6", NULL, "DSP6CLK" },
1735*4882a593Smuzhiyun { "DSP7", NULL, "DSP7CLK" },
1736*4882a593Smuzhiyun { "ISRC1DEC1", NULL, "ISRC1CLK" },
1737*4882a593Smuzhiyun { "ISRC1DEC2", NULL, "ISRC1CLK" },
1738*4882a593Smuzhiyun { "ISRC1DEC3", NULL, "ISRC1CLK" },
1739*4882a593Smuzhiyun { "ISRC1DEC4", NULL, "ISRC1CLK" },
1740*4882a593Smuzhiyun { "ISRC1INT1", NULL, "ISRC1CLK" },
1741*4882a593Smuzhiyun { "ISRC1INT2", NULL, "ISRC1CLK" },
1742*4882a593Smuzhiyun { "ISRC1INT3", NULL, "ISRC1CLK" },
1743*4882a593Smuzhiyun { "ISRC1INT4", NULL, "ISRC1CLK" },
1744*4882a593Smuzhiyun { "ISRC2DEC1", NULL, "ISRC2CLK" },
1745*4882a593Smuzhiyun { "ISRC2DEC2", NULL, "ISRC2CLK" },
1746*4882a593Smuzhiyun { "ISRC2DEC3", NULL, "ISRC2CLK" },
1747*4882a593Smuzhiyun { "ISRC2DEC4", NULL, "ISRC2CLK" },
1748*4882a593Smuzhiyun { "ISRC2INT1", NULL, "ISRC2CLK" },
1749*4882a593Smuzhiyun { "ISRC2INT2", NULL, "ISRC2CLK" },
1750*4882a593Smuzhiyun { "ISRC2INT3", NULL, "ISRC2CLK" },
1751*4882a593Smuzhiyun { "ISRC2INT4", NULL, "ISRC2CLK" },
1752*4882a593Smuzhiyun { "ISRC3DEC1", NULL, "ISRC3CLK" },
1753*4882a593Smuzhiyun { "ISRC3DEC2", NULL, "ISRC3CLK" },
1754*4882a593Smuzhiyun { "ISRC3INT1", NULL, "ISRC3CLK" },
1755*4882a593Smuzhiyun { "ISRC3INT2", NULL, "ISRC3CLK" },
1756*4882a593Smuzhiyun { "ISRC4DEC1", NULL, "ISRC4CLK" },
1757*4882a593Smuzhiyun { "ISRC4DEC2", NULL, "ISRC4CLK" },
1758*4882a593Smuzhiyun { "ISRC4INT1", NULL, "ISRC4CLK" },
1759*4882a593Smuzhiyun { "ISRC4INT2", NULL, "ISRC4CLK" },
1760*4882a593Smuzhiyun { "ASRC1IN1L", NULL, "ASRC1CLK" },
1761*4882a593Smuzhiyun { "ASRC1IN1R", NULL, "ASRC1CLK" },
1762*4882a593Smuzhiyun { "ASRC1IN2L", NULL, "ASRC1CLK" },
1763*4882a593Smuzhiyun { "ASRC1IN2R", NULL, "ASRC1CLK" },
1764*4882a593Smuzhiyun { "ASRC2IN1L", NULL, "ASRC2CLK" },
1765*4882a593Smuzhiyun { "ASRC2IN1R", NULL, "ASRC2CLK" },
1766*4882a593Smuzhiyun { "ASRC2IN2L", NULL, "ASRC2CLK" },
1767*4882a593Smuzhiyun { "ASRC2IN2R", NULL, "ASRC2CLK" },
1768*4882a593Smuzhiyun
1769*4882a593Smuzhiyun { "AIF2 Capture", NULL, "DBVDD2" },
1770*4882a593Smuzhiyun { "AIF2 Playback", NULL, "DBVDD2" },
1771*4882a593Smuzhiyun
1772*4882a593Smuzhiyun { "AIF3 Capture", NULL, "DBVDD3" },
1773*4882a593Smuzhiyun { "AIF3 Playback", NULL, "DBVDD3" },
1774*4882a593Smuzhiyun
1775*4882a593Smuzhiyun { "AIF4 Capture", NULL, "DBVDD3" },
1776*4882a593Smuzhiyun { "AIF4 Playback", NULL, "DBVDD3" },
1777*4882a593Smuzhiyun
1778*4882a593Smuzhiyun { "OUT1L", NULL, "CPVDD1" },
1779*4882a593Smuzhiyun { "OUT1L", NULL, "CPVDD2" },
1780*4882a593Smuzhiyun { "OUT1R", NULL, "CPVDD1" },
1781*4882a593Smuzhiyun { "OUT1R", NULL, "CPVDD2" },
1782*4882a593Smuzhiyun { "OUT2L", NULL, "CPVDD1" },
1783*4882a593Smuzhiyun { "OUT2L", NULL, "CPVDD2" },
1784*4882a593Smuzhiyun { "OUT2R", NULL, "CPVDD1" },
1785*4882a593Smuzhiyun { "OUT2R", NULL, "CPVDD2" },
1786*4882a593Smuzhiyun { "OUT3L", NULL, "CPVDD1" },
1787*4882a593Smuzhiyun { "OUT3L", NULL, "CPVDD2" },
1788*4882a593Smuzhiyun { "OUT3R", NULL, "CPVDD1" },
1789*4882a593Smuzhiyun { "OUT3R", NULL, "CPVDD2" },
1790*4882a593Smuzhiyun
1791*4882a593Smuzhiyun { "OUT4L", NULL, "SPKVDDL" },
1792*4882a593Smuzhiyun { "OUT4R", NULL, "SPKVDDR" },
1793*4882a593Smuzhiyun
1794*4882a593Smuzhiyun { "OUT1L", NULL, "SYSCLK" },
1795*4882a593Smuzhiyun { "OUT1R", NULL, "SYSCLK" },
1796*4882a593Smuzhiyun { "OUT2L", NULL, "SYSCLK" },
1797*4882a593Smuzhiyun { "OUT2R", NULL, "SYSCLK" },
1798*4882a593Smuzhiyun { "OUT3L", NULL, "SYSCLK" },
1799*4882a593Smuzhiyun { "OUT3R", NULL, "SYSCLK" },
1800*4882a593Smuzhiyun { "OUT4L", NULL, "SYSCLK" },
1801*4882a593Smuzhiyun { "OUT4R", NULL, "SYSCLK" },
1802*4882a593Smuzhiyun { "OUT5L", NULL, "SYSCLK" },
1803*4882a593Smuzhiyun { "OUT5R", NULL, "SYSCLK" },
1804*4882a593Smuzhiyun { "OUT6L", NULL, "SYSCLK" },
1805*4882a593Smuzhiyun { "OUT6R", NULL, "SYSCLK" },
1806*4882a593Smuzhiyun
1807*4882a593Smuzhiyun { "SPD1", NULL, "SYSCLK" },
1808*4882a593Smuzhiyun { "SPD1", NULL, "SPD1TX1" },
1809*4882a593Smuzhiyun { "SPD1", NULL, "SPD1TX2" },
1810*4882a593Smuzhiyun
1811*4882a593Smuzhiyun { "IN1L", NULL, "SYSCLK" },
1812*4882a593Smuzhiyun { "IN1R", NULL, "SYSCLK" },
1813*4882a593Smuzhiyun { "IN2L", NULL, "SYSCLK" },
1814*4882a593Smuzhiyun { "IN2R", NULL, "SYSCLK" },
1815*4882a593Smuzhiyun { "IN3L", NULL, "SYSCLK" },
1816*4882a593Smuzhiyun { "IN3R", NULL, "SYSCLK" },
1817*4882a593Smuzhiyun { "IN4L", NULL, "SYSCLK" },
1818*4882a593Smuzhiyun { "IN4R", NULL, "SYSCLK" },
1819*4882a593Smuzhiyun { "IN5L", NULL, "SYSCLK" },
1820*4882a593Smuzhiyun { "IN5R", NULL, "SYSCLK" },
1821*4882a593Smuzhiyun { "IN6L", NULL, "SYSCLK" },
1822*4882a593Smuzhiyun { "IN6R", NULL, "SYSCLK" },
1823*4882a593Smuzhiyun
1824*4882a593Smuzhiyun { "IN4L", NULL, "DBVDD4" },
1825*4882a593Smuzhiyun { "IN4R", NULL, "DBVDD4" },
1826*4882a593Smuzhiyun { "IN5L", NULL, "DBVDD4" },
1827*4882a593Smuzhiyun { "IN5R", NULL, "DBVDD4" },
1828*4882a593Smuzhiyun { "IN6L", NULL, "DBVDD4" },
1829*4882a593Smuzhiyun { "IN6R", NULL, "DBVDD4" },
1830*4882a593Smuzhiyun
1831*4882a593Smuzhiyun { "ASRC1IN1L", NULL, "SYSCLK" },
1832*4882a593Smuzhiyun { "ASRC1IN1R", NULL, "SYSCLK" },
1833*4882a593Smuzhiyun { "ASRC1IN2L", NULL, "SYSCLK" },
1834*4882a593Smuzhiyun { "ASRC1IN2R", NULL, "SYSCLK" },
1835*4882a593Smuzhiyun { "ASRC2IN1L", NULL, "SYSCLK" },
1836*4882a593Smuzhiyun { "ASRC2IN1R", NULL, "SYSCLK" },
1837*4882a593Smuzhiyun { "ASRC2IN2L", NULL, "SYSCLK" },
1838*4882a593Smuzhiyun { "ASRC2IN2R", NULL, "SYSCLK" },
1839*4882a593Smuzhiyun
1840*4882a593Smuzhiyun { "ASRC1IN1L", NULL, "ASYNCCLK" },
1841*4882a593Smuzhiyun { "ASRC1IN1R", NULL, "ASYNCCLK" },
1842*4882a593Smuzhiyun { "ASRC1IN2L", NULL, "ASYNCCLK" },
1843*4882a593Smuzhiyun { "ASRC1IN2R", NULL, "ASYNCCLK" },
1844*4882a593Smuzhiyun { "ASRC2IN1L", NULL, "ASYNCCLK" },
1845*4882a593Smuzhiyun { "ASRC2IN1R", NULL, "ASYNCCLK" },
1846*4882a593Smuzhiyun { "ASRC2IN2L", NULL, "ASYNCCLK" },
1847*4882a593Smuzhiyun { "ASRC2IN2R", NULL, "ASYNCCLK" },
1848*4882a593Smuzhiyun
1849*4882a593Smuzhiyun { "MICBIAS1", NULL, "MICVDD" },
1850*4882a593Smuzhiyun { "MICBIAS2", NULL, "MICVDD" },
1851*4882a593Smuzhiyun { "MICBIAS3", NULL, "MICVDD" },
1852*4882a593Smuzhiyun { "MICBIAS4", NULL, "MICVDD" },
1853*4882a593Smuzhiyun
1854*4882a593Smuzhiyun { "Noise Generator", NULL, "SYSCLK" },
1855*4882a593Smuzhiyun { "Tone Generator 1", NULL, "SYSCLK" },
1856*4882a593Smuzhiyun { "Tone Generator 2", NULL, "SYSCLK" },
1857*4882a593Smuzhiyun
1858*4882a593Smuzhiyun { "Noise Generator", NULL, "NOISE" },
1859*4882a593Smuzhiyun { "Tone Generator 1", NULL, "TONE" },
1860*4882a593Smuzhiyun { "Tone Generator 2", NULL, "TONE" },
1861*4882a593Smuzhiyun
1862*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX1" },
1863*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX2" },
1864*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX3" },
1865*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX4" },
1866*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX5" },
1867*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX6" },
1868*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX7" },
1869*4882a593Smuzhiyun { "AIF1 Capture", NULL, "AIF1TX8" },
1870*4882a593Smuzhiyun
1871*4882a593Smuzhiyun { "AIF1RX1", NULL, "AIF1 Playback" },
1872*4882a593Smuzhiyun { "AIF1RX2", NULL, "AIF1 Playback" },
1873*4882a593Smuzhiyun { "AIF1RX3", NULL, "AIF1 Playback" },
1874*4882a593Smuzhiyun { "AIF1RX4", NULL, "AIF1 Playback" },
1875*4882a593Smuzhiyun { "AIF1RX5", NULL, "AIF1 Playback" },
1876*4882a593Smuzhiyun { "AIF1RX6", NULL, "AIF1 Playback" },
1877*4882a593Smuzhiyun { "AIF1RX7", NULL, "AIF1 Playback" },
1878*4882a593Smuzhiyun { "AIF1RX8", NULL, "AIF1 Playback" },
1879*4882a593Smuzhiyun
1880*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX1" },
1881*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX2" },
1882*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX3" },
1883*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX4" },
1884*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX5" },
1885*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX6" },
1886*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX7" },
1887*4882a593Smuzhiyun { "AIF2 Capture", NULL, "AIF2TX8" },
1888*4882a593Smuzhiyun
1889*4882a593Smuzhiyun { "AIF2RX1", NULL, "AIF2 Playback" },
1890*4882a593Smuzhiyun { "AIF2RX2", NULL, "AIF2 Playback" },
1891*4882a593Smuzhiyun { "AIF2RX3", NULL, "AIF2 Playback" },
1892*4882a593Smuzhiyun { "AIF2RX4", NULL, "AIF2 Playback" },
1893*4882a593Smuzhiyun { "AIF2RX5", NULL, "AIF2 Playback" },
1894*4882a593Smuzhiyun { "AIF2RX6", NULL, "AIF2 Playback" },
1895*4882a593Smuzhiyun { "AIF2RX7", NULL, "AIF2 Playback" },
1896*4882a593Smuzhiyun { "AIF2RX8", NULL, "AIF2 Playback" },
1897*4882a593Smuzhiyun
1898*4882a593Smuzhiyun { "AIF3 Capture", NULL, "AIF3TX1" },
1899*4882a593Smuzhiyun { "AIF3 Capture", NULL, "AIF3TX2" },
1900*4882a593Smuzhiyun
1901*4882a593Smuzhiyun { "AIF3RX1", NULL, "AIF3 Playback" },
1902*4882a593Smuzhiyun { "AIF3RX2", NULL, "AIF3 Playback" },
1903*4882a593Smuzhiyun
1904*4882a593Smuzhiyun { "AIF4 Capture", NULL, "AIF4TX1" },
1905*4882a593Smuzhiyun { "AIF4 Capture", NULL, "AIF4TX2" },
1906*4882a593Smuzhiyun
1907*4882a593Smuzhiyun { "AIF4RX1", NULL, "AIF4 Playback" },
1908*4882a593Smuzhiyun { "AIF4RX2", NULL, "AIF4 Playback" },
1909*4882a593Smuzhiyun
1910*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX1" },
1911*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX2" },
1912*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX3" },
1913*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SLIMTX4" },
1914*4882a593Smuzhiyun
1915*4882a593Smuzhiyun { "SLIMRX1", NULL, "Slim1 Playback" },
1916*4882a593Smuzhiyun { "SLIMRX2", NULL, "Slim1 Playback" },
1917*4882a593Smuzhiyun { "SLIMRX3", NULL, "Slim1 Playback" },
1918*4882a593Smuzhiyun { "SLIMRX4", NULL, "Slim1 Playback" },
1919*4882a593Smuzhiyun
1920*4882a593Smuzhiyun { "Slim2 Capture", NULL, "SLIMTX5" },
1921*4882a593Smuzhiyun { "Slim2 Capture", NULL, "SLIMTX6" },
1922*4882a593Smuzhiyun
1923*4882a593Smuzhiyun { "SLIMRX5", NULL, "Slim2 Playback" },
1924*4882a593Smuzhiyun { "SLIMRX6", NULL, "Slim2 Playback" },
1925*4882a593Smuzhiyun
1926*4882a593Smuzhiyun { "Slim3 Capture", NULL, "SLIMTX7" },
1927*4882a593Smuzhiyun { "Slim3 Capture", NULL, "SLIMTX8" },
1928*4882a593Smuzhiyun
1929*4882a593Smuzhiyun { "SLIMRX7", NULL, "Slim3 Playback" },
1930*4882a593Smuzhiyun { "SLIMRX8", NULL, "Slim3 Playback" },
1931*4882a593Smuzhiyun
1932*4882a593Smuzhiyun { "AIF1 Playback", NULL, "SYSCLK" },
1933*4882a593Smuzhiyun { "AIF2 Playback", NULL, "SYSCLK" },
1934*4882a593Smuzhiyun { "AIF3 Playback", NULL, "SYSCLK" },
1935*4882a593Smuzhiyun { "AIF4 Playback", NULL, "SYSCLK" },
1936*4882a593Smuzhiyun { "Slim1 Playback", NULL, "SYSCLK" },
1937*4882a593Smuzhiyun { "Slim2 Playback", NULL, "SYSCLK" },
1938*4882a593Smuzhiyun { "Slim3 Playback", NULL, "SYSCLK" },
1939*4882a593Smuzhiyun
1940*4882a593Smuzhiyun { "AIF1 Capture", NULL, "SYSCLK" },
1941*4882a593Smuzhiyun { "AIF2 Capture", NULL, "SYSCLK" },
1942*4882a593Smuzhiyun { "AIF3 Capture", NULL, "SYSCLK" },
1943*4882a593Smuzhiyun { "AIF4 Capture", NULL, "SYSCLK" },
1944*4882a593Smuzhiyun { "Slim1 Capture", NULL, "SYSCLK" },
1945*4882a593Smuzhiyun { "Slim2 Capture", NULL, "SYSCLK" },
1946*4882a593Smuzhiyun { "Slim3 Capture", NULL, "SYSCLK" },
1947*4882a593Smuzhiyun
1948*4882a593Smuzhiyun { "Voice Control DSP", NULL, "DSP6" },
1949*4882a593Smuzhiyun
1950*4882a593Smuzhiyun { "Audio Trace DSP", NULL, "DSP1" },
1951*4882a593Smuzhiyun
1952*4882a593Smuzhiyun { "IN1L Analog Mux", "A", "IN1ALN" },
1953*4882a593Smuzhiyun { "IN1L Analog Mux", "A", "IN1ALP" },
1954*4882a593Smuzhiyun { "IN1L Analog Mux", "B", "IN1BN" },
1955*4882a593Smuzhiyun { "IN1L Analog Mux", "B", "IN1BP" },
1956*4882a593Smuzhiyun
1957*4882a593Smuzhiyun { "IN1L Mode", "Analog", "IN1L Analog Mux" },
1958*4882a593Smuzhiyun { "IN1R Mode", "Analog", "IN1RN" },
1959*4882a593Smuzhiyun { "IN1R Mode", "Analog", "IN1RP" },
1960*4882a593Smuzhiyun
1961*4882a593Smuzhiyun { "IN1L Mode", "Digital", "IN1ALN" },
1962*4882a593Smuzhiyun { "IN1L Mode", "Digital", "IN1RN" },
1963*4882a593Smuzhiyun { "IN1R Mode", "Digital", "IN1ALN" },
1964*4882a593Smuzhiyun { "IN1R Mode", "Digital", "IN1RN" },
1965*4882a593Smuzhiyun
1966*4882a593Smuzhiyun { "IN1L", NULL, "IN1L Mode" },
1967*4882a593Smuzhiyun { "IN1R", NULL, "IN1R Mode" },
1968*4882a593Smuzhiyun
1969*4882a593Smuzhiyun { "IN2L Analog Mux", "A", "IN2ALN" },
1970*4882a593Smuzhiyun { "IN2L Analog Mux", "A", "IN2ALP" },
1971*4882a593Smuzhiyun { "IN2L Analog Mux", "B", "IN2BLN" },
1972*4882a593Smuzhiyun { "IN2L Analog Mux", "B", "IN2BLP" },
1973*4882a593Smuzhiyun { "IN2R Analog Mux", "A", "IN2ARN" },
1974*4882a593Smuzhiyun { "IN2R Analog Mux", "A", "IN2ARP" },
1975*4882a593Smuzhiyun { "IN2R Analog Mux", "B", "IN2BRN" },
1976*4882a593Smuzhiyun { "IN2R Analog Mux", "B", "IN2BRP" },
1977*4882a593Smuzhiyun
1978*4882a593Smuzhiyun { "IN2L Mode", "Analog", "IN2L Analog Mux" },
1979*4882a593Smuzhiyun { "IN2R Mode", "Analog", "IN2R Analog Mux" },
1980*4882a593Smuzhiyun
1981*4882a593Smuzhiyun { "IN2L Mode", "Digital", "IN2ALN" },
1982*4882a593Smuzhiyun { "IN2L Mode", "Digital", "IN2ARN" },
1983*4882a593Smuzhiyun { "IN2R Mode", "Digital", "IN2ALN" },
1984*4882a593Smuzhiyun { "IN2R Mode", "Digital", "IN2ARN" },
1985*4882a593Smuzhiyun
1986*4882a593Smuzhiyun { "IN2L", NULL, "IN2L Mode" },
1987*4882a593Smuzhiyun { "IN2R", NULL, "IN2R Mode" },
1988*4882a593Smuzhiyun
1989*4882a593Smuzhiyun { "IN3L Mode", "Analog", "IN3LN" },
1990*4882a593Smuzhiyun { "IN3L Mode", "Analog", "IN3LP" },
1991*4882a593Smuzhiyun { "IN3R Mode", "Analog", "IN3RN" },
1992*4882a593Smuzhiyun { "IN3R Mode", "Analog", "IN3RP" },
1993*4882a593Smuzhiyun
1994*4882a593Smuzhiyun { "IN3L Mode", "Digital", "IN3LN" },
1995*4882a593Smuzhiyun { "IN3L Mode", "Digital", "IN3RN" },
1996*4882a593Smuzhiyun { "IN3R Mode", "Digital", "IN3LN" },
1997*4882a593Smuzhiyun { "IN3R Mode", "Digital", "IN3RN" },
1998*4882a593Smuzhiyun
1999*4882a593Smuzhiyun { "IN3L", NULL, "IN3L Mode" },
2000*4882a593Smuzhiyun { "IN3R", NULL, "IN3R Mode" },
2001*4882a593Smuzhiyun
2002*4882a593Smuzhiyun { "IN4L", NULL, "DMICCLK4" },
2003*4882a593Smuzhiyun { "IN4L", NULL, "DMICDAT4" },
2004*4882a593Smuzhiyun { "IN4R", NULL, "DMICCLK4" },
2005*4882a593Smuzhiyun { "IN4R", NULL, "DMICDAT4" },
2006*4882a593Smuzhiyun
2007*4882a593Smuzhiyun { "IN5L", NULL, "DMICCLK5" },
2008*4882a593Smuzhiyun { "IN5L", NULL, "DMICDAT5" },
2009*4882a593Smuzhiyun { "IN5R", NULL, "DMICCLK5" },
2010*4882a593Smuzhiyun { "IN5R", NULL, "DMICDAT5" },
2011*4882a593Smuzhiyun
2012*4882a593Smuzhiyun { "IN6L", NULL, "DMICCLK6" },
2013*4882a593Smuzhiyun { "IN6L", NULL, "DMICDAT6" },
2014*4882a593Smuzhiyun { "IN6R", NULL, "DMICCLK6" },
2015*4882a593Smuzhiyun { "IN6R", NULL, "DMICDAT6" },
2016*4882a593Smuzhiyun
2017*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
2018*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
2019*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT2L", "HPOUT2L"),
2020*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT2R", "HPOUT2R"),
2021*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT3L", "HPOUT3L"),
2022*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT3R", "HPOUT3R"),
2023*4882a593Smuzhiyun
2024*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT4L", "SPKOUTL"),
2025*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT4R", "SPKOUTR"),
2026*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
2027*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
2028*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
2029*4882a593Smuzhiyun MADERA_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
2030*4882a593Smuzhiyun
2031*4882a593Smuzhiyun MADERA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
2032*4882a593Smuzhiyun MADERA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
2033*4882a593Smuzhiyun
2034*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
2035*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
2036*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
2037*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
2038*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
2039*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
2040*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
2041*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
2042*4882a593Smuzhiyun
2043*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
2044*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
2045*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
2046*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
2047*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"),
2048*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"),
2049*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX7", "AIF2TX7"),
2050*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF2TX8", "AIF2TX8"),
2051*4882a593Smuzhiyun
2052*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
2053*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
2054*4882a593Smuzhiyun
2055*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF4TX1", "AIF4TX1"),
2056*4882a593Smuzhiyun MADERA_MIXER_ROUTES("AIF4TX2", "AIF4TX2"),
2057*4882a593Smuzhiyun
2058*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
2059*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
2060*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
2061*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
2062*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
2063*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
2064*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"),
2065*4882a593Smuzhiyun MADERA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"),
2066*4882a593Smuzhiyun
2067*4882a593Smuzhiyun MADERA_MUX_ROUTES("SPD1TX1", "SPDIF1TX1"),
2068*4882a593Smuzhiyun MADERA_MUX_ROUTES("SPD1TX2", "SPDIF1TX2"),
2069*4882a593Smuzhiyun
2070*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ1", "EQ1"),
2071*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ2", "EQ2"),
2072*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ3", "EQ3"),
2073*4882a593Smuzhiyun MADERA_MIXER_ROUTES("EQ4", "EQ4"),
2074*4882a593Smuzhiyun
2075*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC1L", "DRC1L"),
2076*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC1R", "DRC1R"),
2077*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC2L", "DRC2L"),
2078*4882a593Smuzhiyun MADERA_MIXER_ROUTES("DRC2R", "DRC2R"),
2079*4882a593Smuzhiyun
2080*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF1", "LHPF1"),
2081*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF2", "LHPF2"),
2082*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF3", "LHPF3"),
2083*4882a593Smuzhiyun MADERA_MIXER_ROUTES("LHPF4", "LHPF4"),
2084*4882a593Smuzhiyun
2085*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN1L", "ASRC1IN1L"),
2086*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN1R", "ASRC1IN1R"),
2087*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN2L", "ASRC1IN2L"),
2088*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC1IN2R", "ASRC1IN2R"),
2089*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC2IN1L", "ASRC2IN1L"),
2090*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC2IN1R", "ASRC2IN1R"),
2091*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC2IN2L", "ASRC2IN2L"),
2092*4882a593Smuzhiyun MADERA_MUX_ROUTES("ASRC2IN2R", "ASRC2IN2R"),
2093*4882a593Smuzhiyun
2094*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP1"),
2095*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP2"),
2096*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP3"),
2097*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP4"),
2098*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP5"),
2099*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP6"),
2100*4882a593Smuzhiyun MADERA_DSP_ROUTES("DSP7"),
2101*4882a593Smuzhiyun
2102*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP1 Trigger Output" },
2103*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP2 Trigger Output" },
2104*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP3 Trigger Output" },
2105*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP4 Trigger Output" },
2106*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP5 Trigger Output" },
2107*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP6 Trigger Output" },
2108*4882a593Smuzhiyun { "DSP Trigger Out", NULL, "DSP7 Trigger Output" },
2109*4882a593Smuzhiyun
2110*4882a593Smuzhiyun { "DSP1 Trigger Output", "Switch", "DSP1" },
2111*4882a593Smuzhiyun { "DSP2 Trigger Output", "Switch", "DSP2" },
2112*4882a593Smuzhiyun { "DSP3 Trigger Output", "Switch", "DSP3" },
2113*4882a593Smuzhiyun { "DSP4 Trigger Output", "Switch", "DSP4" },
2114*4882a593Smuzhiyun { "DSP5 Trigger Output", "Switch", "DSP5" },
2115*4882a593Smuzhiyun { "DSP6 Trigger Output", "Switch", "DSP6" },
2116*4882a593Smuzhiyun { "DSP7 Trigger Output", "Switch", "DSP7" },
2117*4882a593Smuzhiyun
2118*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
2119*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
2120*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
2121*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
2122*4882a593Smuzhiyun
2123*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
2124*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
2125*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
2126*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
2127*4882a593Smuzhiyun
2128*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
2129*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
2130*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"),
2131*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"),
2132*4882a593Smuzhiyun
2133*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
2134*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
2135*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
2136*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
2137*4882a593Smuzhiyun
2138*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"),
2139*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"),
2140*4882a593Smuzhiyun
2141*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"),
2142*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"),
2143*4882a593Smuzhiyun
2144*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC4INT1", "ISRC4INT1"),
2145*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC4INT2", "ISRC4INT2"),
2146*4882a593Smuzhiyun
2147*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC4DEC1", "ISRC4DEC1"),
2148*4882a593Smuzhiyun MADERA_MUX_ROUTES("ISRC4DEC2", "ISRC4DEC2"),
2149*4882a593Smuzhiyun
2150*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT1L", "OUT1L" },
2151*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT1R", "OUT1R" },
2152*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT1L", "OUT1L" },
2153*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT1R", "OUT1R" },
2154*4882a593Smuzhiyun { "HPOUT1L", NULL, "OUT1L" },
2155*4882a593Smuzhiyun { "HPOUT1R", NULL, "OUT1R" },
2156*4882a593Smuzhiyun
2157*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT2L", "OUT2L" },
2158*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT2R", "OUT2R" },
2159*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT2L", "OUT2L" },
2160*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT2R", "OUT2R" },
2161*4882a593Smuzhiyun { "HPOUT2L", NULL, "OUT2L" },
2162*4882a593Smuzhiyun { "HPOUT2R", NULL, "OUT2R" },
2163*4882a593Smuzhiyun
2164*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT3L", "OUT3L" },
2165*4882a593Smuzhiyun { "AEC1 Loopback", "HPOUT3R", "OUT3R" },
2166*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT3L", "OUT3L" },
2167*4882a593Smuzhiyun { "AEC2 Loopback", "HPOUT3R", "OUT3R" },
2168*4882a593Smuzhiyun { "HPOUT3L", NULL, "OUT3L" },
2169*4882a593Smuzhiyun { "HPOUT3R", NULL, "OUT3R" },
2170*4882a593Smuzhiyun
2171*4882a593Smuzhiyun { "AEC1 Loopback", "SPKOUTL", "OUT4L" },
2172*4882a593Smuzhiyun { "AEC2 Loopback", "SPKOUTL", "OUT4L" },
2173*4882a593Smuzhiyun { "SPKOUTLN", NULL, "OUT4L" },
2174*4882a593Smuzhiyun { "SPKOUTLP", NULL, "OUT4L" },
2175*4882a593Smuzhiyun
2176*4882a593Smuzhiyun { "AEC1 Loopback", "SPKOUTR", "OUT4R" },
2177*4882a593Smuzhiyun { "AEC2 Loopback", "SPKOUTR", "OUT4R" },
2178*4882a593Smuzhiyun { "SPKOUTRN", NULL, "OUT4R" },
2179*4882a593Smuzhiyun { "SPKOUTRP", NULL, "OUT4R" },
2180*4882a593Smuzhiyun
2181*4882a593Smuzhiyun { "AEC1 Loopback", "SPKDAT1L", "OUT5L" },
2182*4882a593Smuzhiyun { "AEC1 Loopback", "SPKDAT1R", "OUT5R" },
2183*4882a593Smuzhiyun { "AEC2 Loopback", "SPKDAT1L", "OUT5L" },
2184*4882a593Smuzhiyun { "AEC2 Loopback", "SPKDAT1R", "OUT5R" },
2185*4882a593Smuzhiyun { "SPKDAT1L", NULL, "OUT5L" },
2186*4882a593Smuzhiyun { "SPKDAT1R", NULL, "OUT5R" },
2187*4882a593Smuzhiyun
2188*4882a593Smuzhiyun { "AEC1 Loopback", "SPKDAT2L", "OUT6L" },
2189*4882a593Smuzhiyun { "AEC1 Loopback", "SPKDAT2R", "OUT6R" },
2190*4882a593Smuzhiyun { "AEC2 Loopback", "SPKDAT2L", "OUT6L" },
2191*4882a593Smuzhiyun { "AEC2 Loopback", "SPKDAT2R", "OUT6R" },
2192*4882a593Smuzhiyun { "SPKDAT2L", NULL, "OUT6L" },
2193*4882a593Smuzhiyun { "SPKDAT2R", NULL, "OUT6R" },
2194*4882a593Smuzhiyun
2195*4882a593Smuzhiyun CS47L85_RXANC_INPUT_ROUTES("RXANCL", "RXANCL"),
2196*4882a593Smuzhiyun CS47L85_RXANC_INPUT_ROUTES("RXANCR", "RXANCR"),
2197*4882a593Smuzhiyun
2198*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT1L", "HPOUT1L"),
2199*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT1R", "HPOUT1R"),
2200*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT2L", "HPOUT2L"),
2201*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT2R", "HPOUT2R"),
2202*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT3L", "HPOUT3L"),
2203*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT3R", "HPOUT3R"),
2204*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT4L", "SPKOUTL"),
2205*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT4R", "SPKOUTR"),
2206*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT5L", "SPKDAT1L"),
2207*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT5R", "SPKDAT1R"),
2208*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT6L", "SPKDAT2L"),
2209*4882a593Smuzhiyun CS47L85_RXANC_OUTPUT_ROUTES("OUT6R", "SPKDAT2R"),
2210*4882a593Smuzhiyun
2211*4882a593Smuzhiyun { "SPDIF1", NULL, "SPD1" },
2212*4882a593Smuzhiyun
2213*4882a593Smuzhiyun { "MICSUPP", NULL, "SYSCLK" },
2214*4882a593Smuzhiyun
2215*4882a593Smuzhiyun { "DRC1 Signal Activity", NULL, "DRC1 Activity Output" },
2216*4882a593Smuzhiyun { "DRC2 Signal Activity", NULL, "DRC2 Activity Output" },
2217*4882a593Smuzhiyun { "DRC1 Activity Output", "Switch", "DRC1L" },
2218*4882a593Smuzhiyun { "DRC1 Activity Output", "Switch", "DRC1R" },
2219*4882a593Smuzhiyun { "DRC2 Activity Output", "Switch", "DRC2L" },
2220*4882a593Smuzhiyun { "DRC2 Activity Output", "Switch", "DRC2R" },
2221*4882a593Smuzhiyun };
2222*4882a593Smuzhiyun
cs47l85_set_fll(struct snd_soc_component * component,int fll_id,int source,unsigned int fref,unsigned int fout)2223*4882a593Smuzhiyun static int cs47l85_set_fll(struct snd_soc_component *component, int fll_id,
2224*4882a593Smuzhiyun int source, unsigned int fref, unsigned int fout)
2225*4882a593Smuzhiyun {
2226*4882a593Smuzhiyun struct cs47l85 *cs47l85 = snd_soc_component_get_drvdata(component);
2227*4882a593Smuzhiyun
2228*4882a593Smuzhiyun switch (fll_id) {
2229*4882a593Smuzhiyun case MADERA_FLL1_REFCLK:
2230*4882a593Smuzhiyun return madera_set_fll_refclk(&cs47l85->fll[0], source, fref,
2231*4882a593Smuzhiyun fout);
2232*4882a593Smuzhiyun case MADERA_FLL2_REFCLK:
2233*4882a593Smuzhiyun return madera_set_fll_refclk(&cs47l85->fll[1], source, fref,
2234*4882a593Smuzhiyun fout);
2235*4882a593Smuzhiyun case MADERA_FLL3_REFCLK:
2236*4882a593Smuzhiyun return madera_set_fll_refclk(&cs47l85->fll[2], source, fref,
2237*4882a593Smuzhiyun fout);
2238*4882a593Smuzhiyun case MADERA_FLL1_SYNCCLK:
2239*4882a593Smuzhiyun return madera_set_fll_syncclk(&cs47l85->fll[0], source, fref,
2240*4882a593Smuzhiyun fout);
2241*4882a593Smuzhiyun case MADERA_FLL2_SYNCCLK:
2242*4882a593Smuzhiyun return madera_set_fll_syncclk(&cs47l85->fll[1], source, fref,
2243*4882a593Smuzhiyun fout);
2244*4882a593Smuzhiyun case MADERA_FLL3_SYNCCLK:
2245*4882a593Smuzhiyun return madera_set_fll_syncclk(&cs47l85->fll[2], source, fref,
2246*4882a593Smuzhiyun fout);
2247*4882a593Smuzhiyun default:
2248*4882a593Smuzhiyun return -EINVAL;
2249*4882a593Smuzhiyun }
2250*4882a593Smuzhiyun }
2251*4882a593Smuzhiyun
2252*4882a593Smuzhiyun static struct snd_soc_dai_driver cs47l85_dai[] = {
2253*4882a593Smuzhiyun {
2254*4882a593Smuzhiyun .name = "cs47l85-aif1",
2255*4882a593Smuzhiyun .id = 1,
2256*4882a593Smuzhiyun .base = MADERA_AIF1_BCLK_CTRL,
2257*4882a593Smuzhiyun .playback = {
2258*4882a593Smuzhiyun .stream_name = "AIF1 Playback",
2259*4882a593Smuzhiyun .channels_min = 1,
2260*4882a593Smuzhiyun .channels_max = 8,
2261*4882a593Smuzhiyun .rates = MADERA_RATES,
2262*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2263*4882a593Smuzhiyun },
2264*4882a593Smuzhiyun .capture = {
2265*4882a593Smuzhiyun .stream_name = "AIF1 Capture",
2266*4882a593Smuzhiyun .channels_min = 1,
2267*4882a593Smuzhiyun .channels_max = 8,
2268*4882a593Smuzhiyun .rates = MADERA_RATES,
2269*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2270*4882a593Smuzhiyun },
2271*4882a593Smuzhiyun .ops = &madera_dai_ops,
2272*4882a593Smuzhiyun .symmetric_rates = 1,
2273*4882a593Smuzhiyun .symmetric_samplebits = 1,
2274*4882a593Smuzhiyun },
2275*4882a593Smuzhiyun {
2276*4882a593Smuzhiyun .name = "cs47l85-aif2",
2277*4882a593Smuzhiyun .id = 2,
2278*4882a593Smuzhiyun .base = MADERA_AIF2_BCLK_CTRL,
2279*4882a593Smuzhiyun .playback = {
2280*4882a593Smuzhiyun .stream_name = "AIF2 Playback",
2281*4882a593Smuzhiyun .channels_min = 1,
2282*4882a593Smuzhiyun .channels_max = 8,
2283*4882a593Smuzhiyun .rates = MADERA_RATES,
2284*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2285*4882a593Smuzhiyun },
2286*4882a593Smuzhiyun .capture = {
2287*4882a593Smuzhiyun .stream_name = "AIF2 Capture",
2288*4882a593Smuzhiyun .channels_min = 1,
2289*4882a593Smuzhiyun .channels_max = 8,
2290*4882a593Smuzhiyun .rates = MADERA_RATES,
2291*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2292*4882a593Smuzhiyun },
2293*4882a593Smuzhiyun .ops = &madera_dai_ops,
2294*4882a593Smuzhiyun .symmetric_rates = 1,
2295*4882a593Smuzhiyun .symmetric_samplebits = 1,
2296*4882a593Smuzhiyun },
2297*4882a593Smuzhiyun {
2298*4882a593Smuzhiyun .name = "cs47l85-aif3",
2299*4882a593Smuzhiyun .id = 3,
2300*4882a593Smuzhiyun .base = MADERA_AIF3_BCLK_CTRL,
2301*4882a593Smuzhiyun .playback = {
2302*4882a593Smuzhiyun .stream_name = "AIF3 Playback",
2303*4882a593Smuzhiyun .channels_min = 1,
2304*4882a593Smuzhiyun .channels_max = 2,
2305*4882a593Smuzhiyun .rates = MADERA_RATES,
2306*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2307*4882a593Smuzhiyun },
2308*4882a593Smuzhiyun .capture = {
2309*4882a593Smuzhiyun .stream_name = "AIF3 Capture",
2310*4882a593Smuzhiyun .channels_min = 1,
2311*4882a593Smuzhiyun .channels_max = 2,
2312*4882a593Smuzhiyun .rates = MADERA_RATES,
2313*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2314*4882a593Smuzhiyun },
2315*4882a593Smuzhiyun .ops = &madera_dai_ops,
2316*4882a593Smuzhiyun .symmetric_rates = 1,
2317*4882a593Smuzhiyun .symmetric_samplebits = 1,
2318*4882a593Smuzhiyun },
2319*4882a593Smuzhiyun {
2320*4882a593Smuzhiyun .name = "cs47l85-aif4",
2321*4882a593Smuzhiyun .id = 4,
2322*4882a593Smuzhiyun .base = MADERA_AIF4_BCLK_CTRL,
2323*4882a593Smuzhiyun .playback = {
2324*4882a593Smuzhiyun .stream_name = "AIF4 Playback",
2325*4882a593Smuzhiyun .channels_min = 1,
2326*4882a593Smuzhiyun .channels_max = 2,
2327*4882a593Smuzhiyun .rates = MADERA_RATES,
2328*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2329*4882a593Smuzhiyun },
2330*4882a593Smuzhiyun .capture = {
2331*4882a593Smuzhiyun .stream_name = "AIF4 Capture",
2332*4882a593Smuzhiyun .channels_min = 1,
2333*4882a593Smuzhiyun .channels_max = 2,
2334*4882a593Smuzhiyun .rates = MADERA_RATES,
2335*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2336*4882a593Smuzhiyun },
2337*4882a593Smuzhiyun .ops = &madera_dai_ops,
2338*4882a593Smuzhiyun .symmetric_rates = 1,
2339*4882a593Smuzhiyun .symmetric_samplebits = 1,
2340*4882a593Smuzhiyun },
2341*4882a593Smuzhiyun {
2342*4882a593Smuzhiyun .name = "cs47l85-slim1",
2343*4882a593Smuzhiyun .id = 5,
2344*4882a593Smuzhiyun .playback = {
2345*4882a593Smuzhiyun .stream_name = "Slim1 Playback",
2346*4882a593Smuzhiyun .channels_min = 1,
2347*4882a593Smuzhiyun .channels_max = 4,
2348*4882a593Smuzhiyun .rates = MADERA_RATES,
2349*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2350*4882a593Smuzhiyun },
2351*4882a593Smuzhiyun .capture = {
2352*4882a593Smuzhiyun .stream_name = "Slim1 Capture",
2353*4882a593Smuzhiyun .channels_min = 1,
2354*4882a593Smuzhiyun .channels_max = 4,
2355*4882a593Smuzhiyun .rates = MADERA_RATES,
2356*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2357*4882a593Smuzhiyun },
2358*4882a593Smuzhiyun .ops = &madera_simple_dai_ops,
2359*4882a593Smuzhiyun },
2360*4882a593Smuzhiyun {
2361*4882a593Smuzhiyun .name = "cs47l85-slim2",
2362*4882a593Smuzhiyun .id = 6,
2363*4882a593Smuzhiyun .playback = {
2364*4882a593Smuzhiyun .stream_name = "Slim2 Playback",
2365*4882a593Smuzhiyun .channels_min = 1,
2366*4882a593Smuzhiyun .channels_max = 2,
2367*4882a593Smuzhiyun .rates = MADERA_RATES,
2368*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2369*4882a593Smuzhiyun },
2370*4882a593Smuzhiyun .capture = {
2371*4882a593Smuzhiyun .stream_name = "Slim2 Capture",
2372*4882a593Smuzhiyun .channels_min = 1,
2373*4882a593Smuzhiyun .channels_max = 2,
2374*4882a593Smuzhiyun .rates = MADERA_RATES,
2375*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2376*4882a593Smuzhiyun },
2377*4882a593Smuzhiyun .ops = &madera_simple_dai_ops,
2378*4882a593Smuzhiyun },
2379*4882a593Smuzhiyun {
2380*4882a593Smuzhiyun .name = "cs47l85-slim3",
2381*4882a593Smuzhiyun .id = 7,
2382*4882a593Smuzhiyun .playback = {
2383*4882a593Smuzhiyun .stream_name = "Slim3 Playback",
2384*4882a593Smuzhiyun .channels_min = 1,
2385*4882a593Smuzhiyun .channels_max = 2,
2386*4882a593Smuzhiyun .rates = MADERA_RATES,
2387*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2388*4882a593Smuzhiyun },
2389*4882a593Smuzhiyun .capture = {
2390*4882a593Smuzhiyun .stream_name = "Slim3 Capture",
2391*4882a593Smuzhiyun .channels_min = 1,
2392*4882a593Smuzhiyun .channels_max = 2,
2393*4882a593Smuzhiyun .rates = MADERA_RATES,
2394*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2395*4882a593Smuzhiyun },
2396*4882a593Smuzhiyun .ops = &madera_simple_dai_ops,
2397*4882a593Smuzhiyun },
2398*4882a593Smuzhiyun {
2399*4882a593Smuzhiyun .name = "cs47l85-cpu-voicectrl",
2400*4882a593Smuzhiyun .capture = {
2401*4882a593Smuzhiyun .stream_name = "Voice Control CPU",
2402*4882a593Smuzhiyun .channels_min = 1,
2403*4882a593Smuzhiyun .channels_max = 1,
2404*4882a593Smuzhiyun .rates = MADERA_RATES,
2405*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2406*4882a593Smuzhiyun },
2407*4882a593Smuzhiyun .compress_new = &snd_soc_new_compress,
2408*4882a593Smuzhiyun },
2409*4882a593Smuzhiyun {
2410*4882a593Smuzhiyun .name = "cs47l85-dsp-voicectrl",
2411*4882a593Smuzhiyun .capture = {
2412*4882a593Smuzhiyun .stream_name = "Voice Control DSP",
2413*4882a593Smuzhiyun .channels_min = 1,
2414*4882a593Smuzhiyun .channels_max = 1,
2415*4882a593Smuzhiyun .rates = MADERA_RATES,
2416*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2417*4882a593Smuzhiyun },
2418*4882a593Smuzhiyun },
2419*4882a593Smuzhiyun {
2420*4882a593Smuzhiyun .name = "cs47l85-cpu-trace",
2421*4882a593Smuzhiyun .capture = {
2422*4882a593Smuzhiyun .stream_name = "Audio Trace CPU",
2423*4882a593Smuzhiyun .channels_min = 1,
2424*4882a593Smuzhiyun .channels_max = 6,
2425*4882a593Smuzhiyun .rates = MADERA_RATES,
2426*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2427*4882a593Smuzhiyun },
2428*4882a593Smuzhiyun .compress_new = &snd_soc_new_compress,
2429*4882a593Smuzhiyun },
2430*4882a593Smuzhiyun {
2431*4882a593Smuzhiyun .name = "cs47l85-dsp-trace",
2432*4882a593Smuzhiyun .capture = {
2433*4882a593Smuzhiyun .stream_name = "Audio Trace DSP",
2434*4882a593Smuzhiyun .channels_min = 1,
2435*4882a593Smuzhiyun .channels_max = 6,
2436*4882a593Smuzhiyun .rates = MADERA_RATES,
2437*4882a593Smuzhiyun .formats = MADERA_FORMATS,
2438*4882a593Smuzhiyun },
2439*4882a593Smuzhiyun },
2440*4882a593Smuzhiyun };
2441*4882a593Smuzhiyun
cs47l85_open(struct snd_soc_component * component,struct snd_compr_stream * stream)2442*4882a593Smuzhiyun static int cs47l85_open(struct snd_soc_component *component,
2443*4882a593Smuzhiyun struct snd_compr_stream *stream)
2444*4882a593Smuzhiyun {
2445*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = stream->private_data;
2446*4882a593Smuzhiyun struct cs47l85 *cs47l85 = snd_soc_component_get_drvdata(component);
2447*4882a593Smuzhiyun struct madera_priv *priv = &cs47l85->core;
2448*4882a593Smuzhiyun struct madera *madera = priv->madera;
2449*4882a593Smuzhiyun int n_adsp;
2450*4882a593Smuzhiyun
2451*4882a593Smuzhiyun if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l85-dsp-voicectrl") == 0) {
2452*4882a593Smuzhiyun n_adsp = 5;
2453*4882a593Smuzhiyun } else if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l85-dsp-trace") == 0) {
2454*4882a593Smuzhiyun n_adsp = 0;
2455*4882a593Smuzhiyun } else {
2456*4882a593Smuzhiyun dev_err(madera->dev,
2457*4882a593Smuzhiyun "No suitable compressed stream for DAI '%s'\n",
2458*4882a593Smuzhiyun asoc_rtd_to_codec(rtd, 0)->name);
2459*4882a593Smuzhiyun return -EINVAL;
2460*4882a593Smuzhiyun }
2461*4882a593Smuzhiyun
2462*4882a593Smuzhiyun return wm_adsp_compr_open(&priv->adsp[n_adsp], stream);
2463*4882a593Smuzhiyun }
2464*4882a593Smuzhiyun
cs47l85_adsp2_irq(int irq,void * data)2465*4882a593Smuzhiyun static irqreturn_t cs47l85_adsp2_irq(int irq, void *data)
2466*4882a593Smuzhiyun {
2467*4882a593Smuzhiyun struct cs47l85 *cs47l85 = data;
2468*4882a593Smuzhiyun struct madera_priv *priv = &cs47l85->core;
2469*4882a593Smuzhiyun struct madera *madera = priv->madera;
2470*4882a593Smuzhiyun struct madera_voice_trigger_info trig_info;
2471*4882a593Smuzhiyun int serviced = 0;
2472*4882a593Smuzhiyun int i, ret;
2473*4882a593Smuzhiyun
2474*4882a593Smuzhiyun for (i = 0; i < CS47L85_NUM_ADSP; ++i) {
2475*4882a593Smuzhiyun ret = wm_adsp_compr_handle_irq(&priv->adsp[i]);
2476*4882a593Smuzhiyun if (ret != -ENODEV)
2477*4882a593Smuzhiyun serviced++;
2478*4882a593Smuzhiyun if (ret == WM_ADSP_COMPR_VOICE_TRIGGER) {
2479*4882a593Smuzhiyun trig_info.core_num = i + 1;
2480*4882a593Smuzhiyun blocking_notifier_call_chain(&madera->notifier,
2481*4882a593Smuzhiyun MADERA_NOTIFY_VOICE_TRIGGER,
2482*4882a593Smuzhiyun &trig_info);
2483*4882a593Smuzhiyun }
2484*4882a593Smuzhiyun }
2485*4882a593Smuzhiyun
2486*4882a593Smuzhiyun if (!serviced) {
2487*4882a593Smuzhiyun dev_err(madera->dev, "Spurious compressed data IRQ\n");
2488*4882a593Smuzhiyun return IRQ_NONE;
2489*4882a593Smuzhiyun }
2490*4882a593Smuzhiyun
2491*4882a593Smuzhiyun return IRQ_HANDLED;
2492*4882a593Smuzhiyun }
2493*4882a593Smuzhiyun
cs47l85_component_probe(struct snd_soc_component * component)2494*4882a593Smuzhiyun static int cs47l85_component_probe(struct snd_soc_component *component)
2495*4882a593Smuzhiyun {
2496*4882a593Smuzhiyun struct cs47l85 *cs47l85 = snd_soc_component_get_drvdata(component);
2497*4882a593Smuzhiyun struct madera *madera = cs47l85->core.madera;
2498*4882a593Smuzhiyun int i, ret;
2499*4882a593Smuzhiyun
2500*4882a593Smuzhiyun snd_soc_component_init_regmap(component, madera->regmap);
2501*4882a593Smuzhiyun
2502*4882a593Smuzhiyun mutex_lock(&madera->dapm_ptr_lock);
2503*4882a593Smuzhiyun madera->dapm = snd_soc_component_get_dapm(component);
2504*4882a593Smuzhiyun mutex_unlock(&madera->dapm_ptr_lock);
2505*4882a593Smuzhiyun
2506*4882a593Smuzhiyun ret = madera_init_inputs(component);
2507*4882a593Smuzhiyun if (ret)
2508*4882a593Smuzhiyun return ret;
2509*4882a593Smuzhiyun
2510*4882a593Smuzhiyun ret = madera_init_outputs(component, NULL, CS47L85_MONO_OUTPUTS,
2511*4882a593Smuzhiyun CS47L85_MONO_OUTPUTS);
2512*4882a593Smuzhiyun if (ret)
2513*4882a593Smuzhiyun return ret;
2514*4882a593Smuzhiyun
2515*4882a593Smuzhiyun snd_soc_component_disable_pin(component, "HAPTICS");
2516*4882a593Smuzhiyun
2517*4882a593Smuzhiyun ret = snd_soc_add_component_controls(component,
2518*4882a593Smuzhiyun madera_adsp_rate_controls,
2519*4882a593Smuzhiyun CS47L85_NUM_ADSP);
2520*4882a593Smuzhiyun if (ret)
2521*4882a593Smuzhiyun return ret;
2522*4882a593Smuzhiyun
2523*4882a593Smuzhiyun for (i = 0; i < CS47L85_NUM_ADSP; i++)
2524*4882a593Smuzhiyun wm_adsp2_component_probe(&cs47l85->core.adsp[i], component);
2525*4882a593Smuzhiyun
2526*4882a593Smuzhiyun return 0;
2527*4882a593Smuzhiyun }
2528*4882a593Smuzhiyun
cs47l85_component_remove(struct snd_soc_component * component)2529*4882a593Smuzhiyun static void cs47l85_component_remove(struct snd_soc_component *component)
2530*4882a593Smuzhiyun {
2531*4882a593Smuzhiyun struct cs47l85 *cs47l85 = snd_soc_component_get_drvdata(component);
2532*4882a593Smuzhiyun struct madera *madera = cs47l85->core.madera;
2533*4882a593Smuzhiyun int i;
2534*4882a593Smuzhiyun
2535*4882a593Smuzhiyun mutex_lock(&madera->dapm_ptr_lock);
2536*4882a593Smuzhiyun madera->dapm = NULL;
2537*4882a593Smuzhiyun mutex_unlock(&madera->dapm_ptr_lock);
2538*4882a593Smuzhiyun
2539*4882a593Smuzhiyun for (i = 0; i < CS47L85_NUM_ADSP; i++)
2540*4882a593Smuzhiyun wm_adsp2_component_remove(&cs47l85->core.adsp[i], component);
2541*4882a593Smuzhiyun }
2542*4882a593Smuzhiyun
2543*4882a593Smuzhiyun #define MADERA_DIG_VU 0x0200
2544*4882a593Smuzhiyun
2545*4882a593Smuzhiyun static const unsigned int cs47l85_digital_vu[] = {
2546*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1L,
2547*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_1R,
2548*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2L,
2549*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_2R,
2550*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3L,
2551*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_3R,
2552*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_4L,
2553*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_4R,
2554*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5L,
2555*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_5R,
2556*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_6L,
2557*4882a593Smuzhiyun MADERA_DAC_DIGITAL_VOLUME_6R,
2558*4882a593Smuzhiyun };
2559*4882a593Smuzhiyun
2560*4882a593Smuzhiyun static const struct snd_compress_ops cs47l85_compress_ops = {
2561*4882a593Smuzhiyun .open = &cs47l85_open,
2562*4882a593Smuzhiyun .free = &wm_adsp_compr_free,
2563*4882a593Smuzhiyun .set_params = &wm_adsp_compr_set_params,
2564*4882a593Smuzhiyun .get_caps = &wm_adsp_compr_get_caps,
2565*4882a593Smuzhiyun .trigger = &wm_adsp_compr_trigger,
2566*4882a593Smuzhiyun .pointer = &wm_adsp_compr_pointer,
2567*4882a593Smuzhiyun .copy = &wm_adsp_compr_copy,
2568*4882a593Smuzhiyun };
2569*4882a593Smuzhiyun
2570*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_cs47l85 = {
2571*4882a593Smuzhiyun .probe = &cs47l85_component_probe,
2572*4882a593Smuzhiyun .remove = &cs47l85_component_remove,
2573*4882a593Smuzhiyun .set_sysclk = &madera_set_sysclk,
2574*4882a593Smuzhiyun .set_pll = &cs47l85_set_fll,
2575*4882a593Smuzhiyun .name = DRV_NAME,
2576*4882a593Smuzhiyun .compress_ops = &cs47l85_compress_ops,
2577*4882a593Smuzhiyun .controls = cs47l85_snd_controls,
2578*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(cs47l85_snd_controls),
2579*4882a593Smuzhiyun .dapm_widgets = cs47l85_dapm_widgets,
2580*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(cs47l85_dapm_widgets),
2581*4882a593Smuzhiyun .dapm_routes = cs47l85_dapm_routes,
2582*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(cs47l85_dapm_routes),
2583*4882a593Smuzhiyun .use_pmdown_time = 1,
2584*4882a593Smuzhiyun .endianness = 1,
2585*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
2586*4882a593Smuzhiyun };
2587*4882a593Smuzhiyun
cs47l85_probe(struct platform_device * pdev)2588*4882a593Smuzhiyun static int cs47l85_probe(struct platform_device *pdev)
2589*4882a593Smuzhiyun {
2590*4882a593Smuzhiyun struct madera *madera = dev_get_drvdata(pdev->dev.parent);
2591*4882a593Smuzhiyun struct cs47l85 *cs47l85;
2592*4882a593Smuzhiyun int i, ret;
2593*4882a593Smuzhiyun
2594*4882a593Smuzhiyun BUILD_BUG_ON(ARRAY_SIZE(cs47l85_dai) > MADERA_MAX_DAI);
2595*4882a593Smuzhiyun
2596*4882a593Smuzhiyun /* quick exit if Madera irqchip driver hasn't completed probe */
2597*4882a593Smuzhiyun if (!madera->irq_dev) {
2598*4882a593Smuzhiyun dev_dbg(&pdev->dev, "irqchip driver not ready\n");
2599*4882a593Smuzhiyun return -EPROBE_DEFER;
2600*4882a593Smuzhiyun }
2601*4882a593Smuzhiyun
2602*4882a593Smuzhiyun cs47l85 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l85),
2603*4882a593Smuzhiyun GFP_KERNEL);
2604*4882a593Smuzhiyun if (!cs47l85)
2605*4882a593Smuzhiyun return -ENOMEM;
2606*4882a593Smuzhiyun
2607*4882a593Smuzhiyun platform_set_drvdata(pdev, cs47l85);
2608*4882a593Smuzhiyun
2609*4882a593Smuzhiyun cs47l85->core.madera = madera;
2610*4882a593Smuzhiyun cs47l85->core.dev = &pdev->dev;
2611*4882a593Smuzhiyun cs47l85->core.num_inputs = 12;
2612*4882a593Smuzhiyun
2613*4882a593Smuzhiyun ret = madera_core_init(&cs47l85->core);
2614*4882a593Smuzhiyun if (ret)
2615*4882a593Smuzhiyun return ret;
2616*4882a593Smuzhiyun
2617*4882a593Smuzhiyun ret = madera_init_overheat(&cs47l85->core);
2618*4882a593Smuzhiyun if (ret)
2619*4882a593Smuzhiyun goto error_core;
2620*4882a593Smuzhiyun
2621*4882a593Smuzhiyun ret = madera_request_irq(madera, MADERA_IRQ_DSP_IRQ1,
2622*4882a593Smuzhiyun "ADSP2 Compressed IRQ", cs47l85_adsp2_irq,
2623*4882a593Smuzhiyun cs47l85);
2624*4882a593Smuzhiyun if (ret) {
2625*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
2626*4882a593Smuzhiyun goto error_overheat;
2627*4882a593Smuzhiyun }
2628*4882a593Smuzhiyun
2629*4882a593Smuzhiyun ret = madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 1);
2630*4882a593Smuzhiyun if (ret)
2631*4882a593Smuzhiyun dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
2632*4882a593Smuzhiyun
2633*4882a593Smuzhiyun for (i = 0; i < CS47L85_NUM_ADSP; i++) {
2634*4882a593Smuzhiyun cs47l85->core.adsp[i].part = "cs47l85";
2635*4882a593Smuzhiyun cs47l85->core.adsp[i].num = i + 1;
2636*4882a593Smuzhiyun cs47l85->core.adsp[i].type = WMFW_ADSP2;
2637*4882a593Smuzhiyun cs47l85->core.adsp[i].rev = 1;
2638*4882a593Smuzhiyun cs47l85->core.adsp[i].dev = madera->dev;
2639*4882a593Smuzhiyun cs47l85->core.adsp[i].regmap = madera->regmap_32bit;
2640*4882a593Smuzhiyun
2641*4882a593Smuzhiyun cs47l85->core.adsp[i].base = wm_adsp2_control_bases[i];
2642*4882a593Smuzhiyun cs47l85->core.adsp[i].mem = cs47l85_dsp_regions[i];
2643*4882a593Smuzhiyun cs47l85->core.adsp[i].num_mems =
2644*4882a593Smuzhiyun ARRAY_SIZE(cs47l85_dsp1_regions);
2645*4882a593Smuzhiyun
2646*4882a593Smuzhiyun ret = wm_adsp2_init(&cs47l85->core.adsp[i]);
2647*4882a593Smuzhiyun if (ret) {
2648*4882a593Smuzhiyun for (--i; i >= 0; --i)
2649*4882a593Smuzhiyun wm_adsp2_remove(&cs47l85->core.adsp[i]);
2650*4882a593Smuzhiyun goto error_dsp_irq;
2651*4882a593Smuzhiyun }
2652*4882a593Smuzhiyun }
2653*4882a593Smuzhiyun
2654*4882a593Smuzhiyun madera_init_fll(madera, 1, MADERA_FLL1_CONTROL_1 - 1,
2655*4882a593Smuzhiyun &cs47l85->fll[0]);
2656*4882a593Smuzhiyun madera_init_fll(madera, 2, MADERA_FLL2_CONTROL_1 - 1,
2657*4882a593Smuzhiyun &cs47l85->fll[1]);
2658*4882a593Smuzhiyun madera_init_fll(madera, 3, MADERA_FLL3_CONTROL_1 - 1,
2659*4882a593Smuzhiyun &cs47l85->fll[2]);
2660*4882a593Smuzhiyun
2661*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cs47l85_dai); i++)
2662*4882a593Smuzhiyun madera_init_dai(&cs47l85->core, i);
2663*4882a593Smuzhiyun
2664*4882a593Smuzhiyun /* Latch volume update bits */
2665*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cs47l85_digital_vu); i++)
2666*4882a593Smuzhiyun regmap_update_bits(madera->regmap, cs47l85_digital_vu[i],
2667*4882a593Smuzhiyun MADERA_DIG_VU, MADERA_DIG_VU);
2668*4882a593Smuzhiyun
2669*4882a593Smuzhiyun pm_runtime_enable(&pdev->dev);
2670*4882a593Smuzhiyun pm_runtime_idle(&pdev->dev);
2671*4882a593Smuzhiyun
2672*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&pdev->dev,
2673*4882a593Smuzhiyun &soc_component_dev_cs47l85,
2674*4882a593Smuzhiyun cs47l85_dai,
2675*4882a593Smuzhiyun ARRAY_SIZE(cs47l85_dai));
2676*4882a593Smuzhiyun if (ret < 0) {
2677*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
2678*4882a593Smuzhiyun goto error_pm_runtime;
2679*4882a593Smuzhiyun }
2680*4882a593Smuzhiyun
2681*4882a593Smuzhiyun return ret;
2682*4882a593Smuzhiyun
2683*4882a593Smuzhiyun error_pm_runtime:
2684*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
2685*4882a593Smuzhiyun
2686*4882a593Smuzhiyun for (i = 0; i < CS47L85_NUM_ADSP; i++)
2687*4882a593Smuzhiyun wm_adsp2_remove(&cs47l85->core.adsp[i]);
2688*4882a593Smuzhiyun error_dsp_irq:
2689*4882a593Smuzhiyun madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 0);
2690*4882a593Smuzhiyun madera_free_irq(madera, MADERA_IRQ_DSP_IRQ1, cs47l85);
2691*4882a593Smuzhiyun error_overheat:
2692*4882a593Smuzhiyun madera_free_overheat(&cs47l85->core);
2693*4882a593Smuzhiyun error_core:
2694*4882a593Smuzhiyun madera_core_free(&cs47l85->core);
2695*4882a593Smuzhiyun
2696*4882a593Smuzhiyun return ret;
2697*4882a593Smuzhiyun }
2698*4882a593Smuzhiyun
cs47l85_remove(struct platform_device * pdev)2699*4882a593Smuzhiyun static int cs47l85_remove(struct platform_device *pdev)
2700*4882a593Smuzhiyun {
2701*4882a593Smuzhiyun struct cs47l85 *cs47l85 = platform_get_drvdata(pdev);
2702*4882a593Smuzhiyun int i;
2703*4882a593Smuzhiyun
2704*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
2705*4882a593Smuzhiyun
2706*4882a593Smuzhiyun for (i = 0; i < CS47L85_NUM_ADSP; i++)
2707*4882a593Smuzhiyun wm_adsp2_remove(&cs47l85->core.adsp[i]);
2708*4882a593Smuzhiyun
2709*4882a593Smuzhiyun madera_set_irq_wake(cs47l85->core.madera, MADERA_IRQ_DSP_IRQ1, 0);
2710*4882a593Smuzhiyun madera_free_irq(cs47l85->core.madera, MADERA_IRQ_DSP_IRQ1, cs47l85);
2711*4882a593Smuzhiyun madera_free_overheat(&cs47l85->core);
2712*4882a593Smuzhiyun madera_core_free(&cs47l85->core);
2713*4882a593Smuzhiyun
2714*4882a593Smuzhiyun return 0;
2715*4882a593Smuzhiyun }
2716*4882a593Smuzhiyun
2717*4882a593Smuzhiyun static struct platform_driver cs47l85_codec_driver = {
2718*4882a593Smuzhiyun .driver = {
2719*4882a593Smuzhiyun .name = "cs47l85-codec",
2720*4882a593Smuzhiyun },
2721*4882a593Smuzhiyun .probe = &cs47l85_probe,
2722*4882a593Smuzhiyun .remove = &cs47l85_remove,
2723*4882a593Smuzhiyun };
2724*4882a593Smuzhiyun
2725*4882a593Smuzhiyun module_platform_driver(cs47l85_codec_driver);
2726*4882a593Smuzhiyun
2727*4882a593Smuzhiyun MODULE_SOFTDEP("pre: madera irq-madera arizona-micsupp");
2728*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC CS47L85 driver");
2729*4882a593Smuzhiyun MODULE_AUTHOR("Nariman Poushin <nariman@opensource.cirrus.com>");
2730*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
2731*4882a593Smuzhiyun MODULE_ALIAS("platform:cs47l85-codec");
2732