xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/cs47l35.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // ALSA SoC Audio driver for CS47L35 codec
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
6*4882a593Smuzhiyun //                         Cirrus Logic International Semiconductor Ltd.
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/moduleparam.h>
14*4882a593Smuzhiyun #include <linux/pm.h>
15*4882a593Smuzhiyun #include <linux/pm_runtime.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <sound/core.h>
18*4882a593Smuzhiyun #include <sound/pcm.h>
19*4882a593Smuzhiyun #include <sound/pcm_params.h>
20*4882a593Smuzhiyun #include <sound/soc.h>
21*4882a593Smuzhiyun #include <sound/tlv.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include <linux/irqchip/irq-madera.h>
24*4882a593Smuzhiyun #include <linux/mfd/madera/core.h>
25*4882a593Smuzhiyun #include <linux/mfd/madera/registers.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "madera.h"
28*4882a593Smuzhiyun #include "wm_adsp.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define CS47L35_NUM_ADSP	3
31*4882a593Smuzhiyun #define CS47L35_MONO_OUTPUTS	1
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define DRV_NAME "cs47l35-codec"
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun struct cs47l35 {
36*4882a593Smuzhiyun 	struct madera_priv core;
37*4882a593Smuzhiyun 	struct madera_fll fll;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun static const struct wm_adsp_region cs47l35_dsp1_regions[] = {
41*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
42*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun static const struct wm_adsp_region cs47l35_dsp2_regions[] = {
48*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
49*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_ZM, .base = 0x160000 },
50*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_XM, .base = 0x120000 },
51*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_YM, .base = 0x140000 },
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun static const struct wm_adsp_region cs47l35_dsp3_regions[] = {
55*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_PM, .base = 0x180000 },
56*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
57*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_XM, .base = 0x1a0000 },
58*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_YM, .base = 0x1c0000 },
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun static const struct wm_adsp_region *cs47l35_dsp_regions[] = {
62*4882a593Smuzhiyun 	cs47l35_dsp1_regions,
63*4882a593Smuzhiyun 	cs47l35_dsp2_regions,
64*4882a593Smuzhiyun 	cs47l35_dsp3_regions,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun static const int wm_adsp2_control_bases[] = {
68*4882a593Smuzhiyun 	MADERA_DSP1_CONFIG_1,
69*4882a593Smuzhiyun 	MADERA_DSP2_CONFIG_1,
70*4882a593Smuzhiyun 	MADERA_DSP3_CONFIG_1,
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun static const char * const cs47l35_outdemux_texts[] = {
74*4882a593Smuzhiyun 	"HPOUT",
75*4882a593Smuzhiyun 	"EPOUT",
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(cs47l35_outdemux_enum, SND_SOC_NOPM, 0,
79*4882a593Smuzhiyun 			    cs47l35_outdemux_texts);
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l35_outdemux =
82*4882a593Smuzhiyun 	SOC_DAPM_ENUM_EXT("HPOUT1 Demux", cs47l35_outdemux_enum,
83*4882a593Smuzhiyun 			  madera_out1_demux_get, madera_out1_demux_put);
84*4882a593Smuzhiyun 
cs47l35_adsp_power_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)85*4882a593Smuzhiyun static int cs47l35_adsp_power_ev(struct snd_soc_dapm_widget *w,
86*4882a593Smuzhiyun 				 struct snd_kcontrol *kcontrol,
87*4882a593Smuzhiyun 				 int event)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	struct snd_soc_component *component =
90*4882a593Smuzhiyun 		snd_soc_dapm_to_component(w->dapm);
91*4882a593Smuzhiyun 	struct cs47l35 *cs47l35 = snd_soc_component_get_drvdata(component);
92*4882a593Smuzhiyun 	struct madera_priv *priv = &cs47l35->core;
93*4882a593Smuzhiyun 	struct madera *madera = priv->madera;
94*4882a593Smuzhiyun 	unsigned int freq;
95*4882a593Smuzhiyun 	int ret;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	ret = regmap_read(madera->regmap, MADERA_DSP_CLOCK_1, &freq);
98*4882a593Smuzhiyun 	if (ret != 0) {
99*4882a593Smuzhiyun 		dev_err(madera->dev,
100*4882a593Smuzhiyun 			"Failed to read MADERA_DSP_CLOCK_1: %d\n", ret);
101*4882a593Smuzhiyun 		return ret;
102*4882a593Smuzhiyun 	}
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	freq &= MADERA_DSP_CLK_FREQ_LEGACY_MASK;
105*4882a593Smuzhiyun 	freq >>= MADERA_DSP_CLK_FREQ_LEGACY_SHIFT;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	switch (event) {
108*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMU:
109*4882a593Smuzhiyun 		ret = madera_set_adsp_clk(&cs47l35->core, w->shift, freq);
110*4882a593Smuzhiyun 		if (ret)
111*4882a593Smuzhiyun 			return ret;
112*4882a593Smuzhiyun 		break;
113*4882a593Smuzhiyun 	default:
114*4882a593Smuzhiyun 		break;
115*4882a593Smuzhiyun 	}
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	return wm_adsp_early_event(w, kcontrol, event);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun #define CS47L35_NG_SRC(name, base) \
121*4882a593Smuzhiyun 	SOC_SINGLE(name " NG HPOUT1L Switch",  base,  0, 1, 0), \
122*4882a593Smuzhiyun 	SOC_SINGLE(name " NG HPOUT1R Switch",  base,  1, 1, 0), \
123*4882a593Smuzhiyun 	SOC_SINGLE(name " NG SPKOUT Switch",  base,  6, 1, 0), \
124*4882a593Smuzhiyun 	SOC_SINGLE(name " NG SPKDAT1L Switch", base,  8, 1, 0), \
125*4882a593Smuzhiyun 	SOC_SINGLE(name " NG SPKDAT1R Switch", base,  9, 1, 0)
126*4882a593Smuzhiyun 
cs47l35_hp_post_enable(struct snd_soc_dapm_widget * w)127*4882a593Smuzhiyun static void cs47l35_hp_post_enable(struct snd_soc_dapm_widget *w)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	struct snd_soc_component *component =
130*4882a593Smuzhiyun 		snd_soc_dapm_to_component(w->dapm);
131*4882a593Smuzhiyun 	unsigned int val;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	switch (w->shift) {
134*4882a593Smuzhiyun 	case MADERA_OUT1L_ENA_SHIFT:
135*4882a593Smuzhiyun 	case MADERA_OUT1R_ENA_SHIFT:
136*4882a593Smuzhiyun 		val = snd_soc_component_read(component, MADERA_OUTPUT_ENABLES_1);
137*4882a593Smuzhiyun 		val &= (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 		if (val != (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA))
140*4882a593Smuzhiyun 			break;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 		snd_soc_component_update_bits(component,
143*4882a593Smuzhiyun 					      MADERA_EDRE_HP_STEREO_CONTROL,
144*4882a593Smuzhiyun 					      0x0001, 1);
145*4882a593Smuzhiyun 		break;
146*4882a593Smuzhiyun 	default:
147*4882a593Smuzhiyun 		break;
148*4882a593Smuzhiyun 	}
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
cs47l35_hp_post_disable(struct snd_soc_dapm_widget * w)151*4882a593Smuzhiyun static void cs47l35_hp_post_disable(struct snd_soc_dapm_widget *w)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	struct snd_soc_component *component =
154*4882a593Smuzhiyun 		snd_soc_dapm_to_component(w->dapm);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	switch (w->shift) {
157*4882a593Smuzhiyun 	case MADERA_OUT1L_ENA_SHIFT:
158*4882a593Smuzhiyun 		snd_soc_component_write(component, MADERA_DCS_HP1L_CONTROL,
159*4882a593Smuzhiyun 					0x2006);
160*4882a593Smuzhiyun 		break;
161*4882a593Smuzhiyun 	case MADERA_OUT1R_ENA_SHIFT:
162*4882a593Smuzhiyun 		snd_soc_component_write(component, MADERA_DCS_HP1R_CONTROL,
163*4882a593Smuzhiyun 					0x2006);
164*4882a593Smuzhiyun 		break;
165*4882a593Smuzhiyun 	default:
166*4882a593Smuzhiyun 		return;
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	/* Only get to here for OUT1L and OUT1R */
170*4882a593Smuzhiyun 	snd_soc_component_update_bits(component,
171*4882a593Smuzhiyun 				      MADERA_EDRE_HP_STEREO_CONTROL,
172*4882a593Smuzhiyun 				      0x0001, 0);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun 
cs47l35_hp_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)175*4882a593Smuzhiyun static int cs47l35_hp_ev(struct snd_soc_dapm_widget *w,
176*4882a593Smuzhiyun 			 struct snd_kcontrol *kcontrol, int event)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	int ret;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	switch (event) {
181*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMU:
182*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMD:
183*4882a593Smuzhiyun 		return madera_hp_ev(w, kcontrol, event);
184*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMU:
185*4882a593Smuzhiyun 		ret = madera_hp_ev(w, kcontrol, event);
186*4882a593Smuzhiyun 		if (ret < 0)
187*4882a593Smuzhiyun 			return ret;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 		cs47l35_hp_post_enable(w);
190*4882a593Smuzhiyun 		return 0;
191*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:
192*4882a593Smuzhiyun 		ret = madera_hp_ev(w, kcontrol, event);
193*4882a593Smuzhiyun 		cs47l35_hp_post_disable(w);
194*4882a593Smuzhiyun 		return ret;
195*4882a593Smuzhiyun 	default:
196*4882a593Smuzhiyun 		return -EINVAL;
197*4882a593Smuzhiyun 	}
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l35_snd_controls[] = {
201*4882a593Smuzhiyun SOC_ENUM("IN1 OSR", madera_in_dmic_osr[0]),
202*4882a593Smuzhiyun SOC_ENUM("IN2 OSR", madera_in_dmic_osr[1]),
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN1L Volume", MADERA_IN1L_CONTROL,
205*4882a593Smuzhiyun 		     MADERA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
206*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN1R Volume", MADERA_IN1R_CONTROL,
207*4882a593Smuzhiyun 		     MADERA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
208*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN2L Volume", MADERA_IN2L_CONTROL,
209*4882a593Smuzhiyun 		     MADERA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
210*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN2R Volume", MADERA_IN2R_CONTROL,
211*4882a593Smuzhiyun 		     MADERA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun SOC_ENUM("IN HPF Cutoff Frequency", madera_in_hpf_cut_enum),
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun SOC_SINGLE("IN1L HPF Switch", MADERA_IN1L_CONTROL,
216*4882a593Smuzhiyun 	   MADERA_IN1L_HPF_SHIFT, 1, 0),
217*4882a593Smuzhiyun SOC_SINGLE("IN1R HPF Switch", MADERA_IN1R_CONTROL,
218*4882a593Smuzhiyun 	   MADERA_IN1R_HPF_SHIFT, 1, 0),
219*4882a593Smuzhiyun SOC_SINGLE("IN2L HPF Switch", MADERA_IN2L_CONTROL,
220*4882a593Smuzhiyun 	   MADERA_IN2L_HPF_SHIFT, 1, 0),
221*4882a593Smuzhiyun SOC_SINGLE("IN2R HPF Switch", MADERA_IN2R_CONTROL,
222*4882a593Smuzhiyun 	   MADERA_IN2R_HPF_SHIFT, 1, 0),
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1L,
225*4882a593Smuzhiyun 	       MADERA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
226*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1R,
227*4882a593Smuzhiyun 	       MADERA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
228*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2L,
229*4882a593Smuzhiyun 	       MADERA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
230*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2R,
231*4882a593Smuzhiyun 	       MADERA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun SOC_ENUM("Input Ramp Up", madera_in_vi_ramp),
234*4882a593Smuzhiyun SOC_ENUM("Input Ramp Down", madera_in_vd_ramp),
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ1", MADERA_EQ1MIX_INPUT_1_SOURCE),
237*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ2", MADERA_EQ2MIX_INPUT_1_SOURCE),
238*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ3", MADERA_EQ3MIX_INPUT_1_SOURCE),
239*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ4", MADERA_EQ4MIX_INPUT_1_SOURCE),
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ1 Coefficients", MADERA_EQ1_2),
242*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B1 Volume", MADERA_EQ1_1, MADERA_EQ1_B1_GAIN_SHIFT,
243*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
244*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B2 Volume", MADERA_EQ1_1, MADERA_EQ1_B2_GAIN_SHIFT,
245*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
246*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B3 Volume", MADERA_EQ1_1, MADERA_EQ1_B3_GAIN_SHIFT,
247*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
248*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B4 Volume", MADERA_EQ1_2, MADERA_EQ1_B4_GAIN_SHIFT,
249*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
250*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B5 Volume", MADERA_EQ1_2, MADERA_EQ1_B5_GAIN_SHIFT,
251*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ2 Coefficients", MADERA_EQ2_2),
254*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B1 Volume", MADERA_EQ2_1, MADERA_EQ2_B1_GAIN_SHIFT,
255*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
256*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B2 Volume", MADERA_EQ2_1, MADERA_EQ2_B2_GAIN_SHIFT,
257*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
258*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B3 Volume", MADERA_EQ2_1, MADERA_EQ2_B3_GAIN_SHIFT,
259*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
260*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B4 Volume", MADERA_EQ2_2, MADERA_EQ2_B4_GAIN_SHIFT,
261*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
262*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B5 Volume", MADERA_EQ2_2, MADERA_EQ2_B5_GAIN_SHIFT,
263*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ3 Coefficients", MADERA_EQ3_2),
266*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B1 Volume", MADERA_EQ3_1, MADERA_EQ3_B1_GAIN_SHIFT,
267*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
268*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B2 Volume", MADERA_EQ3_1, MADERA_EQ3_B2_GAIN_SHIFT,
269*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
270*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B3 Volume", MADERA_EQ3_1, MADERA_EQ3_B3_GAIN_SHIFT,
271*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
272*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B4 Volume", MADERA_EQ3_2, MADERA_EQ3_B4_GAIN_SHIFT,
273*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
274*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B5 Volume", MADERA_EQ3_2, MADERA_EQ3_B5_GAIN_SHIFT,
275*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ4 Coefficients", MADERA_EQ4_2),
278*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B1 Volume", MADERA_EQ4_1, MADERA_EQ4_B1_GAIN_SHIFT,
279*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
280*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B2 Volume", MADERA_EQ4_1, MADERA_EQ4_B2_GAIN_SHIFT,
281*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
282*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B3 Volume", MADERA_EQ4_1, MADERA_EQ4_B3_GAIN_SHIFT,
283*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
284*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B4 Volume", MADERA_EQ4_2, MADERA_EQ4_B4_GAIN_SHIFT,
285*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
286*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B5 Volume", MADERA_EQ4_2, MADERA_EQ4_B5_GAIN_SHIFT,
287*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC1L", MADERA_DRC1LMIX_INPUT_1_SOURCE),
290*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC1R", MADERA_DRC1RMIX_INPUT_1_SOURCE),
291*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC2L", MADERA_DRC2LMIX_INPUT_1_SOURCE),
292*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC2R", MADERA_DRC2RMIX_INPUT_1_SOURCE),
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun SND_SOC_BYTES_MASK("DRC1", MADERA_DRC1_CTRL1, 5,
295*4882a593Smuzhiyun 		   MADERA_DRC1R_ENA | MADERA_DRC1L_ENA),
296*4882a593Smuzhiyun SND_SOC_BYTES_MASK("DRC2", MADERA_DRC2_CTRL1, 5,
297*4882a593Smuzhiyun 		   MADERA_DRC2R_ENA | MADERA_DRC2L_ENA),
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF1", MADERA_HPLP1MIX_INPUT_1_SOURCE),
300*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF2", MADERA_HPLP2MIX_INPUT_1_SOURCE),
301*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF3", MADERA_HPLP3MIX_INPUT_1_SOURCE),
302*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF4", MADERA_HPLP4MIX_INPUT_1_SOURCE),
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF1 Coefficients", MADERA_HPLPF1_2),
305*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF2 Coefficients", MADERA_HPLPF2_2),
306*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF3 Coefficients", MADERA_HPLPF3_2),
307*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF4 Coefficients", MADERA_HPLPF4_2),
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun SOC_ENUM("LHPF1 Mode", madera_lhpf1_mode),
310*4882a593Smuzhiyun SOC_ENUM("LHPF2 Mode", madera_lhpf2_mode),
311*4882a593Smuzhiyun SOC_ENUM("LHPF3 Mode", madera_lhpf3_mode),
312*4882a593Smuzhiyun SOC_ENUM("LHPF4 Mode", madera_lhpf4_mode),
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC1 FSL", madera_isrc_fsl[0]),
315*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC2 FSL", madera_isrc_fsl[1]),
316*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC1 FSH", madera_isrc_fsh[0]),
317*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC2 FSH", madera_isrc_fsh[1]),
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
320*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP2", 2),
321*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP3", 3),
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP1L", MADERA_DSP1LMIX_INPUT_1_SOURCE),
324*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP1R", MADERA_DSP1RMIX_INPUT_1_SOURCE),
325*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP2L", MADERA_DSP2LMIX_INPUT_1_SOURCE),
326*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP2R", MADERA_DSP2RMIX_INPUT_1_SOURCE),
327*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP3L", MADERA_DSP3LMIX_INPUT_1_SOURCE),
328*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP3R", MADERA_DSP3RMIX_INPUT_1_SOURCE),
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Generator Volume", MADERA_COMFORT_NOISE_GENERATOR,
331*4882a593Smuzhiyun 	       MADERA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, madera_noise_tlv),
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT1L", MADERA_OUT1LMIX_INPUT_1_SOURCE),
334*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT1R", MADERA_OUT1RMIX_INPUT_1_SOURCE),
335*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKOUT", MADERA_OUT4LMIX_INPUT_1_SOURCE),
336*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT1L", MADERA_OUT5LMIX_INPUT_1_SOURCE),
337*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT1R", MADERA_OUT5RMIX_INPUT_1_SOURCE),
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun SOC_SINGLE("HPOUT1 SC Protect Switch", MADERA_HP1_SHORT_CIRCUIT_CTRL,
340*4882a593Smuzhiyun 	   MADERA_HP1_SC_ENA_SHIFT, 1, 0),
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun SOC_SINGLE("SPKDAT1 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_5L,
343*4882a593Smuzhiyun 	   MADERA_OUT5_OSR_SHIFT, 1, 0),
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_1L,
346*4882a593Smuzhiyun 	     MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_MUTE_SHIFT, 1, 1),
347*4882a593Smuzhiyun SOC_SINGLE("Speaker Digital Switch", MADERA_DAC_DIGITAL_VOLUME_4L,
348*4882a593Smuzhiyun 	   MADERA_OUT4L_MUTE_SHIFT, 1, 1),
349*4882a593Smuzhiyun SOC_DOUBLE_R("SPKDAT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_5L,
350*4882a593Smuzhiyun 	     MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_MUTE_SHIFT, 1, 1),
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_1L,
353*4882a593Smuzhiyun 		 MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_VOL_SHIFT,
354*4882a593Smuzhiyun 		 0xbf, 0, madera_digital_tlv),
355*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker Digital Volume", MADERA_DAC_DIGITAL_VOLUME_4L,
356*4882a593Smuzhiyun 	       MADERA_OUT4L_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
357*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_5L,
358*4882a593Smuzhiyun 		 MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_VOL_SHIFT,
359*4882a593Smuzhiyun 		 0xbf, 0, madera_digital_tlv),
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun SOC_DOUBLE("SPKDAT1 Switch", MADERA_PDM_SPK1_CTRL_1, MADERA_SPK1L_MUTE_SHIFT,
362*4882a593Smuzhiyun 	   MADERA_SPK1R_MUTE_SHIFT, 1, 1),
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun SOC_ENUM("Output Ramp Up", madera_out_vi_ramp),
365*4882a593Smuzhiyun SOC_ENUM("Output Ramp Down", madera_out_vd_ramp),
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun SOC_SINGLE("Noise Gate Switch", MADERA_NOISE_GATE_CONTROL,
368*4882a593Smuzhiyun 	   MADERA_NGATE_ENA_SHIFT, 1, 0),
369*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Gate Threshold Volume", MADERA_NOISE_GATE_CONTROL,
370*4882a593Smuzhiyun 	       MADERA_NGATE_THR_SHIFT, 7, 1, madera_ng_tlv),
371*4882a593Smuzhiyun SOC_ENUM("Noise Gate Hold", madera_ng_hold),
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun CS47L35_NG_SRC("HPOUT1L", MADERA_NOISE_GATE_SELECT_1L),
374*4882a593Smuzhiyun CS47L35_NG_SRC("HPOUT1R", MADERA_NOISE_GATE_SELECT_1R),
375*4882a593Smuzhiyun CS47L35_NG_SRC("SPKOUT", MADERA_NOISE_GATE_SELECT_4L),
376*4882a593Smuzhiyun CS47L35_NG_SRC("SPKDAT1L", MADERA_NOISE_GATE_SELECT_5L),
377*4882a593Smuzhiyun CS47L35_NG_SRC("SPKDAT1R", MADERA_NOISE_GATE_SELECT_5R),
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX1", MADERA_AIF1TX1MIX_INPUT_1_SOURCE),
380*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX2", MADERA_AIF1TX2MIX_INPUT_1_SOURCE),
381*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX3", MADERA_AIF1TX3MIX_INPUT_1_SOURCE),
382*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX4", MADERA_AIF1TX4MIX_INPUT_1_SOURCE),
383*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX5", MADERA_AIF1TX5MIX_INPUT_1_SOURCE),
384*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX6", MADERA_AIF1TX6MIX_INPUT_1_SOURCE),
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX1", MADERA_AIF2TX1MIX_INPUT_1_SOURCE),
387*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX2", MADERA_AIF2TX2MIX_INPUT_1_SOURCE),
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX1", MADERA_AIF3TX1MIX_INPUT_1_SOURCE),
390*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX2", MADERA_AIF3TX2MIX_INPUT_1_SOURCE),
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX1", MADERA_SLIMTX1MIX_INPUT_1_SOURCE),
393*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX2", MADERA_SLIMTX2MIX_INPUT_1_SOURCE),
394*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX3", MADERA_SLIMTX3MIX_INPUT_1_SOURCE),
395*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX4", MADERA_SLIMTX4MIX_INPUT_1_SOURCE),
396*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX5", MADERA_SLIMTX5MIX_INPUT_1_SOURCE),
397*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SLIMTX6", MADERA_SLIMTX6MIX_INPUT_1_SOURCE),
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun MADERA_GAINMUX_CONTROLS("SPDIF1TX1", MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE),
400*4882a593Smuzhiyun MADERA_GAINMUX_CONTROLS("SPDIF1TX2", MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE),
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP1", 0),
403*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP2", 1),
404*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP3", 2),
405*4882a593Smuzhiyun };
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ1, MADERA_EQ1MIX_INPUT_1_SOURCE);
408*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ2, MADERA_EQ2MIX_INPUT_1_SOURCE);
409*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ3, MADERA_EQ3MIX_INPUT_1_SOURCE);
410*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ4, MADERA_EQ4MIX_INPUT_1_SOURCE);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC1L, MADERA_DRC1LMIX_INPUT_1_SOURCE);
413*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC1R, MADERA_DRC1RMIX_INPUT_1_SOURCE);
414*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC2L, MADERA_DRC2LMIX_INPUT_1_SOURCE);
415*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC2R, MADERA_DRC2RMIX_INPUT_1_SOURCE);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF1, MADERA_HPLP1MIX_INPUT_1_SOURCE);
418*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF2, MADERA_HPLP2MIX_INPUT_1_SOURCE);
419*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF3, MADERA_HPLP3MIX_INPUT_1_SOURCE);
420*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF4, MADERA_HPLP4MIX_INPUT_1_SOURCE);
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP1L, MADERA_DSP1LMIX_INPUT_1_SOURCE);
423*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP1R, MADERA_DSP1RMIX_INPUT_1_SOURCE);
424*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP1, MADERA_DSP1AUX1MIX_INPUT_1_SOURCE);
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP2L, MADERA_DSP2LMIX_INPUT_1_SOURCE);
427*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP2R, MADERA_DSP2RMIX_INPUT_1_SOURCE);
428*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP2, MADERA_DSP2AUX1MIX_INPUT_1_SOURCE);
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP3L, MADERA_DSP3LMIX_INPUT_1_SOURCE);
431*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP3R, MADERA_DSP3RMIX_INPUT_1_SOURCE);
432*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP3, MADERA_DSP3AUX1MIX_INPUT_1_SOURCE);
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun MADERA_MIXER_ENUMS(PWM1, MADERA_PWM1MIX_INPUT_1_SOURCE);
435*4882a593Smuzhiyun MADERA_MIXER_ENUMS(PWM2, MADERA_PWM2MIX_INPUT_1_SOURCE);
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT1L, MADERA_OUT1LMIX_INPUT_1_SOURCE);
438*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT1R, MADERA_OUT1RMIX_INPUT_1_SOURCE);
439*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKOUT, MADERA_OUT4LMIX_INPUT_1_SOURCE);
440*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT1L, MADERA_OUT5LMIX_INPUT_1_SOURCE);
441*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT1R, MADERA_OUT5RMIX_INPUT_1_SOURCE);
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX1, MADERA_AIF1TX1MIX_INPUT_1_SOURCE);
444*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX2, MADERA_AIF1TX2MIX_INPUT_1_SOURCE);
445*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX3, MADERA_AIF1TX3MIX_INPUT_1_SOURCE);
446*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX4, MADERA_AIF1TX4MIX_INPUT_1_SOURCE);
447*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX5, MADERA_AIF1TX5MIX_INPUT_1_SOURCE);
448*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX6, MADERA_AIF1TX6MIX_INPUT_1_SOURCE);
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX1, MADERA_AIF2TX1MIX_INPUT_1_SOURCE);
451*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX2, MADERA_AIF2TX2MIX_INPUT_1_SOURCE);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX1, MADERA_AIF3TX1MIX_INPUT_1_SOURCE);
454*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX2, MADERA_AIF3TX2MIX_INPUT_1_SOURCE);
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX1, MADERA_SLIMTX1MIX_INPUT_1_SOURCE);
457*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX2, MADERA_SLIMTX2MIX_INPUT_1_SOURCE);
458*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX3, MADERA_SLIMTX3MIX_INPUT_1_SOURCE);
459*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX4, MADERA_SLIMTX4MIX_INPUT_1_SOURCE);
460*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX5, MADERA_SLIMTX5MIX_INPUT_1_SOURCE);
461*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SLIMTX6, MADERA_SLIMTX6MIX_INPUT_1_SOURCE);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun MADERA_MUX_ENUMS(SPD1TX1, MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE);
464*4882a593Smuzhiyun MADERA_MUX_ENUMS(SPD1TX2, MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE);
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT1, MADERA_ISRC1INT1MIX_INPUT_1_SOURCE);
467*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT2, MADERA_ISRC1INT2MIX_INPUT_1_SOURCE);
468*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT3, MADERA_ISRC1INT3MIX_INPUT_1_SOURCE);
469*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT4, MADERA_ISRC1INT4MIX_INPUT_1_SOURCE);
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC1, MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE);
472*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC2, MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE);
473*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC3, MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE);
474*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC4, MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE);
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT1, MADERA_ISRC2INT1MIX_INPUT_1_SOURCE);
477*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT2, MADERA_ISRC2INT2MIX_INPUT_1_SOURCE);
478*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT3, MADERA_ISRC2INT3MIX_INPUT_1_SOURCE);
479*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT4, MADERA_ISRC2INT4MIX_INPUT_1_SOURCE);
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC1, MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE);
482*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC2, MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE);
483*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC3, MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE);
484*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC4, MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE);
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun static const char * const cs47l35_aec_loopback_texts[] = {
487*4882a593Smuzhiyun 	"HPOUT1L", "HPOUT1R", "SPKOUT", "SPKDAT1L", "SPKDAT1R",
488*4882a593Smuzhiyun };
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun static const unsigned int cs47l35_aec_loopback_values[] = {
491*4882a593Smuzhiyun 	0, 1, 6, 8, 9,
492*4882a593Smuzhiyun };
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun static const struct soc_enum cs47l35_aec1_loopback =
495*4882a593Smuzhiyun 	SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_1,
496*4882a593Smuzhiyun 			      MADERA_AEC1_LOOPBACK_SRC_SHIFT, 0xf,
497*4882a593Smuzhiyun 			      ARRAY_SIZE(cs47l35_aec_loopback_texts),
498*4882a593Smuzhiyun 			      cs47l35_aec_loopback_texts,
499*4882a593Smuzhiyun 			      cs47l35_aec_loopback_values);
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun static const struct soc_enum cs47l35_aec2_loopback =
502*4882a593Smuzhiyun 	SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_2,
503*4882a593Smuzhiyun 			      MADERA_AEC2_LOOPBACK_SRC_SHIFT, 0xf,
504*4882a593Smuzhiyun 			      ARRAY_SIZE(cs47l35_aec_loopback_texts),
505*4882a593Smuzhiyun 			      cs47l35_aec_loopback_texts,
506*4882a593Smuzhiyun 			      cs47l35_aec_loopback_values);
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l35_aec_loopback_mux[] = {
509*4882a593Smuzhiyun 	SOC_DAPM_ENUM("AEC1 Loopback", cs47l35_aec1_loopback),
510*4882a593Smuzhiyun 	SOC_DAPM_ENUM("AEC2 Loopback", cs47l35_aec2_loopback),
511*4882a593Smuzhiyun };
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun static const struct snd_soc_dapm_widget cs47l35_dapm_widgets[] = {
514*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SYSCLK", MADERA_SYSTEM_CLOCK_1, MADERA_SYSCLK_ENA_SHIFT,
515*4882a593Smuzhiyun 		    0, madera_sysclk_ev,
516*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
517*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
518*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OPCLK", MADERA_OUTPUT_SYSTEM_CLOCK,
519*4882a593Smuzhiyun 		    MADERA_OPCLK_ENA_SHIFT, 0, NULL, 0),
520*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSPCLK", MADERA_DSP_CLOCK_1, MADERA_DSP_CLK_ENA_SHIFT,
521*4882a593Smuzhiyun 		    0, madera_clk_ev,
522*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
525*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD1", 20, 0),
526*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD2", 20, 0),
527*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
528*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDD", 0, 0),
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1", MADERA_MIC_BIAS_CTRL_1,
531*4882a593Smuzhiyun 		    MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
532*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2", MADERA_MIC_BIAS_CTRL_2,
533*4882a593Smuzhiyun 		    MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1A", MADERA_MIC_BIAS_CTRL_5,
536*4882a593Smuzhiyun 		    MADERA_MICB1A_ENA_SHIFT, 0, NULL, 0),
537*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1B", MADERA_MIC_BIAS_CTRL_5,
538*4882a593Smuzhiyun 		    MADERA_MICB1B_ENA_SHIFT, 0, NULL, 0),
539*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2A", MADERA_MIC_BIAS_CTRL_6,
540*4882a593Smuzhiyun 		    MADERA_MICB2A_ENA_SHIFT, 0, NULL, 0),
541*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2B", MADERA_MIC_BIAS_CTRL_6,
542*4882a593Smuzhiyun 		    MADERA_MICB2B_ENA_SHIFT, 0, NULL, 0),
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("FXCLK", SND_SOC_NOPM,
545*4882a593Smuzhiyun 		    MADERA_DOM_GRP_FX, 0,
546*4882a593Smuzhiyun 		    madera_domain_clk_ev,
547*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
548*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC1CLK", SND_SOC_NOPM,
549*4882a593Smuzhiyun 		    MADERA_DOM_GRP_ISRC1, 0,
550*4882a593Smuzhiyun 		    madera_domain_clk_ev,
551*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
552*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC2CLK", SND_SOC_NOPM,
553*4882a593Smuzhiyun 		    MADERA_DOM_GRP_ISRC2, 0,
554*4882a593Smuzhiyun 		    madera_domain_clk_ev,
555*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
556*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OUTCLK", SND_SOC_NOPM,
557*4882a593Smuzhiyun 		    MADERA_DOM_GRP_OUT, 0,
558*4882a593Smuzhiyun 		    madera_domain_clk_ev,
559*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
560*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SPDCLK", SND_SOC_NOPM,
561*4882a593Smuzhiyun 		    MADERA_DOM_GRP_SPD, 0,
562*4882a593Smuzhiyun 		    madera_domain_clk_ev,
563*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
564*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM,
565*4882a593Smuzhiyun 		    MADERA_DOM_GRP_DSP1, 0,
566*4882a593Smuzhiyun 		    madera_domain_clk_ev,
567*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
568*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM,
569*4882a593Smuzhiyun 		    MADERA_DOM_GRP_DSP2, 0,
570*4882a593Smuzhiyun 		    madera_domain_clk_ev,
571*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
572*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP3CLK", SND_SOC_NOPM,
573*4882a593Smuzhiyun 		    MADERA_DOM_GRP_DSP3, 0,
574*4882a593Smuzhiyun 		    madera_domain_clk_ev,
575*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
576*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF1TXCLK", SND_SOC_NOPM,
577*4882a593Smuzhiyun 		    MADERA_DOM_GRP_AIF1, 0,
578*4882a593Smuzhiyun 		    madera_domain_clk_ev,
579*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
580*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF2TXCLK", SND_SOC_NOPM,
581*4882a593Smuzhiyun 		    MADERA_DOM_GRP_AIF2, 0,
582*4882a593Smuzhiyun 		    madera_domain_clk_ev,
583*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
584*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF3TXCLK", SND_SOC_NOPM,
585*4882a593Smuzhiyun 		    MADERA_DOM_GRP_AIF3, 0,
586*4882a593Smuzhiyun 		    madera_domain_clk_ev,
587*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
588*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SLIMBUSCLK", SND_SOC_NOPM,
589*4882a593Smuzhiyun 		    MADERA_DOM_GRP_SLIMBUS, 0,
590*4882a593Smuzhiyun 		    madera_domain_clk_ev,
591*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
592*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("PWMCLK", SND_SOC_NOPM,
593*4882a593Smuzhiyun 		    MADERA_DOM_GRP_PWM, 0,
594*4882a593Smuzhiyun 		    madera_domain_clk_ev,
595*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("TONE"),
598*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("NOISE"),
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ALN"),
601*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ALP"),
602*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BLN"),
603*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BLP"),
604*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ARN"),
605*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ARP"),
606*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BRN"),
607*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BRP"),
608*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2LN"),
609*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2LP"),
610*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2RN"),
611*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2RP"),
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[0]),
614*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[1]),
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
617*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
620*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
621*4882a593Smuzhiyun 
622*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
623*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DSP Trigger Out"),
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun SND_SOC_DAPM_DEMUX("HPOUT1 Demux", SND_SOC_NOPM, 0, 0, &cs47l35_outdemux),
628*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT1 Mono Mux", SND_SOC_NOPM, 0, 0, &cs47l35_outdemux),
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun SND_SOC_DAPM_PGA("PWM1 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM1_ENA_SHIFT,
631*4882a593Smuzhiyun 		 0, NULL, 0),
632*4882a593Smuzhiyun SND_SOC_DAPM_PGA("PWM2 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM2_ENA_SHIFT,
633*4882a593Smuzhiyun 		 0, NULL, 0),
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
636*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX1_ENA_SHIFT, 0),
637*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
638*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX2_ENA_SHIFT, 0),
639*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
640*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX3_ENA_SHIFT, 0),
641*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
642*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX4_ENA_SHIFT, 0),
643*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
644*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX5_ENA_SHIFT, 0),
645*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
646*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX6_ENA_SHIFT, 0),
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
649*4882a593Smuzhiyun 		     MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX1_ENA_SHIFT, 0),
650*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
651*4882a593Smuzhiyun 		     MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX2_ENA_SHIFT, 0),
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
654*4882a593Smuzhiyun 		     MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX1_ENA_SHIFT, 0),
655*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
656*4882a593Smuzhiyun 		     MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX2_ENA_SHIFT, 0),
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
659*4882a593Smuzhiyun 		     MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
660*4882a593Smuzhiyun 		     MADERA_SLIMTX1_ENA_SHIFT, 0),
661*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
662*4882a593Smuzhiyun 		     MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
663*4882a593Smuzhiyun 		     MADERA_SLIMTX2_ENA_SHIFT, 0),
664*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
665*4882a593Smuzhiyun 		     MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
666*4882a593Smuzhiyun 		     MADERA_SLIMTX3_ENA_SHIFT, 0),
667*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
668*4882a593Smuzhiyun 		     MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
669*4882a593Smuzhiyun 		     MADERA_SLIMTX4_ENA_SHIFT, 0),
670*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
671*4882a593Smuzhiyun 		     MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
672*4882a593Smuzhiyun 		     MADERA_SLIMTX5_ENA_SHIFT, 0),
673*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
674*4882a593Smuzhiyun 		     MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
675*4882a593Smuzhiyun 		     MADERA_SLIMTX6_ENA_SHIFT, 0),
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
678*4882a593Smuzhiyun 		   MADERA_OUT1L_ENA_SHIFT, 0, NULL, 0, cs47l35_hp_ev,
679*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
680*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
681*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
682*4882a593Smuzhiyun 		   MADERA_OUT1R_ENA_SHIFT, 0, NULL, 0, cs47l35_hp_ev,
683*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
684*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
685*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
686*4882a593Smuzhiyun 		   MADERA_OUT4L_ENA_SHIFT, 0, NULL, 0, madera_spk_ev,
687*4882a593Smuzhiyun 		   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
688*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT5L", MADERA_OUTPUT_ENABLES_1,
689*4882a593Smuzhiyun 		   MADERA_OUT5L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
690*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
691*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT5R", MADERA_OUTPUT_ENABLES_1,
692*4882a593Smuzhiyun 		   MADERA_OUT5R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
693*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
694*4882a593Smuzhiyun 
695*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPD1TX1", MADERA_SPD1_TX_CONTROL,
696*4882a593Smuzhiyun 		 MADERA_SPD1_VAL1_SHIFT, 0, NULL, 0),
697*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPD1TX2", MADERA_SPD1_TX_CONTROL,
698*4882a593Smuzhiyun 		 MADERA_SPD1_VAL2_SHIFT, 0, NULL, 0),
699*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("SPD1", MADERA_SPD1_TX_CONTROL,
700*4882a593Smuzhiyun 		     MADERA_SPD1_ENA_SHIFT, 0, NULL, 0),
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun /*
703*4882a593Smuzhiyun  * Input mux widgets arranged in order of sources in MADERA_MIXER_INPUT_ROUTES
704*4882a593Smuzhiyun  * to take advantage of cache lookup in DAPM
705*4882a593Smuzhiyun  */
706*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Noise Generator", MADERA_COMFORT_NOISE_GENERATOR,
707*4882a593Smuzhiyun 		 MADERA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator 1", MADERA_TONE_GENERATOR_1,
710*4882a593Smuzhiyun 		 MADERA_TONE1_ENA_SHIFT, 0, NULL, 0),
711*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator 2", MADERA_TONE_GENERATOR_1,
712*4882a593Smuzhiyun 		 MADERA_TONE2_ENA_SHIFT, 0, NULL, 0),
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("HAPTICS"),
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun SND_SOC_DAPM_MUX("AEC1 Loopback", MADERA_DAC_AEC_CONTROL_1,
717*4882a593Smuzhiyun 		 MADERA_AEC1_LOOPBACK_ENA_SHIFT, 0,
718*4882a593Smuzhiyun 		 &cs47l35_aec_loopback_mux[0]),
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun SND_SOC_DAPM_MUX("AEC2 Loopback", MADERA_DAC_AEC_CONTROL_2,
721*4882a593Smuzhiyun 		 MADERA_AEC2_LOOPBACK_ENA_SHIFT, 0,
722*4882a593Smuzhiyun 		 &cs47l35_aec_loopback_mux[1]),
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN1L", MADERA_INPUT_ENABLES, MADERA_IN1L_ENA_SHIFT,
725*4882a593Smuzhiyun 		   0, NULL, 0, madera_in_ev,
726*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
727*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
728*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN1R", MADERA_INPUT_ENABLES, MADERA_IN1R_ENA_SHIFT,
729*4882a593Smuzhiyun 		   0, NULL, 0, madera_in_ev,
730*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
731*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN2L", MADERA_INPUT_ENABLES, MADERA_IN2L_ENA_SHIFT,
734*4882a593Smuzhiyun 		   0, NULL, 0, madera_in_ev,
735*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
736*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
737*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN2R", MADERA_INPUT_ENABLES, MADERA_IN2R_ENA_SHIFT,
738*4882a593Smuzhiyun 		   0, NULL, 0, madera_in_ev,
739*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
740*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
743*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX1_ENA_SHIFT, 0),
744*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
745*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX2_ENA_SHIFT, 0),
746*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
747*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX3_ENA_SHIFT, 0),
748*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
749*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX4_ENA_SHIFT, 0),
750*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
751*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX5_ENA_SHIFT, 0),
752*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
753*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX6_ENA_SHIFT, 0),
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
756*4882a593Smuzhiyun 		    MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX1_ENA_SHIFT, 0),
757*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
758*4882a593Smuzhiyun 		    MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX2_ENA_SHIFT, 0),
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
761*4882a593Smuzhiyun 		    MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX1_ENA_SHIFT, 0),
762*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
763*4882a593Smuzhiyun 		    MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX2_ENA_SHIFT, 0),
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0,
766*4882a593Smuzhiyun 		    MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
767*4882a593Smuzhiyun 		    MADERA_SLIMRX1_ENA_SHIFT, 0),
768*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1,
769*4882a593Smuzhiyun 		    MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
770*4882a593Smuzhiyun 		    MADERA_SLIMRX2_ENA_SHIFT, 0),
771*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2,
772*4882a593Smuzhiyun 		    MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
773*4882a593Smuzhiyun 		    MADERA_SLIMRX3_ENA_SHIFT, 0),
774*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3,
775*4882a593Smuzhiyun 		    MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
776*4882a593Smuzhiyun 		    MADERA_SLIMRX4_ENA_SHIFT, 0),
777*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4,
778*4882a593Smuzhiyun 		    MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
779*4882a593Smuzhiyun 		    MADERA_SLIMRX5_ENA_SHIFT, 0),
780*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5,
781*4882a593Smuzhiyun 		    MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
782*4882a593Smuzhiyun 		    MADERA_SLIMRX6_ENA_SHIFT, 0),
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ1", MADERA_EQ1_1, MADERA_EQ1_ENA_SHIFT, 0, NULL, 0),
785*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ2", MADERA_EQ2_1, MADERA_EQ2_ENA_SHIFT, 0, NULL, 0),
786*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ3", MADERA_EQ3_1, MADERA_EQ3_ENA_SHIFT, 0, NULL, 0),
787*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ4", MADERA_EQ4_1, MADERA_EQ4_ENA_SHIFT, 0, NULL, 0),
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC1L", MADERA_DRC1_CTRL1, MADERA_DRC1L_ENA_SHIFT, 0,
790*4882a593Smuzhiyun 		 NULL, 0),
791*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC1R", MADERA_DRC1_CTRL1, MADERA_DRC1R_ENA_SHIFT, 0,
792*4882a593Smuzhiyun 		 NULL, 0),
793*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC2L", MADERA_DRC2_CTRL1, MADERA_DRC2L_ENA_SHIFT, 0,
794*4882a593Smuzhiyun 		 NULL, 0),
795*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC2R", MADERA_DRC2_CTRL1, MADERA_DRC2R_ENA_SHIFT, 0,
796*4882a593Smuzhiyun 		 NULL, 0),
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF1", MADERA_HPLPF1_1, MADERA_LHPF1_ENA_SHIFT, 0,
799*4882a593Smuzhiyun 		 NULL, 0),
800*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF2", MADERA_HPLPF2_1, MADERA_LHPF2_ENA_SHIFT, 0,
801*4882a593Smuzhiyun 		 NULL, 0),
802*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF3", MADERA_HPLPF3_1, MADERA_LHPF3_ENA_SHIFT, 0,
803*4882a593Smuzhiyun 		 NULL, 0),
804*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF4", MADERA_HPLPF4_1, MADERA_LHPF4_ENA_SHIFT, 0,
805*4882a593Smuzhiyun 		 NULL, 0),
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC1", MADERA_ISRC_1_CTRL_3,
808*4882a593Smuzhiyun 		 MADERA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
809*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC2", MADERA_ISRC_1_CTRL_3,
810*4882a593Smuzhiyun 		 MADERA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
811*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC3", MADERA_ISRC_1_CTRL_3,
812*4882a593Smuzhiyun 		 MADERA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
813*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC4", MADERA_ISRC_1_CTRL_3,
814*4882a593Smuzhiyun 		 MADERA_ISRC1_DEC4_ENA_SHIFT, 0, NULL, 0),
815*4882a593Smuzhiyun 
816*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT1", MADERA_ISRC_1_CTRL_3,
817*4882a593Smuzhiyun 		 MADERA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
818*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT2", MADERA_ISRC_1_CTRL_3,
819*4882a593Smuzhiyun 		 MADERA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
820*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT3", MADERA_ISRC_1_CTRL_3,
821*4882a593Smuzhiyun 		 MADERA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
822*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT4", MADERA_ISRC_1_CTRL_3,
823*4882a593Smuzhiyun 		 MADERA_ISRC1_INT4_ENA_SHIFT, 0, NULL, 0),
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC1", MADERA_ISRC_2_CTRL_3,
826*4882a593Smuzhiyun 		 MADERA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
827*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC2", MADERA_ISRC_2_CTRL_3,
828*4882a593Smuzhiyun 		 MADERA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
829*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC3", MADERA_ISRC_2_CTRL_3,
830*4882a593Smuzhiyun 		 MADERA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0),
831*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC4", MADERA_ISRC_2_CTRL_3,
832*4882a593Smuzhiyun 		 MADERA_ISRC2_DEC4_ENA_SHIFT, 0, NULL, 0),
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT1", MADERA_ISRC_2_CTRL_3,
835*4882a593Smuzhiyun 		 MADERA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
836*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT2", MADERA_ISRC_2_CTRL_3,
837*4882a593Smuzhiyun 		 MADERA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
838*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT3", MADERA_ISRC_2_CTRL_3,
839*4882a593Smuzhiyun 		 MADERA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0),
840*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT4", MADERA_ISRC_2_CTRL_3,
841*4882a593Smuzhiyun 		 MADERA_ISRC2_INT4_ENA_SHIFT, 0, NULL, 0),
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun WM_ADSP2("DSP1", 0, cs47l35_adsp_power_ev),
844*4882a593Smuzhiyun WM_ADSP2("DSP2", 1, cs47l35_adsp_power_ev),
845*4882a593Smuzhiyun WM_ADSP2("DSP3", 2, cs47l35_adsp_power_ev),
846*4882a593Smuzhiyun 
847*4882a593Smuzhiyun /* End of ordered input mux widgets */
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ1, "EQ1"),
850*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ2, "EQ2"),
851*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ3, "EQ3"),
852*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ4, "EQ4"),
853*4882a593Smuzhiyun 
854*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC1L, "DRC1L"),
855*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC1R, "DRC1R"),
856*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC2L, "DRC2L"),
857*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC2R, "DRC2R"),
858*4882a593Smuzhiyun 
859*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0,
860*4882a593Smuzhiyun 		    &madera_drc_activity_output_mux[0]),
861*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0,
862*4882a593Smuzhiyun 		    &madera_drc_activity_output_mux[1]),
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF1, "LHPF1"),
865*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF2, "LHPF2"),
866*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF3, "LHPF3"),
867*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF4, "LHPF4"),
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(PWM1, "PWM1"),
870*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(PWM2, "PWM2"),
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
873*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
874*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKOUT, "SPKOUT"),
875*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
876*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
879*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
880*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
881*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
882*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
883*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
884*4882a593Smuzhiyun 
885*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
886*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
889*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
890*4882a593Smuzhiyun 
891*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
892*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
893*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
894*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
895*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
896*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
897*4882a593Smuzhiyun 
898*4882a593Smuzhiyun MADERA_MUX_WIDGETS(SPD1TX1, "SPDIF1TX1"),
899*4882a593Smuzhiyun MADERA_MUX_WIDGETS(SPD1TX2, "SPDIF1TX2"),
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP1, "DSP1"),
902*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP2, "DSP2"),
903*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP3, "DSP3"),
904*4882a593Smuzhiyun 
905*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0,
906*4882a593Smuzhiyun 		    &madera_dsp_trigger_output_mux[0]),
907*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP2 Trigger Output", SND_SOC_NOPM, 0, 0,
908*4882a593Smuzhiyun 		    &madera_dsp_trigger_output_mux[1]),
909*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP3 Trigger Output", SND_SOC_NOPM, 0, 0,
910*4882a593Smuzhiyun 		    &madera_dsp_trigger_output_mux[2]),
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
913*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
914*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
915*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
916*4882a593Smuzhiyun 
917*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
918*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
919*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
920*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
923*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
924*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"),
925*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"),
926*4882a593Smuzhiyun 
927*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
928*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
929*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"),
930*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"),
931*4882a593Smuzhiyun 
932*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUTL"),
933*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUTR"),
934*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("EPOUTP"),
935*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("EPOUTN"),
936*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTN"),
937*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTP"),
938*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
939*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
940*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPDIF1"),
941*4882a593Smuzhiyun 
942*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MICSUPP"),
943*4882a593Smuzhiyun };
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun #define MADERA_MIXER_INPUT_ROUTES(name)	\
946*4882a593Smuzhiyun 	{ name, "Noise Generator", "Noise Generator" }, \
947*4882a593Smuzhiyun 	{ name, "Tone Generator 1", "Tone Generator 1" }, \
948*4882a593Smuzhiyun 	{ name, "Tone Generator 2", "Tone Generator 2" }, \
949*4882a593Smuzhiyun 	{ name, "Haptics", "HAPTICS" }, \
950*4882a593Smuzhiyun 	{ name, "AEC1", "AEC1 Loopback" }, \
951*4882a593Smuzhiyun 	{ name, "AEC2", "AEC2 Loopback" }, \
952*4882a593Smuzhiyun 	{ name, "IN1L", "IN1L" }, \
953*4882a593Smuzhiyun 	{ name, "IN1R", "IN1R" }, \
954*4882a593Smuzhiyun 	{ name, "IN2L", "IN2L" }, \
955*4882a593Smuzhiyun 	{ name, "IN2R", "IN2R" }, \
956*4882a593Smuzhiyun 	{ name, "AIF1RX1", "AIF1RX1" }, \
957*4882a593Smuzhiyun 	{ name, "AIF1RX2", "AIF1RX2" }, \
958*4882a593Smuzhiyun 	{ name, "AIF1RX3", "AIF1RX3" }, \
959*4882a593Smuzhiyun 	{ name, "AIF1RX4", "AIF1RX4" }, \
960*4882a593Smuzhiyun 	{ name, "AIF1RX5", "AIF1RX5" }, \
961*4882a593Smuzhiyun 	{ name, "AIF1RX6", "AIF1RX6" }, \
962*4882a593Smuzhiyun 	{ name, "AIF2RX1", "AIF2RX1" }, \
963*4882a593Smuzhiyun 	{ name, "AIF2RX2", "AIF2RX2" }, \
964*4882a593Smuzhiyun 	{ name, "AIF3RX1", "AIF3RX1" }, \
965*4882a593Smuzhiyun 	{ name, "AIF3RX2", "AIF3RX2" }, \
966*4882a593Smuzhiyun 	{ name, "SLIMRX1", "SLIMRX1" }, \
967*4882a593Smuzhiyun 	{ name, "SLIMRX2", "SLIMRX2" }, \
968*4882a593Smuzhiyun 	{ name, "SLIMRX3", "SLIMRX3" }, \
969*4882a593Smuzhiyun 	{ name, "SLIMRX4", "SLIMRX4" }, \
970*4882a593Smuzhiyun 	{ name, "SLIMRX5", "SLIMRX5" }, \
971*4882a593Smuzhiyun 	{ name, "SLIMRX6", "SLIMRX6" }, \
972*4882a593Smuzhiyun 	{ name, "EQ1", "EQ1" }, \
973*4882a593Smuzhiyun 	{ name, "EQ2", "EQ2" }, \
974*4882a593Smuzhiyun 	{ name, "EQ3", "EQ3" }, \
975*4882a593Smuzhiyun 	{ name, "EQ4", "EQ4" }, \
976*4882a593Smuzhiyun 	{ name, "DRC1L", "DRC1L" }, \
977*4882a593Smuzhiyun 	{ name, "DRC1R", "DRC1R" }, \
978*4882a593Smuzhiyun 	{ name, "DRC2L", "DRC2L" }, \
979*4882a593Smuzhiyun 	{ name, "DRC2R", "DRC2R" }, \
980*4882a593Smuzhiyun 	{ name, "LHPF1", "LHPF1" }, \
981*4882a593Smuzhiyun 	{ name, "LHPF2", "LHPF2" }, \
982*4882a593Smuzhiyun 	{ name, "LHPF3", "LHPF3" }, \
983*4882a593Smuzhiyun 	{ name, "LHPF4", "LHPF4" }, \
984*4882a593Smuzhiyun 	{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
985*4882a593Smuzhiyun 	{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
986*4882a593Smuzhiyun 	{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
987*4882a593Smuzhiyun 	{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
988*4882a593Smuzhiyun 	{ name, "ISRC1INT1", "ISRC1INT1" }, \
989*4882a593Smuzhiyun 	{ name, "ISRC1INT2", "ISRC1INT2" }, \
990*4882a593Smuzhiyun 	{ name, "ISRC1INT3", "ISRC1INT3" }, \
991*4882a593Smuzhiyun 	{ name, "ISRC1INT4", "ISRC1INT4" }, \
992*4882a593Smuzhiyun 	{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
993*4882a593Smuzhiyun 	{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
994*4882a593Smuzhiyun 	{ name, "ISRC2DEC3", "ISRC2DEC3" }, \
995*4882a593Smuzhiyun 	{ name, "ISRC2DEC4", "ISRC2DEC4" }, \
996*4882a593Smuzhiyun 	{ name, "ISRC2INT1", "ISRC2INT1" }, \
997*4882a593Smuzhiyun 	{ name, "ISRC2INT2", "ISRC2INT2" }, \
998*4882a593Smuzhiyun 	{ name, "ISRC2INT3", "ISRC2INT3" }, \
999*4882a593Smuzhiyun 	{ name, "ISRC2INT4", "ISRC2INT4" }, \
1000*4882a593Smuzhiyun 	{ name, "DSP1.1", "DSP1" }, \
1001*4882a593Smuzhiyun 	{ name, "DSP1.2", "DSP1" }, \
1002*4882a593Smuzhiyun 	{ name, "DSP1.3", "DSP1" }, \
1003*4882a593Smuzhiyun 	{ name, "DSP1.4", "DSP1" }, \
1004*4882a593Smuzhiyun 	{ name, "DSP1.5", "DSP1" }, \
1005*4882a593Smuzhiyun 	{ name, "DSP1.6", "DSP1" }, \
1006*4882a593Smuzhiyun 	{ name, "DSP2.1", "DSP2" }, \
1007*4882a593Smuzhiyun 	{ name, "DSP2.2", "DSP2" }, \
1008*4882a593Smuzhiyun 	{ name, "DSP2.3", "DSP2" }, \
1009*4882a593Smuzhiyun 	{ name, "DSP2.4", "DSP2" }, \
1010*4882a593Smuzhiyun 	{ name, "DSP2.5", "DSP2" }, \
1011*4882a593Smuzhiyun 	{ name, "DSP2.6", "DSP2" }, \
1012*4882a593Smuzhiyun 	{ name, "DSP3.1", "DSP3" }, \
1013*4882a593Smuzhiyun 	{ name, "DSP3.2", "DSP3" }, \
1014*4882a593Smuzhiyun 	{ name, "DSP3.3", "DSP3" }, \
1015*4882a593Smuzhiyun 	{ name, "DSP3.4", "DSP3" }, \
1016*4882a593Smuzhiyun 	{ name, "DSP3.5", "DSP3" }, \
1017*4882a593Smuzhiyun 	{ name, "DSP3.6", "DSP3" }
1018*4882a593Smuzhiyun 
1019*4882a593Smuzhiyun static const struct snd_soc_dapm_route cs47l35_dapm_routes[] = {
1020*4882a593Smuzhiyun 	/* Internal clock domains */
1021*4882a593Smuzhiyun 	{ "EQ1", NULL, "FXCLK" },
1022*4882a593Smuzhiyun 	{ "EQ2", NULL, "FXCLK" },
1023*4882a593Smuzhiyun 	{ "EQ3", NULL, "FXCLK" },
1024*4882a593Smuzhiyun 	{ "EQ4", NULL, "FXCLK" },
1025*4882a593Smuzhiyun 	{ "DRC1L", NULL, "FXCLK" },
1026*4882a593Smuzhiyun 	{ "DRC1R", NULL, "FXCLK" },
1027*4882a593Smuzhiyun 	{ "DRC2L", NULL, "FXCLK" },
1028*4882a593Smuzhiyun 	{ "DRC2R", NULL, "FXCLK" },
1029*4882a593Smuzhiyun 	{ "LHPF1", NULL, "FXCLK" },
1030*4882a593Smuzhiyun 	{ "LHPF2", NULL, "FXCLK" },
1031*4882a593Smuzhiyun 	{ "LHPF3", NULL, "FXCLK" },
1032*4882a593Smuzhiyun 	{ "LHPF4", NULL, "FXCLK" },
1033*4882a593Smuzhiyun 	{ "PWM1 Mixer", NULL, "PWMCLK" },
1034*4882a593Smuzhiyun 	{ "PWM2 Mixer", NULL, "PWMCLK" },
1035*4882a593Smuzhiyun 	{ "OUT1L", NULL, "OUTCLK" },
1036*4882a593Smuzhiyun 	{ "OUT1R", NULL, "OUTCLK" },
1037*4882a593Smuzhiyun 	{ "OUT4L", NULL, "OUTCLK" },
1038*4882a593Smuzhiyun 	{ "OUT5L", NULL, "OUTCLK" },
1039*4882a593Smuzhiyun 	{ "OUT5R", NULL, "OUTCLK" },
1040*4882a593Smuzhiyun 	{ "AIF1TX1", NULL, "AIF1TXCLK" },
1041*4882a593Smuzhiyun 	{ "AIF1TX2", NULL, "AIF1TXCLK" },
1042*4882a593Smuzhiyun 	{ "AIF1TX3", NULL, "AIF1TXCLK" },
1043*4882a593Smuzhiyun 	{ "AIF1TX4", NULL, "AIF1TXCLK" },
1044*4882a593Smuzhiyun 	{ "AIF1TX5", NULL, "AIF1TXCLK" },
1045*4882a593Smuzhiyun 	{ "AIF1TX6", NULL, "AIF1TXCLK" },
1046*4882a593Smuzhiyun 	{ "AIF2TX1", NULL, "AIF2TXCLK" },
1047*4882a593Smuzhiyun 	{ "AIF2TX2", NULL, "AIF2TXCLK" },
1048*4882a593Smuzhiyun 	{ "AIF3TX1", NULL, "AIF3TXCLK" },
1049*4882a593Smuzhiyun 	{ "AIF3TX2", NULL, "AIF3TXCLK" },
1050*4882a593Smuzhiyun 	{ "SLIMTX1", NULL, "SLIMBUSCLK" },
1051*4882a593Smuzhiyun 	{ "SLIMTX2", NULL, "SLIMBUSCLK" },
1052*4882a593Smuzhiyun 	{ "SLIMTX3", NULL, "SLIMBUSCLK" },
1053*4882a593Smuzhiyun 	{ "SLIMTX4", NULL, "SLIMBUSCLK" },
1054*4882a593Smuzhiyun 	{ "SLIMTX5", NULL, "SLIMBUSCLK" },
1055*4882a593Smuzhiyun 	{ "SLIMTX6", NULL, "SLIMBUSCLK" },
1056*4882a593Smuzhiyun 	{ "SPD1TX1", NULL, "SPDCLK" },
1057*4882a593Smuzhiyun 	{ "SPD1TX2", NULL, "SPDCLK" },
1058*4882a593Smuzhiyun 	{ "DSP1", NULL, "DSP1CLK" },
1059*4882a593Smuzhiyun 	{ "DSP2", NULL, "DSP2CLK" },
1060*4882a593Smuzhiyun 	{ "DSP3", NULL, "DSP3CLK" },
1061*4882a593Smuzhiyun 	{ "ISRC1DEC1", NULL, "ISRC1CLK" },
1062*4882a593Smuzhiyun 	{ "ISRC1DEC2", NULL, "ISRC1CLK" },
1063*4882a593Smuzhiyun 	{ "ISRC1DEC3", NULL, "ISRC1CLK" },
1064*4882a593Smuzhiyun 	{ "ISRC1DEC4", NULL, "ISRC1CLK" },
1065*4882a593Smuzhiyun 	{ "ISRC1INT1", NULL, "ISRC1CLK" },
1066*4882a593Smuzhiyun 	{ "ISRC1INT2", NULL, "ISRC1CLK" },
1067*4882a593Smuzhiyun 	{ "ISRC1INT3", NULL, "ISRC1CLK" },
1068*4882a593Smuzhiyun 	{ "ISRC1INT4", NULL, "ISRC1CLK" },
1069*4882a593Smuzhiyun 	{ "ISRC2DEC1", NULL, "ISRC2CLK" },
1070*4882a593Smuzhiyun 	{ "ISRC2DEC2", NULL, "ISRC2CLK" },
1071*4882a593Smuzhiyun 	{ "ISRC2DEC3", NULL, "ISRC2CLK" },
1072*4882a593Smuzhiyun 	{ "ISRC2DEC4", NULL, "ISRC2CLK" },
1073*4882a593Smuzhiyun 	{ "ISRC2INT1", NULL, "ISRC2CLK" },
1074*4882a593Smuzhiyun 	{ "ISRC2INT2", NULL, "ISRC2CLK" },
1075*4882a593Smuzhiyun 	{ "ISRC2INT3", NULL, "ISRC2CLK" },
1076*4882a593Smuzhiyun 	{ "ISRC2INT4", NULL, "ISRC2CLK" },
1077*4882a593Smuzhiyun 
1078*4882a593Smuzhiyun 	{ "AIF2 Capture", NULL, "DBVDD2" },
1079*4882a593Smuzhiyun 	{ "AIF2 Playback", NULL, "DBVDD2" },
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	{ "AIF3 Capture", NULL, "DBVDD2" },
1082*4882a593Smuzhiyun 	{ "AIF3 Playback", NULL, "DBVDD2" },
1083*4882a593Smuzhiyun 
1084*4882a593Smuzhiyun 	{ "OUT1L", NULL, "CPVDD1" },
1085*4882a593Smuzhiyun 	{ "OUT1R", NULL, "CPVDD1" },
1086*4882a593Smuzhiyun 	{ "OUT1L", NULL, "CPVDD2" },
1087*4882a593Smuzhiyun 	{ "OUT1R", NULL, "CPVDD2" },
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun 	{ "OUT4L", NULL, "SPKVDD" },
1090*4882a593Smuzhiyun 
1091*4882a593Smuzhiyun 	{ "OUT1L", NULL, "SYSCLK" },
1092*4882a593Smuzhiyun 	{ "OUT1R", NULL, "SYSCLK" },
1093*4882a593Smuzhiyun 	{ "OUT4L", NULL, "SYSCLK" },
1094*4882a593Smuzhiyun 	{ "OUT5L", NULL, "SYSCLK" },
1095*4882a593Smuzhiyun 	{ "OUT5R", NULL, "SYSCLK" },
1096*4882a593Smuzhiyun 
1097*4882a593Smuzhiyun 	{ "SPD1", NULL, "SYSCLK" },
1098*4882a593Smuzhiyun 	{ "SPD1", NULL, "SPD1TX1" },
1099*4882a593Smuzhiyun 	{ "SPD1", NULL, "SPD1TX2" },
1100*4882a593Smuzhiyun 
1101*4882a593Smuzhiyun 	{ "IN1L", NULL, "SYSCLK" },
1102*4882a593Smuzhiyun 	{ "IN1R", NULL, "SYSCLK" },
1103*4882a593Smuzhiyun 	{ "IN2L", NULL, "SYSCLK" },
1104*4882a593Smuzhiyun 	{ "IN2R", NULL, "SYSCLK" },
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	{ "MICBIAS1", NULL, "MICVDD" },
1107*4882a593Smuzhiyun 	{ "MICBIAS2", NULL, "MICVDD" },
1108*4882a593Smuzhiyun 
1109*4882a593Smuzhiyun 	{ "MICBIAS1A", NULL, "MICBIAS1" },
1110*4882a593Smuzhiyun 	{ "MICBIAS1B", NULL, "MICBIAS1" },
1111*4882a593Smuzhiyun 	{ "MICBIAS2A", NULL, "MICBIAS2" },
1112*4882a593Smuzhiyun 	{ "MICBIAS2B", NULL, "MICBIAS2" },
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 	{ "Noise Generator", NULL, "SYSCLK" },
1115*4882a593Smuzhiyun 	{ "Tone Generator 1", NULL, "SYSCLK" },
1116*4882a593Smuzhiyun 	{ "Tone Generator 2", NULL, "SYSCLK" },
1117*4882a593Smuzhiyun 
1118*4882a593Smuzhiyun 	{ "Noise Generator", NULL, "NOISE" },
1119*4882a593Smuzhiyun 	{ "Tone Generator 1", NULL, "TONE" },
1120*4882a593Smuzhiyun 	{ "Tone Generator 2", NULL, "TONE" },
1121*4882a593Smuzhiyun 
1122*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX1" },
1123*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX2" },
1124*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX3" },
1125*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX4" },
1126*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX5" },
1127*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX6" },
1128*4882a593Smuzhiyun 
1129*4882a593Smuzhiyun 	{ "AIF1RX1", NULL, "AIF1 Playback" },
1130*4882a593Smuzhiyun 	{ "AIF1RX2", NULL, "AIF1 Playback" },
1131*4882a593Smuzhiyun 	{ "AIF1RX3", NULL, "AIF1 Playback" },
1132*4882a593Smuzhiyun 	{ "AIF1RX4", NULL, "AIF1 Playback" },
1133*4882a593Smuzhiyun 	{ "AIF1RX5", NULL, "AIF1 Playback" },
1134*4882a593Smuzhiyun 	{ "AIF1RX6", NULL, "AIF1 Playback" },
1135*4882a593Smuzhiyun 
1136*4882a593Smuzhiyun 	{ "AIF2 Capture", NULL, "AIF2TX1" },
1137*4882a593Smuzhiyun 	{ "AIF2 Capture", NULL, "AIF2TX2" },
1138*4882a593Smuzhiyun 
1139*4882a593Smuzhiyun 	{ "AIF2RX1", NULL, "AIF2 Playback" },
1140*4882a593Smuzhiyun 	{ "AIF2RX2", NULL, "AIF2 Playback" },
1141*4882a593Smuzhiyun 
1142*4882a593Smuzhiyun 	{ "AIF3 Capture", NULL, "AIF3TX1" },
1143*4882a593Smuzhiyun 	{ "AIF3 Capture", NULL, "AIF3TX2" },
1144*4882a593Smuzhiyun 
1145*4882a593Smuzhiyun 	{ "AIF3RX1", NULL, "AIF3 Playback" },
1146*4882a593Smuzhiyun 	{ "AIF3RX2", NULL, "AIF3 Playback" },
1147*4882a593Smuzhiyun 
1148*4882a593Smuzhiyun 	{ "Slim1 Capture", NULL, "SLIMTX1" },
1149*4882a593Smuzhiyun 	{ "Slim1 Capture", NULL, "SLIMTX2" },
1150*4882a593Smuzhiyun 	{ "Slim1 Capture", NULL, "SLIMTX3" },
1151*4882a593Smuzhiyun 	{ "Slim1 Capture", NULL, "SLIMTX4" },
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun 	{ "SLIMRX1", NULL, "Slim1 Playback" },
1154*4882a593Smuzhiyun 	{ "SLIMRX2", NULL, "Slim1 Playback" },
1155*4882a593Smuzhiyun 	{ "SLIMRX3", NULL, "Slim1 Playback" },
1156*4882a593Smuzhiyun 	{ "SLIMRX4", NULL, "Slim1 Playback" },
1157*4882a593Smuzhiyun 
1158*4882a593Smuzhiyun 	{ "Slim2 Capture", NULL, "SLIMTX5" },
1159*4882a593Smuzhiyun 	{ "Slim2 Capture", NULL, "SLIMTX6" },
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun 	{ "SLIMRX5", NULL, "Slim2 Playback" },
1162*4882a593Smuzhiyun 	{ "SLIMRX6", NULL, "Slim2 Playback" },
1163*4882a593Smuzhiyun 
1164*4882a593Smuzhiyun 	{ "AIF1 Playback", NULL, "SYSCLK" },
1165*4882a593Smuzhiyun 	{ "AIF2 Playback", NULL, "SYSCLK" },
1166*4882a593Smuzhiyun 	{ "AIF3 Playback", NULL, "SYSCLK" },
1167*4882a593Smuzhiyun 	{ "Slim1 Playback", NULL, "SYSCLK" },
1168*4882a593Smuzhiyun 	{ "Slim2 Playback", NULL, "SYSCLK" },
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "SYSCLK" },
1171*4882a593Smuzhiyun 	{ "AIF2 Capture", NULL, "SYSCLK" },
1172*4882a593Smuzhiyun 	{ "AIF3 Capture", NULL, "SYSCLK" },
1173*4882a593Smuzhiyun 	{ "Slim1 Capture", NULL, "SYSCLK" },
1174*4882a593Smuzhiyun 	{ "Slim2 Capture", NULL, "SYSCLK" },
1175*4882a593Smuzhiyun 
1176*4882a593Smuzhiyun 	{ "Voice Control DSP", NULL, "DSP3" },
1177*4882a593Smuzhiyun 
1178*4882a593Smuzhiyun 	{ "Audio Trace DSP", NULL, "DSP1" },
1179*4882a593Smuzhiyun 
1180*4882a593Smuzhiyun 	{ "IN1L Analog Mux", "A", "IN1ALN" },
1181*4882a593Smuzhiyun 	{ "IN1L Analog Mux", "A", "IN1ALP" },
1182*4882a593Smuzhiyun 	{ "IN1L Analog Mux", "B", "IN1BLN" },
1183*4882a593Smuzhiyun 	{ "IN1L Analog Mux", "B", "IN1BLP" },
1184*4882a593Smuzhiyun 
1185*4882a593Smuzhiyun 	{ "IN1R Analog Mux", "A", "IN1ARN" },
1186*4882a593Smuzhiyun 	{ "IN1R Analog Mux", "A", "IN1ARP" },
1187*4882a593Smuzhiyun 	{ "IN1R Analog Mux", "B", "IN1BRN" },
1188*4882a593Smuzhiyun 	{ "IN1R Analog Mux", "B", "IN1BRP" },
1189*4882a593Smuzhiyun 
1190*4882a593Smuzhiyun 	{ "IN1L Mode", "Analog", "IN1L Analog Mux" },
1191*4882a593Smuzhiyun 	{ "IN1R Mode", "Analog", "IN1R Analog Mux" },
1192*4882a593Smuzhiyun 
1193*4882a593Smuzhiyun 	{ "IN1L Mode", "Digital", "IN1ALN" },
1194*4882a593Smuzhiyun 	{ "IN1L Mode", "Digital", "IN1ARN" },
1195*4882a593Smuzhiyun 	{ "IN1R Mode", "Digital", "IN1ALN" },
1196*4882a593Smuzhiyun 	{ "IN1R Mode", "Digital", "IN1ARN" },
1197*4882a593Smuzhiyun 
1198*4882a593Smuzhiyun 	{ "IN1L", NULL, "IN1L Mode" },
1199*4882a593Smuzhiyun 	{ "IN1R", NULL, "IN1R Mode" },
1200*4882a593Smuzhiyun 
1201*4882a593Smuzhiyun 	{ "IN2L Mode", "Analog", "IN2LN" },
1202*4882a593Smuzhiyun 	{ "IN2L Mode", "Analog", "IN2LP" },
1203*4882a593Smuzhiyun 	{ "IN2R Mode", "Analog", "IN2RN" },
1204*4882a593Smuzhiyun 	{ "IN2R Mode", "Analog", "IN2RP" },
1205*4882a593Smuzhiyun 
1206*4882a593Smuzhiyun 	{ "IN2L Mode", "Digital", "IN2LN" },
1207*4882a593Smuzhiyun 	{ "IN2L Mode", "Digital", "IN2RN" },
1208*4882a593Smuzhiyun 	{ "IN2R Mode", "Digital", "IN2LN" },
1209*4882a593Smuzhiyun 	{ "IN2R Mode", "Digital", "IN2RN" },
1210*4882a593Smuzhiyun 
1211*4882a593Smuzhiyun 	{ "IN2L", NULL, "IN2L Mode" },
1212*4882a593Smuzhiyun 	{ "IN2R", NULL, "IN2R Mode" },
1213*4882a593Smuzhiyun 
1214*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1215*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1216*4882a593Smuzhiyun 
1217*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("OUT4L", "SPKOUT"),
1218*4882a593Smuzhiyun 
1219*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1220*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1223*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1224*4882a593Smuzhiyun 
1225*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1226*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1227*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1228*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1229*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1230*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1231*4882a593Smuzhiyun 
1232*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1233*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1234*4882a593Smuzhiyun 
1235*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1236*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1237*4882a593Smuzhiyun 
1238*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
1239*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
1240*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
1241*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
1242*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
1243*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
1244*4882a593Smuzhiyun 
1245*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("SPD1TX1", "SPDIF1TX1"),
1246*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("SPD1TX2", "SPDIF1TX2"),
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("EQ1", "EQ1"),
1249*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("EQ2", "EQ2"),
1250*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("EQ3", "EQ3"),
1251*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("EQ4", "EQ4"),
1252*4882a593Smuzhiyun 
1253*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("DRC1L", "DRC1L"),
1254*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("DRC1R", "DRC1R"),
1255*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("DRC2L", "DRC2L"),
1256*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("DRC2R", "DRC2R"),
1257*4882a593Smuzhiyun 
1258*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("LHPF1", "LHPF1"),
1259*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("LHPF2", "LHPF2"),
1260*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("LHPF3", "LHPF3"),
1261*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("LHPF4", "LHPF4"),
1262*4882a593Smuzhiyun 
1263*4882a593Smuzhiyun 	MADERA_DSP_ROUTES("DSP1"),
1264*4882a593Smuzhiyun 	MADERA_DSP_ROUTES("DSP2"),
1265*4882a593Smuzhiyun 	MADERA_DSP_ROUTES("DSP3"),
1266*4882a593Smuzhiyun 
1267*4882a593Smuzhiyun 	{ "DSP Trigger Out", NULL, "DSP1 Trigger Output" },
1268*4882a593Smuzhiyun 	{ "DSP Trigger Out", NULL, "DSP2 Trigger Output" },
1269*4882a593Smuzhiyun 	{ "DSP Trigger Out", NULL, "DSP3 Trigger Output" },
1270*4882a593Smuzhiyun 
1271*4882a593Smuzhiyun 	{ "DSP1 Trigger Output", "Switch", "DSP1" },
1272*4882a593Smuzhiyun 	{ "DSP2 Trigger Output", "Switch", "DSP2" },
1273*4882a593Smuzhiyun 	{ "DSP3 Trigger Output", "Switch", "DSP3" },
1274*4882a593Smuzhiyun 
1275*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
1276*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
1277*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
1278*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
1279*4882a593Smuzhiyun 
1280*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
1281*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
1282*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
1283*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
1284*4882a593Smuzhiyun 
1285*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
1286*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
1287*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"),
1288*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"),
1289*4882a593Smuzhiyun 
1290*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
1291*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
1292*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
1293*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
1294*4882a593Smuzhiyun 
1295*4882a593Smuzhiyun 	{ "AEC1 Loopback", "HPOUT1L", "OUT1L" },
1296*4882a593Smuzhiyun 	{ "AEC1 Loopback", "HPOUT1R", "OUT1R" },
1297*4882a593Smuzhiyun 	{ "AEC2 Loopback", "HPOUT1L", "OUT1L" },
1298*4882a593Smuzhiyun 	{ "AEC2 Loopback", "HPOUT1R", "OUT1R" },
1299*4882a593Smuzhiyun 	{ "HPOUT1 Demux", NULL, "OUT1L" },
1300*4882a593Smuzhiyun 	{ "HPOUT1 Demux", NULL, "OUT1R" },
1301*4882a593Smuzhiyun 
1302*4882a593Smuzhiyun 	{ "AEC1 Loopback", "SPKOUT", "OUT4L" },
1303*4882a593Smuzhiyun 	{ "AEC2 Loopback", "SPKOUT", "OUT4L" },
1304*4882a593Smuzhiyun 	{ "SPKOUTN", NULL, "OUT4L" },
1305*4882a593Smuzhiyun 	{ "SPKOUTP", NULL, "OUT4L" },
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun 	{ "OUT1R", NULL, "HPOUT1 Mono Mux" },
1308*4882a593Smuzhiyun 	{ "HPOUT1 Mono Mux", "EPOUT", "OUT1L" },
1309*4882a593Smuzhiyun 
1310*4882a593Smuzhiyun 	{ "HPOUTL", "HPOUT", "HPOUT1 Demux" },
1311*4882a593Smuzhiyun 	{ "HPOUTR", "HPOUT", "HPOUT1 Demux" },
1312*4882a593Smuzhiyun 	{ "EPOUTP", "EPOUT", "HPOUT1 Demux" },
1313*4882a593Smuzhiyun 	{ "EPOUTN", "EPOUT", "HPOUT1 Demux" },
1314*4882a593Smuzhiyun 
1315*4882a593Smuzhiyun 	{ "AEC1 Loopback", "SPKDAT1L", "OUT5L" },
1316*4882a593Smuzhiyun 	{ "AEC1 Loopback", "SPKDAT1R", "OUT5R" },
1317*4882a593Smuzhiyun 	{ "AEC2 Loopback", "SPKDAT1L", "OUT5L" },
1318*4882a593Smuzhiyun 	{ "AEC2 Loopback", "SPKDAT1R", "OUT5R" },
1319*4882a593Smuzhiyun 	{ "SPKDAT1L", NULL, "OUT5L" },
1320*4882a593Smuzhiyun 	{ "SPKDAT1R", NULL, "OUT5R" },
1321*4882a593Smuzhiyun 
1322*4882a593Smuzhiyun 	{ "SPDIF1", NULL, "SPD1" },
1323*4882a593Smuzhiyun 
1324*4882a593Smuzhiyun 	{ "MICSUPP", NULL, "SYSCLK" },
1325*4882a593Smuzhiyun 
1326*4882a593Smuzhiyun 	{ "DRC1 Signal Activity", NULL, "DRC1 Activity Output" },
1327*4882a593Smuzhiyun 	{ "DRC2 Signal Activity", NULL, "DRC2 Activity Output" },
1328*4882a593Smuzhiyun 	{ "DRC1 Activity Output", "Switch", "DRC1L" },
1329*4882a593Smuzhiyun 	{ "DRC1 Activity Output", "Switch", "DRC1R" },
1330*4882a593Smuzhiyun 	{ "DRC2 Activity Output", "Switch", "DRC2L" },
1331*4882a593Smuzhiyun 	{ "DRC2 Activity Output", "Switch", "DRC2R" },
1332*4882a593Smuzhiyun };
1333*4882a593Smuzhiyun 
cs47l35_set_fll(struct snd_soc_component * component,int fll_id,int source,unsigned int fref,unsigned int fout)1334*4882a593Smuzhiyun static int cs47l35_set_fll(struct snd_soc_component *component, int fll_id,
1335*4882a593Smuzhiyun 			   int source, unsigned int fref, unsigned int fout)
1336*4882a593Smuzhiyun {
1337*4882a593Smuzhiyun 	struct cs47l35 *cs47l35 = snd_soc_component_get_drvdata(component);
1338*4882a593Smuzhiyun 
1339*4882a593Smuzhiyun 	switch (fll_id) {
1340*4882a593Smuzhiyun 	case MADERA_FLL1_REFCLK:
1341*4882a593Smuzhiyun 		return madera_set_fll_refclk(&cs47l35->fll, source, fref,
1342*4882a593Smuzhiyun 					     fout);
1343*4882a593Smuzhiyun 	case MADERA_FLL1_SYNCCLK:
1344*4882a593Smuzhiyun 		return madera_set_fll_syncclk(&cs47l35->fll, source, fref,
1345*4882a593Smuzhiyun 					      fout);
1346*4882a593Smuzhiyun 	default:
1347*4882a593Smuzhiyun 		return -EINVAL;
1348*4882a593Smuzhiyun 	}
1349*4882a593Smuzhiyun }
1350*4882a593Smuzhiyun 
1351*4882a593Smuzhiyun static struct snd_soc_dai_driver cs47l35_dai[] = {
1352*4882a593Smuzhiyun 	{
1353*4882a593Smuzhiyun 		.name = "cs47l35-aif1",
1354*4882a593Smuzhiyun 		.id = 1,
1355*4882a593Smuzhiyun 		.base = MADERA_AIF1_BCLK_CTRL,
1356*4882a593Smuzhiyun 		.playback = {
1357*4882a593Smuzhiyun 			.stream_name = "AIF1 Playback",
1358*4882a593Smuzhiyun 			.channels_min = 1,
1359*4882a593Smuzhiyun 			.channels_max = 6,
1360*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1361*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1362*4882a593Smuzhiyun 		},
1363*4882a593Smuzhiyun 		.capture = {
1364*4882a593Smuzhiyun 			.stream_name = "AIF1 Capture",
1365*4882a593Smuzhiyun 			.channels_min = 1,
1366*4882a593Smuzhiyun 			.channels_max = 6,
1367*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1368*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1369*4882a593Smuzhiyun 		 },
1370*4882a593Smuzhiyun 		.ops = &madera_dai_ops,
1371*4882a593Smuzhiyun 		.symmetric_rates = 1,
1372*4882a593Smuzhiyun 		.symmetric_samplebits = 1,
1373*4882a593Smuzhiyun 	},
1374*4882a593Smuzhiyun 	{
1375*4882a593Smuzhiyun 		.name = "cs47l35-aif2",
1376*4882a593Smuzhiyun 		.id = 2,
1377*4882a593Smuzhiyun 		.base = MADERA_AIF2_BCLK_CTRL,
1378*4882a593Smuzhiyun 		.playback = {
1379*4882a593Smuzhiyun 			.stream_name = "AIF2 Playback",
1380*4882a593Smuzhiyun 			.channels_min = 1,
1381*4882a593Smuzhiyun 			.channels_max = 2,
1382*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1383*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1384*4882a593Smuzhiyun 		},
1385*4882a593Smuzhiyun 		.capture = {
1386*4882a593Smuzhiyun 			.stream_name = "AIF2 Capture",
1387*4882a593Smuzhiyun 			.channels_min = 1,
1388*4882a593Smuzhiyun 			.channels_max = 2,
1389*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1390*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1391*4882a593Smuzhiyun 		 },
1392*4882a593Smuzhiyun 		.ops = &madera_dai_ops,
1393*4882a593Smuzhiyun 		.symmetric_rates = 1,
1394*4882a593Smuzhiyun 		.symmetric_samplebits = 1,
1395*4882a593Smuzhiyun 	},
1396*4882a593Smuzhiyun 	{
1397*4882a593Smuzhiyun 		.name = "cs47l35-aif3",
1398*4882a593Smuzhiyun 		.id = 3,
1399*4882a593Smuzhiyun 		.base = MADERA_AIF3_BCLK_CTRL,
1400*4882a593Smuzhiyun 		.playback = {
1401*4882a593Smuzhiyun 			.stream_name = "AIF3 Playback",
1402*4882a593Smuzhiyun 			.channels_min = 1,
1403*4882a593Smuzhiyun 			.channels_max = 2,
1404*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1405*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1406*4882a593Smuzhiyun 		},
1407*4882a593Smuzhiyun 		.capture = {
1408*4882a593Smuzhiyun 			.stream_name = "AIF3 Capture",
1409*4882a593Smuzhiyun 			.channels_min = 1,
1410*4882a593Smuzhiyun 			.channels_max = 2,
1411*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1412*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1413*4882a593Smuzhiyun 		 },
1414*4882a593Smuzhiyun 		.ops = &madera_dai_ops,
1415*4882a593Smuzhiyun 		.symmetric_rates = 1,
1416*4882a593Smuzhiyun 		.symmetric_samplebits = 1,
1417*4882a593Smuzhiyun 	},
1418*4882a593Smuzhiyun 	{
1419*4882a593Smuzhiyun 		.name = "cs47l35-slim1",
1420*4882a593Smuzhiyun 		.id = 4,
1421*4882a593Smuzhiyun 		.playback = {
1422*4882a593Smuzhiyun 			.stream_name = "Slim1 Playback",
1423*4882a593Smuzhiyun 			.channels_min = 1,
1424*4882a593Smuzhiyun 			.channels_max = 4,
1425*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1426*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1427*4882a593Smuzhiyun 		},
1428*4882a593Smuzhiyun 		.capture = {
1429*4882a593Smuzhiyun 			.stream_name = "Slim1 Capture",
1430*4882a593Smuzhiyun 			.channels_min = 1,
1431*4882a593Smuzhiyun 			.channels_max = 4,
1432*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1433*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1434*4882a593Smuzhiyun 		 },
1435*4882a593Smuzhiyun 		.ops = &madera_simple_dai_ops,
1436*4882a593Smuzhiyun 	},
1437*4882a593Smuzhiyun 	{
1438*4882a593Smuzhiyun 		.name = "cs47l35-slim2",
1439*4882a593Smuzhiyun 		.id = 5,
1440*4882a593Smuzhiyun 		.playback = {
1441*4882a593Smuzhiyun 			.stream_name = "Slim2 Playback",
1442*4882a593Smuzhiyun 			.channels_min = 1,
1443*4882a593Smuzhiyun 			.channels_max = 2,
1444*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1445*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1446*4882a593Smuzhiyun 		},
1447*4882a593Smuzhiyun 		.capture = {
1448*4882a593Smuzhiyun 			.stream_name = "Slim2 Capture",
1449*4882a593Smuzhiyun 			.channels_min = 1,
1450*4882a593Smuzhiyun 			.channels_max = 2,
1451*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1452*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1453*4882a593Smuzhiyun 		 },
1454*4882a593Smuzhiyun 		.ops = &madera_simple_dai_ops,
1455*4882a593Smuzhiyun 	},
1456*4882a593Smuzhiyun 	{
1457*4882a593Smuzhiyun 		.name = "cs47l35-cpu-voicectrl",
1458*4882a593Smuzhiyun 		.capture = {
1459*4882a593Smuzhiyun 			.stream_name = "Voice Control CPU",
1460*4882a593Smuzhiyun 			.channels_min = 1,
1461*4882a593Smuzhiyun 			.channels_max = 1,
1462*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1463*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1464*4882a593Smuzhiyun 		},
1465*4882a593Smuzhiyun 		.compress_new = &snd_soc_new_compress,
1466*4882a593Smuzhiyun 	},
1467*4882a593Smuzhiyun 	{
1468*4882a593Smuzhiyun 		.name = "cs47l35-dsp-voicectrl",
1469*4882a593Smuzhiyun 		.capture = {
1470*4882a593Smuzhiyun 			.stream_name = "Voice Control DSP",
1471*4882a593Smuzhiyun 			.channels_min = 1,
1472*4882a593Smuzhiyun 			.channels_max = 1,
1473*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1474*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1475*4882a593Smuzhiyun 		},
1476*4882a593Smuzhiyun 	},
1477*4882a593Smuzhiyun 	{
1478*4882a593Smuzhiyun 		.name = "cs47l35-cpu-trace",
1479*4882a593Smuzhiyun 		.capture = {
1480*4882a593Smuzhiyun 			.stream_name = "Audio Trace CPU",
1481*4882a593Smuzhiyun 			.channels_min = 1,
1482*4882a593Smuzhiyun 			.channels_max = 6,
1483*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1484*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1485*4882a593Smuzhiyun 		},
1486*4882a593Smuzhiyun 		.compress_new = &snd_soc_new_compress,
1487*4882a593Smuzhiyun 	},
1488*4882a593Smuzhiyun 	{
1489*4882a593Smuzhiyun 		.name = "cs47l35-dsp-trace",
1490*4882a593Smuzhiyun 		.capture = {
1491*4882a593Smuzhiyun 			.stream_name = "Audio Trace DSP",
1492*4882a593Smuzhiyun 			.channels_min = 1,
1493*4882a593Smuzhiyun 			.channels_max = 6,
1494*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1495*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1496*4882a593Smuzhiyun 		},
1497*4882a593Smuzhiyun 	},
1498*4882a593Smuzhiyun };
1499*4882a593Smuzhiyun 
cs47l35_open(struct snd_soc_component * component,struct snd_compr_stream * stream)1500*4882a593Smuzhiyun static int cs47l35_open(struct snd_soc_component *component,
1501*4882a593Smuzhiyun 			struct snd_compr_stream *stream)
1502*4882a593Smuzhiyun {
1503*4882a593Smuzhiyun 	struct snd_soc_pcm_runtime *rtd = stream->private_data;
1504*4882a593Smuzhiyun 	struct cs47l35 *cs47l35 = snd_soc_component_get_drvdata(component);
1505*4882a593Smuzhiyun 	struct madera_priv *priv = &cs47l35->core;
1506*4882a593Smuzhiyun 	struct madera *madera = priv->madera;
1507*4882a593Smuzhiyun 	int n_adsp;
1508*4882a593Smuzhiyun 
1509*4882a593Smuzhiyun 	if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l35-dsp-voicectrl") == 0) {
1510*4882a593Smuzhiyun 		n_adsp = 2;
1511*4882a593Smuzhiyun 	} else if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l35-dsp-trace") == 0) {
1512*4882a593Smuzhiyun 		n_adsp = 0;
1513*4882a593Smuzhiyun 	} else {
1514*4882a593Smuzhiyun 		dev_err(madera->dev,
1515*4882a593Smuzhiyun 			"No suitable compressed stream for DAI '%s'\n",
1516*4882a593Smuzhiyun 			asoc_rtd_to_codec(rtd, 0)->name);
1517*4882a593Smuzhiyun 		return -EINVAL;
1518*4882a593Smuzhiyun 	}
1519*4882a593Smuzhiyun 
1520*4882a593Smuzhiyun 	return wm_adsp_compr_open(&priv->adsp[n_adsp], stream);
1521*4882a593Smuzhiyun }
1522*4882a593Smuzhiyun 
cs47l35_adsp2_irq(int irq,void * data)1523*4882a593Smuzhiyun static irqreturn_t cs47l35_adsp2_irq(int irq, void *data)
1524*4882a593Smuzhiyun {
1525*4882a593Smuzhiyun 	struct cs47l35 *cs47l35 = data;
1526*4882a593Smuzhiyun 	struct madera_priv *priv = &cs47l35->core;
1527*4882a593Smuzhiyun 	struct madera *madera = priv->madera;
1528*4882a593Smuzhiyun 	struct madera_voice_trigger_info trig_info;
1529*4882a593Smuzhiyun 	int serviced = 0;
1530*4882a593Smuzhiyun 	int i, ret;
1531*4882a593Smuzhiyun 
1532*4882a593Smuzhiyun 	for (i = 0; i < CS47L35_NUM_ADSP; ++i) {
1533*4882a593Smuzhiyun 		ret = wm_adsp_compr_handle_irq(&priv->adsp[i]);
1534*4882a593Smuzhiyun 		if (ret != -ENODEV)
1535*4882a593Smuzhiyun 			serviced++;
1536*4882a593Smuzhiyun 		if (ret == WM_ADSP_COMPR_VOICE_TRIGGER) {
1537*4882a593Smuzhiyun 			trig_info.core_num = i + 1;
1538*4882a593Smuzhiyun 			blocking_notifier_call_chain(&madera->notifier,
1539*4882a593Smuzhiyun 						MADERA_NOTIFY_VOICE_TRIGGER,
1540*4882a593Smuzhiyun 						&trig_info);
1541*4882a593Smuzhiyun 		}
1542*4882a593Smuzhiyun 	}
1543*4882a593Smuzhiyun 
1544*4882a593Smuzhiyun 	if (!serviced) {
1545*4882a593Smuzhiyun 		dev_err(madera->dev, "Spurious compressed data IRQ\n");
1546*4882a593Smuzhiyun 		return IRQ_NONE;
1547*4882a593Smuzhiyun 	}
1548*4882a593Smuzhiyun 
1549*4882a593Smuzhiyun 	return IRQ_HANDLED;
1550*4882a593Smuzhiyun }
1551*4882a593Smuzhiyun 
1552*4882a593Smuzhiyun static const struct snd_soc_dapm_route cs47l35_mono_routes[] = {
1553*4882a593Smuzhiyun 	{ "HPOUT1 Mono Mux", "HPOUT", "OUT1L" },
1554*4882a593Smuzhiyun };
1555*4882a593Smuzhiyun 
cs47l35_component_probe(struct snd_soc_component * component)1556*4882a593Smuzhiyun static int cs47l35_component_probe(struct snd_soc_component *component)
1557*4882a593Smuzhiyun {
1558*4882a593Smuzhiyun 	struct cs47l35 *cs47l35 = snd_soc_component_get_drvdata(component);
1559*4882a593Smuzhiyun 	struct madera *madera = cs47l35->core.madera;
1560*4882a593Smuzhiyun 	int i, ret;
1561*4882a593Smuzhiyun 
1562*4882a593Smuzhiyun 	snd_soc_component_init_regmap(component, madera->regmap);
1563*4882a593Smuzhiyun 
1564*4882a593Smuzhiyun 	mutex_lock(&madera->dapm_ptr_lock);
1565*4882a593Smuzhiyun 	madera->dapm = snd_soc_component_get_dapm(component);
1566*4882a593Smuzhiyun 	mutex_unlock(&madera->dapm_ptr_lock);
1567*4882a593Smuzhiyun 
1568*4882a593Smuzhiyun 	ret = madera_init_inputs(component);
1569*4882a593Smuzhiyun 	if (ret)
1570*4882a593Smuzhiyun 		return ret;
1571*4882a593Smuzhiyun 
1572*4882a593Smuzhiyun 	ret = madera_init_outputs(component, cs47l35_mono_routes,
1573*4882a593Smuzhiyun 				  ARRAY_SIZE(cs47l35_mono_routes),
1574*4882a593Smuzhiyun 				  CS47L35_MONO_OUTPUTS);
1575*4882a593Smuzhiyun 	if (ret)
1576*4882a593Smuzhiyun 		return ret;
1577*4882a593Smuzhiyun 
1578*4882a593Smuzhiyun 	snd_soc_component_disable_pin(component, "HAPTICS");
1579*4882a593Smuzhiyun 
1580*4882a593Smuzhiyun 	ret = snd_soc_add_component_controls(component,
1581*4882a593Smuzhiyun 					     madera_adsp_rate_controls,
1582*4882a593Smuzhiyun 					     CS47L35_NUM_ADSP);
1583*4882a593Smuzhiyun 	if (ret)
1584*4882a593Smuzhiyun 		return ret;
1585*4882a593Smuzhiyun 
1586*4882a593Smuzhiyun 	for (i = 0; i < CS47L35_NUM_ADSP; i++)
1587*4882a593Smuzhiyun 		wm_adsp2_component_probe(&cs47l35->core.adsp[i], component);
1588*4882a593Smuzhiyun 
1589*4882a593Smuzhiyun 	return 0;
1590*4882a593Smuzhiyun }
1591*4882a593Smuzhiyun 
cs47l35_component_remove(struct snd_soc_component * component)1592*4882a593Smuzhiyun static void cs47l35_component_remove(struct snd_soc_component *component)
1593*4882a593Smuzhiyun {
1594*4882a593Smuzhiyun 	struct cs47l35 *cs47l35 = snd_soc_component_get_drvdata(component);
1595*4882a593Smuzhiyun 	struct madera *madera = cs47l35->core.madera;
1596*4882a593Smuzhiyun 	int i;
1597*4882a593Smuzhiyun 
1598*4882a593Smuzhiyun 	mutex_lock(&madera->dapm_ptr_lock);
1599*4882a593Smuzhiyun 	madera->dapm = NULL;
1600*4882a593Smuzhiyun 	mutex_unlock(&madera->dapm_ptr_lock);
1601*4882a593Smuzhiyun 
1602*4882a593Smuzhiyun 	for (i = 0; i < CS47L35_NUM_ADSP; i++)
1603*4882a593Smuzhiyun 		wm_adsp2_component_remove(&cs47l35->core.adsp[i], component);
1604*4882a593Smuzhiyun }
1605*4882a593Smuzhiyun 
1606*4882a593Smuzhiyun #define CS47L35_DIG_VU 0x0200
1607*4882a593Smuzhiyun 
1608*4882a593Smuzhiyun static unsigned int cs47l35_digital_vu[] = {
1609*4882a593Smuzhiyun 	MADERA_DAC_DIGITAL_VOLUME_1L,
1610*4882a593Smuzhiyun 	MADERA_DAC_DIGITAL_VOLUME_1R,
1611*4882a593Smuzhiyun 	MADERA_DAC_DIGITAL_VOLUME_4L,
1612*4882a593Smuzhiyun 	MADERA_DAC_DIGITAL_VOLUME_5L,
1613*4882a593Smuzhiyun 	MADERA_DAC_DIGITAL_VOLUME_5R,
1614*4882a593Smuzhiyun };
1615*4882a593Smuzhiyun 
1616*4882a593Smuzhiyun static const struct snd_compress_ops cs47l35_compress_ops = {
1617*4882a593Smuzhiyun 	.open = &cs47l35_open,
1618*4882a593Smuzhiyun 	.free = &wm_adsp_compr_free,
1619*4882a593Smuzhiyun 	.set_params = &wm_adsp_compr_set_params,
1620*4882a593Smuzhiyun 	.get_caps = &wm_adsp_compr_get_caps,
1621*4882a593Smuzhiyun 	.trigger = &wm_adsp_compr_trigger,
1622*4882a593Smuzhiyun 	.pointer = &wm_adsp_compr_pointer,
1623*4882a593Smuzhiyun 	.copy = &wm_adsp_compr_copy,
1624*4882a593Smuzhiyun };
1625*4882a593Smuzhiyun 
1626*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_cs47l35 = {
1627*4882a593Smuzhiyun 	.probe			= &cs47l35_component_probe,
1628*4882a593Smuzhiyun 	.remove			= &cs47l35_component_remove,
1629*4882a593Smuzhiyun 	.set_sysclk		= &madera_set_sysclk,
1630*4882a593Smuzhiyun 	.set_pll		= &cs47l35_set_fll,
1631*4882a593Smuzhiyun 	.name			= DRV_NAME,
1632*4882a593Smuzhiyun 	.compress_ops		= &cs47l35_compress_ops,
1633*4882a593Smuzhiyun 	.controls		= cs47l35_snd_controls,
1634*4882a593Smuzhiyun 	.num_controls		= ARRAY_SIZE(cs47l35_snd_controls),
1635*4882a593Smuzhiyun 	.dapm_widgets		= cs47l35_dapm_widgets,
1636*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(cs47l35_dapm_widgets),
1637*4882a593Smuzhiyun 	.dapm_routes		= cs47l35_dapm_routes,
1638*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(cs47l35_dapm_routes),
1639*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
1640*4882a593Smuzhiyun 	.endianness		= 1,
1641*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
1642*4882a593Smuzhiyun };
1643*4882a593Smuzhiyun 
cs47l35_probe(struct platform_device * pdev)1644*4882a593Smuzhiyun static int cs47l35_probe(struct platform_device *pdev)
1645*4882a593Smuzhiyun {
1646*4882a593Smuzhiyun 	struct madera *madera = dev_get_drvdata(pdev->dev.parent);
1647*4882a593Smuzhiyun 	struct cs47l35 *cs47l35;
1648*4882a593Smuzhiyun 	int i, ret;
1649*4882a593Smuzhiyun 
1650*4882a593Smuzhiyun 	BUILD_BUG_ON(ARRAY_SIZE(cs47l35_dai) > MADERA_MAX_DAI);
1651*4882a593Smuzhiyun 
1652*4882a593Smuzhiyun 	/* quick exit if Madera irqchip driver hasn't completed probe */
1653*4882a593Smuzhiyun 	if (!madera->irq_dev) {
1654*4882a593Smuzhiyun 		dev_dbg(&pdev->dev, "irqchip driver not ready\n");
1655*4882a593Smuzhiyun 		return -EPROBE_DEFER;
1656*4882a593Smuzhiyun 	}
1657*4882a593Smuzhiyun 
1658*4882a593Smuzhiyun 	cs47l35 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l35), GFP_KERNEL);
1659*4882a593Smuzhiyun 	if (!cs47l35)
1660*4882a593Smuzhiyun 		return -ENOMEM;
1661*4882a593Smuzhiyun 	platform_set_drvdata(pdev, cs47l35);
1662*4882a593Smuzhiyun 
1663*4882a593Smuzhiyun 	cs47l35->core.madera = madera;
1664*4882a593Smuzhiyun 	cs47l35->core.dev = &pdev->dev;
1665*4882a593Smuzhiyun 	cs47l35->core.num_inputs = 4;
1666*4882a593Smuzhiyun 
1667*4882a593Smuzhiyun 	ret = madera_core_init(&cs47l35->core);
1668*4882a593Smuzhiyun 	if (ret)
1669*4882a593Smuzhiyun 		return ret;
1670*4882a593Smuzhiyun 
1671*4882a593Smuzhiyun 	ret = madera_init_overheat(&cs47l35->core);
1672*4882a593Smuzhiyun 	if (ret)
1673*4882a593Smuzhiyun 		goto error_core;
1674*4882a593Smuzhiyun 
1675*4882a593Smuzhiyun 	ret = madera_request_irq(madera, MADERA_IRQ_DSP_IRQ1,
1676*4882a593Smuzhiyun 				 "ADSP2 Compressed IRQ", cs47l35_adsp2_irq,
1677*4882a593Smuzhiyun 				 cs47l35);
1678*4882a593Smuzhiyun 	if (ret) {
1679*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
1680*4882a593Smuzhiyun 		goto error_overheat;
1681*4882a593Smuzhiyun 	}
1682*4882a593Smuzhiyun 
1683*4882a593Smuzhiyun 	ret = madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 1);
1684*4882a593Smuzhiyun 	if (ret)
1685*4882a593Smuzhiyun 		dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
1686*4882a593Smuzhiyun 
1687*4882a593Smuzhiyun 	for (i = 0; i < CS47L35_NUM_ADSP; i++) {
1688*4882a593Smuzhiyun 		cs47l35->core.adsp[i].part = "cs47l35";
1689*4882a593Smuzhiyun 		cs47l35->core.adsp[i].num = i + 1;
1690*4882a593Smuzhiyun 		cs47l35->core.adsp[i].type = WMFW_ADSP2;
1691*4882a593Smuzhiyun 		cs47l35->core.adsp[i].rev = 1;
1692*4882a593Smuzhiyun 		cs47l35->core.adsp[i].dev = madera->dev;
1693*4882a593Smuzhiyun 		cs47l35->core.adsp[i].regmap = madera->regmap_32bit;
1694*4882a593Smuzhiyun 
1695*4882a593Smuzhiyun 		cs47l35->core.adsp[i].base = wm_adsp2_control_bases[i];
1696*4882a593Smuzhiyun 		cs47l35->core.adsp[i].mem = cs47l35_dsp_regions[i];
1697*4882a593Smuzhiyun 		cs47l35->core.adsp[i].num_mems =
1698*4882a593Smuzhiyun 			ARRAY_SIZE(cs47l35_dsp1_regions);
1699*4882a593Smuzhiyun 
1700*4882a593Smuzhiyun 		ret = wm_adsp2_init(&cs47l35->core.adsp[i]);
1701*4882a593Smuzhiyun 		if (ret) {
1702*4882a593Smuzhiyun 			for (--i; i >= 0; --i)
1703*4882a593Smuzhiyun 				wm_adsp2_remove(&cs47l35->core.adsp[i]);
1704*4882a593Smuzhiyun 			goto error_dsp_irq;
1705*4882a593Smuzhiyun 		}
1706*4882a593Smuzhiyun 	}
1707*4882a593Smuzhiyun 
1708*4882a593Smuzhiyun 	madera_init_fll(madera, 1, MADERA_FLL1_CONTROL_1 - 1, &cs47l35->fll);
1709*4882a593Smuzhiyun 
1710*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(cs47l35_dai); i++)
1711*4882a593Smuzhiyun 		madera_init_dai(&cs47l35->core, i);
1712*4882a593Smuzhiyun 
1713*4882a593Smuzhiyun 	/* Latch volume update bits */
1714*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(cs47l35_digital_vu); i++)
1715*4882a593Smuzhiyun 		regmap_update_bits(madera->regmap, cs47l35_digital_vu[i],
1716*4882a593Smuzhiyun 				   CS47L35_DIG_VU, CS47L35_DIG_VU);
1717*4882a593Smuzhiyun 
1718*4882a593Smuzhiyun 	pm_runtime_enable(&pdev->dev);
1719*4882a593Smuzhiyun 	pm_runtime_idle(&pdev->dev);
1720*4882a593Smuzhiyun 
1721*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(&pdev->dev,
1722*4882a593Smuzhiyun 					      &soc_component_dev_cs47l35,
1723*4882a593Smuzhiyun 					      cs47l35_dai,
1724*4882a593Smuzhiyun 					      ARRAY_SIZE(cs47l35_dai));
1725*4882a593Smuzhiyun 	if (ret < 0) {
1726*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
1727*4882a593Smuzhiyun 		goto error_pm_runtime;
1728*4882a593Smuzhiyun 	}
1729*4882a593Smuzhiyun 
1730*4882a593Smuzhiyun 	return ret;
1731*4882a593Smuzhiyun 
1732*4882a593Smuzhiyun error_pm_runtime:
1733*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
1734*4882a593Smuzhiyun 
1735*4882a593Smuzhiyun 	for (i = 0; i < CS47L35_NUM_ADSP; i++)
1736*4882a593Smuzhiyun 		wm_adsp2_remove(&cs47l35->core.adsp[i]);
1737*4882a593Smuzhiyun error_dsp_irq:
1738*4882a593Smuzhiyun 	madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 0);
1739*4882a593Smuzhiyun 	madera_free_irq(madera, MADERA_IRQ_DSP_IRQ1, cs47l35);
1740*4882a593Smuzhiyun error_overheat:
1741*4882a593Smuzhiyun 	madera_free_overheat(&cs47l35->core);
1742*4882a593Smuzhiyun error_core:
1743*4882a593Smuzhiyun 	madera_core_free(&cs47l35->core);
1744*4882a593Smuzhiyun 
1745*4882a593Smuzhiyun 	return ret;
1746*4882a593Smuzhiyun }
1747*4882a593Smuzhiyun 
cs47l35_remove(struct platform_device * pdev)1748*4882a593Smuzhiyun static int cs47l35_remove(struct platform_device *pdev)
1749*4882a593Smuzhiyun {
1750*4882a593Smuzhiyun 	struct cs47l35 *cs47l35 = platform_get_drvdata(pdev);
1751*4882a593Smuzhiyun 	int i;
1752*4882a593Smuzhiyun 
1753*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
1754*4882a593Smuzhiyun 
1755*4882a593Smuzhiyun 	for (i = 0; i < CS47L35_NUM_ADSP; i++)
1756*4882a593Smuzhiyun 		wm_adsp2_remove(&cs47l35->core.adsp[i]);
1757*4882a593Smuzhiyun 
1758*4882a593Smuzhiyun 	madera_set_irq_wake(cs47l35->core.madera, MADERA_IRQ_DSP_IRQ1, 0);
1759*4882a593Smuzhiyun 	madera_free_irq(cs47l35->core.madera, MADERA_IRQ_DSP_IRQ1, cs47l35);
1760*4882a593Smuzhiyun 	madera_free_overheat(&cs47l35->core);
1761*4882a593Smuzhiyun 	madera_core_free(&cs47l35->core);
1762*4882a593Smuzhiyun 
1763*4882a593Smuzhiyun 	return 0;
1764*4882a593Smuzhiyun }
1765*4882a593Smuzhiyun 
1766*4882a593Smuzhiyun static struct platform_driver cs47l35_codec_driver = {
1767*4882a593Smuzhiyun 	.driver = {
1768*4882a593Smuzhiyun 		.name = "cs47l35-codec",
1769*4882a593Smuzhiyun 	},
1770*4882a593Smuzhiyun 	.probe = &cs47l35_probe,
1771*4882a593Smuzhiyun 	.remove = &cs47l35_remove,
1772*4882a593Smuzhiyun };
1773*4882a593Smuzhiyun 
1774*4882a593Smuzhiyun module_platform_driver(cs47l35_codec_driver);
1775*4882a593Smuzhiyun 
1776*4882a593Smuzhiyun MODULE_SOFTDEP("pre: madera irq-madera arizona-micsupp");
1777*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC CS47L35 driver");
1778*4882a593Smuzhiyun MODULE_AUTHOR("Piotr Stankiewicz <piotrs@opensource.cirrus.com>");
1779*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1780*4882a593Smuzhiyun MODULE_ALIAS("platform:cs47l35-codec");
1781