xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/cs47l15.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // ALSA SoC Audio driver for CS47L15 codec
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2016-2019 Cirrus Logic, Inc. and
6*4882a593Smuzhiyun //                         Cirrus Logic International Semiconductor Ltd.
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/moduleparam.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/pm.h>
15*4882a593Smuzhiyun #include <linux/pm_runtime.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <sound/core.h>
18*4882a593Smuzhiyun #include <sound/pcm.h>
19*4882a593Smuzhiyun #include <sound/pcm_params.h>
20*4882a593Smuzhiyun #include <sound/soc.h>
21*4882a593Smuzhiyun #include <sound/tlv.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include <linux/irqchip/irq-madera.h>
24*4882a593Smuzhiyun #include <linux/mfd/madera/core.h>
25*4882a593Smuzhiyun #include <linux/mfd/madera/registers.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "madera.h"
28*4882a593Smuzhiyun #include "wm_adsp.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define CS47L15_NUM_ADSP 1
31*4882a593Smuzhiyun #define CS47L15_MONO_OUTPUTS 1
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* Mid-mode registers */
34*4882a593Smuzhiyun #define CS47L15_ADC_INT_BIAS_MASK	0x3800
35*4882a593Smuzhiyun #define CS47L15_ADC_INT_BIAS_SHIFT	11
36*4882a593Smuzhiyun #define CS47L15_PGA_BIAS_SEL_MASK	0x03
37*4882a593Smuzhiyun #define CS47L15_PGA_BIAS_SEL_SHIFT	0
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define DRV_NAME "cs47l15-codec"
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun struct cs47l15 {
42*4882a593Smuzhiyun 	struct madera_priv core;
43*4882a593Smuzhiyun 	struct madera_fll fll[2];
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	bool in1_lp_mode;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun static const struct wm_adsp_region cs47l15_dsp1_regions[] = {
49*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
50*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
51*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
52*4882a593Smuzhiyun 	{ .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun static const char * const cs47l15_outdemux_texts[] = {
56*4882a593Smuzhiyun 	"HPOUT",
57*4882a593Smuzhiyun 	"EPOUT",
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(cs47l15_outdemux_enum, SND_SOC_NOPM, 0,
61*4882a593Smuzhiyun 			    cs47l15_outdemux_texts);
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l15_outdemux =
64*4882a593Smuzhiyun 	SOC_DAPM_ENUM_EXT("HPOUT1 Demux", cs47l15_outdemux_enum,
65*4882a593Smuzhiyun 			  madera_out1_demux_get, madera_out1_demux_put);
66*4882a593Smuzhiyun 
cs47l15_adsp_power_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)67*4882a593Smuzhiyun static int cs47l15_adsp_power_ev(struct snd_soc_dapm_widget *w,
68*4882a593Smuzhiyun 				 struct snd_kcontrol *kcontrol,
69*4882a593Smuzhiyun 				 int event)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	struct snd_soc_component *component =
72*4882a593Smuzhiyun 		snd_soc_dapm_to_component(w->dapm);
73*4882a593Smuzhiyun 	struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
74*4882a593Smuzhiyun 	struct madera_priv *priv = &cs47l15->core;
75*4882a593Smuzhiyun 	struct madera *madera = priv->madera;
76*4882a593Smuzhiyun 	unsigned int freq;
77*4882a593Smuzhiyun 	int ret;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	ret = regmap_read(madera->regmap, MADERA_DSP_CLOCK_2, &freq);
80*4882a593Smuzhiyun 	if (ret != 0) {
81*4882a593Smuzhiyun 		dev_err(madera->dev,
82*4882a593Smuzhiyun 			"Failed to read MADERA_DSP_CLOCK_2: %d\n", ret);
83*4882a593Smuzhiyun 		return ret;
84*4882a593Smuzhiyun 	}
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	switch (event) {
87*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMU:
88*4882a593Smuzhiyun 		ret = madera_set_adsp_clk(&cs47l15->core, w->shift, freq);
89*4882a593Smuzhiyun 		if (ret)
90*4882a593Smuzhiyun 			return ret;
91*4882a593Smuzhiyun 		break;
92*4882a593Smuzhiyun 	default:
93*4882a593Smuzhiyun 		break;
94*4882a593Smuzhiyun 	}
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	return wm_adsp_early_event(w, kcontrol, event);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #define CS47L15_NG_SRC(name, base) \
100*4882a593Smuzhiyun 	SOC_SINGLE(name " NG HPOUT1L Switch",  base,  0, 1, 0), \
101*4882a593Smuzhiyun 	SOC_SINGLE(name " NG HPOUT1R Switch",  base,  1, 1, 0), \
102*4882a593Smuzhiyun 	SOC_SINGLE(name " NG SPKOUTL Switch",  base,  6, 1, 0), \
103*4882a593Smuzhiyun 	SOC_SINGLE(name " NG SPKDAT1L Switch", base,  8, 1, 0), \
104*4882a593Smuzhiyun 	SOC_SINGLE(name " NG SPKDAT1R Switch", base,  9, 1, 0)
105*4882a593Smuzhiyun 
cs47l15_in1_adc_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)106*4882a593Smuzhiyun static int cs47l15_in1_adc_get(struct snd_kcontrol *kcontrol,
107*4882a593Smuzhiyun 			       struct snd_ctl_elem_value *ucontrol)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	struct snd_soc_component *component =
110*4882a593Smuzhiyun 		snd_soc_kcontrol_component(kcontrol);
111*4882a593Smuzhiyun 	struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = !!cs47l15->in1_lp_mode;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	return 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun 
cs47l15_in1_adc_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)118*4882a593Smuzhiyun static int cs47l15_in1_adc_put(struct snd_kcontrol *kcontrol,
119*4882a593Smuzhiyun 			       struct snd_ctl_elem_value *ucontrol)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun 	struct snd_soc_component *component =
122*4882a593Smuzhiyun 		snd_soc_kcontrol_component(kcontrol);
123*4882a593Smuzhiyun 	struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	if (!!ucontrol->value.integer.value[0] == cs47l15->in1_lp_mode)
126*4882a593Smuzhiyun 		return 0;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	switch (ucontrol->value.integer.value[0]) {
129*4882a593Smuzhiyun 	case 0:
130*4882a593Smuzhiyun 		/* Set IN1 to normal mode */
131*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, MADERA_DMIC1L_CONTROL,
132*4882a593Smuzhiyun 					      MADERA_IN1_OSR_MASK,
133*4882a593Smuzhiyun 					      5 << MADERA_IN1_OSR_SHIFT);
134*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS47L15_ADC_INT_BIAS,
135*4882a593Smuzhiyun 					      CS47L15_ADC_INT_BIAS_MASK,
136*4882a593Smuzhiyun 					      4 << CS47L15_ADC_INT_BIAS_SHIFT);
137*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS47L15_PGA_BIAS_SEL,
138*4882a593Smuzhiyun 					      CS47L15_PGA_BIAS_SEL_MASK, 0);
139*4882a593Smuzhiyun 		cs47l15->in1_lp_mode = false;
140*4882a593Smuzhiyun 		break;
141*4882a593Smuzhiyun 	default:
142*4882a593Smuzhiyun 		/* Set IN1 to LP mode */
143*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, MADERA_DMIC1L_CONTROL,
144*4882a593Smuzhiyun 					      MADERA_IN1_OSR_MASK,
145*4882a593Smuzhiyun 					      4 << MADERA_IN1_OSR_SHIFT);
146*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS47L15_ADC_INT_BIAS,
147*4882a593Smuzhiyun 					      CS47L15_ADC_INT_BIAS_MASK,
148*4882a593Smuzhiyun 					      1 << CS47L15_ADC_INT_BIAS_SHIFT);
149*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS47L15_PGA_BIAS_SEL,
150*4882a593Smuzhiyun 					      CS47L15_PGA_BIAS_SEL_MASK,
151*4882a593Smuzhiyun 					      3 << CS47L15_PGA_BIAS_SEL_SHIFT);
152*4882a593Smuzhiyun 		cs47l15->in1_lp_mode = true;
153*4882a593Smuzhiyun 		break;
154*4882a593Smuzhiyun 	}
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	return 1;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l15_snd_controls[] = {
160*4882a593Smuzhiyun SOC_ENUM("IN1 OSR", madera_in_dmic_osr[0]),
161*4882a593Smuzhiyun SOC_ENUM("IN2 OSR", madera_in_dmic_osr[1]),
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN1L Volume", MADERA_IN1L_CONTROL,
164*4882a593Smuzhiyun 		     MADERA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
165*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("IN1R Volume", MADERA_IN1R_CONTROL,
166*4882a593Smuzhiyun 		     MADERA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun SOC_ENUM("IN HPF Cutoff Frequency", madera_in_hpf_cut_enum),
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun SOC_SINGLE("IN1L HPF Switch", MADERA_IN1L_CONTROL, MADERA_IN1L_HPF_SHIFT, 1, 0),
171*4882a593Smuzhiyun SOC_SINGLE("IN1R HPF Switch", MADERA_IN1R_CONTROL, MADERA_IN1R_HPF_SHIFT, 1, 0),
172*4882a593Smuzhiyun SOC_SINGLE("IN2L HPF Switch", MADERA_IN2L_CONTROL, MADERA_IN2L_HPF_SHIFT, 1, 0),
173*4882a593Smuzhiyun SOC_SINGLE("IN2R HPF Switch", MADERA_IN2R_CONTROL, MADERA_IN2R_HPF_SHIFT, 1, 0),
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1L,
176*4882a593Smuzhiyun 	       MADERA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
177*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1R,
178*4882a593Smuzhiyun 	       MADERA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
179*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2L,
180*4882a593Smuzhiyun 	       MADERA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
181*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2R,
182*4882a593Smuzhiyun 	       MADERA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun SOC_ENUM("Input Ramp Up", madera_in_vi_ramp),
185*4882a593Smuzhiyun SOC_ENUM("Input Ramp Down", madera_in_vd_ramp),
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ1", MADERA_EQ1MIX_INPUT_1_SOURCE),
188*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ2", MADERA_EQ2MIX_INPUT_1_SOURCE),
189*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ3", MADERA_EQ3MIX_INPUT_1_SOURCE),
190*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("EQ4", MADERA_EQ4MIX_INPUT_1_SOURCE),
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ1 Coefficients", MADERA_EQ1_2),
193*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B1 Volume", MADERA_EQ1_1, MADERA_EQ1_B1_GAIN_SHIFT,
194*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
195*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B2 Volume", MADERA_EQ1_1, MADERA_EQ1_B2_GAIN_SHIFT,
196*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
197*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B3 Volume", MADERA_EQ1_1, MADERA_EQ1_B3_GAIN_SHIFT,
198*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
199*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B4 Volume", MADERA_EQ1_2, MADERA_EQ1_B4_GAIN_SHIFT,
200*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
201*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 B5 Volume", MADERA_EQ1_2, MADERA_EQ1_B5_GAIN_SHIFT,
202*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ2 Coefficients", MADERA_EQ2_2),
205*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B1 Volume", MADERA_EQ2_1, MADERA_EQ2_B1_GAIN_SHIFT,
206*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
207*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B2 Volume", MADERA_EQ2_1, MADERA_EQ2_B2_GAIN_SHIFT,
208*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
209*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B3 Volume", MADERA_EQ2_1, MADERA_EQ2_B3_GAIN_SHIFT,
210*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
211*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B4 Volume", MADERA_EQ2_2, MADERA_EQ2_B4_GAIN_SHIFT,
212*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
213*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 B5 Volume", MADERA_EQ2_2, MADERA_EQ2_B5_GAIN_SHIFT,
214*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ3 Coefficients", MADERA_EQ3_2),
217*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B1 Volume", MADERA_EQ3_1, MADERA_EQ3_B1_GAIN_SHIFT,
218*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
219*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B2 Volume", MADERA_EQ3_1, MADERA_EQ3_B2_GAIN_SHIFT,
220*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
221*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B3 Volume", MADERA_EQ3_1, MADERA_EQ3_B3_GAIN_SHIFT,
222*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
223*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B4 Volume", MADERA_EQ3_2, MADERA_EQ3_B4_GAIN_SHIFT,
224*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
225*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 B5 Volume", MADERA_EQ3_2, MADERA_EQ3_B5_GAIN_SHIFT,
226*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun MADERA_EQ_CONTROL("EQ4 Coefficients", MADERA_EQ4_2),
229*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B1 Volume", MADERA_EQ4_1, MADERA_EQ4_B1_GAIN_SHIFT,
230*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
231*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B2 Volume", MADERA_EQ4_1, MADERA_EQ4_B2_GAIN_SHIFT,
232*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
233*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B3 Volume", MADERA_EQ4_1, MADERA_EQ4_B3_GAIN_SHIFT,
234*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
235*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B4 Volume", MADERA_EQ4_2, MADERA_EQ4_B4_GAIN_SHIFT,
236*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
237*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 B5 Volume", MADERA_EQ4_2, MADERA_EQ4_B5_GAIN_SHIFT,
238*4882a593Smuzhiyun 	       24, 0, madera_eq_tlv),
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC1L", MADERA_DRC1LMIX_INPUT_1_SOURCE),
241*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC1R", MADERA_DRC1RMIX_INPUT_1_SOURCE),
242*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC2L", MADERA_DRC2LMIX_INPUT_1_SOURCE),
243*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DRC2R", MADERA_DRC2RMIX_INPUT_1_SOURCE),
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun SND_SOC_BYTES_MASK("DRC1", MADERA_DRC1_CTRL1, 5,
246*4882a593Smuzhiyun 		   MADERA_DRC1R_ENA | MADERA_DRC1L_ENA),
247*4882a593Smuzhiyun SND_SOC_BYTES_MASK("DRC2", MADERA_DRC2_CTRL1, 5,
248*4882a593Smuzhiyun 		   MADERA_DRC2R_ENA | MADERA_DRC2L_ENA),
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF1", MADERA_HPLP1MIX_INPUT_1_SOURCE),
251*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF2", MADERA_HPLP2MIX_INPUT_1_SOURCE),
252*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF3", MADERA_HPLP3MIX_INPUT_1_SOURCE),
253*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("LHPF4", MADERA_HPLP4MIX_INPUT_1_SOURCE),
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF1 Coefficients", MADERA_HPLPF1_2),
256*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF2 Coefficients", MADERA_HPLPF2_2),
257*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF3 Coefficients", MADERA_HPLPF3_2),
258*4882a593Smuzhiyun MADERA_LHPF_CONTROL("LHPF4 Coefficients", MADERA_HPLPF4_2),
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun SOC_ENUM("LHPF1 Mode", madera_lhpf1_mode),
261*4882a593Smuzhiyun SOC_ENUM("LHPF2 Mode", madera_lhpf2_mode),
262*4882a593Smuzhiyun SOC_ENUM("LHPF3 Mode", madera_lhpf3_mode),
263*4882a593Smuzhiyun SOC_ENUM("LHPF4 Mode", madera_lhpf4_mode),
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC1 FSL", madera_isrc_fsl[0]),
266*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC2 FSL", madera_isrc_fsl[1]),
267*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC1 FSH", madera_isrc_fsh[0]),
268*4882a593Smuzhiyun MADERA_RATE_ENUM("ISRC2 FSH", madera_isrc_fsh[1]),
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP1L", MADERA_DSP1LMIX_INPUT_1_SOURCE),
273*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("DSP1R", MADERA_DSP1RMIX_INPUT_1_SOURCE),
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Generator Volume", MADERA_COMFORT_NOISE_GENERATOR,
276*4882a593Smuzhiyun 	       MADERA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, madera_noise_tlv),
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT1L", MADERA_OUT1LMIX_INPUT_1_SOURCE),
279*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("HPOUT1R", MADERA_OUT1RMIX_INPUT_1_SOURCE),
280*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKOUTL", MADERA_OUT4LMIX_INPUT_1_SOURCE),
281*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT1L", MADERA_OUT5LMIX_INPUT_1_SOURCE),
282*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("SPKDAT1R", MADERA_OUT5RMIX_INPUT_1_SOURCE),
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun SOC_SINGLE("HPOUT1 SC Protect Switch", MADERA_HP1_SHORT_CIRCUIT_CTRL,
285*4882a593Smuzhiyun 	   MADERA_HP1_SC_ENA_SHIFT, 1, 0),
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun SOC_SINGLE("SPKDAT1 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_5L,
288*4882a593Smuzhiyun 	   MADERA_OUT5_OSR_SHIFT, 1, 0),
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun SOC_DOUBLE_R("HPOUT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_1L,
291*4882a593Smuzhiyun 	     MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_MUTE_SHIFT, 1, 1),
292*4882a593Smuzhiyun SOC_SINGLE("Speaker Digital Switch", MADERA_DAC_DIGITAL_VOLUME_4L,
293*4882a593Smuzhiyun 	   MADERA_OUT4L_MUTE_SHIFT, 1, 1),
294*4882a593Smuzhiyun SOC_DOUBLE_R("SPKDAT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_5L,
295*4882a593Smuzhiyun 	     MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_MUTE_SHIFT, 1, 1),
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_1L,
298*4882a593Smuzhiyun 		 MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_VOL_SHIFT,
299*4882a593Smuzhiyun 		 0xbf, 0, madera_digital_tlv),
300*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker Digital Volume", MADERA_DAC_DIGITAL_VOLUME_4L,
301*4882a593Smuzhiyun 	       MADERA_OUT4L_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
302*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_5L,
303*4882a593Smuzhiyun 		 MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_VOL_SHIFT,
304*4882a593Smuzhiyun 		 0xbf, 0, madera_digital_tlv),
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun SOC_DOUBLE("SPKDAT1 Switch", MADERA_PDM_SPK1_CTRL_1, MADERA_SPK1L_MUTE_SHIFT,
307*4882a593Smuzhiyun 	   MADERA_SPK1R_MUTE_SHIFT, 1, 1),
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun SOC_ENUM("Output Ramp Up", madera_out_vi_ramp),
310*4882a593Smuzhiyun SOC_ENUM("Output Ramp Down", madera_out_vd_ramp),
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun SOC_SINGLE("Noise Gate Switch", MADERA_NOISE_GATE_CONTROL,
313*4882a593Smuzhiyun 	   MADERA_NGATE_ENA_SHIFT, 1, 0),
314*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Gate Threshold Volume", MADERA_NOISE_GATE_CONTROL,
315*4882a593Smuzhiyun 	       MADERA_NGATE_THR_SHIFT, 7, 1, madera_ng_tlv),
316*4882a593Smuzhiyun SOC_ENUM("Noise Gate Hold", madera_ng_hold),
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun SOC_SINGLE_BOOL_EXT("IN1 LP Mode Switch", 0,
319*4882a593Smuzhiyun 		    cs47l15_in1_adc_get, cs47l15_in1_adc_put),
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun CS47L15_NG_SRC("HPOUT1L", MADERA_NOISE_GATE_SELECT_1L),
322*4882a593Smuzhiyun CS47L15_NG_SRC("HPOUT1R", MADERA_NOISE_GATE_SELECT_1R),
323*4882a593Smuzhiyun CS47L15_NG_SRC("SPKOUTL", MADERA_NOISE_GATE_SELECT_4L),
324*4882a593Smuzhiyun CS47L15_NG_SRC("SPKDAT1L", MADERA_NOISE_GATE_SELECT_5L),
325*4882a593Smuzhiyun CS47L15_NG_SRC("SPKDAT1R", MADERA_NOISE_GATE_SELECT_5R),
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX1", MADERA_AIF1TX1MIX_INPUT_1_SOURCE),
328*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX2", MADERA_AIF1TX2MIX_INPUT_1_SOURCE),
329*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX3", MADERA_AIF1TX3MIX_INPUT_1_SOURCE),
330*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX4", MADERA_AIF1TX4MIX_INPUT_1_SOURCE),
331*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX5", MADERA_AIF1TX5MIX_INPUT_1_SOURCE),
332*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF1TX6", MADERA_AIF1TX6MIX_INPUT_1_SOURCE),
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX1", MADERA_AIF2TX1MIX_INPUT_1_SOURCE),
335*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX2", MADERA_AIF2TX2MIX_INPUT_1_SOURCE),
336*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX3", MADERA_AIF2TX3MIX_INPUT_1_SOURCE),
337*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF2TX4", MADERA_AIF2TX4MIX_INPUT_1_SOURCE),
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX1", MADERA_AIF3TX1MIX_INPUT_1_SOURCE),
340*4882a593Smuzhiyun MADERA_MIXER_CONTROLS("AIF3TX2", MADERA_AIF3TX2MIX_INPUT_1_SOURCE),
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun MADERA_GAINMUX_CONTROLS("SPDIF1TX1", MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE),
343*4882a593Smuzhiyun MADERA_GAINMUX_CONTROLS("SPDIF1TX2", MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE),
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun WM_ADSP_FW_CONTROL("DSP1", 0),
346*4882a593Smuzhiyun };
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ1, MADERA_EQ1MIX_INPUT_1_SOURCE);
349*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ2, MADERA_EQ2MIX_INPUT_1_SOURCE);
350*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ3, MADERA_EQ3MIX_INPUT_1_SOURCE);
351*4882a593Smuzhiyun MADERA_MIXER_ENUMS(EQ4, MADERA_EQ4MIX_INPUT_1_SOURCE);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC1L, MADERA_DRC1LMIX_INPUT_1_SOURCE);
354*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC1R, MADERA_DRC1RMIX_INPUT_1_SOURCE);
355*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC2L, MADERA_DRC2LMIX_INPUT_1_SOURCE);
356*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DRC2R, MADERA_DRC2RMIX_INPUT_1_SOURCE);
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF1, MADERA_HPLP1MIX_INPUT_1_SOURCE);
359*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF2, MADERA_HPLP2MIX_INPUT_1_SOURCE);
360*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF3, MADERA_HPLP3MIX_INPUT_1_SOURCE);
361*4882a593Smuzhiyun MADERA_MIXER_ENUMS(LHPF4, MADERA_HPLP4MIX_INPUT_1_SOURCE);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP1L, MADERA_DSP1LMIX_INPUT_1_SOURCE);
364*4882a593Smuzhiyun MADERA_MIXER_ENUMS(DSP1R, MADERA_DSP1RMIX_INPUT_1_SOURCE);
365*4882a593Smuzhiyun MADERA_DSP_AUX_ENUMS(DSP1, MADERA_DSP1AUX1MIX_INPUT_1_SOURCE);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun MADERA_MIXER_ENUMS(PWM1, MADERA_PWM1MIX_INPUT_1_SOURCE);
368*4882a593Smuzhiyun MADERA_MIXER_ENUMS(PWM2, MADERA_PWM2MIX_INPUT_1_SOURCE);
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT1L, MADERA_OUT1LMIX_INPUT_1_SOURCE);
371*4882a593Smuzhiyun MADERA_MIXER_ENUMS(OUT1R, MADERA_OUT1RMIX_INPUT_1_SOURCE);
372*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKOUTL, MADERA_OUT4LMIX_INPUT_1_SOURCE);
373*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT1L, MADERA_OUT5LMIX_INPUT_1_SOURCE);
374*4882a593Smuzhiyun MADERA_MIXER_ENUMS(SPKDAT1R, MADERA_OUT5RMIX_INPUT_1_SOURCE);
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX1, MADERA_AIF1TX1MIX_INPUT_1_SOURCE);
377*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX2, MADERA_AIF1TX2MIX_INPUT_1_SOURCE);
378*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX3, MADERA_AIF1TX3MIX_INPUT_1_SOURCE);
379*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX4, MADERA_AIF1TX4MIX_INPUT_1_SOURCE);
380*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX5, MADERA_AIF1TX5MIX_INPUT_1_SOURCE);
381*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF1TX6, MADERA_AIF1TX6MIX_INPUT_1_SOURCE);
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX1, MADERA_AIF2TX1MIX_INPUT_1_SOURCE);
384*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX2, MADERA_AIF2TX2MIX_INPUT_1_SOURCE);
385*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX3, MADERA_AIF2TX3MIX_INPUT_1_SOURCE);
386*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF2TX4, MADERA_AIF2TX4MIX_INPUT_1_SOURCE);
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX1, MADERA_AIF3TX1MIX_INPUT_1_SOURCE);
389*4882a593Smuzhiyun MADERA_MIXER_ENUMS(AIF3TX2, MADERA_AIF3TX2MIX_INPUT_1_SOURCE);
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun MADERA_MUX_ENUMS(SPD1TX1, MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE);
392*4882a593Smuzhiyun MADERA_MUX_ENUMS(SPD1TX2, MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE);
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT1, MADERA_ISRC1INT1MIX_INPUT_1_SOURCE);
395*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT2, MADERA_ISRC1INT2MIX_INPUT_1_SOURCE);
396*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT3, MADERA_ISRC1INT3MIX_INPUT_1_SOURCE);
397*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1INT4, MADERA_ISRC1INT4MIX_INPUT_1_SOURCE);
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC1, MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE);
400*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC2, MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE);
401*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC3, MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE);
402*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC1DEC4, MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT1, MADERA_ISRC2INT1MIX_INPUT_1_SOURCE);
405*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT2, MADERA_ISRC2INT2MIX_INPUT_1_SOURCE);
406*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT3, MADERA_ISRC2INT3MIX_INPUT_1_SOURCE);
407*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2INT4, MADERA_ISRC2INT4MIX_INPUT_1_SOURCE);
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC1, MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE);
410*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC2, MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE);
411*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC3, MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE);
412*4882a593Smuzhiyun MADERA_MUX_ENUMS(ISRC2DEC4, MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE);
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun static const char * const cs47l15_aec_loopback_texts[] = {
415*4882a593Smuzhiyun 	"HPOUT1L", "HPOUT1R", "SPKOUTL", "SPKDAT1L", "SPKDAT1R",
416*4882a593Smuzhiyun };
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun static const unsigned int cs47l15_aec_loopback_values[] = {
419*4882a593Smuzhiyun 	0, 1, 6, 8, 9,
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun static const struct soc_enum cs47l15_aec1_loopback =
423*4882a593Smuzhiyun 	SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_1,
424*4882a593Smuzhiyun 			      MADERA_AEC1_LOOPBACK_SRC_SHIFT, 0xf,
425*4882a593Smuzhiyun 			      ARRAY_SIZE(cs47l15_aec_loopback_texts),
426*4882a593Smuzhiyun 			      cs47l15_aec_loopback_texts,
427*4882a593Smuzhiyun 			      cs47l15_aec_loopback_values);
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun static const struct soc_enum cs47l15_aec2_loopback =
430*4882a593Smuzhiyun 	SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_2,
431*4882a593Smuzhiyun 			      MADERA_AEC2_LOOPBACK_SRC_SHIFT, 0xf,
432*4882a593Smuzhiyun 			      ARRAY_SIZE(cs47l15_aec_loopback_texts),
433*4882a593Smuzhiyun 			      cs47l15_aec_loopback_texts,
434*4882a593Smuzhiyun 			      cs47l15_aec_loopback_values);
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun static const struct snd_kcontrol_new cs47l15_aec_loopback_mux[] = {
437*4882a593Smuzhiyun 	SOC_DAPM_ENUM("AEC1 Loopback", cs47l15_aec1_loopback),
438*4882a593Smuzhiyun 	SOC_DAPM_ENUM("AEC2 Loopback", cs47l15_aec2_loopback),
439*4882a593Smuzhiyun };
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun static const struct snd_soc_dapm_widget cs47l15_dapm_widgets[] = {
442*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SYSCLK", MADERA_SYSTEM_CLOCK_1, MADERA_SYSCLK_ENA_SHIFT,
443*4882a593Smuzhiyun 		    0, madera_sysclk_ev,
444*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
445*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
446*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OPCLK", MADERA_OUTPUT_SYSTEM_CLOCK,
447*4882a593Smuzhiyun 		    MADERA_OPCLK_ENA_SHIFT, 0, NULL, 0),
448*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSPCLK", MADERA_DSP_CLOCK_1, MADERA_DSP_CLK_ENA_SHIFT,
449*4882a593Smuzhiyun 		    0, madera_clk_ev,
450*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD1", 20, 0),
453*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
454*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDD", 0, 0),
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1", MADERA_MIC_BIAS_CTRL_1,
457*4882a593Smuzhiyun 		    MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1A", MADERA_MIC_BIAS_CTRL_5,
460*4882a593Smuzhiyun 		    MADERA_MICB1A_ENA_SHIFT, 0, NULL, 0),
461*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1B", MADERA_MIC_BIAS_CTRL_5,
462*4882a593Smuzhiyun 		    MADERA_MICB1B_ENA_SHIFT, 0, NULL, 0),
463*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1C", MADERA_MIC_BIAS_CTRL_5,
464*4882a593Smuzhiyun 		    MADERA_MICB1C_ENA_SHIFT, 0, NULL, 0),
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("FXCLK", SND_SOC_NOPM,
467*4882a593Smuzhiyun 		    MADERA_DOM_GRP_FX, 0,
468*4882a593Smuzhiyun 		    madera_domain_clk_ev,
469*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
470*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC1CLK", SND_SOC_NOPM,
471*4882a593Smuzhiyun 		    MADERA_DOM_GRP_ISRC1, 0,
472*4882a593Smuzhiyun 		    madera_domain_clk_ev,
473*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
474*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("ISRC2CLK", SND_SOC_NOPM,
475*4882a593Smuzhiyun 		    MADERA_DOM_GRP_ISRC2, 0,
476*4882a593Smuzhiyun 		    madera_domain_clk_ev,
477*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
478*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OUTCLK", SND_SOC_NOPM,
479*4882a593Smuzhiyun 		    MADERA_DOM_GRP_OUT, 0,
480*4882a593Smuzhiyun 		    madera_domain_clk_ev,
481*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
482*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("SPDCLK", SND_SOC_NOPM,
483*4882a593Smuzhiyun 		    MADERA_DOM_GRP_SPD, 0,
484*4882a593Smuzhiyun 		    madera_domain_clk_ev,
485*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
486*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM,
487*4882a593Smuzhiyun 		    MADERA_DOM_GRP_DSP1, 0,
488*4882a593Smuzhiyun 		    madera_domain_clk_ev,
489*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
490*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF1TXCLK", SND_SOC_NOPM,
491*4882a593Smuzhiyun 		    MADERA_DOM_GRP_AIF1, 0,
492*4882a593Smuzhiyun 		    madera_domain_clk_ev,
493*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
494*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF2TXCLK", SND_SOC_NOPM,
495*4882a593Smuzhiyun 		    MADERA_DOM_GRP_AIF2, 0,
496*4882a593Smuzhiyun 		    madera_domain_clk_ev,
497*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
498*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("AIF3TXCLK", SND_SOC_NOPM,
499*4882a593Smuzhiyun 		    MADERA_DOM_GRP_AIF3, 0,
500*4882a593Smuzhiyun 		    madera_domain_clk_ev,
501*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
502*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("PWMCLK", SND_SOC_NOPM,
503*4882a593Smuzhiyun 		    MADERA_DOM_GRP_PWM, 0,
504*4882a593Smuzhiyun 		    madera_domain_clk_ev,
505*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("TONE"),
508*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("NOISE"),
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ALN"),
511*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ALP"),
512*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BLN"),
513*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BLP"),
514*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ARN"),
515*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1ARP"),
516*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BRN"),
517*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1BRP"),
518*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2N"),
519*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2P"),
520*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("SPKRXDAT"),
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[0]),
523*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[1]),
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
526*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
529*4882a593Smuzhiyun SND_SOC_DAPM_MUX("IN2R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
532*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("DSP Trigger Out"),
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun SND_SOC_DAPM_DEMUX("HPOUT1 Demux", SND_SOC_NOPM, 0, 0, &cs47l15_outdemux),
537*4882a593Smuzhiyun SND_SOC_DAPM_MUX("HPOUT1 Mono Mux", SND_SOC_NOPM, 0, 0, &cs47l15_outdemux),
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun SND_SOC_DAPM_PGA("PWM1 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM1_ENA_SHIFT,
540*4882a593Smuzhiyun 		 0, NULL, 0),
541*4882a593Smuzhiyun SND_SOC_DAPM_PGA("PWM2 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM2_ENA_SHIFT,
542*4882a593Smuzhiyun 		 0, NULL, 0),
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
545*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX1_ENA_SHIFT, 0),
546*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
547*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX2_ENA_SHIFT, 0),
548*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
549*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX3_ENA_SHIFT, 0),
550*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
551*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX4_ENA_SHIFT, 0),
552*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
553*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX5_ENA_SHIFT, 0),
554*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
555*4882a593Smuzhiyun 		     MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX6_ENA_SHIFT, 0),
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
558*4882a593Smuzhiyun 		     MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX1_ENA_SHIFT, 0),
559*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
560*4882a593Smuzhiyun 		     MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX2_ENA_SHIFT, 0),
561*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
562*4882a593Smuzhiyun 		     MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX3_ENA_SHIFT, 0),
563*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
564*4882a593Smuzhiyun 		     MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX4_ENA_SHIFT, 0),
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
567*4882a593Smuzhiyun 		     MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX1_ENA_SHIFT, 0),
568*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
569*4882a593Smuzhiyun 		     MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX2_ENA_SHIFT, 0),
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
572*4882a593Smuzhiyun 		   MADERA_OUT1L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
573*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
574*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
575*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
576*4882a593Smuzhiyun 		   MADERA_OUT1R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
577*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
578*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
579*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
580*4882a593Smuzhiyun 		   MADERA_OUT4L_ENA_SHIFT, 0, NULL, 0, madera_spk_ev,
581*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
582*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT5L", MADERA_OUTPUT_ENABLES_1,
583*4882a593Smuzhiyun 		   MADERA_OUT5L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
584*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
585*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("OUT5R", MADERA_OUTPUT_ENABLES_1,
586*4882a593Smuzhiyun 		   MADERA_OUT5R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
587*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPD1TX1", MADERA_SPD1_TX_CONTROL,
590*4882a593Smuzhiyun 		 MADERA_SPD1_VAL1_SHIFT, 0, NULL, 0),
591*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPD1TX2", MADERA_SPD1_TX_CONTROL,
592*4882a593Smuzhiyun 		 MADERA_SPD1_VAL2_SHIFT, 0, NULL, 0),
593*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("SPD1", MADERA_SPD1_TX_CONTROL,
594*4882a593Smuzhiyun 		     MADERA_SPD1_ENA_SHIFT, 0, NULL, 0),
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun /*
597*4882a593Smuzhiyun  * mux_in widgets : arranged in the order of sources
598*4882a593Smuzhiyun  * specified in MADERA_MIXER_INPUT_ROUTES
599*4882a593Smuzhiyun  */
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Noise Generator", MADERA_COMFORT_NOISE_GENERATOR,
602*4882a593Smuzhiyun 		 MADERA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator 1", MADERA_TONE_GENERATOR_1,
605*4882a593Smuzhiyun 		 MADERA_TONE1_ENA_SHIFT, 0, NULL, 0),
606*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator 2", MADERA_TONE_GENERATOR_1,
607*4882a593Smuzhiyun 		 MADERA_TONE2_ENA_SHIFT, 0, NULL, 0),
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("HAPTICS"),
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun SND_SOC_DAPM_MUX("AEC1 Loopback", MADERA_DAC_AEC_CONTROL_1,
612*4882a593Smuzhiyun 		 MADERA_AEC1_LOOPBACK_ENA_SHIFT, 0,
613*4882a593Smuzhiyun 		 &cs47l15_aec_loopback_mux[0]),
614*4882a593Smuzhiyun SND_SOC_DAPM_MUX("AEC2 Loopback", MADERA_DAC_AEC_CONTROL_2,
615*4882a593Smuzhiyun 		 MADERA_AEC2_LOOPBACK_ENA_SHIFT, 0,
616*4882a593Smuzhiyun 		 &cs47l15_aec_loopback_mux[1]),
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN1L", MADERA_INPUT_ENABLES, MADERA_IN1L_ENA_SHIFT,
619*4882a593Smuzhiyun 		   0, NULL, 0, madera_in_ev,
620*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
621*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
622*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN1R", MADERA_INPUT_ENABLES, MADERA_IN1R_ENA_SHIFT,
623*4882a593Smuzhiyun 		   0, NULL, 0, madera_in_ev,
624*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
625*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
626*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN2L", MADERA_INPUT_ENABLES, MADERA_IN2L_ENA_SHIFT,
627*4882a593Smuzhiyun 		   0, NULL, 0, madera_in_ev,
628*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
629*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
630*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("IN2R", MADERA_INPUT_ENABLES, MADERA_IN2R_ENA_SHIFT,
631*4882a593Smuzhiyun 		   0, NULL, 0, madera_in_ev,
632*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
633*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
636*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX1_ENA_SHIFT, 0),
637*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
638*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX2_ENA_SHIFT, 0),
639*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
640*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX3_ENA_SHIFT, 0),
641*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
642*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX4_ENA_SHIFT, 0),
643*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
644*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX5_ENA_SHIFT, 0),
645*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
646*4882a593Smuzhiyun 		    MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX6_ENA_SHIFT, 0),
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
649*4882a593Smuzhiyun 		    MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX1_ENA_SHIFT, 0),
650*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
651*4882a593Smuzhiyun 		    MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX2_ENA_SHIFT, 0),
652*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
653*4882a593Smuzhiyun 		    MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX3_ENA_SHIFT, 0),
654*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
655*4882a593Smuzhiyun 		    MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX4_ENA_SHIFT, 0),
656*4882a593Smuzhiyun 
657*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
658*4882a593Smuzhiyun 		    MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX1_ENA_SHIFT, 0),
659*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
660*4882a593Smuzhiyun 		    MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX2_ENA_SHIFT, 0),
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ1", MADERA_EQ1_1, MADERA_EQ1_ENA_SHIFT, 0, NULL, 0),
663*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ2", MADERA_EQ2_1, MADERA_EQ2_ENA_SHIFT, 0, NULL, 0),
664*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ3", MADERA_EQ3_1, MADERA_EQ3_ENA_SHIFT, 0, NULL, 0),
665*4882a593Smuzhiyun SND_SOC_DAPM_PGA("EQ4", MADERA_EQ4_1, MADERA_EQ4_ENA_SHIFT, 0, NULL, 0),
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC1L", MADERA_DRC1_CTRL1, MADERA_DRC1L_ENA_SHIFT, 0,
668*4882a593Smuzhiyun 		 NULL, 0),
669*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC1R", MADERA_DRC1_CTRL1, MADERA_DRC1R_ENA_SHIFT, 0,
670*4882a593Smuzhiyun 		 NULL, 0),
671*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC2L", MADERA_DRC2_CTRL1, MADERA_DRC2L_ENA_SHIFT, 0,
672*4882a593Smuzhiyun 		 NULL, 0),
673*4882a593Smuzhiyun SND_SOC_DAPM_PGA("DRC2R", MADERA_DRC2_CTRL1, MADERA_DRC2R_ENA_SHIFT, 0,
674*4882a593Smuzhiyun 		 NULL, 0),
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF1", MADERA_HPLPF1_1, MADERA_LHPF1_ENA_SHIFT, 0, NULL, 0),
677*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF2", MADERA_HPLPF2_1, MADERA_LHPF2_ENA_SHIFT, 0, NULL, 0),
678*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF3", MADERA_HPLPF3_1, MADERA_LHPF3_ENA_SHIFT, 0, NULL, 0),
679*4882a593Smuzhiyun SND_SOC_DAPM_PGA("LHPF4", MADERA_HPLPF4_1, MADERA_LHPF4_ENA_SHIFT, 0, NULL, 0),
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC1", MADERA_ISRC_1_CTRL_3,
682*4882a593Smuzhiyun 		 MADERA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
683*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC2", MADERA_ISRC_1_CTRL_3,
684*4882a593Smuzhiyun 		 MADERA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
685*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC3", MADERA_ISRC_1_CTRL_3,
686*4882a593Smuzhiyun 		 MADERA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
687*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1DEC4", MADERA_ISRC_1_CTRL_3,
688*4882a593Smuzhiyun 		 MADERA_ISRC1_DEC4_ENA_SHIFT, 0, NULL, 0),
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT1", MADERA_ISRC_1_CTRL_3,
691*4882a593Smuzhiyun 		 MADERA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
692*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT2", MADERA_ISRC_1_CTRL_3,
693*4882a593Smuzhiyun 		 MADERA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
694*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT3", MADERA_ISRC_1_CTRL_3,
695*4882a593Smuzhiyun 		 MADERA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
696*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC1INT4", MADERA_ISRC_1_CTRL_3,
697*4882a593Smuzhiyun 		 MADERA_ISRC1_INT4_ENA_SHIFT, 0, NULL, 0),
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC1", MADERA_ISRC_2_CTRL_3,
700*4882a593Smuzhiyun 		 MADERA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
701*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC2", MADERA_ISRC_2_CTRL_3,
702*4882a593Smuzhiyun 		 MADERA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
703*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC3", MADERA_ISRC_2_CTRL_3,
704*4882a593Smuzhiyun 		 MADERA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0),
705*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2DEC4", MADERA_ISRC_2_CTRL_3,
706*4882a593Smuzhiyun 		 MADERA_ISRC2_DEC4_ENA_SHIFT, 0, NULL, 0),
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT1", MADERA_ISRC_2_CTRL_3,
709*4882a593Smuzhiyun 		 MADERA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
710*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT2", MADERA_ISRC_2_CTRL_3,
711*4882a593Smuzhiyun 		 MADERA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
712*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT3", MADERA_ISRC_2_CTRL_3,
713*4882a593Smuzhiyun 		 MADERA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0),
714*4882a593Smuzhiyun SND_SOC_DAPM_PGA("ISRC2INT4", MADERA_ISRC_2_CTRL_3,
715*4882a593Smuzhiyun 		 MADERA_ISRC2_INT4_ENA_SHIFT, 0, NULL, 0),
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun WM_ADSP2("DSP1", 0, cs47l15_adsp_power_ev),
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun /* end of ordered widget list */
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ1, "EQ1"),
722*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ2, "EQ2"),
723*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ3, "EQ3"),
724*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(EQ4, "EQ4"),
725*4882a593Smuzhiyun 
726*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC1L, "DRC1L"),
727*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC1R, "DRC1R"),
728*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC2L, "DRC2L"),
729*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(DRC2R, "DRC2R"),
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0,
732*4882a593Smuzhiyun 		    &madera_drc_activity_output_mux[0]),
733*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0,
734*4882a593Smuzhiyun 		    &madera_drc_activity_output_mux[1]),
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF1, "LHPF1"),
737*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF2, "LHPF2"),
738*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF3, "LHPF3"),
739*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(LHPF4, "LHPF4"),
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(PWM1, "PWM1"),
742*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(PWM2, "PWM2"),
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
745*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
746*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
747*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
748*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
751*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
752*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
753*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
754*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
755*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
758*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
759*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
760*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
763*4882a593Smuzhiyun MADERA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun MADERA_MUX_WIDGETS(SPD1TX1, "SPDIF1TX1"),
766*4882a593Smuzhiyun MADERA_MUX_WIDGETS(SPD1TX2, "SPDIF1TX2"),
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun MADERA_DSP_WIDGETS(DSP1, "DSP1"),
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0,
771*4882a593Smuzhiyun 		    &madera_dsp_trigger_output_mux[0]),
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
774*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
775*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
776*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
779*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
780*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
781*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
784*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
785*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"),
786*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"),
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
789*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
790*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"),
791*4882a593Smuzhiyun MADERA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"),
792*4882a593Smuzhiyun 
793*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUTL"),
794*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUTR"),
795*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("EPOUTP"),
796*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("EPOUTN"),
797*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTN"),
798*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTP"),
799*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
800*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
801*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPDIF1"),
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MICSUPP"),
804*4882a593Smuzhiyun };
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun #define MADERA_MIXER_INPUT_ROUTES(name)	\
807*4882a593Smuzhiyun 	{ name, "Noise Generator", "Noise Generator" }, \
808*4882a593Smuzhiyun 	{ name, "Tone Generator 1", "Tone Generator 1" }, \
809*4882a593Smuzhiyun 	{ name, "Tone Generator 2", "Tone Generator 2" }, \
810*4882a593Smuzhiyun 	{ name, "Haptics", "HAPTICS" }, \
811*4882a593Smuzhiyun 	{ name, "AEC1", "AEC1 Loopback" }, \
812*4882a593Smuzhiyun 	{ name, "AEC2", "AEC2 Loopback" }, \
813*4882a593Smuzhiyun 	{ name, "IN1L", "IN1L" }, \
814*4882a593Smuzhiyun 	{ name, "IN1R", "IN1R" }, \
815*4882a593Smuzhiyun 	{ name, "IN2L", "IN2L" }, \
816*4882a593Smuzhiyun 	{ name, "IN2R", "IN2R" }, \
817*4882a593Smuzhiyun 	{ name, "AIF1RX1", "AIF1RX1" }, \
818*4882a593Smuzhiyun 	{ name, "AIF1RX2", "AIF1RX2" }, \
819*4882a593Smuzhiyun 	{ name, "AIF1RX3", "AIF1RX3" }, \
820*4882a593Smuzhiyun 	{ name, "AIF1RX4", "AIF1RX4" }, \
821*4882a593Smuzhiyun 	{ name, "AIF1RX5", "AIF1RX5" }, \
822*4882a593Smuzhiyun 	{ name, "AIF1RX6", "AIF1RX6" }, \
823*4882a593Smuzhiyun 	{ name, "AIF2RX1", "AIF2RX1" }, \
824*4882a593Smuzhiyun 	{ name, "AIF2RX2", "AIF2RX2" }, \
825*4882a593Smuzhiyun 	{ name, "AIF2RX3", "AIF2RX3" }, \
826*4882a593Smuzhiyun 	{ name, "AIF2RX4", "AIF2RX4" }, \
827*4882a593Smuzhiyun 	{ name, "AIF3RX1", "AIF3RX1" }, \
828*4882a593Smuzhiyun 	{ name, "AIF3RX2", "AIF3RX2" }, \
829*4882a593Smuzhiyun 	{ name, "EQ1", "EQ1" }, \
830*4882a593Smuzhiyun 	{ name, "EQ2", "EQ2" }, \
831*4882a593Smuzhiyun 	{ name, "EQ3", "EQ3" }, \
832*4882a593Smuzhiyun 	{ name, "EQ4", "EQ4" }, \
833*4882a593Smuzhiyun 	{ name, "DRC1L", "DRC1L" }, \
834*4882a593Smuzhiyun 	{ name, "DRC1R", "DRC1R" }, \
835*4882a593Smuzhiyun 	{ name, "DRC2L", "DRC2L" }, \
836*4882a593Smuzhiyun 	{ name, "DRC2R", "DRC2R" }, \
837*4882a593Smuzhiyun 	{ name, "LHPF1", "LHPF1" }, \
838*4882a593Smuzhiyun 	{ name, "LHPF2", "LHPF2" }, \
839*4882a593Smuzhiyun 	{ name, "LHPF3", "LHPF3" }, \
840*4882a593Smuzhiyun 	{ name, "LHPF4", "LHPF4" }, \
841*4882a593Smuzhiyun 	{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
842*4882a593Smuzhiyun 	{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
843*4882a593Smuzhiyun 	{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
844*4882a593Smuzhiyun 	{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
845*4882a593Smuzhiyun 	{ name, "ISRC1INT1", "ISRC1INT1" }, \
846*4882a593Smuzhiyun 	{ name, "ISRC1INT2", "ISRC1INT2" }, \
847*4882a593Smuzhiyun 	{ name, "ISRC1INT3", "ISRC1INT3" }, \
848*4882a593Smuzhiyun 	{ name, "ISRC1INT4", "ISRC1INT4" }, \
849*4882a593Smuzhiyun 	{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
850*4882a593Smuzhiyun 	{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
851*4882a593Smuzhiyun 	{ name, "ISRC2DEC3", "ISRC2DEC3" }, \
852*4882a593Smuzhiyun 	{ name, "ISRC2DEC4", "ISRC2DEC4" }, \
853*4882a593Smuzhiyun 	{ name, "ISRC2INT1", "ISRC2INT1" }, \
854*4882a593Smuzhiyun 	{ name, "ISRC2INT2", "ISRC2INT2" }, \
855*4882a593Smuzhiyun 	{ name, "ISRC2INT3", "ISRC2INT3" }, \
856*4882a593Smuzhiyun 	{ name, "ISRC2INT4", "ISRC2INT4" }, \
857*4882a593Smuzhiyun 	{ name, "DSP1.1", "DSP1" }, \
858*4882a593Smuzhiyun 	{ name, "DSP1.2", "DSP1" }, \
859*4882a593Smuzhiyun 	{ name, "DSP1.3", "DSP1" }, \
860*4882a593Smuzhiyun 	{ name, "DSP1.4", "DSP1" }, \
861*4882a593Smuzhiyun 	{ name, "DSP1.5", "DSP1" }, \
862*4882a593Smuzhiyun 	{ name, "DSP1.6", "DSP1" }
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun static const struct snd_soc_dapm_route cs47l15_dapm_routes[] = {
865*4882a593Smuzhiyun 	/* Internal clock domains */
866*4882a593Smuzhiyun 	{ "EQ1", NULL, "FXCLK" },
867*4882a593Smuzhiyun 	{ "EQ2", NULL, "FXCLK" },
868*4882a593Smuzhiyun 	{ "EQ3", NULL, "FXCLK" },
869*4882a593Smuzhiyun 	{ "EQ4", NULL, "FXCLK" },
870*4882a593Smuzhiyun 	{ "DRC1L", NULL, "FXCLK" },
871*4882a593Smuzhiyun 	{ "DRC1R", NULL, "FXCLK" },
872*4882a593Smuzhiyun 	{ "DRC2L", NULL, "FXCLK" },
873*4882a593Smuzhiyun 	{ "DRC2R", NULL, "FXCLK" },
874*4882a593Smuzhiyun 	{ "LHPF1", NULL, "FXCLK" },
875*4882a593Smuzhiyun 	{ "LHPF2", NULL, "FXCLK" },
876*4882a593Smuzhiyun 	{ "LHPF3", NULL, "FXCLK" },
877*4882a593Smuzhiyun 	{ "LHPF4", NULL, "FXCLK" },
878*4882a593Smuzhiyun 	{ "PWM1 Mixer", NULL, "PWMCLK" },
879*4882a593Smuzhiyun 	{ "PWM2 Mixer", NULL, "PWMCLK" },
880*4882a593Smuzhiyun 	{ "OUT1L", NULL, "OUTCLK" },
881*4882a593Smuzhiyun 	{ "OUT1R", NULL, "OUTCLK" },
882*4882a593Smuzhiyun 	{ "OUT4L", NULL, "OUTCLK" },
883*4882a593Smuzhiyun 	{ "OUT5L", NULL, "OUTCLK" },
884*4882a593Smuzhiyun 	{ "OUT5R", NULL, "OUTCLK" },
885*4882a593Smuzhiyun 	{ "AIF1TX1", NULL, "AIF1TXCLK" },
886*4882a593Smuzhiyun 	{ "AIF1TX2", NULL, "AIF1TXCLK" },
887*4882a593Smuzhiyun 	{ "AIF1TX3", NULL, "AIF1TXCLK" },
888*4882a593Smuzhiyun 	{ "AIF1TX4", NULL, "AIF1TXCLK" },
889*4882a593Smuzhiyun 	{ "AIF1TX5", NULL, "AIF1TXCLK" },
890*4882a593Smuzhiyun 	{ "AIF1TX6", NULL, "AIF1TXCLK" },
891*4882a593Smuzhiyun 	{ "AIF2TX1", NULL, "AIF2TXCLK" },
892*4882a593Smuzhiyun 	{ "AIF2TX2", NULL, "AIF2TXCLK" },
893*4882a593Smuzhiyun 	{ "AIF2TX3", NULL, "AIF2TXCLK" },
894*4882a593Smuzhiyun 	{ "AIF2TX4", NULL, "AIF2TXCLK" },
895*4882a593Smuzhiyun 	{ "AIF3TX1", NULL, "AIF3TXCLK" },
896*4882a593Smuzhiyun 	{ "AIF3TX2", NULL, "AIF3TXCLK" },
897*4882a593Smuzhiyun 	{ "SPD1TX1", NULL, "SPDCLK" },
898*4882a593Smuzhiyun 	{ "SPD1TX2", NULL, "SPDCLK" },
899*4882a593Smuzhiyun 	{ "DSP1", NULL, "DSP1CLK" },
900*4882a593Smuzhiyun 	{ "ISRC1DEC1", NULL, "ISRC1CLK" },
901*4882a593Smuzhiyun 	{ "ISRC1DEC2", NULL, "ISRC1CLK" },
902*4882a593Smuzhiyun 	{ "ISRC1DEC3", NULL, "ISRC1CLK" },
903*4882a593Smuzhiyun 	{ "ISRC1DEC4", NULL, "ISRC1CLK" },
904*4882a593Smuzhiyun 	{ "ISRC1INT1", NULL, "ISRC1CLK" },
905*4882a593Smuzhiyun 	{ "ISRC1INT2", NULL, "ISRC1CLK" },
906*4882a593Smuzhiyun 	{ "ISRC1INT3", NULL, "ISRC1CLK" },
907*4882a593Smuzhiyun 	{ "ISRC1INT4", NULL, "ISRC1CLK" },
908*4882a593Smuzhiyun 	{ "ISRC2DEC1", NULL, "ISRC2CLK" },
909*4882a593Smuzhiyun 	{ "ISRC2DEC2", NULL, "ISRC2CLK" },
910*4882a593Smuzhiyun 	{ "ISRC2DEC3", NULL, "ISRC2CLK" },
911*4882a593Smuzhiyun 	{ "ISRC2DEC4", NULL, "ISRC2CLK" },
912*4882a593Smuzhiyun 	{ "ISRC2INT1", NULL, "ISRC2CLK" },
913*4882a593Smuzhiyun 	{ "ISRC2INT2", NULL, "ISRC2CLK" },
914*4882a593Smuzhiyun 	{ "ISRC2INT3", NULL, "ISRC2CLK" },
915*4882a593Smuzhiyun 	{ "ISRC2INT4", NULL, "ISRC2CLK" },
916*4882a593Smuzhiyun 
917*4882a593Smuzhiyun 	{ "OUT1L", NULL, "CPVDD1" },
918*4882a593Smuzhiyun 	{ "OUT1R", NULL, "CPVDD1" },
919*4882a593Smuzhiyun 	{ "OUT4L", NULL, "SPKVDD" },
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun 	{ "OUT1L", NULL, "SYSCLK" },
922*4882a593Smuzhiyun 	{ "OUT1R", NULL, "SYSCLK" },
923*4882a593Smuzhiyun 	{ "OUT4L", NULL, "SYSCLK" },
924*4882a593Smuzhiyun 	{ "OUT5L", NULL, "SYSCLK" },
925*4882a593Smuzhiyun 	{ "OUT5R", NULL, "SYSCLK" },
926*4882a593Smuzhiyun 
927*4882a593Smuzhiyun 	{ "SPD1", NULL, "SYSCLK" },
928*4882a593Smuzhiyun 	{ "SPD1", NULL, "SPD1TX1" },
929*4882a593Smuzhiyun 	{ "SPD1", NULL, "SPD1TX2" },
930*4882a593Smuzhiyun 
931*4882a593Smuzhiyun 	{ "IN1L", NULL, "SYSCLK" },
932*4882a593Smuzhiyun 	{ "IN1R", NULL, "SYSCLK" },
933*4882a593Smuzhiyun 	{ "IN2L", NULL, "SYSCLK" },
934*4882a593Smuzhiyun 	{ "IN2R", NULL, "SYSCLK" },
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun 	{ "MICBIAS1", NULL, "MICVDD" },
937*4882a593Smuzhiyun 
938*4882a593Smuzhiyun 	{ "MICBIAS1A", NULL, "MICBIAS1" },
939*4882a593Smuzhiyun 	{ "MICBIAS1B", NULL, "MICBIAS1" },
940*4882a593Smuzhiyun 	{ "MICBIAS1C", NULL, "MICBIAS1" },
941*4882a593Smuzhiyun 
942*4882a593Smuzhiyun 	{ "Noise Generator", NULL, "SYSCLK" },
943*4882a593Smuzhiyun 	{ "Tone Generator 1", NULL, "SYSCLK" },
944*4882a593Smuzhiyun 	{ "Tone Generator 2", NULL, "SYSCLK" },
945*4882a593Smuzhiyun 
946*4882a593Smuzhiyun 	{ "Noise Generator", NULL, "NOISE" },
947*4882a593Smuzhiyun 	{ "Tone Generator 1", NULL, "TONE" },
948*4882a593Smuzhiyun 	{ "Tone Generator 2", NULL, "TONE" },
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX1" },
951*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX2" },
952*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX3" },
953*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX4" },
954*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX5" },
955*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "AIF1TX6" },
956*4882a593Smuzhiyun 
957*4882a593Smuzhiyun 	{ "AIF1RX1", NULL, "AIF1 Playback" },
958*4882a593Smuzhiyun 	{ "AIF1RX2", NULL, "AIF1 Playback" },
959*4882a593Smuzhiyun 	{ "AIF1RX3", NULL, "AIF1 Playback" },
960*4882a593Smuzhiyun 	{ "AIF1RX4", NULL, "AIF1 Playback" },
961*4882a593Smuzhiyun 	{ "AIF1RX5", NULL, "AIF1 Playback" },
962*4882a593Smuzhiyun 	{ "AIF1RX6", NULL, "AIF1 Playback" },
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 	{ "AIF2 Capture", NULL, "AIF2TX1" },
965*4882a593Smuzhiyun 	{ "AIF2 Capture", NULL, "AIF2TX2" },
966*4882a593Smuzhiyun 	{ "AIF2 Capture", NULL, "AIF2TX3" },
967*4882a593Smuzhiyun 	{ "AIF2 Capture", NULL, "AIF2TX4" },
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun 	{ "AIF2RX1", NULL, "AIF2 Playback" },
970*4882a593Smuzhiyun 	{ "AIF2RX2", NULL, "AIF2 Playback" },
971*4882a593Smuzhiyun 	{ "AIF2RX3", NULL, "AIF2 Playback" },
972*4882a593Smuzhiyun 	{ "AIF2RX4", NULL, "AIF2 Playback" },
973*4882a593Smuzhiyun 
974*4882a593Smuzhiyun 	{ "AIF3 Capture", NULL, "AIF3TX1" },
975*4882a593Smuzhiyun 	{ "AIF3 Capture", NULL, "AIF3TX2" },
976*4882a593Smuzhiyun 
977*4882a593Smuzhiyun 	{ "AIF3RX1", NULL, "AIF3 Playback" },
978*4882a593Smuzhiyun 	{ "AIF3RX2", NULL, "AIF3 Playback" },
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun 	{ "AIF1 Playback", NULL, "SYSCLK" },
981*4882a593Smuzhiyun 	{ "AIF2 Playback", NULL, "SYSCLK" },
982*4882a593Smuzhiyun 	{ "AIF3 Playback", NULL, "SYSCLK" },
983*4882a593Smuzhiyun 
984*4882a593Smuzhiyun 	{ "AIF1 Capture", NULL, "SYSCLK" },
985*4882a593Smuzhiyun 	{ "AIF2 Capture", NULL, "SYSCLK" },
986*4882a593Smuzhiyun 	{ "AIF3 Capture", NULL, "SYSCLK" },
987*4882a593Smuzhiyun 
988*4882a593Smuzhiyun 	{ "Audio Trace DSP", NULL, "DSP1" },
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun 	{ "IN1L Analog Mux", "A", "IN1ALN" },
991*4882a593Smuzhiyun 	{ "IN1L Analog Mux", "A", "IN1ALP" },
992*4882a593Smuzhiyun 	{ "IN1L Analog Mux", "B", "IN1BLN" },
993*4882a593Smuzhiyun 	{ "IN1L Analog Mux", "B", "IN1BLP" },
994*4882a593Smuzhiyun 	{ "IN1R Analog Mux", "A", "IN1ARN" },
995*4882a593Smuzhiyun 	{ "IN1R Analog Mux", "A", "IN1ARP" },
996*4882a593Smuzhiyun 	{ "IN1R Analog Mux", "B", "IN1BRN" },
997*4882a593Smuzhiyun 	{ "IN1R Analog Mux", "B", "IN1BRP" },
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun 	{ "IN1L Mode", "Analog", "IN1L Analog Mux" },
1000*4882a593Smuzhiyun 	{ "IN1R Mode", "Analog", "IN1R Analog Mux" },
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 	{ "IN1L Mode", "Digital", "IN1ALN" },
1003*4882a593Smuzhiyun 	{ "IN1L Mode", "Digital", "IN1ALP" },
1004*4882a593Smuzhiyun 	{ "IN1R Mode", "Digital", "IN1ALN" },
1005*4882a593Smuzhiyun 	{ "IN1R Mode", "Digital", "IN1ALP" },
1006*4882a593Smuzhiyun 
1007*4882a593Smuzhiyun 	{ "IN1L", NULL, "IN1L Mode" },
1008*4882a593Smuzhiyun 	{ "IN1R", NULL, "IN1R Mode" },
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	{ "IN2L Mode", "Analog", "IN2N" },
1011*4882a593Smuzhiyun 	{ "IN2L Mode", "Analog", "IN2P" },
1012*4882a593Smuzhiyun 
1013*4882a593Smuzhiyun 	{ "IN2L Mode", "Digital", "SPKRXDAT" },
1014*4882a593Smuzhiyun 	{ "IN2R Mode", "Digital", "SPKRXDAT" },
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	{ "IN2L", NULL, "IN2L Mode" },
1017*4882a593Smuzhiyun 	{ "IN2R", NULL, "IN2R Mode" },
1018*4882a593Smuzhiyun 
1019*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1020*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1021*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1022*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1023*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1024*4882a593Smuzhiyun 
1025*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1026*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1029*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1030*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1031*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1032*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1033*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1034*4882a593Smuzhiyun 
1035*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1036*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1037*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
1038*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1041*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1042*4882a593Smuzhiyun 
1043*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("SPD1TX1", "SPDIF1TX1"),
1044*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("SPD1TX2", "SPDIF1TX2"),
1045*4882a593Smuzhiyun 
1046*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("EQ1", "EQ1"),
1047*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("EQ2", "EQ2"),
1048*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("EQ3", "EQ3"),
1049*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("EQ4", "EQ4"),
1050*4882a593Smuzhiyun 
1051*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("DRC1L", "DRC1L"),
1052*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("DRC1R", "DRC1R"),
1053*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("DRC2L", "DRC2L"),
1054*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("DRC2R", "DRC2R"),
1055*4882a593Smuzhiyun 
1056*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("LHPF1", "LHPF1"),
1057*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("LHPF2", "LHPF2"),
1058*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("LHPF3", "LHPF3"),
1059*4882a593Smuzhiyun 	MADERA_MIXER_ROUTES("LHPF4", "LHPF4"),
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	MADERA_DSP_ROUTES("DSP1"),
1062*4882a593Smuzhiyun 
1063*4882a593Smuzhiyun 	{ "DSP Trigger Out", NULL, "DSP1 Trigger Output" },
1064*4882a593Smuzhiyun 
1065*4882a593Smuzhiyun 	{ "DSP1 Trigger Output", "Switch", "DSP1" },
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
1068*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
1069*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
1070*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
1073*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
1074*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
1075*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
1078*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
1079*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"),
1080*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"),
1081*4882a593Smuzhiyun 
1082*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
1083*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
1084*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
1085*4882a593Smuzhiyun 	MADERA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun 	{ "AEC1 Loopback", "HPOUT1L", "OUT1L" },
1088*4882a593Smuzhiyun 	{ "AEC1 Loopback", "HPOUT1R", "OUT1R" },
1089*4882a593Smuzhiyun 	{ "AEC2 Loopback", "HPOUT1L", "OUT1L" },
1090*4882a593Smuzhiyun 	{ "AEC2 Loopback", "HPOUT1R", "OUT1R" },
1091*4882a593Smuzhiyun 	{ "HPOUT1 Demux", NULL, "OUT1L" },
1092*4882a593Smuzhiyun 	{ "HPOUT1 Demux", NULL, "OUT1R" },
1093*4882a593Smuzhiyun 
1094*4882a593Smuzhiyun 	{ "OUT1R", NULL, "HPOUT1 Mono Mux" },
1095*4882a593Smuzhiyun 	{ "HPOUT1 Mono Mux", "EPOUT", "OUT1L" },
1096*4882a593Smuzhiyun 
1097*4882a593Smuzhiyun 	{ "HPOUTL", "HPOUT", "HPOUT1 Demux" },
1098*4882a593Smuzhiyun 	{ "HPOUTR", "HPOUT", "HPOUT1 Demux" },
1099*4882a593Smuzhiyun 	{ "EPOUTP", "EPOUT", "HPOUT1 Demux" },
1100*4882a593Smuzhiyun 	{ "EPOUTN", "EPOUT", "HPOUT1 Demux" },
1101*4882a593Smuzhiyun 
1102*4882a593Smuzhiyun 	{ "AEC1 Loopback", "SPKOUTL", "OUT4L" },
1103*4882a593Smuzhiyun 	{ "AEC2 Loopback", "SPKOUTL", "OUT4L" },
1104*4882a593Smuzhiyun 	{ "SPKOUTN", NULL, "OUT4L" },
1105*4882a593Smuzhiyun 	{ "SPKOUTP", NULL, "OUT4L" },
1106*4882a593Smuzhiyun 
1107*4882a593Smuzhiyun 	{ "AEC1 Loopback", "SPKDAT1L", "OUT5L" },
1108*4882a593Smuzhiyun 	{ "AEC1 Loopback", "SPKDAT1R", "OUT5R" },
1109*4882a593Smuzhiyun 	{ "AEC2 Loopback", "SPKDAT1L", "OUT5L" },
1110*4882a593Smuzhiyun 	{ "AEC2 Loopback", "SPKDAT1R", "OUT5R" },
1111*4882a593Smuzhiyun 	{ "SPKDAT1L", NULL, "OUT5L" },
1112*4882a593Smuzhiyun 	{ "SPKDAT1R", NULL, "OUT5R" },
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 	{ "SPDIF1", NULL, "SPD1" },
1115*4882a593Smuzhiyun 
1116*4882a593Smuzhiyun 	{ "MICSUPP", NULL, "SYSCLK" },
1117*4882a593Smuzhiyun 
1118*4882a593Smuzhiyun 	{ "DRC1 Signal Activity", NULL, "DRC1 Activity Output" },
1119*4882a593Smuzhiyun 	{ "DRC2 Signal Activity", NULL, "DRC2 Activity Output" },
1120*4882a593Smuzhiyun 	{ "DRC1 Activity Output", "Switch", "DRC1L" },
1121*4882a593Smuzhiyun 	{ "DRC1 Activity Output", "Switch", "DRC1R" },
1122*4882a593Smuzhiyun 	{ "DRC2 Activity Output", "Switch", "DRC2L" },
1123*4882a593Smuzhiyun 	{ "DRC2 Activity Output", "Switch", "DRC2R" },
1124*4882a593Smuzhiyun };
1125*4882a593Smuzhiyun 
cs47l15_set_fll(struct snd_soc_component * component,int fll_id,int source,unsigned int fref,unsigned int fout)1126*4882a593Smuzhiyun static int cs47l15_set_fll(struct snd_soc_component *component, int fll_id,
1127*4882a593Smuzhiyun 			   int source, unsigned int fref, unsigned int fout)
1128*4882a593Smuzhiyun {
1129*4882a593Smuzhiyun 	struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
1130*4882a593Smuzhiyun 
1131*4882a593Smuzhiyun 	switch (fll_id) {
1132*4882a593Smuzhiyun 	case MADERA_FLL1_REFCLK:
1133*4882a593Smuzhiyun 		return madera_set_fll_refclk(&cs47l15->fll[0], source, fref,
1134*4882a593Smuzhiyun 					     fout);
1135*4882a593Smuzhiyun 	case MADERA_FLLAO_REFCLK:
1136*4882a593Smuzhiyun 		return madera_set_fll_ao_refclk(&cs47l15->fll[1], source, fref,
1137*4882a593Smuzhiyun 						fout);
1138*4882a593Smuzhiyun 	case MADERA_FLL1_SYNCCLK:
1139*4882a593Smuzhiyun 		return madera_set_fll_syncclk(&cs47l15->fll[0], source, fref,
1140*4882a593Smuzhiyun 					      fout);
1141*4882a593Smuzhiyun 	default:
1142*4882a593Smuzhiyun 		return -EINVAL;
1143*4882a593Smuzhiyun 	}
1144*4882a593Smuzhiyun }
1145*4882a593Smuzhiyun 
1146*4882a593Smuzhiyun static struct snd_soc_dai_driver cs47l15_dai[] = {
1147*4882a593Smuzhiyun 	{
1148*4882a593Smuzhiyun 		.name = "cs47l15-aif1",
1149*4882a593Smuzhiyun 		.id = 1,
1150*4882a593Smuzhiyun 		.base = MADERA_AIF1_BCLK_CTRL,
1151*4882a593Smuzhiyun 		.playback = {
1152*4882a593Smuzhiyun 			.stream_name = "AIF1 Playback",
1153*4882a593Smuzhiyun 			.channels_min = 1,
1154*4882a593Smuzhiyun 			.channels_max = 6,
1155*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1156*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1157*4882a593Smuzhiyun 		},
1158*4882a593Smuzhiyun 		.capture = {
1159*4882a593Smuzhiyun 			.stream_name = "AIF1 Capture",
1160*4882a593Smuzhiyun 			.channels_min = 1,
1161*4882a593Smuzhiyun 			.channels_max = 6,
1162*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1163*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1164*4882a593Smuzhiyun 		 },
1165*4882a593Smuzhiyun 		.ops = &madera_dai_ops,
1166*4882a593Smuzhiyun 		.symmetric_rates = 1,
1167*4882a593Smuzhiyun 		.symmetric_samplebits = 1,
1168*4882a593Smuzhiyun 	},
1169*4882a593Smuzhiyun 	{
1170*4882a593Smuzhiyun 		.name = "cs47l15-aif2",
1171*4882a593Smuzhiyun 		.id = 2,
1172*4882a593Smuzhiyun 		.base = MADERA_AIF2_BCLK_CTRL,
1173*4882a593Smuzhiyun 		.playback = {
1174*4882a593Smuzhiyun 			.stream_name = "AIF2 Playback",
1175*4882a593Smuzhiyun 			.channels_min = 1,
1176*4882a593Smuzhiyun 			.channels_max = 4,
1177*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1178*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1179*4882a593Smuzhiyun 		},
1180*4882a593Smuzhiyun 		.capture = {
1181*4882a593Smuzhiyun 			.stream_name = "AIF2 Capture",
1182*4882a593Smuzhiyun 			.channels_min = 1,
1183*4882a593Smuzhiyun 			.channels_max = 4,
1184*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1185*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1186*4882a593Smuzhiyun 		 },
1187*4882a593Smuzhiyun 		.ops = &madera_dai_ops,
1188*4882a593Smuzhiyun 		.symmetric_rates = 1,
1189*4882a593Smuzhiyun 		.symmetric_samplebits = 1,
1190*4882a593Smuzhiyun 	},
1191*4882a593Smuzhiyun 	{
1192*4882a593Smuzhiyun 		.name = "cs47l15-aif3",
1193*4882a593Smuzhiyun 		.id = 3,
1194*4882a593Smuzhiyun 		.base = MADERA_AIF3_BCLK_CTRL,
1195*4882a593Smuzhiyun 		.playback = {
1196*4882a593Smuzhiyun 			.stream_name = "AIF3 Playback",
1197*4882a593Smuzhiyun 			.channels_min = 1,
1198*4882a593Smuzhiyun 			.channels_max = 2,
1199*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1200*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1201*4882a593Smuzhiyun 		},
1202*4882a593Smuzhiyun 		.capture = {
1203*4882a593Smuzhiyun 			.stream_name = "AIF3 Capture",
1204*4882a593Smuzhiyun 			.channels_min = 1,
1205*4882a593Smuzhiyun 			.channels_max = 2,
1206*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1207*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1208*4882a593Smuzhiyun 		 },
1209*4882a593Smuzhiyun 		.ops = &madera_dai_ops,
1210*4882a593Smuzhiyun 		.symmetric_rates = 1,
1211*4882a593Smuzhiyun 		.symmetric_samplebits = 1,
1212*4882a593Smuzhiyun 	},
1213*4882a593Smuzhiyun 	{
1214*4882a593Smuzhiyun 		.name = "cs47l15-cpu-trace",
1215*4882a593Smuzhiyun 		.capture = {
1216*4882a593Smuzhiyun 			.stream_name = "Audio Trace CPU",
1217*4882a593Smuzhiyun 			.channels_min = 1,
1218*4882a593Smuzhiyun 			.channels_max = 6,
1219*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1220*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1221*4882a593Smuzhiyun 		},
1222*4882a593Smuzhiyun 		.compress_new = snd_soc_new_compress,
1223*4882a593Smuzhiyun 	},
1224*4882a593Smuzhiyun 	{
1225*4882a593Smuzhiyun 		.name = "cs47l15-dsp-trace",
1226*4882a593Smuzhiyun 		.capture = {
1227*4882a593Smuzhiyun 			.stream_name = "Audio Trace DSP",
1228*4882a593Smuzhiyun 			.channels_min = 1,
1229*4882a593Smuzhiyun 			.channels_max = 6,
1230*4882a593Smuzhiyun 			.rates = MADERA_RATES,
1231*4882a593Smuzhiyun 			.formats = MADERA_FORMATS,
1232*4882a593Smuzhiyun 		},
1233*4882a593Smuzhiyun 	},
1234*4882a593Smuzhiyun };
1235*4882a593Smuzhiyun 
cs47l15_open(struct snd_soc_component * component,struct snd_compr_stream * stream)1236*4882a593Smuzhiyun static int cs47l15_open(struct snd_soc_component *component,
1237*4882a593Smuzhiyun 			struct snd_compr_stream *stream)
1238*4882a593Smuzhiyun {
1239*4882a593Smuzhiyun 	struct snd_soc_pcm_runtime *rtd = stream->private_data;
1240*4882a593Smuzhiyun 	struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
1241*4882a593Smuzhiyun 	struct madera_priv *priv = &cs47l15->core;
1242*4882a593Smuzhiyun 	struct madera *madera = priv->madera;
1243*4882a593Smuzhiyun 	int n_adsp;
1244*4882a593Smuzhiyun 
1245*4882a593Smuzhiyun 	if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l15-dsp-trace") == 0) {
1246*4882a593Smuzhiyun 		n_adsp = 0;
1247*4882a593Smuzhiyun 	} else {
1248*4882a593Smuzhiyun 		dev_err(madera->dev,
1249*4882a593Smuzhiyun 			"No suitable compressed stream for DAI '%s'\n",
1250*4882a593Smuzhiyun 			asoc_rtd_to_codec(rtd, 0)->name);
1251*4882a593Smuzhiyun 		return -EINVAL;
1252*4882a593Smuzhiyun 	}
1253*4882a593Smuzhiyun 
1254*4882a593Smuzhiyun 	return wm_adsp_compr_open(&priv->adsp[n_adsp], stream);
1255*4882a593Smuzhiyun }
1256*4882a593Smuzhiyun 
cs47l15_adsp2_irq(int irq,void * data)1257*4882a593Smuzhiyun static irqreturn_t cs47l15_adsp2_irq(int irq, void *data)
1258*4882a593Smuzhiyun {
1259*4882a593Smuzhiyun 	struct cs47l15 *cs47l15 = data;
1260*4882a593Smuzhiyun 	struct madera_priv *priv = &cs47l15->core;
1261*4882a593Smuzhiyun 	struct madera *madera = priv->madera;
1262*4882a593Smuzhiyun 	int ret;
1263*4882a593Smuzhiyun 
1264*4882a593Smuzhiyun 	ret = wm_adsp_compr_handle_irq(&priv->adsp[0]);
1265*4882a593Smuzhiyun 	if (ret == -ENODEV) {
1266*4882a593Smuzhiyun 		dev_err(madera->dev, "Spurious compressed data IRQ\n");
1267*4882a593Smuzhiyun 		return IRQ_NONE;
1268*4882a593Smuzhiyun 	}
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun 	return IRQ_HANDLED;
1271*4882a593Smuzhiyun }
1272*4882a593Smuzhiyun 
1273*4882a593Smuzhiyun static const struct snd_soc_dapm_route cs47l15_mono_routes[] = {
1274*4882a593Smuzhiyun 	{ "HPOUT1 Mono Mux", "HPOUT", "OUT1L" },
1275*4882a593Smuzhiyun };
1276*4882a593Smuzhiyun 
cs47l15_component_probe(struct snd_soc_component * component)1277*4882a593Smuzhiyun static int cs47l15_component_probe(struct snd_soc_component *component)
1278*4882a593Smuzhiyun {
1279*4882a593Smuzhiyun 	struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
1280*4882a593Smuzhiyun 	struct madera *madera = cs47l15->core.madera;
1281*4882a593Smuzhiyun 	int ret;
1282*4882a593Smuzhiyun 
1283*4882a593Smuzhiyun 	snd_soc_component_init_regmap(component, madera->regmap);
1284*4882a593Smuzhiyun 
1285*4882a593Smuzhiyun 	mutex_lock(&madera->dapm_ptr_lock);
1286*4882a593Smuzhiyun 	madera->dapm = snd_soc_component_get_dapm(component);
1287*4882a593Smuzhiyun 	mutex_unlock(&madera->dapm_ptr_lock);
1288*4882a593Smuzhiyun 
1289*4882a593Smuzhiyun 	ret = madera_init_inputs(component);
1290*4882a593Smuzhiyun 	if (ret)
1291*4882a593Smuzhiyun 		return ret;
1292*4882a593Smuzhiyun 
1293*4882a593Smuzhiyun 	ret = madera_init_outputs(component, cs47l15_mono_routes,
1294*4882a593Smuzhiyun 				  ARRAY_SIZE(cs47l15_mono_routes),
1295*4882a593Smuzhiyun 				  CS47L15_MONO_OUTPUTS);
1296*4882a593Smuzhiyun 	if (ret)
1297*4882a593Smuzhiyun 		return ret;
1298*4882a593Smuzhiyun 
1299*4882a593Smuzhiyun 	snd_soc_component_disable_pin(component, "HAPTICS");
1300*4882a593Smuzhiyun 
1301*4882a593Smuzhiyun 	ret = snd_soc_add_component_controls(component,
1302*4882a593Smuzhiyun 					     madera_adsp_rate_controls,
1303*4882a593Smuzhiyun 					     CS47L15_NUM_ADSP);
1304*4882a593Smuzhiyun 	if (ret)
1305*4882a593Smuzhiyun 		return ret;
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun 	wm_adsp2_component_probe(&cs47l15->core.adsp[0], component);
1308*4882a593Smuzhiyun 
1309*4882a593Smuzhiyun 	return 0;
1310*4882a593Smuzhiyun }
1311*4882a593Smuzhiyun 
cs47l15_component_remove(struct snd_soc_component * component)1312*4882a593Smuzhiyun static void cs47l15_component_remove(struct snd_soc_component *component)
1313*4882a593Smuzhiyun {
1314*4882a593Smuzhiyun 	struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
1315*4882a593Smuzhiyun 	struct madera *madera = cs47l15->core.madera;
1316*4882a593Smuzhiyun 
1317*4882a593Smuzhiyun 	mutex_lock(&madera->dapm_ptr_lock);
1318*4882a593Smuzhiyun 	madera->dapm = NULL;
1319*4882a593Smuzhiyun 	mutex_unlock(&madera->dapm_ptr_lock);
1320*4882a593Smuzhiyun 
1321*4882a593Smuzhiyun 	wm_adsp2_component_remove(&cs47l15->core.adsp[0], component);
1322*4882a593Smuzhiyun }
1323*4882a593Smuzhiyun 
1324*4882a593Smuzhiyun #define CS47L15_DIG_VU 0x0200
1325*4882a593Smuzhiyun 
1326*4882a593Smuzhiyun static unsigned int cs47l15_digital_vu[] = {
1327*4882a593Smuzhiyun 	MADERA_DAC_DIGITAL_VOLUME_1L,
1328*4882a593Smuzhiyun 	MADERA_DAC_DIGITAL_VOLUME_1R,
1329*4882a593Smuzhiyun 	MADERA_DAC_DIGITAL_VOLUME_4L,
1330*4882a593Smuzhiyun 	MADERA_DAC_DIGITAL_VOLUME_5L,
1331*4882a593Smuzhiyun 	MADERA_DAC_DIGITAL_VOLUME_5R,
1332*4882a593Smuzhiyun };
1333*4882a593Smuzhiyun 
1334*4882a593Smuzhiyun static const struct snd_compress_ops cs47l15_compress_ops = {
1335*4882a593Smuzhiyun 	.open = &cs47l15_open,
1336*4882a593Smuzhiyun 	.free = &wm_adsp_compr_free,
1337*4882a593Smuzhiyun 	.set_params = &wm_adsp_compr_set_params,
1338*4882a593Smuzhiyun 	.get_caps = &wm_adsp_compr_get_caps,
1339*4882a593Smuzhiyun 	.trigger = &wm_adsp_compr_trigger,
1340*4882a593Smuzhiyun 	.pointer = &wm_adsp_compr_pointer,
1341*4882a593Smuzhiyun 	.copy = &wm_adsp_compr_copy,
1342*4882a593Smuzhiyun };
1343*4882a593Smuzhiyun 
1344*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_cs47l15 = {
1345*4882a593Smuzhiyun 	.probe			= &cs47l15_component_probe,
1346*4882a593Smuzhiyun 	.remove			= &cs47l15_component_remove,
1347*4882a593Smuzhiyun 	.set_sysclk		= &madera_set_sysclk,
1348*4882a593Smuzhiyun 	.set_pll		= &cs47l15_set_fll,
1349*4882a593Smuzhiyun 	.name			= DRV_NAME,
1350*4882a593Smuzhiyun 	.compress_ops		= &cs47l15_compress_ops,
1351*4882a593Smuzhiyun 	.controls		= cs47l15_snd_controls,
1352*4882a593Smuzhiyun 	.num_controls		= ARRAY_SIZE(cs47l15_snd_controls),
1353*4882a593Smuzhiyun 	.dapm_widgets		= cs47l15_dapm_widgets,
1354*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(cs47l15_dapm_widgets),
1355*4882a593Smuzhiyun 	.dapm_routes		= cs47l15_dapm_routes,
1356*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(cs47l15_dapm_routes),
1357*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
1358*4882a593Smuzhiyun 	.endianness		= 1,
1359*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
1360*4882a593Smuzhiyun };
1361*4882a593Smuzhiyun 
cs47l15_probe(struct platform_device * pdev)1362*4882a593Smuzhiyun static int cs47l15_probe(struct platform_device *pdev)
1363*4882a593Smuzhiyun {
1364*4882a593Smuzhiyun 	struct madera *madera = dev_get_drvdata(pdev->dev.parent);
1365*4882a593Smuzhiyun 	struct cs47l15 *cs47l15;
1366*4882a593Smuzhiyun 	int i, ret;
1367*4882a593Smuzhiyun 
1368*4882a593Smuzhiyun 	BUILD_BUG_ON(ARRAY_SIZE(cs47l15_dai) > MADERA_MAX_DAI);
1369*4882a593Smuzhiyun 
1370*4882a593Smuzhiyun 	/* quick exit if Madera irqchip driver hasn't completed probe */
1371*4882a593Smuzhiyun 	if (!madera->irq_dev) {
1372*4882a593Smuzhiyun 		dev_dbg(&pdev->dev, "irqchip driver not ready\n");
1373*4882a593Smuzhiyun 		return -EPROBE_DEFER;
1374*4882a593Smuzhiyun 	}
1375*4882a593Smuzhiyun 
1376*4882a593Smuzhiyun 	cs47l15 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l15),
1377*4882a593Smuzhiyun 			       GFP_KERNEL);
1378*4882a593Smuzhiyun 	if (!cs47l15)
1379*4882a593Smuzhiyun 		return -ENOMEM;
1380*4882a593Smuzhiyun 
1381*4882a593Smuzhiyun 	platform_set_drvdata(pdev, cs47l15);
1382*4882a593Smuzhiyun 
1383*4882a593Smuzhiyun 	cs47l15->core.madera = madera;
1384*4882a593Smuzhiyun 	cs47l15->core.dev = &pdev->dev;
1385*4882a593Smuzhiyun 	cs47l15->core.num_inputs = 4;
1386*4882a593Smuzhiyun 
1387*4882a593Smuzhiyun 	ret = madera_core_init(&cs47l15->core);
1388*4882a593Smuzhiyun 	if (ret)
1389*4882a593Smuzhiyun 		return ret;
1390*4882a593Smuzhiyun 
1391*4882a593Smuzhiyun 	ret = madera_init_overheat(&cs47l15->core);
1392*4882a593Smuzhiyun 	if (ret)
1393*4882a593Smuzhiyun 		goto error_core;
1394*4882a593Smuzhiyun 
1395*4882a593Smuzhiyun 	ret = madera_request_irq(madera, MADERA_IRQ_DSP_IRQ1,
1396*4882a593Smuzhiyun 				 "ADSP2 Compressed IRQ", cs47l15_adsp2_irq,
1397*4882a593Smuzhiyun 				 cs47l15);
1398*4882a593Smuzhiyun 	if (ret != 0) {
1399*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
1400*4882a593Smuzhiyun 		goto error_overheat;
1401*4882a593Smuzhiyun 	}
1402*4882a593Smuzhiyun 
1403*4882a593Smuzhiyun 	ret = madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 1);
1404*4882a593Smuzhiyun 	if (ret)
1405*4882a593Smuzhiyun 		dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
1406*4882a593Smuzhiyun 
1407*4882a593Smuzhiyun 	cs47l15->core.adsp[0].part = "cs47l15";
1408*4882a593Smuzhiyun 	cs47l15->core.adsp[0].num = 1;
1409*4882a593Smuzhiyun 	cs47l15->core.adsp[0].type = WMFW_ADSP2;
1410*4882a593Smuzhiyun 	cs47l15->core.adsp[0].rev = 2;
1411*4882a593Smuzhiyun 	cs47l15->core.adsp[0].dev = madera->dev;
1412*4882a593Smuzhiyun 	cs47l15->core.adsp[0].regmap = madera->regmap_32bit;
1413*4882a593Smuzhiyun 
1414*4882a593Smuzhiyun 	cs47l15->core.adsp[0].base = MADERA_DSP1_CONFIG_1;
1415*4882a593Smuzhiyun 	cs47l15->core.adsp[0].mem = cs47l15_dsp1_regions;
1416*4882a593Smuzhiyun 	cs47l15->core.adsp[0].num_mems = ARRAY_SIZE(cs47l15_dsp1_regions);
1417*4882a593Smuzhiyun 
1418*4882a593Smuzhiyun 	cs47l15->core.adsp[0].lock_regions =
1419*4882a593Smuzhiyun 		WM_ADSP2_REGION_1 | WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3;
1420*4882a593Smuzhiyun 
1421*4882a593Smuzhiyun 	ret = wm_adsp2_init(&cs47l15->core.adsp[0]);
1422*4882a593Smuzhiyun 	if (ret != 0)
1423*4882a593Smuzhiyun 		goto error_dsp_irq;
1424*4882a593Smuzhiyun 
1425*4882a593Smuzhiyun 	ret = madera_init_bus_error_irq(&cs47l15->core, 0, wm_adsp2_bus_error);
1426*4882a593Smuzhiyun 	if (ret)
1427*4882a593Smuzhiyun 		goto error_adsp;
1428*4882a593Smuzhiyun 
1429*4882a593Smuzhiyun 	madera_init_fll(madera, 1, MADERA_FLL1_CONTROL_1 - 1,
1430*4882a593Smuzhiyun 			&cs47l15->fll[0]);
1431*4882a593Smuzhiyun 	madera_init_fll(madera, 4, MADERA_FLLAO_CONTROL_1 - 1,
1432*4882a593Smuzhiyun 			&cs47l15->fll[1]);
1433*4882a593Smuzhiyun 
1434*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(cs47l15_dai); i++)
1435*4882a593Smuzhiyun 		madera_init_dai(&cs47l15->core, i);
1436*4882a593Smuzhiyun 
1437*4882a593Smuzhiyun 	/* Latch volume update bits */
1438*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(cs47l15_digital_vu); i++)
1439*4882a593Smuzhiyun 		regmap_update_bits(madera->regmap, cs47l15_digital_vu[i],
1440*4882a593Smuzhiyun 				   CS47L15_DIG_VU, CS47L15_DIG_VU);
1441*4882a593Smuzhiyun 
1442*4882a593Smuzhiyun 	pm_runtime_enable(&pdev->dev);
1443*4882a593Smuzhiyun 	pm_runtime_idle(&pdev->dev);
1444*4882a593Smuzhiyun 
1445*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(&pdev->dev,
1446*4882a593Smuzhiyun 					      &soc_component_dev_cs47l15,
1447*4882a593Smuzhiyun 					      cs47l15_dai,
1448*4882a593Smuzhiyun 					      ARRAY_SIZE(cs47l15_dai));
1449*4882a593Smuzhiyun 	if (ret < 0) {
1450*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
1451*4882a593Smuzhiyun 		goto error_pm_runtime;
1452*4882a593Smuzhiyun 	}
1453*4882a593Smuzhiyun 
1454*4882a593Smuzhiyun 	return ret;
1455*4882a593Smuzhiyun 
1456*4882a593Smuzhiyun error_pm_runtime:
1457*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
1458*4882a593Smuzhiyun 	madera_free_bus_error_irq(&cs47l15->core, 0);
1459*4882a593Smuzhiyun error_adsp:
1460*4882a593Smuzhiyun 	wm_adsp2_remove(&cs47l15->core.adsp[0]);
1461*4882a593Smuzhiyun error_dsp_irq:
1462*4882a593Smuzhiyun 	madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 0);
1463*4882a593Smuzhiyun 	madera_free_irq(madera, MADERA_IRQ_DSP_IRQ1, cs47l15);
1464*4882a593Smuzhiyun error_overheat:
1465*4882a593Smuzhiyun 	madera_free_overheat(&cs47l15->core);
1466*4882a593Smuzhiyun error_core:
1467*4882a593Smuzhiyun 	madera_core_free(&cs47l15->core);
1468*4882a593Smuzhiyun 
1469*4882a593Smuzhiyun 	return ret;
1470*4882a593Smuzhiyun }
1471*4882a593Smuzhiyun 
cs47l15_remove(struct platform_device * pdev)1472*4882a593Smuzhiyun static int cs47l15_remove(struct platform_device *pdev)
1473*4882a593Smuzhiyun {
1474*4882a593Smuzhiyun 	struct cs47l15 *cs47l15 = platform_get_drvdata(pdev);
1475*4882a593Smuzhiyun 
1476*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
1477*4882a593Smuzhiyun 
1478*4882a593Smuzhiyun 	madera_free_bus_error_irq(&cs47l15->core, 0);
1479*4882a593Smuzhiyun 
1480*4882a593Smuzhiyun 	wm_adsp2_remove(&cs47l15->core.adsp[0]);
1481*4882a593Smuzhiyun 
1482*4882a593Smuzhiyun 	madera_set_irq_wake(cs47l15->core.madera, MADERA_IRQ_DSP_IRQ1, 0);
1483*4882a593Smuzhiyun 	madera_free_irq(cs47l15->core.madera, MADERA_IRQ_DSP_IRQ1, cs47l15);
1484*4882a593Smuzhiyun 	madera_free_overheat(&cs47l15->core);
1485*4882a593Smuzhiyun 	madera_core_free(&cs47l15->core);
1486*4882a593Smuzhiyun 
1487*4882a593Smuzhiyun 	return 0;
1488*4882a593Smuzhiyun }
1489*4882a593Smuzhiyun 
1490*4882a593Smuzhiyun static struct platform_driver cs47l15_codec_driver = {
1491*4882a593Smuzhiyun 	.driver = {
1492*4882a593Smuzhiyun 		.name = "cs47l15-codec",
1493*4882a593Smuzhiyun 	},
1494*4882a593Smuzhiyun 	.probe = &cs47l15_probe,
1495*4882a593Smuzhiyun 	.remove = &cs47l15_remove,
1496*4882a593Smuzhiyun };
1497*4882a593Smuzhiyun 
1498*4882a593Smuzhiyun module_platform_driver(cs47l15_codec_driver);
1499*4882a593Smuzhiyun 
1500*4882a593Smuzhiyun MODULE_SOFTDEP("pre: madera irq-madera arizona-micsupp");
1501*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC CS47L15 driver");
1502*4882a593Smuzhiyun MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
1503*4882a593Smuzhiyun MODULE_AUTHOR("Jaswinder Jassal <jjassal@opensource.cirrus.com>");
1504*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1505*4882a593Smuzhiyun MODULE_ALIAS("platform:cs47l15-codec");
1506