1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ALSA SoC CS4349 codec driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2015 Cirrus Logic, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Tim Howe <Tim.Howe@cirrus.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CS4349_H__ 11*4882a593Smuzhiyun #define __CS4349_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* CS4349 registers addresses */ 14*4882a593Smuzhiyun #define CS4349_CHIPID 0x01 /* Device and Rev ID, Read Only */ 15*4882a593Smuzhiyun #define CS4349_MODE 0x02 /* Mode Control */ 16*4882a593Smuzhiyun #define CS4349_VMI 0x03 /* Volume, Mixing, Inversion Control */ 17*4882a593Smuzhiyun #define CS4349_MUTE 0x04 /* Mute Control */ 18*4882a593Smuzhiyun #define CS4349_VOLA 0x05 /* DAC Channel A Volume Control */ 19*4882a593Smuzhiyun #define CS4349_VOLB 0x06 /* DAC Channel B Volume Control */ 20*4882a593Smuzhiyun #define CS4349_RMPFLT 0x07 /* Ramp and Filter Control */ 21*4882a593Smuzhiyun #define CS4349_MISC 0x08 /* Power Down,Freeze Control,Pop Stop*/ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CS4349_I2C_INCR 0x80 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Device and Revision ID */ 27*4882a593Smuzhiyun #define CS4349_REVA 0xF0 /* Rev A */ 28*4882a593Smuzhiyun #define CS4349_REVB 0xF1 /* Rev B */ 29*4882a593Smuzhiyun #define CS4349_REVC2 0xFF /* Rev C2 */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* PDN_DONE Poll Maximum 33*4882a593Smuzhiyun * If soft ramp is set it will take much longer to power down 34*4882a593Smuzhiyun * the system. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define PDN_POLL_MAX 900 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Bitfield Definitions */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* CS4349_MODE */ 42*4882a593Smuzhiyun /* (Digital Interface Format, De-Emphasis Control, Functional Mode */ 43*4882a593Smuzhiyun #define DIF2 (1 << 6) 44*4882a593Smuzhiyun #define DIF1 (1 << 5) 45*4882a593Smuzhiyun #define DIF0 (1 << 4) 46*4882a593Smuzhiyun #define DEM1 (1 << 3) 47*4882a593Smuzhiyun #define DEM0 (1 << 2) 48*4882a593Smuzhiyun #define FM1 (1 << 1) 49*4882a593Smuzhiyun #define DIF_LEFT_JST 0x00 50*4882a593Smuzhiyun #define DIF_I2S 0x01 51*4882a593Smuzhiyun #define DIF_RGHT_JST16 0x02 52*4882a593Smuzhiyun #define DIF_RGHT_JST24 0x03 53*4882a593Smuzhiyun #define DIF_TDM0 0x04 54*4882a593Smuzhiyun #define DIF_TDM1 0x05 55*4882a593Smuzhiyun #define DIF_TDM2 0x06 56*4882a593Smuzhiyun #define DIF_TDM3 0x07 57*4882a593Smuzhiyun #define DIF_MASK 0x70 58*4882a593Smuzhiyun #define MODE_FORMAT(x) (((x)&7)<<4) 59*4882a593Smuzhiyun #define DEM_MASK 0x0C 60*4882a593Smuzhiyun #define NO_DEM 0x00 61*4882a593Smuzhiyun #define DEM_441 0x04 62*4882a593Smuzhiyun #define DEM_48K 0x08 63*4882a593Smuzhiyun #define DEM_32K 0x0C 64*4882a593Smuzhiyun #define FM_AUTO 0x00 65*4882a593Smuzhiyun #define FM_SNGL 0x01 66*4882a593Smuzhiyun #define FM_DBL 0x02 67*4882a593Smuzhiyun #define FM_QUAD 0x03 68*4882a593Smuzhiyun #define FM_SNGL_MIN 30000 69*4882a593Smuzhiyun #define FM_SNGL_MAX 54000 70*4882a593Smuzhiyun #define FM_DBL_MAX 108000 71*4882a593Smuzhiyun #define FM_QUAD_MAX 216000 72*4882a593Smuzhiyun #define FM_MASK 0x03 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* CS4349_VMI (VMI = Volume, Mixing and Inversion Controls) */ 75*4882a593Smuzhiyun #define VOLBISA (1 << 7) 76*4882a593Smuzhiyun #define VOLAISB (1 << 7) 77*4882a593Smuzhiyun /* INVERT_A only available for Left Jstfd, Right Jstfd16 and Right Jstfd24 */ 78*4882a593Smuzhiyun #define INVERT_A (1 << 6) 79*4882a593Smuzhiyun /* INVERT_B only available for Left Jstfd, Right Jstfd16 and Right Jstfd24 */ 80*4882a593Smuzhiyun #define INVERT_B (1 << 5) 81*4882a593Smuzhiyun #define ATAPI3 (1 << 3) 82*4882a593Smuzhiyun #define ATAPI2 (1 << 2) 83*4882a593Smuzhiyun #define ATAPI1 (1 << 1) 84*4882a593Smuzhiyun #define ATAPI0 (1 << 0) 85*4882a593Smuzhiyun #define MUTEAB 0x00 86*4882a593Smuzhiyun #define MUTEA_RIGHTB 0x01 87*4882a593Smuzhiyun #define MUTEA_LEFTB 0x02 88*4882a593Smuzhiyun #define MUTEA_SUMLRDIV2B 0x03 89*4882a593Smuzhiyun #define RIGHTA_MUTEB 0x04 90*4882a593Smuzhiyun #define RIGHTA_RIGHTB 0x05 91*4882a593Smuzhiyun #define RIGHTA_LEFTB 0x06 92*4882a593Smuzhiyun #define RIGHTA_SUMLRDIV2B 0x07 93*4882a593Smuzhiyun #define LEFTA_MUTEB 0x08 94*4882a593Smuzhiyun #define LEFTA_RIGHTB 0x09 /* Default */ 95*4882a593Smuzhiyun #define LEFTA_LEFTB 0x0A 96*4882a593Smuzhiyun #define LEFTA_SUMLRDIV2B 0x0B 97*4882a593Smuzhiyun #define SUMLRDIV2A_MUTEB 0x0C 98*4882a593Smuzhiyun #define SUMLRDIV2A_RIGHTB 0x0D 99*4882a593Smuzhiyun #define SUMLRDIV2A_LEFTB 0x0E 100*4882a593Smuzhiyun #define SUMLRDIV2_AB 0x0F 101*4882a593Smuzhiyun #define CHMIX_MASK 0x0F 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* CS4349_MUTE */ 104*4882a593Smuzhiyun #define AUTOMUTE (1 << 7) 105*4882a593Smuzhiyun #define MUTEC_AB (1 << 5) 106*4882a593Smuzhiyun #define MUTE_A (1 << 4) 107*4882a593Smuzhiyun #define MUTE_B (1 << 3) 108*4882a593Smuzhiyun #define MUTE_AB_MASK 0x18 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* CS4349_RMPFLT (Ramp and Filter Control) */ 111*4882a593Smuzhiyun #define SCZ1 (1 << 7) 112*4882a593Smuzhiyun #define SCZ0 (1 << 6) 113*4882a593Smuzhiyun #define RMP_UP (1 << 5) 114*4882a593Smuzhiyun #define RMP_DN (1 << 4) 115*4882a593Smuzhiyun #define FILT_SEL (1 << 2) 116*4882a593Smuzhiyun #define IMMDT_CHNG 0x31 117*4882a593Smuzhiyun #define ZEROCRSS 0x71 118*4882a593Smuzhiyun #define SOFT_RMP 0xB1 119*4882a593Smuzhiyun #define SFTRMP_ZEROCRSS 0xF1 120*4882a593Smuzhiyun #define SR_ZC_MASK 0xC0 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* CS4349_MISC */ 123*4882a593Smuzhiyun #define PWR_DWN (1 << 7) 124*4882a593Smuzhiyun #define FREEZE (1 << 5) 125*4882a593Smuzhiyun #define POPG_EN (1 << 4) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #endif /* __CS4349_H__ */ 128