1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * cs42xx8.h - Cirrus Logic CS42448/CS42888 Audio CODEC driver header file 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2014 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: Nicolin Chen <Guangyu.Chen@freescale.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License 9*4882a593Smuzhiyun * version 2. This program is licensed "as is" without any warranty of any 10*4882a593Smuzhiyun * kind, whether express or implied. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _CS42XX8_H 14*4882a593Smuzhiyun #define _CS42XX8_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct cs42xx8_driver_data { 17*4882a593Smuzhiyun char name[32]; 18*4882a593Smuzhiyun int num_adcs; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun extern const struct dev_pm_ops cs42xx8_pm; 22*4882a593Smuzhiyun extern const struct cs42xx8_driver_data cs42448_data; 23*4882a593Smuzhiyun extern const struct cs42xx8_driver_data cs42888_data; 24*4882a593Smuzhiyun extern const struct regmap_config cs42xx8_regmap_config; 25*4882a593Smuzhiyun extern const struct of_device_id cs42xx8_of_match[]; 26*4882a593Smuzhiyun int cs42xx8_probe(struct device *dev, struct regmap *regmap); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* CS42888 register map */ 29*4882a593Smuzhiyun #define CS42XX8_CHIPID 0x01 /* Chip ID */ 30*4882a593Smuzhiyun #define CS42XX8_PWRCTL 0x02 /* Power Control */ 31*4882a593Smuzhiyun #define CS42XX8_FUNCMOD 0x03 /* Functional Mode */ 32*4882a593Smuzhiyun #define CS42XX8_INTF 0x04 /* Interface Formats */ 33*4882a593Smuzhiyun #define CS42XX8_ADCCTL 0x05 /* ADC Control */ 34*4882a593Smuzhiyun #define CS42XX8_TXCTL 0x06 /* Transition Control */ 35*4882a593Smuzhiyun #define CS42XX8_DACMUTE 0x07 /* DAC Mute Control */ 36*4882a593Smuzhiyun #define CS42XX8_VOLAOUT1 0x08 /* Volume Control AOUT1 */ 37*4882a593Smuzhiyun #define CS42XX8_VOLAOUT2 0x09 /* Volume Control AOUT2 */ 38*4882a593Smuzhiyun #define CS42XX8_VOLAOUT3 0x0A /* Volume Control AOUT3 */ 39*4882a593Smuzhiyun #define CS42XX8_VOLAOUT4 0x0B /* Volume Control AOUT4 */ 40*4882a593Smuzhiyun #define CS42XX8_VOLAOUT5 0x0C /* Volume Control AOUT5 */ 41*4882a593Smuzhiyun #define CS42XX8_VOLAOUT6 0x0D /* Volume Control AOUT6 */ 42*4882a593Smuzhiyun #define CS42XX8_VOLAOUT7 0x0E /* Volume Control AOUT7 */ 43*4882a593Smuzhiyun #define CS42XX8_VOLAOUT8 0x0F /* Volume Control AOUT8 */ 44*4882a593Smuzhiyun #define CS42XX8_DACINV 0x10 /* DAC Channel Invert */ 45*4882a593Smuzhiyun #define CS42XX8_VOLAIN1 0x11 /* Volume Control AIN1 */ 46*4882a593Smuzhiyun #define CS42XX8_VOLAIN2 0x12 /* Volume Control AIN2 */ 47*4882a593Smuzhiyun #define CS42XX8_VOLAIN3 0x13 /* Volume Control AIN3 */ 48*4882a593Smuzhiyun #define CS42XX8_VOLAIN4 0x14 /* Volume Control AIN4 */ 49*4882a593Smuzhiyun #define CS42XX8_VOLAIN5 0x15 /* Volume Control AIN5 */ 50*4882a593Smuzhiyun #define CS42XX8_VOLAIN6 0x16 /* Volume Control AIN6 */ 51*4882a593Smuzhiyun #define CS42XX8_ADCINV 0x17 /* ADC Channel Invert */ 52*4882a593Smuzhiyun #define CS42XX8_STATUSCTL 0x18 /* Status Control */ 53*4882a593Smuzhiyun #define CS42XX8_STATUS 0x19 /* Status */ 54*4882a593Smuzhiyun #define CS42XX8_STATUSM 0x1A /* Status Mask */ 55*4882a593Smuzhiyun #define CS42XX8_MUTEC 0x1B /* MUTEC Pin Control */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define CS42XX8_FIRSTREG CS42XX8_CHIPID 58*4882a593Smuzhiyun #define CS42XX8_LASTREG CS42XX8_MUTEC 59*4882a593Smuzhiyun #define CS42XX8_NUMREGS (CS42XX8_LASTREG - CS42XX8_FIRSTREG + 1) 60*4882a593Smuzhiyun #define CS42XX8_I2C_INCR 0x80 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Chip I.D. and Revision Register (Address 01h) */ 63*4882a593Smuzhiyun #define CS42XX8_CHIPID_CHIP_ID_MASK 0xF0 64*4882a593Smuzhiyun #define CS42XX8_CHIPID_REV_ID_MASK 0x0F 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Power Control (Address 02h) */ 67*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_ADC3_SHIFT 7 68*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_ADC3_MASK (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT) 69*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_ADC3 (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT) 70*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_ADC2_SHIFT 6 71*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_ADC2_MASK (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT) 72*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_ADC2 (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT) 73*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_ADC1_SHIFT 5 74*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_ADC1_MASK (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT) 75*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_ADC1 (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT) 76*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC4_SHIFT 4 77*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC4_MASK (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT) 78*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC4 (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT) 79*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC3_SHIFT 3 80*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC3_MASK (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT) 81*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC3 (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT) 82*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC2_SHIFT 2 83*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC2_MASK (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT) 84*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC2 (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT) 85*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC1_SHIFT 1 86*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC1_MASK (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT) 87*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_DAC1 (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT) 88*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_SHIFT 0 89*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN_MASK (1 << CS42XX8_PWRCTL_PDN_SHIFT) 90*4882a593Smuzhiyun #define CS42XX8_PWRCTL_PDN (1 << CS42XX8_PWRCTL_PDN_SHIFT) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Functional Mode (Address 03h) */ 93*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_DAC_FM_SHIFT 6 94*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_DAC_FM_WIDTH 2 95*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_DAC_FM_MASK (((1 << CS42XX8_FUNCMOD_DAC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_DAC_FM_SHIFT) 96*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_DAC_FM(v) ((v) << CS42XX8_FUNCMOD_DAC_FM_SHIFT) 97*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_ADC_FM_SHIFT 4 98*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_ADC_FM_WIDTH 2 99*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_ADC_FM_MASK (((1 << CS42XX8_FUNCMOD_ADC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_ADC_FM_SHIFT) 100*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_ADC_FM(v) ((v) << CS42XX8_FUNCMOD_ADC_FM_SHIFT) 101*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_xC_FM_MASK(x) ((x) ? CS42XX8_FUNCMOD_DAC_FM_MASK : CS42XX8_FUNCMOD_ADC_FM_MASK) 102*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_xC_FM(x, v) ((x) ? CS42XX8_FUNCMOD_DAC_FM(v) : CS42XX8_FUNCMOD_ADC_FM(v)) 103*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_MFREQ_SHIFT 1 104*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_MFREQ_WIDTH 3 105*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_MFREQ_MASK (((1 << CS42XX8_FUNCMOD_MFREQ_WIDTH) - 1) << CS42XX8_FUNCMOD_MFREQ_SHIFT) 106*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_MFREQ_256(s) ((0 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1)) 107*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_MFREQ_384(s) ((1 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1)) 108*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_MFREQ_512(s) ((2 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1)) 109*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_MFREQ_768(s) ((3 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1)) 110*4882a593Smuzhiyun #define CS42XX8_FUNCMOD_MFREQ_1024(s) ((4 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1)) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define CS42XX8_FM_SINGLE 0 113*4882a593Smuzhiyun #define CS42XX8_FM_DOUBLE 1 114*4882a593Smuzhiyun #define CS42XX8_FM_QUAD 2 115*4882a593Smuzhiyun #define CS42XX8_FM_AUTO 3 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* Interface Formats (Address 04h) */ 118*4882a593Smuzhiyun #define CS42XX8_INTF_FREEZE_SHIFT 7 119*4882a593Smuzhiyun #define CS42XX8_INTF_FREEZE_MASK (1 << CS42XX8_INTF_FREEZE_SHIFT) 120*4882a593Smuzhiyun #define CS42XX8_INTF_FREEZE (1 << CS42XX8_INTF_FREEZE_SHIFT) 121*4882a593Smuzhiyun #define CS42XX8_INTF_AUX_DIF_SHIFT 6 122*4882a593Smuzhiyun #define CS42XX8_INTF_AUX_DIF_MASK (1 << CS42XX8_INTF_AUX_DIF_SHIFT) 123*4882a593Smuzhiyun #define CS42XX8_INTF_AUX_DIF (1 << CS42XX8_INTF_AUX_DIF_SHIFT) 124*4882a593Smuzhiyun #define CS42XX8_INTF_DAC_DIF_SHIFT 3 125*4882a593Smuzhiyun #define CS42XX8_INTF_DAC_DIF_WIDTH 3 126*4882a593Smuzhiyun #define CS42XX8_INTF_DAC_DIF_MASK (((1 << CS42XX8_INTF_DAC_DIF_WIDTH) - 1) << CS42XX8_INTF_DAC_DIF_SHIFT) 127*4882a593Smuzhiyun #define CS42XX8_INTF_DAC_DIF_LEFTJ (0 << CS42XX8_INTF_DAC_DIF_SHIFT) 128*4882a593Smuzhiyun #define CS42XX8_INTF_DAC_DIF_I2S (1 << CS42XX8_INTF_DAC_DIF_SHIFT) 129*4882a593Smuzhiyun #define CS42XX8_INTF_DAC_DIF_RIGHTJ (2 << CS42XX8_INTF_DAC_DIF_SHIFT) 130*4882a593Smuzhiyun #define CS42XX8_INTF_DAC_DIF_RIGHTJ_16 (3 << CS42XX8_INTF_DAC_DIF_SHIFT) 131*4882a593Smuzhiyun #define CS42XX8_INTF_DAC_DIF_ONELINE_20 (4 << CS42XX8_INTF_DAC_DIF_SHIFT) 132*4882a593Smuzhiyun #define CS42XX8_INTF_DAC_DIF_ONELINE_24 (5 << CS42XX8_INTF_DAC_DIF_SHIFT) 133*4882a593Smuzhiyun #define CS42XX8_INTF_DAC_DIF_TDM (6 << CS42XX8_INTF_DAC_DIF_SHIFT) 134*4882a593Smuzhiyun #define CS42XX8_INTF_ADC_DIF_SHIFT 0 135*4882a593Smuzhiyun #define CS42XX8_INTF_ADC_DIF_WIDTH 3 136*4882a593Smuzhiyun #define CS42XX8_INTF_ADC_DIF_MASK (((1 << CS42XX8_INTF_ADC_DIF_WIDTH) - 1) << CS42XX8_INTF_ADC_DIF_SHIFT) 137*4882a593Smuzhiyun #define CS42XX8_INTF_ADC_DIF_LEFTJ (0 << CS42XX8_INTF_ADC_DIF_SHIFT) 138*4882a593Smuzhiyun #define CS42XX8_INTF_ADC_DIF_I2S (1 << CS42XX8_INTF_ADC_DIF_SHIFT) 139*4882a593Smuzhiyun #define CS42XX8_INTF_ADC_DIF_RIGHTJ (2 << CS42XX8_INTF_ADC_DIF_SHIFT) 140*4882a593Smuzhiyun #define CS42XX8_INTF_ADC_DIF_RIGHTJ_16 (3 << CS42XX8_INTF_ADC_DIF_SHIFT) 141*4882a593Smuzhiyun #define CS42XX8_INTF_ADC_DIF_ONELINE_20 (4 << CS42XX8_INTF_ADC_DIF_SHIFT) 142*4882a593Smuzhiyun #define CS42XX8_INTF_ADC_DIF_ONELINE_24 (5 << CS42XX8_INTF_ADC_DIF_SHIFT) 143*4882a593Smuzhiyun #define CS42XX8_INTF_ADC_DIF_TDM (6 << CS42XX8_INTF_ADC_DIF_SHIFT) 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* ADC Control & DAC De-Emphasis (Address 05h) */ 146*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT 7 147*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC_HPF_FREEZE_MASK (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT) 148*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC_HPF_FREEZE (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT) 149*4882a593Smuzhiyun #define CS42XX8_ADCCTL_DAC_DEM_SHIFT 5 150*4882a593Smuzhiyun #define CS42XX8_ADCCTL_DAC_DEM_MASK (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT) 151*4882a593Smuzhiyun #define CS42XX8_ADCCTL_DAC_DEM (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT) 152*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT 4 153*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC1_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT) 154*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC1_SINGLE (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT) 155*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT 3 156*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC2_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT) 157*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC2_SINGLE (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT) 158*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT 2 159*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC3_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT) 160*4882a593Smuzhiyun #define CS42XX8_ADCCTL_ADC3_SINGLE (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT) 161*4882a593Smuzhiyun #define CS42XX8_ADCCTL_AIN5_MUX_SHIFT 1 162*4882a593Smuzhiyun #define CS42XX8_ADCCTL_AIN5_MUX_MASK (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT) 163*4882a593Smuzhiyun #define CS42XX8_ADCCTL_AIN5_MUX (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT) 164*4882a593Smuzhiyun #define CS42XX8_ADCCTL_AIN6_MUX_SHIFT 0 165*4882a593Smuzhiyun #define CS42XX8_ADCCTL_AIN6_MUX_MASK (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT) 166*4882a593Smuzhiyun #define CS42XX8_ADCCTL_AIN6_MUX (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT) 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* Transition Control (Address 06h) */ 169*4882a593Smuzhiyun #define CS42XX8_TXCTL_DAC_SNGVOL_SHIFT 7 170*4882a593Smuzhiyun #define CS42XX8_TXCTL_DAC_SNGVOL_MASK (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT) 171*4882a593Smuzhiyun #define CS42XX8_TXCTL_DAC_SNGVOL (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT) 172*4882a593Smuzhiyun #define CS42XX8_TXCTL_DAC_SZC_SHIFT 5 173*4882a593Smuzhiyun #define CS42XX8_TXCTL_DAC_SZC_WIDTH 2 174*4882a593Smuzhiyun #define CS42XX8_TXCTL_DAC_SZC_MASK (((1 << CS42XX8_TXCTL_DAC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_DAC_SZC_SHIFT) 175*4882a593Smuzhiyun #define CS42XX8_TXCTL_DAC_SZC_IC (0 << CS42XX8_TXCTL_DAC_SZC_SHIFT) 176*4882a593Smuzhiyun #define CS42XX8_TXCTL_DAC_SZC_ZC (1 << CS42XX8_TXCTL_DAC_SZC_SHIFT) 177*4882a593Smuzhiyun #define CS42XX8_TXCTL_DAC_SZC_SR (2 << CS42XX8_TXCTL_DAC_SZC_SHIFT) 178*4882a593Smuzhiyun #define CS42XX8_TXCTL_DAC_SZC_SRZC (3 << CS42XX8_TXCTL_DAC_SZC_SHIFT) 179*4882a593Smuzhiyun #define CS42XX8_TXCTL_AMUTE_SHIFT 4 180*4882a593Smuzhiyun #define CS42XX8_TXCTL_AMUTE_MASK (1 << CS42XX8_TXCTL_AMUTE_SHIFT) 181*4882a593Smuzhiyun #define CS42XX8_TXCTL_AMUTE (1 << CS42XX8_TXCTL_AMUTE_SHIFT) 182*4882a593Smuzhiyun #define CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT 3 183*4882a593Smuzhiyun #define CS42XX8_TXCTL_MUTE_ADC_SP_MASK (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT) 184*4882a593Smuzhiyun #define CS42XX8_TXCTL_MUTE_ADC_SP (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT) 185*4882a593Smuzhiyun #define CS42XX8_TXCTL_ADC_SNGVOL_SHIFT 2 186*4882a593Smuzhiyun #define CS42XX8_TXCTL_ADC_SNGVOL_MASK (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT) 187*4882a593Smuzhiyun #define CS42XX8_TXCTL_ADC_SNGVOL (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT) 188*4882a593Smuzhiyun #define CS42XX8_TXCTL_ADC_SZC_SHIFT 0 189*4882a593Smuzhiyun #define CS42XX8_TXCTL_ADC_SZC_MASK (((1 << CS42XX8_TXCTL_ADC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_ADC_SZC_SHIFT) 190*4882a593Smuzhiyun #define CS42XX8_TXCTL_ADC_SZC_IC (0 << CS42XX8_TXCTL_ADC_SZC_SHIFT) 191*4882a593Smuzhiyun #define CS42XX8_TXCTL_ADC_SZC_ZC (1 << CS42XX8_TXCTL_ADC_SZC_SHIFT) 192*4882a593Smuzhiyun #define CS42XX8_TXCTL_ADC_SZC_SR (2 << CS42XX8_TXCTL_ADC_SZC_SHIFT) 193*4882a593Smuzhiyun #define CS42XX8_TXCTL_ADC_SZC_SRZC (3 << CS42XX8_TXCTL_ADC_SZC_SHIFT) 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* DAC Channel Mute (Address 07h) */ 196*4882a593Smuzhiyun #define CS42XX8_DACMUTE_AOUT(n) (0x1 << n) 197*4882a593Smuzhiyun #define CS42XX8_DACMUTE_ALL 0xff 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* Status Control (Address 18h)*/ 200*4882a593Smuzhiyun #define CS42XX8_STATUSCTL_INI_SHIFT 2 201*4882a593Smuzhiyun #define CS42XX8_STATUSCTL_INI_WIDTH 2 202*4882a593Smuzhiyun #define CS42XX8_STATUSCTL_INI_MASK (((1 << CS42XX8_STATUSCTL_INI_WIDTH) - 1) << CS42XX8_STATUSCTL_INI_SHIFT) 203*4882a593Smuzhiyun #define CS42XX8_STATUSCTL_INT_ACTIVE_HIGH (0 << CS42XX8_STATUSCTL_INI_SHIFT) 204*4882a593Smuzhiyun #define CS42XX8_STATUSCTL_INT_ACTIVE_LOW (1 << CS42XX8_STATUSCTL_INI_SHIFT) 205*4882a593Smuzhiyun #define CS42XX8_STATUSCTL_INT_OPEN_DRAIN (2 << CS42XX8_STATUSCTL_INI_SHIFT) 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* Status (Address 19h)*/ 208*4882a593Smuzhiyun #define CS42XX8_STATUS_DAC_CLK_ERR_SHIFT 4 209*4882a593Smuzhiyun #define CS42XX8_STATUS_DAC_CLK_ERR_MASK (1 << CS42XX8_STATUS_DAC_CLK_ERR_SHIFT) 210*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC_CLK_ERR_SHIFT 3 211*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC_CLK_ERR_MASK (1 << CS42XX8_STATUS_ADC_CLK_ERR_SHIFT) 212*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC3_OVFL_SHIFT 2 213*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC3_OVFL_MASK (1 << CS42XX8_STATUS_ADC3_OVFL_SHIFT) 214*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC2_OVFL_SHIFT 1 215*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC2_OVFL_MASK (1 << CS42XX8_STATUS_ADC2_OVFL_SHIFT) 216*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC1_OVFL_SHIFT 0 217*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC1_OVFL_MASK (1 << CS42XX8_STATUS_ADC1_OVFL_SHIFT) 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun /* Status Mask (Address 1Ah) */ 220*4882a593Smuzhiyun #define CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT 4 221*4882a593Smuzhiyun #define CS42XX8_STATUS_DAC_CLK_ERR_M_MASK (1 << CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT) 222*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT 3 223*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC_CLK_ERR_M_MASK (1 << CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT) 224*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC3_OVFL_M_SHIFT 2 225*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC3_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC3_OVFL_M_SHIFT) 226*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC2_OVFL_M_SHIFT 1 227*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC2_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC2_OVFL_M_SHIFT) 228*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC1_OVFL_M_SHIFT 0 229*4882a593Smuzhiyun #define CS42XX8_STATUS_ADC1_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC1_OVFL_M_SHIFT) 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* MUTEC Pin Control (Address 1Bh) */ 232*4882a593Smuzhiyun #define CS42XX8_MUTEC_MCPOLARITY_SHIFT 1 233*4882a593Smuzhiyun #define CS42XX8_MUTEC_MCPOLARITY_MASK (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT) 234*4882a593Smuzhiyun #define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_LOW (0 << CS42XX8_MUTEC_MCPOLARITY_SHIFT) 235*4882a593Smuzhiyun #define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_HIGH (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT) 236*4882a593Smuzhiyun #define CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT 0 237*4882a593Smuzhiyun #define CS42XX8_MUTEC_MUTEC_ACTIVE_MASK (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT) 238*4882a593Smuzhiyun #define CS42XX8_MUTEC_MUTEC_ACTIVE (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT) 239*4882a593Smuzhiyun #endif /* _CS42XX8_H */ 240