1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ALSA SoC CS42L73 codec driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2011 Cirrus Logic, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Georgi Vlaev <joe@nucleusys.com> 8*4882a593Smuzhiyun * Brian Austin <brian.austin@cirrus.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __CS42L73_H__ 12*4882a593Smuzhiyun #define __CS42L73_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* I2C Registers */ 15*4882a593Smuzhiyun /* I2C Address: 1001010[R/W] - 10010100 = 0x94(Write); 10010101 = 0x95(Read) */ 16*4882a593Smuzhiyun #define CS42L73_CHIP_ID 0x4a 17*4882a593Smuzhiyun #define CS42L73_DEVID_AB 0x01 /* Device ID A & B [RO]. */ 18*4882a593Smuzhiyun #define CS42L73_DEVID_CD 0x02 /* Device ID C & D [RO]. */ 19*4882a593Smuzhiyun #define CS42L73_DEVID_E 0x03 /* Device ID E [RO]. */ 20*4882a593Smuzhiyun #define CS42L73_REVID 0x05 /* Revision ID [RO]. */ 21*4882a593Smuzhiyun #define CS42L73_PWRCTL1 0x06 /* Power Control 1. */ 22*4882a593Smuzhiyun #define CS42L73_PWRCTL2 0x07 /* Power Control 2. */ 23*4882a593Smuzhiyun #define CS42L73_PWRCTL3 0x08 /* Power Control 3. */ 24*4882a593Smuzhiyun #define CS42L73_CPFCHC 0x09 /* Charge Pump Freq. Class H Ctl. */ 25*4882a593Smuzhiyun #define CS42L73_OLMBMSDC 0x0A /* Output Load, MIC Bias, MIC2 SDT */ 26*4882a593Smuzhiyun #define CS42L73_DMMCC 0x0B /* Digital MIC & Master Clock Ctl. */ 27*4882a593Smuzhiyun #define CS42L73_XSPC 0x0C /* Auxiliary Serial Port (XSP) Ctl. */ 28*4882a593Smuzhiyun #define CS42L73_XSPMMCC 0x0D /* XSP Master Mode Clocking Control. */ 29*4882a593Smuzhiyun #define CS42L73_ASPC 0x0E /* Audio Serial Port (ASP) Control. */ 30*4882a593Smuzhiyun #define CS42L73_ASPMMCC 0x0F /* ASP Master Mode Clocking Control. */ 31*4882a593Smuzhiyun #define CS42L73_VSPC 0x10 /* Voice Serial Port (VSP) Control. */ 32*4882a593Smuzhiyun #define CS42L73_VSPMMCC 0x11 /* VSP Master Mode Clocking Control. */ 33*4882a593Smuzhiyun #define CS42L73_VXSPFS 0x12 /* VSP & XSP Sample Rate. */ 34*4882a593Smuzhiyun #define CS42L73_MIOPC 0x13 /* Misc. Input & Output Path Control. */ 35*4882a593Smuzhiyun #define CS42L73_ADCIPC 0x14 /* ADC/IP Control. */ 36*4882a593Smuzhiyun #define CS42L73_MICAPREPGAAVOL 0x15 /* MIC 1 [A] PreAmp, PGAA Vol. */ 37*4882a593Smuzhiyun #define CS42L73_MICBPREPGABVOL 0x16 /* MIC 2 [B] PreAmp, PGAB Vol. */ 38*4882a593Smuzhiyun #define CS42L73_IPADVOL 0x17 /* Input Pat7h A Digital Volume. */ 39*4882a593Smuzhiyun #define CS42L73_IPBDVOL 0x18 /* Input Path B Digital Volume. */ 40*4882a593Smuzhiyun #define CS42L73_PBDC 0x19 /* Playback Digital Control. */ 41*4882a593Smuzhiyun #define CS42L73_HLADVOL 0x1A /* HP/Line A Out Digital Vol. */ 42*4882a593Smuzhiyun #define CS42L73_HLBDVOL 0x1B /* HP/Line B Out Digital Vol. */ 43*4882a593Smuzhiyun #define CS42L73_SPKDVOL 0x1C /* Spkphone Out [A] Digital Vol. */ 44*4882a593Smuzhiyun #define CS42L73_ESLDVOL 0x1D /* Ear/Spkphone LO [B] Digital */ 45*4882a593Smuzhiyun #define CS42L73_HPAAVOL 0x1E /* HP A Analog Volume. */ 46*4882a593Smuzhiyun #define CS42L73_HPBAVOL 0x1F /* HP B Analog Volume. */ 47*4882a593Smuzhiyun #define CS42L73_LOAAVOL 0x20 /* Line Out A Analog Volume. */ 48*4882a593Smuzhiyun #define CS42L73_LOBAVOL 0x21 /* Line Out B Analog Volume. */ 49*4882a593Smuzhiyun #define CS42L73_STRINV 0x22 /* Stereo Input Path Adv. Vol. */ 50*4882a593Smuzhiyun #define CS42L73_XSPINV 0x23 /* Auxiliary Port Input Advisory Vol. */ 51*4882a593Smuzhiyun #define CS42L73_ASPINV 0x24 /* Audio Port Input Advisory Vol. */ 52*4882a593Smuzhiyun #define CS42L73_VSPINV 0x25 /* Voice Port Input Advisory Vol. */ 53*4882a593Smuzhiyun #define CS42L73_LIMARATEHL 0x26 /* Lmtr Attack Rate HP/Line. */ 54*4882a593Smuzhiyun #define CS42L73_LIMRRATEHL 0x27 /* Lmtr Ctl, Rel.Rate HP/Line. */ 55*4882a593Smuzhiyun #define CS42L73_LMAXHL 0x28 /* Lmtr Thresholds HP/Line. */ 56*4882a593Smuzhiyun #define CS42L73_LIMARATESPK 0x29 /* Lmtr Attack Rate Spkphone [A]. */ 57*4882a593Smuzhiyun #define CS42L73_LIMRRATESPK 0x2A /* Lmtr Ctl,Release Rate Spk. [A]. */ 58*4882a593Smuzhiyun #define CS42L73_LMAXSPK 0x2B /* Lmtr Thresholds Spkphone [A]. */ 59*4882a593Smuzhiyun #define CS42L73_LIMARATEESL 0x2C /* Lmtr Attack Rate */ 60*4882a593Smuzhiyun #define CS42L73_LIMRRATEESL 0x2D /* Lmtr Ctl,Release Rate */ 61*4882a593Smuzhiyun #define CS42L73_LMAXESL 0x2E /* Lmtr Thresholds */ 62*4882a593Smuzhiyun #define CS42L73_ALCARATE 0x2F /* ALC Enable, Attack Rate AB. */ 63*4882a593Smuzhiyun #define CS42L73_ALCRRATE 0x30 /* ALC Release Rate AB. */ 64*4882a593Smuzhiyun #define CS42L73_ALCMINMAX 0x31 /* ALC Thresholds AB. */ 65*4882a593Smuzhiyun #define CS42L73_NGCAB 0x32 /* Noise Gate Ctl AB. */ 66*4882a593Smuzhiyun #define CS42L73_ALCNGMC 0x33 /* ALC & Noise Gate Misc Ctl. */ 67*4882a593Smuzhiyun #define CS42L73_MIXERCTL 0x34 /* Mixer Control. */ 68*4882a593Smuzhiyun #define CS42L73_HLAIPAA 0x35 /* HP/LO Left Mixer: L. */ 69*4882a593Smuzhiyun #define CS42L73_HLBIPBA 0x36 /* HP/LO Right Mixer: R. */ 70*4882a593Smuzhiyun #define CS42L73_HLAXSPAA 0x37 /* HP/LO Left Mixer: XSP L */ 71*4882a593Smuzhiyun #define CS42L73_HLBXSPBA 0x38 /* HP/LO Right Mixer: XSP R */ 72*4882a593Smuzhiyun #define CS42L73_HLAASPAA 0x39 /* HP/LO Left Mixer: ASP L */ 73*4882a593Smuzhiyun #define CS42L73_HLBASPBA 0x3A /* HP/LO Right Mixer: ASP R */ 74*4882a593Smuzhiyun #define CS42L73_HLAVSPMA 0x3B /* HP/LO Left Mixer: VSP. */ 75*4882a593Smuzhiyun #define CS42L73_HLBVSPMA 0x3C /* HP/LO Right Mixer: VSP */ 76*4882a593Smuzhiyun #define CS42L73_XSPAIPAA 0x3D /* XSP Left Mixer: Left */ 77*4882a593Smuzhiyun #define CS42L73_XSPBIPBA 0x3E /* XSP Rt. Mixer: Right */ 78*4882a593Smuzhiyun #define CS42L73_XSPAXSPAA 0x3F /* XSP Left Mixer: XSP L */ 79*4882a593Smuzhiyun #define CS42L73_XSPBXSPBA 0x40 /* XSP Rt. Mixer: XSP R */ 80*4882a593Smuzhiyun #define CS42L73_XSPAASPAA 0x41 /* XSP Left Mixer: ASP L */ 81*4882a593Smuzhiyun #define CS42L73_XSPAASPBA 0x42 /* XSP Rt. Mixer: ASP R */ 82*4882a593Smuzhiyun #define CS42L73_XSPAVSPMA 0x43 /* XSP Left Mixer: VSP */ 83*4882a593Smuzhiyun #define CS42L73_XSPBVSPMA 0x44 /* XSP Rt. Mixer: VSP */ 84*4882a593Smuzhiyun #define CS42L73_ASPAIPAA 0x45 /* ASP Left Mixer: Left */ 85*4882a593Smuzhiyun #define CS42L73_ASPBIPBA 0x46 /* ASP Rt. Mixer: Right */ 86*4882a593Smuzhiyun #define CS42L73_ASPAXSPAA 0x47 /* ASP Left Mixer: XSP L */ 87*4882a593Smuzhiyun #define CS42L73_ASPBXSPBA 0x48 /* ASP Rt. Mixer: XSP R */ 88*4882a593Smuzhiyun #define CS42L73_ASPAASPAA 0x49 /* ASP Left Mixer: ASP L */ 89*4882a593Smuzhiyun #define CS42L73_ASPBASPBA 0x4A /* ASP Rt. Mixer: ASP R */ 90*4882a593Smuzhiyun #define CS42L73_ASPAVSPMA 0x4B /* ASP Left Mixer: VSP */ 91*4882a593Smuzhiyun #define CS42L73_ASPBVSPMA 0x4C /* ASP Rt. Mixer: VSP */ 92*4882a593Smuzhiyun #define CS42L73_VSPAIPAA 0x4D /* VSP Left Mixer: Left */ 93*4882a593Smuzhiyun #define CS42L73_VSPBIPBA 0x4E /* VSP Rt. Mixer: Right */ 94*4882a593Smuzhiyun #define CS42L73_VSPAXSPAA 0x4F /* VSP Left Mixer: XSP L */ 95*4882a593Smuzhiyun #define CS42L73_VSPBXSPBA 0x50 /* VSP Rt. Mixer: XSP R */ 96*4882a593Smuzhiyun #define CS42L73_VSPAASPAA 0x51 /* VSP Left Mixer: ASP Left */ 97*4882a593Smuzhiyun #define CS42L73_VSPBASPBA 0x52 /* VSP Rt. Mixer: ASP Right */ 98*4882a593Smuzhiyun #define CS42L73_VSPAVSPMA 0x53 /* VSP Left Mixer: VSP */ 99*4882a593Smuzhiyun #define CS42L73_VSPBVSPMA 0x54 /* VSP Rt. Mixer: VSP */ 100*4882a593Smuzhiyun #define CS42L73_MMIXCTL 0x55 /* Mono Mixer Controls. */ 101*4882a593Smuzhiyun #define CS42L73_SPKMIPMA 0x56 /* SPK Mono Mixer: In. Path */ 102*4882a593Smuzhiyun #define CS42L73_SPKMXSPA 0x57 /* SPK Mono Mixer: XSP Mono/L/R Att. */ 103*4882a593Smuzhiyun #define CS42L73_SPKMASPA 0x58 /* SPK Mono Mixer: ASP Mono/L/R Att. */ 104*4882a593Smuzhiyun #define CS42L73_SPKMVSPMA 0x59 /* SPK Mono Mixer: VSP Mono Atten. */ 105*4882a593Smuzhiyun #define CS42L73_ESLMIPMA 0x5A /* Ear/SpLO Mono Mixer: */ 106*4882a593Smuzhiyun #define CS42L73_ESLMXSPA 0x5B /* Ear/SpLO Mono Mixer: XSP */ 107*4882a593Smuzhiyun #define CS42L73_ESLMASPA 0x5C /* Ear/SpLO Mono Mixer: ASP */ 108*4882a593Smuzhiyun #define CS42L73_ESLMVSPMA 0x5D /* Ear/SpLO Mono Mixer: VSP */ 109*4882a593Smuzhiyun #define CS42L73_IM1 0x5E /* Interrupt Mask 1. */ 110*4882a593Smuzhiyun #define CS42L73_IM2 0x5F /* Interrupt Mask 2. */ 111*4882a593Smuzhiyun #define CS42L73_IS1 0x60 /* Interrupt Status 1 [RO]. */ 112*4882a593Smuzhiyun #define CS42L73_IS2 0x61 /* Interrupt Status 2 [RO]. */ 113*4882a593Smuzhiyun #define CS42L73_MAX_REGISTER 0x61 /* Total Registers */ 114*4882a593Smuzhiyun /* Bitfield Definitions */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* CS42L73_PWRCTL1 */ 117*4882a593Smuzhiyun #define CS42L73_PDN_ADCB (1 << 7) 118*4882a593Smuzhiyun #define CS42L73_PDN_DMICB (1 << 6) 119*4882a593Smuzhiyun #define CS42L73_PDN_ADCA (1 << 5) 120*4882a593Smuzhiyun #define CS42L73_PDN_DMICA (1 << 4) 121*4882a593Smuzhiyun #define CS42L73_PDN_LDO (1 << 2) 122*4882a593Smuzhiyun #define CS42L73_DISCHG_FILT (1 << 1) 123*4882a593Smuzhiyun #define CS42L73_PDN (1 << 0) 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* CS42L73_PWRCTL2 */ 126*4882a593Smuzhiyun #define CS42L73_PDN_MIC2_BIAS (1 << 7) 127*4882a593Smuzhiyun #define CS42L73_PDN_MIC1_BIAS (1 << 6) 128*4882a593Smuzhiyun #define CS42L73_PDN_VSP (1 << 4) 129*4882a593Smuzhiyun #define CS42L73_PDN_ASP_SDOUT (1 << 3) 130*4882a593Smuzhiyun #define CS42L73_PDN_ASP_SDIN (1 << 2) 131*4882a593Smuzhiyun #define CS42L73_PDN_XSP_SDOUT (1 << 1) 132*4882a593Smuzhiyun #define CS42L73_PDN_XSP_SDIN (1 << 0) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* CS42L73_PWRCTL3 */ 135*4882a593Smuzhiyun #define CS42L73_PDN_THMS (1 << 5) 136*4882a593Smuzhiyun #define CS42L73_PDN_SPKLO (1 << 4) 137*4882a593Smuzhiyun #define CS42L73_PDN_EAR (1 << 3) 138*4882a593Smuzhiyun #define CS42L73_PDN_SPK (1 << 2) 139*4882a593Smuzhiyun #define CS42L73_PDN_LO (1 << 1) 140*4882a593Smuzhiyun #define CS42L73_PDN_HP (1 << 0) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* Thermal Overload Detect. Requires interrupt ... */ 143*4882a593Smuzhiyun #define CS42L73_THMOVLD_150C 0 144*4882a593Smuzhiyun #define CS42L73_THMOVLD_132C 1 145*4882a593Smuzhiyun #define CS42L73_THMOVLD_115C 2 146*4882a593Smuzhiyun #define CS42L73_THMOVLD_098C 3 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define CS42L73_CHARGEPUMP_MASK (0xF0) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* CS42L73_ASPC, CS42L73_XSPC, CS42L73_VSPC */ 151*4882a593Smuzhiyun #define CS42L73_SP_3ST (1 << 7) 152*4882a593Smuzhiyun #define CS42L73_SPDIF_I2S (0 << 6) 153*4882a593Smuzhiyun #define CS42L73_SPDIF_PCM (1 << 6) 154*4882a593Smuzhiyun #define CS42L73_PCM_MODE0 (0 << 4) 155*4882a593Smuzhiyun #define CS42L73_PCM_MODE1 (1 << 4) 156*4882a593Smuzhiyun #define CS42L73_PCM_MODE2 (2 << 4) 157*4882a593Smuzhiyun #define CS42L73_PCM_MODE_MASK (3 << 4) 158*4882a593Smuzhiyun #define CS42L73_PCM_BIT_ORDER (1 << 3) 159*4882a593Smuzhiyun #define CS42L73_MCK_SCLK_64FS (0 << 0) 160*4882a593Smuzhiyun #define CS42L73_MCK_SCLK_MCLK (2 << 0) 161*4882a593Smuzhiyun #define CS42L73_MCK_SCLK_PREMCLK (3 << 0) 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* CS42L73_xSPMMCC */ 164*4882a593Smuzhiyun #define CS42L73_MS_MASTER (1 << 7) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* CS42L73_DMMCC */ 168*4882a593Smuzhiyun #define CS42L73_MCLKDIS (1 << 0) 169*4882a593Smuzhiyun #define CS42L73_MCLKSEL_MCLK2 (1 << 4) 170*4882a593Smuzhiyun #define CS42L73_MCLKSEL_MCLK1 (0 << 4) 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* CS42L73 MCLK derived from MCLK1 or MCLK2 */ 173*4882a593Smuzhiyun #define CS42L73_CLKID_MCLK1 0 174*4882a593Smuzhiyun #define CS42L73_CLKID_MCLK2 1 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define CS42L73_MCLKXDIV 0 177*4882a593Smuzhiyun #define CS42L73_MMCCDIV 1 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #define CS42L73_XSP 0 180*4882a593Smuzhiyun #define CS42L73_ASP 1 181*4882a593Smuzhiyun #define CS42L73_VSP 2 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* IS1, IM1 */ 184*4882a593Smuzhiyun #define CS42L73_MIC2_SDET (1 << 6) 185*4882a593Smuzhiyun #define CS42L73_THMOVLD (1 << 4) 186*4882a593Smuzhiyun #define CS42L73_DIGMIXOVFL (1 << 3) 187*4882a593Smuzhiyun #define CS42L73_IPBOVFL (1 << 1) 188*4882a593Smuzhiyun #define CS42L73_IPAOVFL (1 << 0) 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun /* Analog Softramp */ 191*4882a593Smuzhiyun #define CS42L73_ANLGOSFT (1 << 0) 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* HP A/B Analog Mute */ 194*4882a593Smuzhiyun #define CS42L73_HPA_MUTE (1 << 7) 195*4882a593Smuzhiyun /* LO A/B Analog Mute */ 196*4882a593Smuzhiyun #define CS42L73_LOA_MUTE (1 << 7) 197*4882a593Smuzhiyun /* Digital Mute */ 198*4882a593Smuzhiyun #define CS42L73_HLAD_MUTE (1 << 0) 199*4882a593Smuzhiyun #define CS42L73_HLBD_MUTE (1 << 1) 200*4882a593Smuzhiyun #define CS42L73_SPKD_MUTE (1 << 2) 201*4882a593Smuzhiyun #define CS42L73_ESLD_MUTE (1 << 3) 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* Misc defines for codec */ 204*4882a593Smuzhiyun #define CS42L73_DEVID 0x00042A73 205*4882a593Smuzhiyun #define CS42L73_MCLKX_MIN 5644800 206*4882a593Smuzhiyun #define CS42L73_MCLKX_MAX 38400000 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define CS42L73_SPC(id) (CS42L73_XSPC + (id << 1)) 209*4882a593Smuzhiyun #define CS42L73_MMCC(id) (CS42L73_XSPMMCC + (id << 1)) 210*4882a593Smuzhiyun #define CS42L73_SPFS(id) ((id == CS42L73_ASP) ? CS42L73_ASPC : CS42L73_VXSPFS) 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun #endif /* __CS42L73_H__ */ 213