xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/cs42l56.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * cs42l56.c -- CS42L56 ALSA SoC audio driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2014 CirrusLogic, Inc.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Brian Austin <brian.austin@cirrus.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/moduleparam.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/pm.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/input.h>
18*4882a593Smuzhiyun #include <linux/regmap.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/workqueue.h>
21*4882a593Smuzhiyun #include <linux/platform_device.h>
22*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
23*4882a593Smuzhiyun #include <linux/of_device.h>
24*4882a593Smuzhiyun #include <linux/of_gpio.h>
25*4882a593Smuzhiyun #include <sound/core.h>
26*4882a593Smuzhiyun #include <sound/pcm.h>
27*4882a593Smuzhiyun #include <sound/pcm_params.h>
28*4882a593Smuzhiyun #include <sound/soc.h>
29*4882a593Smuzhiyun #include <sound/soc-dapm.h>
30*4882a593Smuzhiyun #include <sound/initval.h>
31*4882a593Smuzhiyun #include <sound/tlv.h>
32*4882a593Smuzhiyun #include <sound/cs42l56.h>
33*4882a593Smuzhiyun #include "cs42l56.h"
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define CS42L56_NUM_SUPPLIES 3
36*4882a593Smuzhiyun static const char *const cs42l56_supply_names[CS42L56_NUM_SUPPLIES] = {
37*4882a593Smuzhiyun 	"VA",
38*4882a593Smuzhiyun 	"VCP",
39*4882a593Smuzhiyun 	"VLDO",
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun struct  cs42l56_private {
43*4882a593Smuzhiyun 	struct regmap *regmap;
44*4882a593Smuzhiyun 	struct snd_soc_component *component;
45*4882a593Smuzhiyun 	struct device *dev;
46*4882a593Smuzhiyun 	struct cs42l56_platform_data pdata;
47*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[CS42L56_NUM_SUPPLIES];
48*4882a593Smuzhiyun 	u32 mclk;
49*4882a593Smuzhiyun 	u8 mclk_prediv;
50*4882a593Smuzhiyun 	u8 mclk_div2;
51*4882a593Smuzhiyun 	u8 mclk_ratio;
52*4882a593Smuzhiyun 	u8 iface;
53*4882a593Smuzhiyun 	u8 iface_fmt;
54*4882a593Smuzhiyun 	u8 iface_inv;
55*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_INPUT)
56*4882a593Smuzhiyun 	struct input_dev *beep;
57*4882a593Smuzhiyun 	struct work_struct beep_work;
58*4882a593Smuzhiyun 	int beep_rate;
59*4882a593Smuzhiyun #endif
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun static const struct reg_default cs42l56_reg_defaults[] = {
63*4882a593Smuzhiyun 	{ 3, 0x7f },	/* r03	- Power Ctl 1 */
64*4882a593Smuzhiyun 	{ 4, 0xff },	/* r04	- Power Ctl 2 */
65*4882a593Smuzhiyun 	{ 5, 0x00 },	/* ro5	- Clocking Ctl 1 */
66*4882a593Smuzhiyun 	{ 6, 0x0b },	/* r06	- Clocking Ctl 2 */
67*4882a593Smuzhiyun 	{ 7, 0x00 },	/* r07	- Serial Format */
68*4882a593Smuzhiyun 	{ 8, 0x05 },	/* r08	- Class H Ctl */
69*4882a593Smuzhiyun 	{ 9, 0x0c },	/* r09	- Misc Ctl */
70*4882a593Smuzhiyun 	{ 10, 0x80 },	/* r0a	- INT Status */
71*4882a593Smuzhiyun 	{ 11, 0x00 },	/* r0b	- Playback Ctl */
72*4882a593Smuzhiyun 	{ 12, 0x0c },	/* r0c	- DSP Mute Ctl */
73*4882a593Smuzhiyun 	{ 13, 0x00 },	/* r0d	- ADCA Mixer Volume */
74*4882a593Smuzhiyun 	{ 14, 0x00 },	/* r0e	- ADCB Mixer Volume */
75*4882a593Smuzhiyun 	{ 15, 0x00 },	/* r0f	- PCMA Mixer Volume */
76*4882a593Smuzhiyun 	{ 16, 0x00 },	/* r10	- PCMB Mixer Volume */
77*4882a593Smuzhiyun 	{ 17, 0x00 },	/* r11	- Analog Input Advisory Volume */
78*4882a593Smuzhiyun 	{ 18, 0x00 },	/* r12	- Digital Input Advisory Volume */
79*4882a593Smuzhiyun 	{ 19, 0x00 },	/* r13	- Master A Volume */
80*4882a593Smuzhiyun 	{ 20, 0x00 },	/* r14	- Master B Volume */
81*4882a593Smuzhiyun 	{ 21, 0x00 },	/* r15	- Beep Freq / On Time */
82*4882a593Smuzhiyun 	{ 22, 0x00 },	/* r16	- Beep Volume / Off Time */
83*4882a593Smuzhiyun 	{ 23, 0x00 },	/* r17	- Beep Tone Ctl */
84*4882a593Smuzhiyun 	{ 24, 0x88 },	/* r18	- Tone Ctl */
85*4882a593Smuzhiyun 	{ 25, 0x00 },	/* r19	- Channel Mixer & Swap */
86*4882a593Smuzhiyun 	{ 26, 0x00 },	/* r1a	- AIN Ref Config / ADC Mux */
87*4882a593Smuzhiyun 	{ 27, 0xa0 },	/* r1b	- High-Pass Filter Ctl */
88*4882a593Smuzhiyun 	{ 28, 0x00 },	/* r1c	- Misc ADC Ctl */
89*4882a593Smuzhiyun 	{ 29, 0x00 },	/* r1d	- Gain & Bias Ctl */
90*4882a593Smuzhiyun 	{ 30, 0x00 },	/* r1e	- PGAA Mux & Volume */
91*4882a593Smuzhiyun 	{ 31, 0x00 },	/* r1f	- PGAB Mux & Volume */
92*4882a593Smuzhiyun 	{ 32, 0x00 },	/* r20	- ADCA Attenuator */
93*4882a593Smuzhiyun 	{ 33, 0x00 },	/* r21	- ADCB Attenuator */
94*4882a593Smuzhiyun 	{ 34, 0x00 },	/* r22	- ALC Enable & Attack Rate */
95*4882a593Smuzhiyun 	{ 35, 0xbf },	/* r23	- ALC Release Rate */
96*4882a593Smuzhiyun 	{ 36, 0x00 },	/* r24	- ALC Threshold */
97*4882a593Smuzhiyun 	{ 37, 0x00 },	/* r25	- Noise Gate Ctl */
98*4882a593Smuzhiyun 	{ 38, 0x00 },	/* r26	- ALC, Limiter, SFT, ZeroCross */
99*4882a593Smuzhiyun 	{ 39, 0x00 },	/* r27	- Analog Mute, LO & HP Mux */
100*4882a593Smuzhiyun 	{ 40, 0x00 },	/* r28	- HP A Volume */
101*4882a593Smuzhiyun 	{ 41, 0x00 },	/* r29	- HP B Volume */
102*4882a593Smuzhiyun 	{ 42, 0x00 },	/* r2a	- LINEOUT A Volume */
103*4882a593Smuzhiyun 	{ 43, 0x00 },	/* r2b	- LINEOUT B Volume */
104*4882a593Smuzhiyun 	{ 44, 0x00 },	/* r2c	- Limit Threshold Ctl */
105*4882a593Smuzhiyun 	{ 45, 0x7f },	/* r2d	- Limiter Ctl & Release Rate */
106*4882a593Smuzhiyun 	{ 46, 0x00 },	/* r2e	- Limiter Attack Rate */
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun 
cs42l56_readable_register(struct device * dev,unsigned int reg)109*4882a593Smuzhiyun static bool cs42l56_readable_register(struct device *dev, unsigned int reg)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	switch (reg) {
112*4882a593Smuzhiyun 	case CS42L56_CHIP_ID_1 ... CS42L56_LIM_ATTACK_RATE:
113*4882a593Smuzhiyun 		return true;
114*4882a593Smuzhiyun 	default:
115*4882a593Smuzhiyun 		return false;
116*4882a593Smuzhiyun 	}
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun 
cs42l56_volatile_register(struct device * dev,unsigned int reg)119*4882a593Smuzhiyun static bool cs42l56_volatile_register(struct device *dev, unsigned int reg)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun 	switch (reg) {
122*4882a593Smuzhiyun 	case CS42L56_INT_STATUS:
123*4882a593Smuzhiyun 		return true;
124*4882a593Smuzhiyun 	default:
125*4882a593Smuzhiyun 		return false;
126*4882a593Smuzhiyun 	}
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(beep_tlv, -5000, 200, 0);
130*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(hl_tlv, -6000, 50, 0);
131*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(adv_tlv, -10200, 50, 0);
132*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, 0);
133*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
134*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(preamp_tlv, 0, 1000, 0);
135*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(ngnb_tlv,
138*4882a593Smuzhiyun 	0, 1, TLV_DB_SCALE_ITEM(-8200, 600, 0),
139*4882a593Smuzhiyun 	2, 5, TLV_DB_SCALE_ITEM(-7600, 300, 0)
140*4882a593Smuzhiyun );
141*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(ngb_tlv,
142*4882a593Smuzhiyun 	0, 2, TLV_DB_SCALE_ITEM(-6400, 600, 0),
143*4882a593Smuzhiyun 	3, 7, TLV_DB_SCALE_ITEM(-4600, 300, 0)
144*4882a593Smuzhiyun );
145*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(alc_tlv,
146*4882a593Smuzhiyun 	0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
147*4882a593Smuzhiyun 	3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
148*4882a593Smuzhiyun );
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun static const char * const beep_config_text[] = {
151*4882a593Smuzhiyun 	"Off", "Single", "Multiple", "Continuous"
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun static const struct soc_enum beep_config_enum =
155*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 6,
156*4882a593Smuzhiyun 			ARRAY_SIZE(beep_config_text), beep_config_text);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun static const char * const beep_pitch_text[] = {
159*4882a593Smuzhiyun 	"C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
160*4882a593Smuzhiyun 	"C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun static const struct soc_enum beep_pitch_enum =
164*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTIME, 4,
165*4882a593Smuzhiyun 			ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun static const char * const beep_ontime_text[] = {
168*4882a593Smuzhiyun 	"86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
169*4882a593Smuzhiyun 	"1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
170*4882a593Smuzhiyun 	"3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun static const struct soc_enum beep_ontime_enum =
174*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTIME, 0,
175*4882a593Smuzhiyun 			ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun static const char * const beep_offtime_text[] = {
178*4882a593Smuzhiyun 	"1.23 s", "2.58 s", "3.90 s", "5.20 s",
179*4882a593Smuzhiyun 	"6.60 s", "8.05 s", "9.35 s", "10.80 s"
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun static const struct soc_enum beep_offtime_enum =
183*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_OFFTIME, 5,
184*4882a593Smuzhiyun 			ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun static const char * const beep_treble_text[] = {
187*4882a593Smuzhiyun 	"5kHz", "7kHz", "10kHz", "15kHz"
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static const struct soc_enum beep_treble_enum =
191*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 3,
192*4882a593Smuzhiyun 			ARRAY_SIZE(beep_treble_text), beep_treble_text);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun static const char * const beep_bass_text[] = {
195*4882a593Smuzhiyun 	"50Hz", "100Hz", "200Hz", "250Hz"
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun static const struct soc_enum beep_bass_enum =
199*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 1,
200*4882a593Smuzhiyun 			ARRAY_SIZE(beep_bass_text), beep_bass_text);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static const char * const pgaa_mux_text[] = {
203*4882a593Smuzhiyun 	"AIN1A", "AIN2A", "AIN3A"};
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun static const struct soc_enum pgaa_mux_enum =
206*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_PGAA_MUX_VOLUME, 0,
207*4882a593Smuzhiyun 			      ARRAY_SIZE(pgaa_mux_text),
208*4882a593Smuzhiyun 			      pgaa_mux_text);
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun static const struct snd_kcontrol_new pgaa_mux =
211*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", pgaa_mux_enum);
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun static const char * const pgab_mux_text[] = {
214*4882a593Smuzhiyun 	"AIN1B", "AIN2B", "AIN3B"};
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun static const struct soc_enum pgab_mux_enum =
217*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_PGAB_MUX_VOLUME, 0,
218*4882a593Smuzhiyun 			      ARRAY_SIZE(pgab_mux_text),
219*4882a593Smuzhiyun 			      pgab_mux_text);
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun static const struct snd_kcontrol_new pgab_mux =
222*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", pgab_mux_enum);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun static const char * const adca_mux_text[] = {
225*4882a593Smuzhiyun 	"PGAA", "AIN1A", "AIN2A", "AIN3A"};
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun static const struct soc_enum adca_mux_enum =
228*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC_MUX, 0,
229*4882a593Smuzhiyun 			      ARRAY_SIZE(adca_mux_text),
230*4882a593Smuzhiyun 			      adca_mux_text);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun static const struct snd_kcontrol_new adca_mux =
233*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", adca_mux_enum);
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun static const char * const adcb_mux_text[] = {
236*4882a593Smuzhiyun 	"PGAB", "AIN1B", "AIN2B", "AIN3B"};
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun static const struct soc_enum adcb_mux_enum =
239*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC_MUX, 2,
240*4882a593Smuzhiyun 			      ARRAY_SIZE(adcb_mux_text),
241*4882a593Smuzhiyun 			      adcb_mux_text);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun static const struct snd_kcontrol_new adcb_mux =
244*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", adcb_mux_enum);
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun static const char * const left_swap_text[] = {
247*4882a593Smuzhiyun 	"Left", "LR 2", "Right"};
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun static const char * const right_swap_text[] = {
250*4882a593Smuzhiyun 	"Right", "LR 2", "Left"};
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun static const unsigned int swap_values[] = { 0, 1, 3 };
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun static const struct soc_enum adca_swap_enum =
255*4882a593Smuzhiyun 	SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 0, 3,
256*4882a593Smuzhiyun 			      ARRAY_SIZE(left_swap_text),
257*4882a593Smuzhiyun 			      left_swap_text,
258*4882a593Smuzhiyun 			      swap_values);
259*4882a593Smuzhiyun static const struct snd_kcontrol_new adca_swap_mux =
260*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", adca_swap_enum);
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun static const struct soc_enum pcma_swap_enum =
263*4882a593Smuzhiyun 	SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 4, 3,
264*4882a593Smuzhiyun 			      ARRAY_SIZE(left_swap_text),
265*4882a593Smuzhiyun 			      left_swap_text,
266*4882a593Smuzhiyun 			      swap_values);
267*4882a593Smuzhiyun static const struct snd_kcontrol_new pcma_swap_mux =
268*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", pcma_swap_enum);
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun static const struct soc_enum adcb_swap_enum =
271*4882a593Smuzhiyun 	SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 2, 3,
272*4882a593Smuzhiyun 			      ARRAY_SIZE(right_swap_text),
273*4882a593Smuzhiyun 			      right_swap_text,
274*4882a593Smuzhiyun 			      swap_values);
275*4882a593Smuzhiyun static const struct snd_kcontrol_new adcb_swap_mux =
276*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", adcb_swap_enum);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun static const struct soc_enum pcmb_swap_enum =
279*4882a593Smuzhiyun 	SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 6, 3,
280*4882a593Smuzhiyun 			      ARRAY_SIZE(right_swap_text),
281*4882a593Smuzhiyun 			      right_swap_text,
282*4882a593Smuzhiyun 			      swap_values);
283*4882a593Smuzhiyun static const struct snd_kcontrol_new pcmb_swap_mux =
284*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", pcmb_swap_enum);
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun static const struct snd_kcontrol_new hpa_switch =
287*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 6, 1, 1);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun static const struct snd_kcontrol_new hpb_switch =
290*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 4, 1, 1);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun static const struct snd_kcontrol_new loa_switch =
293*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 2, 1, 1);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun static const struct snd_kcontrol_new lob_switch =
296*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 0, 1, 1);
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun static const char * const hploa_input_text[] = {
299*4882a593Smuzhiyun 	"DACA", "PGAA"};
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun static const struct soc_enum lineouta_input_enum =
302*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 2,
303*4882a593Smuzhiyun 			      ARRAY_SIZE(hploa_input_text),
304*4882a593Smuzhiyun 			      hploa_input_text);
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun static const struct snd_kcontrol_new lineouta_input =
307*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", lineouta_input_enum);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun static const struct soc_enum hpa_input_enum =
310*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 0,
311*4882a593Smuzhiyun 			      ARRAY_SIZE(hploa_input_text),
312*4882a593Smuzhiyun 			      hploa_input_text);
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun static const struct snd_kcontrol_new hpa_input =
315*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", hpa_input_enum);
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun static const char * const hplob_input_text[] = {
318*4882a593Smuzhiyun 	"DACB", "PGAB"};
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun static const struct soc_enum lineoutb_input_enum =
321*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 3,
322*4882a593Smuzhiyun 			      ARRAY_SIZE(hplob_input_text),
323*4882a593Smuzhiyun 			      hplob_input_text);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun static const struct snd_kcontrol_new lineoutb_input =
326*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", lineoutb_input_enum);
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun static const struct soc_enum hpb_input_enum =
329*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 1,
330*4882a593Smuzhiyun 			      ARRAY_SIZE(hplob_input_text),
331*4882a593Smuzhiyun 			      hplob_input_text);
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun static const struct snd_kcontrol_new hpb_input =
334*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", hpb_input_enum);
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun static const char * const dig_mux_text[] = {
337*4882a593Smuzhiyun 	"ADC", "DSP"};
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun static const struct soc_enum dig_mux_enum =
340*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_MISC_CTL, 7,
341*4882a593Smuzhiyun 			      ARRAY_SIZE(dig_mux_text),
342*4882a593Smuzhiyun 			      dig_mux_text);
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun static const struct snd_kcontrol_new dig_mux =
345*4882a593Smuzhiyun 	SOC_DAPM_ENUM("Route", dig_mux_enum);
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun static const char * const hpf_freq_text[] = {
348*4882a593Smuzhiyun 	"1.8Hz", "119Hz", "236Hz", "464Hz"
349*4882a593Smuzhiyun };
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun static const struct soc_enum hpfa_freq_enum =
352*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 0,
353*4882a593Smuzhiyun 			ARRAY_SIZE(hpf_freq_text), hpf_freq_text);
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun static const struct soc_enum hpfb_freq_enum =
356*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 2,
357*4882a593Smuzhiyun 			ARRAY_SIZE(hpf_freq_text), hpf_freq_text);
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun static const char * const ng_delay_text[] = {
360*4882a593Smuzhiyun 	"50ms", "100ms", "150ms", "200ms"
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun static const struct soc_enum ng_delay_enum =
364*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(CS42L56_NOISE_GATE_CTL, 0,
365*4882a593Smuzhiyun 			ARRAY_SIZE(ng_delay_text), ng_delay_text);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun static const struct snd_kcontrol_new cs42l56_snd_controls[] = {
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L56_MASTER_A_VOLUME,
370*4882a593Smuzhiyun 			      CS42L56_MASTER_B_VOLUME, 0, 0x34, 0xE4, adv_tlv),
371*4882a593Smuzhiyun 	SOC_DOUBLE("Master Mute Switch", CS42L56_DSP_MUTE_CTL, 0, 1, 1, 1),
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume", CS42L56_ADCA_MIX_VOLUME,
374*4882a593Smuzhiyun 			      CS42L56_ADCB_MIX_VOLUME, 0, 0x88, 0x90, hl_tlv),
375*4882a593Smuzhiyun 	SOC_DOUBLE("ADC Mixer Mute Switch", CS42L56_DSP_MUTE_CTL, 6, 7, 1, 1),
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume", CS42L56_PCMA_MIX_VOLUME,
378*4882a593Smuzhiyun 			      CS42L56_PCMB_MIX_VOLUME, 0, 0x88, 0x90, hl_tlv),
379*4882a593Smuzhiyun 	SOC_DOUBLE("PCM Mixer Mute Switch", CS42L56_DSP_MUTE_CTL, 4, 5, 1, 1),
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Analog Advisory Volume",
382*4882a593Smuzhiyun 			  CS42L56_ANAINPUT_ADV_VOLUME, 0, 0x00, 1, adv_tlv),
383*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Digital Advisory Volume",
384*4882a593Smuzhiyun 			  CS42L56_DIGINPUT_ADV_VOLUME, 0, 0x00, 1, adv_tlv),
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L56_PGAA_MUX_VOLUME,
387*4882a593Smuzhiyun 			      CS42L56_PGAB_MUX_VOLUME, 0, 0x34, 0x24, pga_tlv),
388*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("ADC Volume", CS42L56_ADCA_ATTENUATOR,
389*4882a593Smuzhiyun 			      CS42L56_ADCB_ATTENUATOR, 0, 0x00, 1, adc_tlv),
390*4882a593Smuzhiyun 	SOC_DOUBLE("ADC Mute Switch", CS42L56_MISC_ADC_CTL, 2, 3, 1, 1),
391*4882a593Smuzhiyun 	SOC_DOUBLE("ADC Boost Switch", CS42L56_GAIN_BIAS_CTL, 3, 2, 1, 1),
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L56_HPA_VOLUME,
394*4882a593Smuzhiyun 			      CS42L56_HPB_VOLUME, 0, 0x44, 0x48, hl_tlv),
395*4882a593Smuzhiyun 	SOC_DOUBLE_R_SX_TLV("LineOut Volume", CS42L56_LOA_VOLUME,
396*4882a593Smuzhiyun 			      CS42L56_LOB_VOLUME, 0, 0x44, 0x48, hl_tlv),
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Bass Shelving Volume", CS42L56_TONE_CTL,
399*4882a593Smuzhiyun 			0, 0x00, 1, tone_tlv),
400*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Treble Shelving Volume", CS42L56_TONE_CTL,
401*4882a593Smuzhiyun 			4, 0x00, 1, tone_tlv),
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	SOC_DOUBLE_TLV("PGA Preamp Volume", CS42L56_GAIN_BIAS_CTL,
404*4882a593Smuzhiyun 			4, 6, 0x02, 1, preamp_tlv),
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	SOC_SINGLE("DSP Switch", CS42L56_PLAYBACK_CTL, 7, 1, 1),
407*4882a593Smuzhiyun 	SOC_SINGLE("Gang Playback Switch", CS42L56_PLAYBACK_CTL, 4, 1, 1),
408*4882a593Smuzhiyun 	SOC_SINGLE("Gang ADC Switch", CS42L56_MISC_ADC_CTL, 7, 1, 1),
409*4882a593Smuzhiyun 	SOC_SINGLE("Gang PGA Switch", CS42L56_MISC_ADC_CTL, 6, 1, 1),
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	SOC_SINGLE("PCMA Invert", CS42L56_PLAYBACK_CTL, 2, 1, 1),
412*4882a593Smuzhiyun 	SOC_SINGLE("PCMB Invert", CS42L56_PLAYBACK_CTL, 3, 1, 1),
413*4882a593Smuzhiyun 	SOC_SINGLE("ADCA Invert", CS42L56_MISC_ADC_CTL, 2, 1, 1),
414*4882a593Smuzhiyun 	SOC_SINGLE("ADCB Invert", CS42L56_MISC_ADC_CTL, 3, 1, 1),
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	SOC_DOUBLE("HPF Switch", CS42L56_HPF_CTL, 5, 7, 1, 1),
417*4882a593Smuzhiyun 	SOC_DOUBLE("HPF Freeze Switch", CS42L56_HPF_CTL, 4, 6, 1, 1),
418*4882a593Smuzhiyun 	SOC_ENUM("HPFA Corner Freq", hpfa_freq_enum),
419*4882a593Smuzhiyun 	SOC_ENUM("HPFB Corner Freq", hpfb_freq_enum),
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	SOC_SINGLE("Analog Soft Ramp", CS42L56_MISC_CTL, 4, 1, 1),
422*4882a593Smuzhiyun 	SOC_DOUBLE("Analog Soft Ramp Disable", CS42L56_ALC_LIM_SFT_ZC,
423*4882a593Smuzhiyun 		7, 5, 1, 1),
424*4882a593Smuzhiyun 	SOC_SINGLE("Analog Zero Cross", CS42L56_MISC_CTL, 3, 1, 1),
425*4882a593Smuzhiyun 	SOC_DOUBLE("Analog Zero Cross Disable", CS42L56_ALC_LIM_SFT_ZC,
426*4882a593Smuzhiyun 		6, 4, 1, 1),
427*4882a593Smuzhiyun 	SOC_SINGLE("Digital Soft Ramp", CS42L56_MISC_CTL, 2, 1, 1),
428*4882a593Smuzhiyun 	SOC_SINGLE("Digital Soft Ramp Disable", CS42L56_ALC_LIM_SFT_ZC,
429*4882a593Smuzhiyun 		3, 1, 1),
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	SOC_SINGLE("HL Deemphasis", CS42L56_PLAYBACK_CTL, 6, 1, 1),
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	SOC_SINGLE("ALC Switch", CS42L56_ALC_EN_ATTACK_RATE, 6, 1, 1),
434*4882a593Smuzhiyun 	SOC_SINGLE("ALC Limit All Switch", CS42L56_ALC_RELEASE_RATE, 7, 1, 1),
435*4882a593Smuzhiyun 	SOC_SINGLE_RANGE("ALC Attack", CS42L56_ALC_EN_ATTACK_RATE,
436*4882a593Smuzhiyun 			0, 0, 0x3f, 0),
437*4882a593Smuzhiyun 	SOC_SINGLE_RANGE("ALC Release", CS42L56_ALC_RELEASE_RATE,
438*4882a593Smuzhiyun 			0, 0x3f, 0, 0),
439*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ALC MAX", CS42L56_ALC_THRESHOLD,
440*4882a593Smuzhiyun 			5, 0x07, 1, alc_tlv),
441*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ALC MIN", CS42L56_ALC_THRESHOLD,
442*4882a593Smuzhiyun 			2, 0x07, 1, alc_tlv),
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	SOC_SINGLE("Limiter Switch", CS42L56_LIM_CTL_RELEASE_RATE, 7, 1, 1),
445*4882a593Smuzhiyun 	SOC_SINGLE("Limit All Switch", CS42L56_LIM_CTL_RELEASE_RATE, 6, 1, 1),
446*4882a593Smuzhiyun 	SOC_SINGLE_RANGE("Limiter Attack", CS42L56_LIM_ATTACK_RATE,
447*4882a593Smuzhiyun 			0, 0, 0x3f, 0),
448*4882a593Smuzhiyun 	SOC_SINGLE_RANGE("Limiter Release", CS42L56_LIM_CTL_RELEASE_RATE,
449*4882a593Smuzhiyun 			0, 0x3f, 0, 0),
450*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Limiter MAX", CS42L56_LIM_THRESHOLD_CTL,
451*4882a593Smuzhiyun 			5, 0x07, 1, alc_tlv),
452*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Limiter Cushion", CS42L56_ALC_THRESHOLD,
453*4882a593Smuzhiyun 			2, 0x07, 1, alc_tlv),
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	SOC_SINGLE("NG Switch", CS42L56_NOISE_GATE_CTL, 6, 1, 1),
456*4882a593Smuzhiyun 	SOC_SINGLE("NG All Switch", CS42L56_NOISE_GATE_CTL, 7, 1, 1),
457*4882a593Smuzhiyun 	SOC_SINGLE("NG Boost Switch", CS42L56_NOISE_GATE_CTL, 5, 1, 1),
458*4882a593Smuzhiyun 	SOC_SINGLE_TLV("NG Unboost Threshold", CS42L56_NOISE_GATE_CTL,
459*4882a593Smuzhiyun 			2, 0x07, 1, ngnb_tlv),
460*4882a593Smuzhiyun 	SOC_SINGLE_TLV("NG Boost Threshold", CS42L56_NOISE_GATE_CTL,
461*4882a593Smuzhiyun 			2, 0x07, 1, ngb_tlv),
462*4882a593Smuzhiyun 	SOC_ENUM("NG Delay", ng_delay_enum),
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	SOC_ENUM("Beep Config", beep_config_enum),
465*4882a593Smuzhiyun 	SOC_ENUM("Beep Pitch", beep_pitch_enum),
466*4882a593Smuzhiyun 	SOC_ENUM("Beep on Time", beep_ontime_enum),
467*4882a593Smuzhiyun 	SOC_ENUM("Beep off Time", beep_offtime_enum),
468*4882a593Smuzhiyun 	SOC_SINGLE_SX_TLV("Beep Volume", CS42L56_BEEP_FREQ_OFFTIME,
469*4882a593Smuzhiyun 			0, 0x07, 0x23, beep_tlv),
470*4882a593Smuzhiyun 	SOC_SINGLE("Beep Tone Ctl Switch", CS42L56_BEEP_TONE_CFG, 0, 1, 1),
471*4882a593Smuzhiyun 	SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
472*4882a593Smuzhiyun 	SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun };
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun static const struct snd_soc_dapm_widget cs42l56_dapm_widgets[] = {
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	SND_SOC_DAPM_SIGGEN("Beep"),
479*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("VBUF", CS42L56_PWRCTL_1, 5, 1, NULL, 0),
480*4882a593Smuzhiyun 	SND_SOC_DAPM_MICBIAS("MIC1 Bias", CS42L56_PWRCTL_1, 4, 1),
481*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L56_PWRCTL_1, 3, 1, NULL, 0),
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AIN1A"),
484*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AIN2A"),
485*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AIN1B"),
486*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AIN2B"),
487*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AIN3A"),
488*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AIN3B"),
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_OUT("SDOUT", NULL,  0,
491*4882a593Smuzhiyun 			SND_SOC_NOPM, 0, 0),
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_IN("SDIN", NULL,  0,
494*4882a593Smuzhiyun 			SND_SOC_NOPM, 0, 0),
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("Digital Output Mux", SND_SOC_NOPM,
497*4882a593Smuzhiyun 			 0, 0, &dig_mux),
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("PGAA", SND_SOC_NOPM, 0, 0, NULL, 0),
500*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("PGAB", SND_SOC_NOPM, 0, 0, NULL, 0),
501*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("PGAA Input Mux",
502*4882a593Smuzhiyun 			SND_SOC_NOPM, 0, 0, &pgaa_mux),
503*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("PGAB Input Mux",
504*4882a593Smuzhiyun 			SND_SOC_NOPM, 0, 0, &pgab_mux),
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("ADCA Mux", SND_SOC_NOPM,
507*4882a593Smuzhiyun 			 0, 0, &adca_mux),
508*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("ADCB Mux", SND_SOC_NOPM,
509*4882a593Smuzhiyun 			 0, 0, &adcb_mux),
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADCA", NULL, CS42L56_PWRCTL_1, 1, 1),
512*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADCB", NULL, CS42L56_PWRCTL_1, 2, 1),
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("ADCA Swap Mux", SND_SOC_NOPM, 0, 0,
515*4882a593Smuzhiyun 		&adca_swap_mux),
516*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("ADCB Swap Mux", SND_SOC_NOPM, 0, 0,
517*4882a593Smuzhiyun 		&adcb_swap_mux),
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("PCMA Swap Mux", SND_SOC_NOPM, 0, 0,
520*4882a593Smuzhiyun 		&pcma_swap_mux),
521*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("PCMB Swap Mux", SND_SOC_NOPM, 0, 0,
522*4882a593Smuzhiyun 		&pcmb_swap_mux),
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DACA", NULL, SND_SOC_NOPM, 0, 0),
525*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DACB", NULL, SND_SOC_NOPM, 0, 0),
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HPA"),
528*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("LOA"),
529*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HPB"),
530*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("LOB"),
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Headphone Right",
533*4882a593Smuzhiyun 			    CS42L56_PWRCTL_2, 4, 1, &hpb_switch),
534*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Headphone Left",
535*4882a593Smuzhiyun 			    CS42L56_PWRCTL_2, 6, 1, &hpa_switch),
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Lineout Right",
538*4882a593Smuzhiyun 			    CS42L56_PWRCTL_2, 0, 1, &lob_switch),
539*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Lineout Left",
540*4882a593Smuzhiyun 			    CS42L56_PWRCTL_2, 2, 1, &loa_switch),
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("LINEOUTA Input Mux", SND_SOC_NOPM,
543*4882a593Smuzhiyun 			 0, 0, &lineouta_input),
544*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("LINEOUTB Input Mux", SND_SOC_NOPM,
545*4882a593Smuzhiyun 			 0, 0, &lineoutb_input),
546*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("HPA Input Mux", SND_SOC_NOPM,
547*4882a593Smuzhiyun 			 0, 0, &hpa_input),
548*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("HPB Input Mux", SND_SOC_NOPM,
549*4882a593Smuzhiyun 			 0, 0, &hpb_input),
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun };
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun static const struct snd_soc_dapm_route cs42l56_audio_map[] = {
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	{"HiFi Capture", "DSP", "Digital Output Mux"},
556*4882a593Smuzhiyun 	{"HiFi Capture", "ADC", "Digital Output Mux"},
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	{"Digital Output Mux", NULL, "ADCA"},
559*4882a593Smuzhiyun 	{"Digital Output Mux", NULL, "ADCB"},
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	{"ADCB", NULL, "ADCB Swap Mux"},
562*4882a593Smuzhiyun 	{"ADCA", NULL, "ADCA Swap Mux"},
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	{"ADCA Swap Mux", NULL, "ADCA"},
565*4882a593Smuzhiyun 	{"ADCB Swap Mux", NULL, "ADCB"},
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	{"DACA", "Left", "ADCA Swap Mux"},
568*4882a593Smuzhiyun 	{"DACA", "LR 2", "ADCA Swap Mux"},
569*4882a593Smuzhiyun 	{"DACA", "Right", "ADCA Swap Mux"},
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	{"DACB", "Left", "ADCB Swap Mux"},
572*4882a593Smuzhiyun 	{"DACB", "LR 2", "ADCB Swap Mux"},
573*4882a593Smuzhiyun 	{"DACB", "Right", "ADCB Swap Mux"},
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	{"ADCA Mux", NULL, "AIN3A"},
576*4882a593Smuzhiyun 	{"ADCA Mux", NULL, "AIN2A"},
577*4882a593Smuzhiyun 	{"ADCA Mux", NULL, "AIN1A"},
578*4882a593Smuzhiyun 	{"ADCA Mux", NULL, "PGAA"},
579*4882a593Smuzhiyun 	{"ADCB Mux", NULL, "AIN3B"},
580*4882a593Smuzhiyun 	{"ADCB Mux", NULL, "AIN2B"},
581*4882a593Smuzhiyun 	{"ADCB Mux", NULL, "AIN1B"},
582*4882a593Smuzhiyun 	{"ADCB Mux", NULL, "PGAB"},
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	{"PGAA", "AIN1A", "PGAA Input Mux"},
585*4882a593Smuzhiyun 	{"PGAA", "AIN2A", "PGAA Input Mux"},
586*4882a593Smuzhiyun 	{"PGAA", "AIN3A", "PGAA Input Mux"},
587*4882a593Smuzhiyun 	{"PGAB", "AIN1B", "PGAB Input Mux"},
588*4882a593Smuzhiyun 	{"PGAB", "AIN2B", "PGAB Input Mux"},
589*4882a593Smuzhiyun 	{"PGAB", "AIN3B", "PGAB Input Mux"},
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	{"PGAA Input Mux", NULL, "AIN1A"},
592*4882a593Smuzhiyun 	{"PGAA Input Mux", NULL, "AIN2A"},
593*4882a593Smuzhiyun 	{"PGAA Input Mux", NULL, "AIN3A"},
594*4882a593Smuzhiyun 	{"PGAB Input Mux", NULL, "AIN1B"},
595*4882a593Smuzhiyun 	{"PGAB Input Mux", NULL, "AIN2B"},
596*4882a593Smuzhiyun 	{"PGAB Input Mux", NULL, "AIN3B"},
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 	{"LOB", "Switch", "LINEOUTB Input Mux"},
599*4882a593Smuzhiyun 	{"LOA", "Switch", "LINEOUTA Input Mux"},
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	{"LINEOUTA Input Mux", "PGAA", "PGAA"},
602*4882a593Smuzhiyun 	{"LINEOUTB Input Mux", "PGAB", "PGAB"},
603*4882a593Smuzhiyun 	{"LINEOUTA Input Mux", "DACA", "DACA"},
604*4882a593Smuzhiyun 	{"LINEOUTB Input Mux", "DACB", "DACB"},
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	{"HPA", "Switch", "HPB Input Mux"},
607*4882a593Smuzhiyun 	{"HPB", "Switch", "HPA Input Mux"},
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	{"HPA Input Mux", "PGAA", "PGAA"},
610*4882a593Smuzhiyun 	{"HPB Input Mux", "PGAB", "PGAB"},
611*4882a593Smuzhiyun 	{"HPA Input Mux", "DACA", "DACA"},
612*4882a593Smuzhiyun 	{"HPB Input Mux", "DACB", "DACB"},
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	{"DACA", NULL, "PCMA Swap Mux"},
615*4882a593Smuzhiyun 	{"DACB", NULL, "PCMB Swap Mux"},
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun 	{"PCMB Swap Mux", "Left", "HiFi Playback"},
618*4882a593Smuzhiyun 	{"PCMB Swap Mux", "LR 2", "HiFi Playback"},
619*4882a593Smuzhiyun 	{"PCMB Swap Mux", "Right", "HiFi Playback"},
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	{"PCMA Swap Mux", "Left", "HiFi Playback"},
622*4882a593Smuzhiyun 	{"PCMA Swap Mux", "LR 2", "HiFi Playback"},
623*4882a593Smuzhiyun 	{"PCMA Swap Mux", "Right", "HiFi Playback"},
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun };
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun struct cs42l56_clk_para {
628*4882a593Smuzhiyun 	u32 mclk;
629*4882a593Smuzhiyun 	u32 srate;
630*4882a593Smuzhiyun 	u8 ratio;
631*4882a593Smuzhiyun };
632*4882a593Smuzhiyun 
633*4882a593Smuzhiyun static const struct cs42l56_clk_para clk_ratio_table[] = {
634*4882a593Smuzhiyun 	/* 8k */
635*4882a593Smuzhiyun 	{ 6000000, 8000, CS42L56_MCLK_LRCLK_768 },
636*4882a593Smuzhiyun 	{ 6144000, 8000, CS42L56_MCLK_LRCLK_750 },
637*4882a593Smuzhiyun 	{ 12000000, 8000, CS42L56_MCLK_LRCLK_768 },
638*4882a593Smuzhiyun 	{ 12288000, 8000, CS42L56_MCLK_LRCLK_750 },
639*4882a593Smuzhiyun 	{ 24000000, 8000, CS42L56_MCLK_LRCLK_768 },
640*4882a593Smuzhiyun 	{ 24576000, 8000, CS42L56_MCLK_LRCLK_750 },
641*4882a593Smuzhiyun 	/* 11.025k */
642*4882a593Smuzhiyun 	{ 5644800, 11025, CS42L56_MCLK_LRCLK_512},
643*4882a593Smuzhiyun 	{ 11289600, 11025, CS42L56_MCLK_LRCLK_512},
644*4882a593Smuzhiyun 	{ 22579200, 11025, CS42L56_MCLK_LRCLK_512 },
645*4882a593Smuzhiyun 	/* 11.0294k */
646*4882a593Smuzhiyun 	{ 6000000, 110294, CS42L56_MCLK_LRCLK_544 },
647*4882a593Smuzhiyun 	{ 12000000, 110294, CS42L56_MCLK_LRCLK_544 },
648*4882a593Smuzhiyun 	{ 24000000, 110294, CS42L56_MCLK_LRCLK_544 },
649*4882a593Smuzhiyun 	/* 12k */
650*4882a593Smuzhiyun 	{ 6000000, 12000, CS42L56_MCLK_LRCLK_500 },
651*4882a593Smuzhiyun 	{ 6144000, 12000, CS42L56_MCLK_LRCLK_512 },
652*4882a593Smuzhiyun 	{ 12000000, 12000, CS42L56_MCLK_LRCLK_500 },
653*4882a593Smuzhiyun 	{ 12288000, 12000, CS42L56_MCLK_LRCLK_512 },
654*4882a593Smuzhiyun 	{ 24000000, 12000, CS42L56_MCLK_LRCLK_500 },
655*4882a593Smuzhiyun 	{ 24576000, 12000, CS42L56_MCLK_LRCLK_512 },
656*4882a593Smuzhiyun 	/* 16k */
657*4882a593Smuzhiyun 	{ 6000000, 16000, CS42L56_MCLK_LRCLK_375 },
658*4882a593Smuzhiyun 	{ 6144000, 16000, CS42L56_MCLK_LRCLK_384 },
659*4882a593Smuzhiyun 	{ 12000000, 16000, CS42L56_MCLK_LRCLK_375 },
660*4882a593Smuzhiyun 	{ 12288000, 16000, CS42L56_MCLK_LRCLK_384 },
661*4882a593Smuzhiyun 	{ 24000000, 16000, CS42L56_MCLK_LRCLK_375 },
662*4882a593Smuzhiyun 	{ 24576000, 16000, CS42L56_MCLK_LRCLK_384 },
663*4882a593Smuzhiyun 	/* 22.050k */
664*4882a593Smuzhiyun 	{ 5644800, 22050, CS42L56_MCLK_LRCLK_256 },
665*4882a593Smuzhiyun 	{ 11289600, 22050, CS42L56_MCLK_LRCLK_256 },
666*4882a593Smuzhiyun 	{ 22579200, 22050, CS42L56_MCLK_LRCLK_256 },
667*4882a593Smuzhiyun 	/* 22.0588k */
668*4882a593Smuzhiyun 	{ 6000000, 220588, CS42L56_MCLK_LRCLK_272 },
669*4882a593Smuzhiyun 	{ 12000000, 220588, CS42L56_MCLK_LRCLK_272 },
670*4882a593Smuzhiyun 	{ 24000000, 220588, CS42L56_MCLK_LRCLK_272 },
671*4882a593Smuzhiyun 	/* 24k */
672*4882a593Smuzhiyun 	{ 6000000, 24000, CS42L56_MCLK_LRCLK_250 },
673*4882a593Smuzhiyun 	{ 6144000, 24000, CS42L56_MCLK_LRCLK_256 },
674*4882a593Smuzhiyun 	{ 12000000, 24000, CS42L56_MCLK_LRCLK_250 },
675*4882a593Smuzhiyun 	{ 12288000, 24000, CS42L56_MCLK_LRCLK_256 },
676*4882a593Smuzhiyun 	{ 24000000, 24000, CS42L56_MCLK_LRCLK_250 },
677*4882a593Smuzhiyun 	{ 24576000, 24000, CS42L56_MCLK_LRCLK_256 },
678*4882a593Smuzhiyun 	/* 32k */
679*4882a593Smuzhiyun 	{ 6000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
680*4882a593Smuzhiyun 	{ 6144000, 32000, CS42L56_MCLK_LRCLK_192 },
681*4882a593Smuzhiyun 	{ 12000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
682*4882a593Smuzhiyun 	{ 12288000, 32000, CS42L56_MCLK_LRCLK_192 },
683*4882a593Smuzhiyun 	{ 24000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
684*4882a593Smuzhiyun 	{ 24576000, 32000, CS42L56_MCLK_LRCLK_192 },
685*4882a593Smuzhiyun 	/* 44.118k */
686*4882a593Smuzhiyun 	{ 6000000, 44118, CS42L56_MCLK_LRCLK_136 },
687*4882a593Smuzhiyun 	{ 12000000, 44118, CS42L56_MCLK_LRCLK_136 },
688*4882a593Smuzhiyun 	{ 24000000, 44118, CS42L56_MCLK_LRCLK_136 },
689*4882a593Smuzhiyun 	/* 44.1k */
690*4882a593Smuzhiyun 	{ 5644800, 44100, CS42L56_MCLK_LRCLK_128 },
691*4882a593Smuzhiyun 	{ 11289600, 44100, CS42L56_MCLK_LRCLK_128 },
692*4882a593Smuzhiyun 	{ 22579200, 44100, CS42L56_MCLK_LRCLK_128 },
693*4882a593Smuzhiyun 	/* 48k */
694*4882a593Smuzhiyun 	{ 6000000, 48000, CS42L56_MCLK_LRCLK_125 },
695*4882a593Smuzhiyun 	{ 6144000, 48000, CS42L56_MCLK_LRCLK_128 },
696*4882a593Smuzhiyun 	{ 12000000, 48000, CS42L56_MCLK_LRCLK_125 },
697*4882a593Smuzhiyun 	{ 12288000, 48000, CS42L56_MCLK_LRCLK_128 },
698*4882a593Smuzhiyun 	{ 24000000, 48000, CS42L56_MCLK_LRCLK_125 },
699*4882a593Smuzhiyun 	{ 24576000, 48000, CS42L56_MCLK_LRCLK_128 },
700*4882a593Smuzhiyun };
701*4882a593Smuzhiyun 
cs42l56_get_mclk_ratio(int mclk,int rate)702*4882a593Smuzhiyun static int cs42l56_get_mclk_ratio(int mclk, int rate)
703*4882a593Smuzhiyun {
704*4882a593Smuzhiyun 	int i;
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(clk_ratio_table); i++) {
707*4882a593Smuzhiyun 		if (clk_ratio_table[i].mclk == mclk &&
708*4882a593Smuzhiyun 		    clk_ratio_table[i].srate == rate)
709*4882a593Smuzhiyun 			return clk_ratio_table[i].ratio;
710*4882a593Smuzhiyun 	}
711*4882a593Smuzhiyun 	return -EINVAL;
712*4882a593Smuzhiyun }
713*4882a593Smuzhiyun 
cs42l56_set_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)714*4882a593Smuzhiyun static int cs42l56_set_sysclk(struct snd_soc_dai *codec_dai,
715*4882a593Smuzhiyun 			int clk_id, unsigned int freq, int dir)
716*4882a593Smuzhiyun {
717*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
718*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun 	switch (freq) {
721*4882a593Smuzhiyun 	case CS42L56_MCLK_5P6448MHZ:
722*4882a593Smuzhiyun 	case CS42L56_MCLK_6MHZ:
723*4882a593Smuzhiyun 	case CS42L56_MCLK_6P144MHZ:
724*4882a593Smuzhiyun 		cs42l56->mclk_div2 = 0;
725*4882a593Smuzhiyun 		cs42l56->mclk_prediv = 0;
726*4882a593Smuzhiyun 		break;
727*4882a593Smuzhiyun 	case CS42L56_MCLK_11P2896MHZ:
728*4882a593Smuzhiyun 	case CS42L56_MCLK_12MHZ:
729*4882a593Smuzhiyun 	case CS42L56_MCLK_12P288MHZ:
730*4882a593Smuzhiyun 		cs42l56->mclk_div2 = CS42L56_MCLK_DIV2;
731*4882a593Smuzhiyun 		cs42l56->mclk_prediv = 0;
732*4882a593Smuzhiyun 		break;
733*4882a593Smuzhiyun 	case CS42L56_MCLK_22P5792MHZ:
734*4882a593Smuzhiyun 	case CS42L56_MCLK_24MHZ:
735*4882a593Smuzhiyun 	case CS42L56_MCLK_24P576MHZ:
736*4882a593Smuzhiyun 		cs42l56->mclk_div2 = CS42L56_MCLK_DIV2;
737*4882a593Smuzhiyun 		cs42l56->mclk_prediv = CS42L56_MCLK_PREDIV;
738*4882a593Smuzhiyun 		break;
739*4882a593Smuzhiyun 	default:
740*4882a593Smuzhiyun 		return -EINVAL;
741*4882a593Smuzhiyun 	}
742*4882a593Smuzhiyun 	cs42l56->mclk = freq;
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
745*4882a593Smuzhiyun 			    CS42L56_MCLK_PREDIV_MASK,
746*4882a593Smuzhiyun 				cs42l56->mclk_prediv);
747*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
748*4882a593Smuzhiyun 			    CS42L56_MCLK_DIV2_MASK,
749*4882a593Smuzhiyun 				cs42l56->mclk_div2);
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 	return 0;
752*4882a593Smuzhiyun }
753*4882a593Smuzhiyun 
cs42l56_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)754*4882a593Smuzhiyun static int cs42l56_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
755*4882a593Smuzhiyun {
756*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
757*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
760*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
761*4882a593Smuzhiyun 		cs42l56->iface = CS42L56_MASTER_MODE;
762*4882a593Smuzhiyun 		break;
763*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
764*4882a593Smuzhiyun 		cs42l56->iface = CS42L56_SLAVE_MODE;
765*4882a593Smuzhiyun 		break;
766*4882a593Smuzhiyun 	default:
767*4882a593Smuzhiyun 		return -EINVAL;
768*4882a593Smuzhiyun 	}
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	 /* interface format */
771*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
772*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_I2S:
773*4882a593Smuzhiyun 		cs42l56->iface_fmt = CS42L56_DIG_FMT_I2S;
774*4882a593Smuzhiyun 		break;
775*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_LEFT_J:
776*4882a593Smuzhiyun 		cs42l56->iface_fmt = CS42L56_DIG_FMT_LEFT_J;
777*4882a593Smuzhiyun 		break;
778*4882a593Smuzhiyun 	default:
779*4882a593Smuzhiyun 		return -EINVAL;
780*4882a593Smuzhiyun 	}
781*4882a593Smuzhiyun 
782*4882a593Smuzhiyun 	/* sclk inversion */
783*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
784*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_NB_NF:
785*4882a593Smuzhiyun 		cs42l56->iface_inv = 0;
786*4882a593Smuzhiyun 		break;
787*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_IB_NF:
788*4882a593Smuzhiyun 		cs42l56->iface_inv = CS42L56_SCLK_INV;
789*4882a593Smuzhiyun 		break;
790*4882a593Smuzhiyun 	default:
791*4882a593Smuzhiyun 		return -EINVAL;
792*4882a593Smuzhiyun 	}
793*4882a593Smuzhiyun 
794*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
795*4882a593Smuzhiyun 			    CS42L56_MS_MODE_MASK, cs42l56->iface);
796*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, CS42L56_SERIAL_FMT,
797*4882a593Smuzhiyun 			    CS42L56_DIG_FMT_MASK, cs42l56->iface_fmt);
798*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
799*4882a593Smuzhiyun 			    CS42L56_SCLK_INV_MASK, cs42l56->iface_inv);
800*4882a593Smuzhiyun 	return 0;
801*4882a593Smuzhiyun }
802*4882a593Smuzhiyun 
cs42l56_mute(struct snd_soc_dai * dai,int mute,int direction)803*4882a593Smuzhiyun static int cs42l56_mute(struct snd_soc_dai *dai, int mute, int direction)
804*4882a593Smuzhiyun {
805*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun 	if (mute) {
808*4882a593Smuzhiyun 		/* Hit the DSP Mixer first */
809*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_DSP_MUTE_CTL,
810*4882a593Smuzhiyun 				    CS42L56_ADCAMIX_MUTE_MASK |
811*4882a593Smuzhiyun 				    CS42L56_ADCBMIX_MUTE_MASK |
812*4882a593Smuzhiyun 				    CS42L56_PCMAMIX_MUTE_MASK |
813*4882a593Smuzhiyun 				    CS42L56_PCMBMIX_MUTE_MASK |
814*4882a593Smuzhiyun 				    CS42L56_MSTB_MUTE_MASK |
815*4882a593Smuzhiyun 				    CS42L56_MSTA_MUTE_MASK,
816*4882a593Smuzhiyun 				    CS42L56_MUTE_ALL);
817*4882a593Smuzhiyun 		/* Mute ADC's */
818*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_MISC_ADC_CTL,
819*4882a593Smuzhiyun 				    CS42L56_ADCA_MUTE_MASK |
820*4882a593Smuzhiyun 				    CS42L56_ADCB_MUTE_MASK,
821*4882a593Smuzhiyun 				    CS42L56_MUTE_ALL);
822*4882a593Smuzhiyun 		/* HP And LO */
823*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_HPA_VOLUME,
824*4882a593Smuzhiyun 				    CS42L56_HP_MUTE_MASK, CS42L56_MUTE_ALL);
825*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_HPB_VOLUME,
826*4882a593Smuzhiyun 				    CS42L56_HP_MUTE_MASK, CS42L56_MUTE_ALL);
827*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_LOA_VOLUME,
828*4882a593Smuzhiyun 				    CS42L56_LO_MUTE_MASK, CS42L56_MUTE_ALL);
829*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_LOB_VOLUME,
830*4882a593Smuzhiyun 				    CS42L56_LO_MUTE_MASK, CS42L56_MUTE_ALL);
831*4882a593Smuzhiyun 	} else {
832*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_DSP_MUTE_CTL,
833*4882a593Smuzhiyun 				    CS42L56_ADCAMIX_MUTE_MASK |
834*4882a593Smuzhiyun 				    CS42L56_ADCBMIX_MUTE_MASK |
835*4882a593Smuzhiyun 				    CS42L56_PCMAMIX_MUTE_MASK |
836*4882a593Smuzhiyun 				    CS42L56_PCMBMIX_MUTE_MASK |
837*4882a593Smuzhiyun 				    CS42L56_MSTB_MUTE_MASK |
838*4882a593Smuzhiyun 				    CS42L56_MSTA_MUTE_MASK,
839*4882a593Smuzhiyun 				    CS42L56_UNMUTE);
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_MISC_ADC_CTL,
842*4882a593Smuzhiyun 				    CS42L56_ADCA_MUTE_MASK |
843*4882a593Smuzhiyun 				    CS42L56_ADCB_MUTE_MASK,
844*4882a593Smuzhiyun 				    CS42L56_UNMUTE);
845*4882a593Smuzhiyun 
846*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_HPA_VOLUME,
847*4882a593Smuzhiyun 				    CS42L56_HP_MUTE_MASK, CS42L56_UNMUTE);
848*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_HPB_VOLUME,
849*4882a593Smuzhiyun 				    CS42L56_HP_MUTE_MASK, CS42L56_UNMUTE);
850*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_LOA_VOLUME,
851*4882a593Smuzhiyun 				    CS42L56_LO_MUTE_MASK, CS42L56_UNMUTE);
852*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_LOB_VOLUME,
853*4882a593Smuzhiyun 				    CS42L56_LO_MUTE_MASK, CS42L56_UNMUTE);
854*4882a593Smuzhiyun 	}
855*4882a593Smuzhiyun 	return 0;
856*4882a593Smuzhiyun }
857*4882a593Smuzhiyun 
cs42l56_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)858*4882a593Smuzhiyun static int cs42l56_pcm_hw_params(struct snd_pcm_substream *substream,
859*4882a593Smuzhiyun 				     struct snd_pcm_hw_params *params,
860*4882a593Smuzhiyun 				     struct snd_soc_dai *dai)
861*4882a593Smuzhiyun {
862*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
863*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
864*4882a593Smuzhiyun 	int ratio;
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun 	ratio = cs42l56_get_mclk_ratio(cs42l56->mclk, params_rate(params));
867*4882a593Smuzhiyun 	if (ratio >= 0) {
868*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_CLKCTL_2,
869*4882a593Smuzhiyun 				    CS42L56_CLK_RATIO_MASK, ratio);
870*4882a593Smuzhiyun 	} else {
871*4882a593Smuzhiyun 		dev_err(component->dev, "unsupported mclk/sclk/lrclk ratio\n");
872*4882a593Smuzhiyun 		return -EINVAL;
873*4882a593Smuzhiyun 	}
874*4882a593Smuzhiyun 
875*4882a593Smuzhiyun 	return 0;
876*4882a593Smuzhiyun }
877*4882a593Smuzhiyun 
cs42l56_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)878*4882a593Smuzhiyun static int cs42l56_set_bias_level(struct snd_soc_component *component,
879*4882a593Smuzhiyun 					enum snd_soc_bias_level level)
880*4882a593Smuzhiyun {
881*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
882*4882a593Smuzhiyun 	int ret;
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun 	switch (level) {
885*4882a593Smuzhiyun 	case SND_SOC_BIAS_ON:
886*4882a593Smuzhiyun 		break;
887*4882a593Smuzhiyun 	case SND_SOC_BIAS_PREPARE:
888*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
889*4882a593Smuzhiyun 				    CS42L56_MCLK_DIS_MASK, 0);
890*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_PWRCTL_1,
891*4882a593Smuzhiyun 				    CS42L56_PDN_ALL_MASK, 0);
892*4882a593Smuzhiyun 		break;
893*4882a593Smuzhiyun 	case SND_SOC_BIAS_STANDBY:
894*4882a593Smuzhiyun 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
895*4882a593Smuzhiyun 			regcache_cache_only(cs42l56->regmap, false);
896*4882a593Smuzhiyun 			regcache_sync(cs42l56->regmap);
897*4882a593Smuzhiyun 			ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
898*4882a593Smuzhiyun 						    cs42l56->supplies);
899*4882a593Smuzhiyun 			if (ret != 0) {
900*4882a593Smuzhiyun 				dev_err(cs42l56->dev,
901*4882a593Smuzhiyun 					"Failed to enable regulators: %d\n",
902*4882a593Smuzhiyun 					ret);
903*4882a593Smuzhiyun 				return ret;
904*4882a593Smuzhiyun 			}
905*4882a593Smuzhiyun 		}
906*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_PWRCTL_1,
907*4882a593Smuzhiyun 				    CS42L56_PDN_ALL_MASK, 1);
908*4882a593Smuzhiyun 		break;
909*4882a593Smuzhiyun 	case SND_SOC_BIAS_OFF:
910*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_PWRCTL_1,
911*4882a593Smuzhiyun 				    CS42L56_PDN_ALL_MASK, 1);
912*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
913*4882a593Smuzhiyun 				    CS42L56_MCLK_DIS_MASK, 1);
914*4882a593Smuzhiyun 		regcache_cache_only(cs42l56->regmap, true);
915*4882a593Smuzhiyun 		regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
916*4882a593Smuzhiyun 						    cs42l56->supplies);
917*4882a593Smuzhiyun 		break;
918*4882a593Smuzhiyun 	}
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun 	return 0;
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun 
923*4882a593Smuzhiyun #define CS42L56_RATES (SNDRV_PCM_RATE_8000_48000)
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun #define CS42L56_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
926*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
927*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S32_LE)
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun static const struct snd_soc_dai_ops cs42l56_ops = {
931*4882a593Smuzhiyun 	.hw_params	= cs42l56_pcm_hw_params,
932*4882a593Smuzhiyun 	.mute_stream	= cs42l56_mute,
933*4882a593Smuzhiyun 	.set_fmt	= cs42l56_set_dai_fmt,
934*4882a593Smuzhiyun 	.set_sysclk	= cs42l56_set_sysclk,
935*4882a593Smuzhiyun 	.no_capture_mute = 1,
936*4882a593Smuzhiyun };
937*4882a593Smuzhiyun 
938*4882a593Smuzhiyun static struct snd_soc_dai_driver cs42l56_dai = {
939*4882a593Smuzhiyun 		.name = "cs42l56",
940*4882a593Smuzhiyun 		.playback = {
941*4882a593Smuzhiyun 			.stream_name = "HiFi Playback",
942*4882a593Smuzhiyun 			.channels_min = 1,
943*4882a593Smuzhiyun 			.channels_max = 2,
944*4882a593Smuzhiyun 			.rates = CS42L56_RATES,
945*4882a593Smuzhiyun 			.formats = CS42L56_FORMATS,
946*4882a593Smuzhiyun 		},
947*4882a593Smuzhiyun 		.capture = {
948*4882a593Smuzhiyun 			.stream_name = "HiFi Capture",
949*4882a593Smuzhiyun 			.channels_min = 1,
950*4882a593Smuzhiyun 			.channels_max = 2,
951*4882a593Smuzhiyun 			.rates = CS42L56_RATES,
952*4882a593Smuzhiyun 			.formats = CS42L56_FORMATS,
953*4882a593Smuzhiyun 		},
954*4882a593Smuzhiyun 		.ops = &cs42l56_ops,
955*4882a593Smuzhiyun };
956*4882a593Smuzhiyun 
957*4882a593Smuzhiyun static int beep_freq[] = {
958*4882a593Smuzhiyun 	261, 522, 585, 667, 706, 774, 889, 1000,
959*4882a593Smuzhiyun 	1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
960*4882a593Smuzhiyun };
961*4882a593Smuzhiyun 
cs42l56_beep_work(struct work_struct * work)962*4882a593Smuzhiyun static void cs42l56_beep_work(struct work_struct *work)
963*4882a593Smuzhiyun {
964*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56 =
965*4882a593Smuzhiyun 		container_of(work, struct cs42l56_private, beep_work);
966*4882a593Smuzhiyun 	struct snd_soc_component *component = cs42l56->component;
967*4882a593Smuzhiyun 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
968*4882a593Smuzhiyun 	int i;
969*4882a593Smuzhiyun 	int val = 0;
970*4882a593Smuzhiyun 	int best = 0;
971*4882a593Smuzhiyun 
972*4882a593Smuzhiyun 	if (cs42l56->beep_rate) {
973*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(beep_freq); i++) {
974*4882a593Smuzhiyun 			if (abs(cs42l56->beep_rate - beep_freq[i]) <
975*4882a593Smuzhiyun 			    abs(cs42l56->beep_rate - beep_freq[best]))
976*4882a593Smuzhiyun 				best = i;
977*4882a593Smuzhiyun 		}
978*4882a593Smuzhiyun 
979*4882a593Smuzhiyun 		dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
980*4882a593Smuzhiyun 			beep_freq[best], cs42l56->beep_rate);
981*4882a593Smuzhiyun 
982*4882a593Smuzhiyun 		val = (best << CS42L56_BEEP_RATE_SHIFT);
983*4882a593Smuzhiyun 
984*4882a593Smuzhiyun 		snd_soc_dapm_enable_pin(dapm, "Beep");
985*4882a593Smuzhiyun 	} else {
986*4882a593Smuzhiyun 		dev_dbg(component->dev, "Disabling beep\n");
987*4882a593Smuzhiyun 		snd_soc_dapm_disable_pin(dapm, "Beep");
988*4882a593Smuzhiyun 	}
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, CS42L56_BEEP_FREQ_ONTIME,
991*4882a593Smuzhiyun 			    CS42L56_BEEP_FREQ_MASK, val);
992*4882a593Smuzhiyun 
993*4882a593Smuzhiyun 	snd_soc_dapm_sync(dapm);
994*4882a593Smuzhiyun }
995*4882a593Smuzhiyun 
996*4882a593Smuzhiyun /* For usability define a way of injecting beep events for the device -
997*4882a593Smuzhiyun  * many systems will not have a keyboard.
998*4882a593Smuzhiyun  */
cs42l56_beep_event(struct input_dev * dev,unsigned int type,unsigned int code,int hz)999*4882a593Smuzhiyun static int cs42l56_beep_event(struct input_dev *dev, unsigned int type,
1000*4882a593Smuzhiyun 			     unsigned int code, int hz)
1001*4882a593Smuzhiyun {
1002*4882a593Smuzhiyun 	struct snd_soc_component *component = input_get_drvdata(dev);
1003*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun 	dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
1006*4882a593Smuzhiyun 
1007*4882a593Smuzhiyun 	switch (code) {
1008*4882a593Smuzhiyun 	case SND_BELL:
1009*4882a593Smuzhiyun 		if (hz)
1010*4882a593Smuzhiyun 			hz = 261;
1011*4882a593Smuzhiyun 	case SND_TONE:
1012*4882a593Smuzhiyun 		break;
1013*4882a593Smuzhiyun 	default:
1014*4882a593Smuzhiyun 		return -1;
1015*4882a593Smuzhiyun 	}
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun 	/* Kick the beep from a workqueue */
1018*4882a593Smuzhiyun 	cs42l56->beep_rate = hz;
1019*4882a593Smuzhiyun 	schedule_work(&cs42l56->beep_work);
1020*4882a593Smuzhiyun 	return 0;
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun 
cs42l56_beep_set(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1023*4882a593Smuzhiyun static ssize_t cs42l56_beep_set(struct device *dev,
1024*4882a593Smuzhiyun 			       struct device_attribute *attr,
1025*4882a593Smuzhiyun 			       const char *buf, size_t count)
1026*4882a593Smuzhiyun {
1027*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56 = dev_get_drvdata(dev);
1028*4882a593Smuzhiyun 	long int time;
1029*4882a593Smuzhiyun 	int ret;
1030*4882a593Smuzhiyun 
1031*4882a593Smuzhiyun 	ret = kstrtol(buf, 10, &time);
1032*4882a593Smuzhiyun 	if (ret != 0)
1033*4882a593Smuzhiyun 		return ret;
1034*4882a593Smuzhiyun 
1035*4882a593Smuzhiyun 	input_event(cs42l56->beep, EV_SND, SND_TONE, time);
1036*4882a593Smuzhiyun 
1037*4882a593Smuzhiyun 	return count;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun static DEVICE_ATTR(beep, 0200, NULL, cs42l56_beep_set);
1041*4882a593Smuzhiyun 
cs42l56_init_beep(struct snd_soc_component * component)1042*4882a593Smuzhiyun static void cs42l56_init_beep(struct snd_soc_component *component)
1043*4882a593Smuzhiyun {
1044*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
1045*4882a593Smuzhiyun 	int ret;
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	cs42l56->beep = devm_input_allocate_device(component->dev);
1048*4882a593Smuzhiyun 	if (!cs42l56->beep) {
1049*4882a593Smuzhiyun 		dev_err(component->dev, "Failed to allocate beep device\n");
1050*4882a593Smuzhiyun 		return;
1051*4882a593Smuzhiyun 	}
1052*4882a593Smuzhiyun 
1053*4882a593Smuzhiyun 	INIT_WORK(&cs42l56->beep_work, cs42l56_beep_work);
1054*4882a593Smuzhiyun 	cs42l56->beep_rate = 0;
1055*4882a593Smuzhiyun 
1056*4882a593Smuzhiyun 	cs42l56->beep->name = "CS42L56 Beep Generator";
1057*4882a593Smuzhiyun 	cs42l56->beep->phys = dev_name(component->dev);
1058*4882a593Smuzhiyun 	cs42l56->beep->id.bustype = BUS_I2C;
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun 	cs42l56->beep->evbit[0] = BIT_MASK(EV_SND);
1061*4882a593Smuzhiyun 	cs42l56->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1062*4882a593Smuzhiyun 	cs42l56->beep->event = cs42l56_beep_event;
1063*4882a593Smuzhiyun 	cs42l56->beep->dev.parent = component->dev;
1064*4882a593Smuzhiyun 	input_set_drvdata(cs42l56->beep, component);
1065*4882a593Smuzhiyun 
1066*4882a593Smuzhiyun 	ret = input_register_device(cs42l56->beep);
1067*4882a593Smuzhiyun 	if (ret != 0) {
1068*4882a593Smuzhiyun 		cs42l56->beep = NULL;
1069*4882a593Smuzhiyun 		dev_err(component->dev, "Failed to register beep device\n");
1070*4882a593Smuzhiyun 	}
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 	ret = device_create_file(component->dev, &dev_attr_beep);
1073*4882a593Smuzhiyun 	if (ret != 0) {
1074*4882a593Smuzhiyun 		dev_err(component->dev, "Failed to create keyclick file: %d\n",
1075*4882a593Smuzhiyun 			ret);
1076*4882a593Smuzhiyun 	}
1077*4882a593Smuzhiyun }
1078*4882a593Smuzhiyun 
cs42l56_free_beep(struct snd_soc_component * component)1079*4882a593Smuzhiyun static void cs42l56_free_beep(struct snd_soc_component *component)
1080*4882a593Smuzhiyun {
1081*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 	device_remove_file(component->dev, &dev_attr_beep);
1084*4882a593Smuzhiyun 	cancel_work_sync(&cs42l56->beep_work);
1085*4882a593Smuzhiyun 	cs42l56->beep = NULL;
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, CS42L56_BEEP_TONE_CFG,
1088*4882a593Smuzhiyun 			    CS42L56_BEEP_EN_MASK, 0);
1089*4882a593Smuzhiyun }
1090*4882a593Smuzhiyun 
cs42l56_probe(struct snd_soc_component * component)1091*4882a593Smuzhiyun static int cs42l56_probe(struct snd_soc_component *component)
1092*4882a593Smuzhiyun {
1093*4882a593Smuzhiyun 	cs42l56_init_beep(component);
1094*4882a593Smuzhiyun 
1095*4882a593Smuzhiyun 	return 0;
1096*4882a593Smuzhiyun }
1097*4882a593Smuzhiyun 
cs42l56_remove(struct snd_soc_component * component)1098*4882a593Smuzhiyun static void cs42l56_remove(struct snd_soc_component *component)
1099*4882a593Smuzhiyun {
1100*4882a593Smuzhiyun 	cs42l56_free_beep(component);
1101*4882a593Smuzhiyun }
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_cs42l56 = {
1104*4882a593Smuzhiyun 	.probe			= cs42l56_probe,
1105*4882a593Smuzhiyun 	.remove			= cs42l56_remove,
1106*4882a593Smuzhiyun 	.set_bias_level		= cs42l56_set_bias_level,
1107*4882a593Smuzhiyun 	.controls		= cs42l56_snd_controls,
1108*4882a593Smuzhiyun 	.num_controls		= ARRAY_SIZE(cs42l56_snd_controls),
1109*4882a593Smuzhiyun 	.dapm_widgets		= cs42l56_dapm_widgets,
1110*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(cs42l56_dapm_widgets),
1111*4882a593Smuzhiyun 	.dapm_routes		= cs42l56_audio_map,
1112*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(cs42l56_audio_map),
1113*4882a593Smuzhiyun 	.suspend_bias_off	= 1,
1114*4882a593Smuzhiyun 	.idle_bias_on		= 1,
1115*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
1116*4882a593Smuzhiyun 	.endianness		= 1,
1117*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
1118*4882a593Smuzhiyun };
1119*4882a593Smuzhiyun 
1120*4882a593Smuzhiyun static const struct regmap_config cs42l56_regmap = {
1121*4882a593Smuzhiyun 	.reg_bits = 8,
1122*4882a593Smuzhiyun 	.val_bits = 8,
1123*4882a593Smuzhiyun 
1124*4882a593Smuzhiyun 	.max_register = CS42L56_MAX_REGISTER,
1125*4882a593Smuzhiyun 	.reg_defaults = cs42l56_reg_defaults,
1126*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(cs42l56_reg_defaults),
1127*4882a593Smuzhiyun 	.readable_reg = cs42l56_readable_register,
1128*4882a593Smuzhiyun 	.volatile_reg = cs42l56_volatile_register,
1129*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
1130*4882a593Smuzhiyun };
1131*4882a593Smuzhiyun 
cs42l56_handle_of_data(struct i2c_client * i2c_client,struct cs42l56_platform_data * pdata)1132*4882a593Smuzhiyun static int cs42l56_handle_of_data(struct i2c_client *i2c_client,
1133*4882a593Smuzhiyun 				    struct cs42l56_platform_data *pdata)
1134*4882a593Smuzhiyun {
1135*4882a593Smuzhiyun 	struct device_node *np = i2c_client->dev.of_node;
1136*4882a593Smuzhiyun 	u32 val32;
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	if (of_property_read_bool(np, "cirrus,ain1a-reference-cfg"))
1139*4882a593Smuzhiyun 		pdata->ain1a_ref_cfg = true;
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	if (of_property_read_bool(np, "cirrus,ain2a-reference-cfg"))
1142*4882a593Smuzhiyun 		pdata->ain2a_ref_cfg = true;
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun 	if (of_property_read_bool(np, "cirrus,ain1b-reference-cfg"))
1145*4882a593Smuzhiyun 		pdata->ain1b_ref_cfg = true;
1146*4882a593Smuzhiyun 
1147*4882a593Smuzhiyun 	if (of_property_read_bool(np, "cirrus,ain2b-reference-cfg"))
1148*4882a593Smuzhiyun 		pdata->ain2b_ref_cfg = true;
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun 	if (of_property_read_u32(np, "cirrus,micbias-lvl", &val32) >= 0)
1151*4882a593Smuzhiyun 		pdata->micbias_lvl = val32;
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun 	if (of_property_read_u32(np, "cirrus,chgfreq-divisor", &val32) >= 0)
1154*4882a593Smuzhiyun 		pdata->chgfreq = val32;
1155*4882a593Smuzhiyun 
1156*4882a593Smuzhiyun 	if (of_property_read_u32(np, "cirrus,adaptive-pwr-cfg", &val32) >= 0)
1157*4882a593Smuzhiyun 		pdata->adaptive_pwr = val32;
1158*4882a593Smuzhiyun 
1159*4882a593Smuzhiyun 	if (of_property_read_u32(np, "cirrus,hpf-left-freq", &val32) >= 0)
1160*4882a593Smuzhiyun 		pdata->hpfa_freq = val32;
1161*4882a593Smuzhiyun 
1162*4882a593Smuzhiyun 	if (of_property_read_u32(np, "cirrus,hpf-left-freq", &val32) >= 0)
1163*4882a593Smuzhiyun 		pdata->hpfb_freq = val32;
1164*4882a593Smuzhiyun 
1165*4882a593Smuzhiyun 	pdata->gpio_nreset = of_get_named_gpio(np, "cirrus,gpio-nreset", 0);
1166*4882a593Smuzhiyun 
1167*4882a593Smuzhiyun 	return 0;
1168*4882a593Smuzhiyun }
1169*4882a593Smuzhiyun 
cs42l56_i2c_probe(struct i2c_client * i2c_client,const struct i2c_device_id * id)1170*4882a593Smuzhiyun static int cs42l56_i2c_probe(struct i2c_client *i2c_client,
1171*4882a593Smuzhiyun 			     const struct i2c_device_id *id)
1172*4882a593Smuzhiyun {
1173*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56;
1174*4882a593Smuzhiyun 	struct cs42l56_platform_data *pdata =
1175*4882a593Smuzhiyun 		dev_get_platdata(&i2c_client->dev);
1176*4882a593Smuzhiyun 	int ret, i;
1177*4882a593Smuzhiyun 	unsigned int devid = 0;
1178*4882a593Smuzhiyun 	unsigned int alpha_rev, metal_rev;
1179*4882a593Smuzhiyun 	unsigned int reg;
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun 	cs42l56 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l56), GFP_KERNEL);
1182*4882a593Smuzhiyun 	if (cs42l56 == NULL)
1183*4882a593Smuzhiyun 		return -ENOMEM;
1184*4882a593Smuzhiyun 	cs42l56->dev = &i2c_client->dev;
1185*4882a593Smuzhiyun 
1186*4882a593Smuzhiyun 	cs42l56->regmap = devm_regmap_init_i2c(i2c_client, &cs42l56_regmap);
1187*4882a593Smuzhiyun 	if (IS_ERR(cs42l56->regmap)) {
1188*4882a593Smuzhiyun 		ret = PTR_ERR(cs42l56->regmap);
1189*4882a593Smuzhiyun 		dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1190*4882a593Smuzhiyun 		return ret;
1191*4882a593Smuzhiyun 	}
1192*4882a593Smuzhiyun 
1193*4882a593Smuzhiyun 	if (pdata) {
1194*4882a593Smuzhiyun 		cs42l56->pdata = *pdata;
1195*4882a593Smuzhiyun 	} else {
1196*4882a593Smuzhiyun 		pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
1197*4882a593Smuzhiyun 				     GFP_KERNEL);
1198*4882a593Smuzhiyun 		if (!pdata)
1199*4882a593Smuzhiyun 			return -ENOMEM;
1200*4882a593Smuzhiyun 
1201*4882a593Smuzhiyun 		if (i2c_client->dev.of_node) {
1202*4882a593Smuzhiyun 			ret = cs42l56_handle_of_data(i2c_client,
1203*4882a593Smuzhiyun 						     &cs42l56->pdata);
1204*4882a593Smuzhiyun 			if (ret != 0)
1205*4882a593Smuzhiyun 				return ret;
1206*4882a593Smuzhiyun 		}
1207*4882a593Smuzhiyun 		cs42l56->pdata = *pdata;
1208*4882a593Smuzhiyun 	}
1209*4882a593Smuzhiyun 
1210*4882a593Smuzhiyun 	if (cs42l56->pdata.gpio_nreset) {
1211*4882a593Smuzhiyun 		ret = gpio_request_one(cs42l56->pdata.gpio_nreset,
1212*4882a593Smuzhiyun 				       GPIOF_OUT_INIT_HIGH, "CS42L56 /RST");
1213*4882a593Smuzhiyun 		if (ret < 0) {
1214*4882a593Smuzhiyun 			dev_err(&i2c_client->dev,
1215*4882a593Smuzhiyun 				"Failed to request /RST %d: %d\n",
1216*4882a593Smuzhiyun 				cs42l56->pdata.gpio_nreset, ret);
1217*4882a593Smuzhiyun 			return ret;
1218*4882a593Smuzhiyun 		}
1219*4882a593Smuzhiyun 		gpio_set_value_cansleep(cs42l56->pdata.gpio_nreset, 0);
1220*4882a593Smuzhiyun 		gpio_set_value_cansleep(cs42l56->pdata.gpio_nreset, 1);
1221*4882a593Smuzhiyun 	}
1222*4882a593Smuzhiyun 
1223*4882a593Smuzhiyun 
1224*4882a593Smuzhiyun 	i2c_set_clientdata(i2c_client, cs42l56);
1225*4882a593Smuzhiyun 
1226*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(cs42l56->supplies); i++)
1227*4882a593Smuzhiyun 		cs42l56->supplies[i].supply = cs42l56_supply_names[i];
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun 	ret = devm_regulator_bulk_get(&i2c_client->dev,
1230*4882a593Smuzhiyun 				      ARRAY_SIZE(cs42l56->supplies),
1231*4882a593Smuzhiyun 				      cs42l56->supplies);
1232*4882a593Smuzhiyun 	if (ret != 0) {
1233*4882a593Smuzhiyun 		dev_err(&i2c_client->dev,
1234*4882a593Smuzhiyun 			"Failed to request supplies: %d\n", ret);
1235*4882a593Smuzhiyun 		return ret;
1236*4882a593Smuzhiyun 	}
1237*4882a593Smuzhiyun 
1238*4882a593Smuzhiyun 	ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
1239*4882a593Smuzhiyun 				    cs42l56->supplies);
1240*4882a593Smuzhiyun 	if (ret != 0) {
1241*4882a593Smuzhiyun 		dev_err(&i2c_client->dev,
1242*4882a593Smuzhiyun 			"Failed to enable supplies: %d\n", ret);
1243*4882a593Smuzhiyun 		return ret;
1244*4882a593Smuzhiyun 	}
1245*4882a593Smuzhiyun 
1246*4882a593Smuzhiyun 	ret = regmap_read(cs42l56->regmap, CS42L56_CHIP_ID_1, &reg);
1247*4882a593Smuzhiyun 	devid = reg & CS42L56_CHIP_ID_MASK;
1248*4882a593Smuzhiyun 	if (devid != CS42L56_DEVID) {
1249*4882a593Smuzhiyun 		dev_err(&i2c_client->dev,
1250*4882a593Smuzhiyun 			"CS42L56 Device ID (%X). Expected %X\n",
1251*4882a593Smuzhiyun 			devid, CS42L56_DEVID);
1252*4882a593Smuzhiyun 		ret = -EINVAL;
1253*4882a593Smuzhiyun 		goto err_enable;
1254*4882a593Smuzhiyun 	}
1255*4882a593Smuzhiyun 	alpha_rev = reg & CS42L56_AREV_MASK;
1256*4882a593Smuzhiyun 	metal_rev = reg & CS42L56_MTLREV_MASK;
1257*4882a593Smuzhiyun 
1258*4882a593Smuzhiyun 	dev_info(&i2c_client->dev, "Cirrus Logic CS42L56 ");
1259*4882a593Smuzhiyun 	dev_info(&i2c_client->dev, "Alpha Rev %X Metal Rev %X\n",
1260*4882a593Smuzhiyun 		 alpha_rev, metal_rev);
1261*4882a593Smuzhiyun 
1262*4882a593Smuzhiyun 	if (cs42l56->pdata.ain1a_ref_cfg)
1263*4882a593Smuzhiyun 		regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1264*4882a593Smuzhiyun 				   CS42L56_AIN1A_REF_MASK,
1265*4882a593Smuzhiyun 				   CS42L56_AIN1A_REF_MASK);
1266*4882a593Smuzhiyun 
1267*4882a593Smuzhiyun 	if (cs42l56->pdata.ain1b_ref_cfg)
1268*4882a593Smuzhiyun 		regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1269*4882a593Smuzhiyun 				   CS42L56_AIN1B_REF_MASK,
1270*4882a593Smuzhiyun 				   CS42L56_AIN1B_REF_MASK);
1271*4882a593Smuzhiyun 
1272*4882a593Smuzhiyun 	if (cs42l56->pdata.ain2a_ref_cfg)
1273*4882a593Smuzhiyun 		regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1274*4882a593Smuzhiyun 				   CS42L56_AIN2A_REF_MASK,
1275*4882a593Smuzhiyun 				   CS42L56_AIN2A_REF_MASK);
1276*4882a593Smuzhiyun 
1277*4882a593Smuzhiyun 	if (cs42l56->pdata.ain2b_ref_cfg)
1278*4882a593Smuzhiyun 		regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1279*4882a593Smuzhiyun 				   CS42L56_AIN2B_REF_MASK,
1280*4882a593Smuzhiyun 				   CS42L56_AIN2B_REF_MASK);
1281*4882a593Smuzhiyun 
1282*4882a593Smuzhiyun 	if (cs42l56->pdata.micbias_lvl)
1283*4882a593Smuzhiyun 		regmap_update_bits(cs42l56->regmap, CS42L56_GAIN_BIAS_CTL,
1284*4882a593Smuzhiyun 				   CS42L56_MIC_BIAS_MASK,
1285*4882a593Smuzhiyun 				cs42l56->pdata.micbias_lvl);
1286*4882a593Smuzhiyun 
1287*4882a593Smuzhiyun 	if (cs42l56->pdata.chgfreq)
1288*4882a593Smuzhiyun 		regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,
1289*4882a593Smuzhiyun 				   CS42L56_CHRG_FREQ_MASK,
1290*4882a593Smuzhiyun 				cs42l56->pdata.chgfreq);
1291*4882a593Smuzhiyun 
1292*4882a593Smuzhiyun 	if (cs42l56->pdata.hpfb_freq)
1293*4882a593Smuzhiyun 		regmap_update_bits(cs42l56->regmap, CS42L56_HPF_CTL,
1294*4882a593Smuzhiyun 				   CS42L56_HPFB_FREQ_MASK,
1295*4882a593Smuzhiyun 				cs42l56->pdata.hpfb_freq);
1296*4882a593Smuzhiyun 
1297*4882a593Smuzhiyun 	if (cs42l56->pdata.hpfa_freq)
1298*4882a593Smuzhiyun 		regmap_update_bits(cs42l56->regmap, CS42L56_HPF_CTL,
1299*4882a593Smuzhiyun 				   CS42L56_HPFA_FREQ_MASK,
1300*4882a593Smuzhiyun 				cs42l56->pdata.hpfa_freq);
1301*4882a593Smuzhiyun 
1302*4882a593Smuzhiyun 	if (cs42l56->pdata.adaptive_pwr)
1303*4882a593Smuzhiyun 		regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,
1304*4882a593Smuzhiyun 				   CS42L56_ADAPT_PWR_MASK,
1305*4882a593Smuzhiyun 				cs42l56->pdata.adaptive_pwr);
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun 	ret =  devm_snd_soc_register_component(&i2c_client->dev,
1308*4882a593Smuzhiyun 			&soc_component_dev_cs42l56, &cs42l56_dai, 1);
1309*4882a593Smuzhiyun 	if (ret < 0)
1310*4882a593Smuzhiyun 		goto err_enable;
1311*4882a593Smuzhiyun 
1312*4882a593Smuzhiyun 	return 0;
1313*4882a593Smuzhiyun 
1314*4882a593Smuzhiyun err_enable:
1315*4882a593Smuzhiyun 	regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
1316*4882a593Smuzhiyun 			       cs42l56->supplies);
1317*4882a593Smuzhiyun 	return ret;
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun 
cs42l56_i2c_remove(struct i2c_client * client)1320*4882a593Smuzhiyun static int cs42l56_i2c_remove(struct i2c_client *client)
1321*4882a593Smuzhiyun {
1322*4882a593Smuzhiyun 	struct cs42l56_private *cs42l56 = i2c_get_clientdata(client);
1323*4882a593Smuzhiyun 
1324*4882a593Smuzhiyun 	regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
1325*4882a593Smuzhiyun 			       cs42l56->supplies);
1326*4882a593Smuzhiyun 	return 0;
1327*4882a593Smuzhiyun }
1328*4882a593Smuzhiyun 
1329*4882a593Smuzhiyun static const struct of_device_id cs42l56_of_match[] = {
1330*4882a593Smuzhiyun 	{ .compatible = "cirrus,cs42l56", },
1331*4882a593Smuzhiyun 	{ }
1332*4882a593Smuzhiyun };
1333*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, cs42l56_of_match);
1334*4882a593Smuzhiyun 
1335*4882a593Smuzhiyun 
1336*4882a593Smuzhiyun static const struct i2c_device_id cs42l56_id[] = {
1337*4882a593Smuzhiyun 	{ "cs42l56", 0 },
1338*4882a593Smuzhiyun 	{ }
1339*4882a593Smuzhiyun };
1340*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, cs42l56_id);
1341*4882a593Smuzhiyun 
1342*4882a593Smuzhiyun static struct i2c_driver cs42l56_i2c_driver = {
1343*4882a593Smuzhiyun 	.driver = {
1344*4882a593Smuzhiyun 		.name = "cs42l56",
1345*4882a593Smuzhiyun 		.of_match_table = cs42l56_of_match,
1346*4882a593Smuzhiyun 	},
1347*4882a593Smuzhiyun 	.id_table = cs42l56_id,
1348*4882a593Smuzhiyun 	.probe =    cs42l56_i2c_probe,
1349*4882a593Smuzhiyun 	.remove =   cs42l56_i2c_remove,
1350*4882a593Smuzhiyun };
1351*4882a593Smuzhiyun 
1352*4882a593Smuzhiyun module_i2c_driver(cs42l56_i2c_driver);
1353*4882a593Smuzhiyun 
1354*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC CS42L56 driver");
1355*4882a593Smuzhiyun MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1356*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1357