1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * cs4265.h -- CS4265 ALSA SoC audio driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2014 Cirrus Logic, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Paul Handrigan <paul.handrigan@cirrus.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CS4265_H__ 11*4882a593Smuzhiyun #define __CS4265_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CS4265_CHIP_ID 0x1 14*4882a593Smuzhiyun #define CS4265_CHIP_ID_VAL 0xD0 15*4882a593Smuzhiyun #define CS4265_CHIP_ID_MASK 0xF0 16*4882a593Smuzhiyun #define CS4265_REV_ID_MASK 0x0F 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CS4265_PWRCTL 0x02 19*4882a593Smuzhiyun #define CS4265_PWRCTL_PDN 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CS4265_DAC_CTL 0x3 22*4882a593Smuzhiyun #define CS4265_DAC_CTL_MUTE (1 << 2) 23*4882a593Smuzhiyun #define CS4265_DAC_CTL_DIF (3 << 4) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CS4265_ADC_CTL 0x4 26*4882a593Smuzhiyun #define CS4265_ADC_MASTER 1 27*4882a593Smuzhiyun #define CS4265_ADC_DIF (1 << 4) 28*4882a593Smuzhiyun #define CS4265_ADC_FM (3 << 6) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CS4265_MCLK_FREQ 0x5 31*4882a593Smuzhiyun #define CS4265_MCLK_FREQ_MASK (7 << 4) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CS4265_SIG_SEL 0x6 34*4882a593Smuzhiyun #define CS4265_SIG_SEL_LOOP (1 << 1) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define CS4265_CHB_PGA_CTL 0x7 37*4882a593Smuzhiyun #define CS4265_CHA_PGA_CTL 0x8 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CS4265_ADC_CTL2 0x9 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CS4265_DAC_CHA_VOL 0xA 42*4882a593Smuzhiyun #define CS4265_DAC_CHB_VOL 0xB 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CS4265_DAC_CTL2 0xC 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CS4265_INT_STATUS 0xD 47*4882a593Smuzhiyun #define CS4265_INT_MASK 0xE 48*4882a593Smuzhiyun #define CS4265_STATUS_MODE_MSB 0xF 49*4882a593Smuzhiyun #define CS4265_STATUS_MODE_LSB 0x10 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CS4265_SPDIF_CTL1 0x11 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define CS4265_SPDIF_CTL2 0x12 54*4882a593Smuzhiyun #define CS4265_SPDIF_CTL2_MUTE (1 << 4) 55*4882a593Smuzhiyun #define CS4265_SPDIF_CTL2_DIF (3 << 6) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define CS4265_C_DATA_BUFF 0x13 58*4882a593Smuzhiyun #define CS4265_MAX_REGISTER 0x2A 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif 61