xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/cs35l36.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * cs35l36.h -- CS35L36 ALSA SoC audio driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2018 Cirrus Logic, Inc.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: James Schulman <james.schulman@cirrus.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #ifndef __CS35L36_H__
12*4882a593Smuzhiyun #define __CS35L36_H__
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define CS35L36_FIRSTREG		0x00000000
17*4882a593Smuzhiyun #define CS35L36_LASTREG			0x00E037FC
18*4882a593Smuzhiyun #define CS35L36_SW_RESET		0x00000000
19*4882a593Smuzhiyun #define CS35L36_SW_REV			0x00000004
20*4882a593Smuzhiyun #define CS35L36_HW_REV			0x00000008
21*4882a593Smuzhiyun #define CS35L36_TESTKEY_CTRL		0x00000020
22*4882a593Smuzhiyun #define CS35L36_USERKEY_CTL		0x00000024
23*4882a593Smuzhiyun #define CS35L36_OTP_MEM30		0x00000478
24*4882a593Smuzhiyun #define CS35L36_OTP_CTRL1		0x00000500
25*4882a593Smuzhiyun #define CS35L36_OTP_CTRL2		0x00000504
26*4882a593Smuzhiyun #define CS35L36_OTP_CTRL3		0x00000508
27*4882a593Smuzhiyun #define CS35L36_OTP_CTRL4		0x0000050C
28*4882a593Smuzhiyun #define CS35L36_OTP_CTRL5		0x00000510
29*4882a593Smuzhiyun #define CS35L36_PAC_CTL1		0x00000C00
30*4882a593Smuzhiyun #define CS35L36_PAC_CTL2		0x00000C04
31*4882a593Smuzhiyun #define CS35L36_PAC_CTL3		0x00000C08
32*4882a593Smuzhiyun #define CS35L36_DEVICE_ID		0x00002004
33*4882a593Smuzhiyun #define CS35L36_FAB_ID			0x00002008
34*4882a593Smuzhiyun #define CS35L36_REV_ID			0x0000200C
35*4882a593Smuzhiyun #define CS35L36_PWR_CTRL1		0x00002014
36*4882a593Smuzhiyun #define CS35L36_PWR_CTRL2		0x00002018
37*4882a593Smuzhiyun #define CS35L36_PWR_CTRL3		0x0000201C
38*4882a593Smuzhiyun #define CS35L36_CTRL_OVRRIDE		0x00002020
39*4882a593Smuzhiyun #define CS35L36_AMP_OUT_MUTE		0x00002024
40*4882a593Smuzhiyun #define CS35L36_OTP_TRIM_STATUS		0x00002028
41*4882a593Smuzhiyun #define CS35L36_DISCH_FILT		0x0000202C
42*4882a593Smuzhiyun #define CS35L36_OSC_TRIM		0x00002030
43*4882a593Smuzhiyun #define CS35L36_PROTECT_REL_ERR		0x00002034
44*4882a593Smuzhiyun #define CS35L36_PAD_INTERFACE		0x00002400
45*4882a593Smuzhiyun #define CS35L36_PLL_CLK_CTRL		0x00002C04
46*4882a593Smuzhiyun #define CS35L36_GLOBAL_CLK_CTRL		0x00002C0C
47*4882a593Smuzhiyun #define CS35L36_ADC_CLK_CTRL		0x00002C10
48*4882a593Smuzhiyun #define CS35L36_SWIRE_CLK_CTRL		0x00002C14
49*4882a593Smuzhiyun #define CS35L36_SP_SCLK_CLK_CTRL	0x00002D00
50*4882a593Smuzhiyun #define CS35L36_TST_FS_MON0		0x00002D10
51*4882a593Smuzhiyun #define CS35L36_PLL_LOOP_PARAMS		0x00003008
52*4882a593Smuzhiyun #define CS35L36_DCO_CTRL		0x00003010
53*4882a593Smuzhiyun #define CS35L36_MISC_CTRL		0x00003014
54*4882a593Smuzhiyun #define CS35L36_MDSYNC_EN		0x00003404
55*4882a593Smuzhiyun #define CS35L36_MDSYNC_TX_ID		0x00003408
56*4882a593Smuzhiyun #define CS35L36_MDSYNC_PWR_CTRL		0x0000340C
57*4882a593Smuzhiyun #define CS35L36_MDSYNC_DATA_TX		0x00003410
58*4882a593Smuzhiyun #define CS35L36_MDSYNC_TX_STATUS	0x0000341C
59*4882a593Smuzhiyun #define CS35L36_MDSYNC_RX_STATUS	0x00003420
60*4882a593Smuzhiyun #define CS35L36_MDSYNC_ERR_STATUS	0x00003424
61*4882a593Smuzhiyun #define CS35L36_BSTCVRT_VCTRL1		0x00003800
62*4882a593Smuzhiyun #define CS35L36_BSTCVRT_VCTRL2		0x00003804
63*4882a593Smuzhiyun #define CS35L36_BSTCVRT_PEAK_CUR	0x00003808
64*4882a593Smuzhiyun #define CS35L36_BSTCVRT_SFT_RAMP	0x0000380C
65*4882a593Smuzhiyun #define CS35L36_BSTCVRT_COEFF		0x00003810
66*4882a593Smuzhiyun #define CS35L36_BSTCVRT_SLOPE_LBST	0x00003814
67*4882a593Smuzhiyun #define CS35L36_BSTCVRT_SW_FREQ		0x00003818
68*4882a593Smuzhiyun #define CS35L36_BSTCVRT_DCM_CTRL	0x0000381C
69*4882a593Smuzhiyun #define CS35L36_BSTCVRT_DCM_MODE_FORCE	0x00003820
70*4882a593Smuzhiyun #define CS35L36_BSTCVRT_OVERVOLT_CTRL	0x00003830
71*4882a593Smuzhiyun #define CS35L36_BST_TST_MANUAL		0x0000393C
72*4882a593Smuzhiyun #define CS35L36_BST_ANA2_TEST		0x0000394C
73*4882a593Smuzhiyun #define CS35L36_VPI_LIMIT_MODE		0x00003C04
74*4882a593Smuzhiyun #define CS35L36_VPI_LIMIT_MINMAX	0x00003C08
75*4882a593Smuzhiyun #define CS35L36_VPI_VP_THLD		0x00003C0C
76*4882a593Smuzhiyun #define CS35L36_VPI_TRACK_CTRL		0x00003C10
77*4882a593Smuzhiyun #define CS35L36_VPI_TRIG_MODE_CTRL	0x00003C14
78*4882a593Smuzhiyun #define CS35L36_VPI_TRIG_STEPS		0x00003C18
79*4882a593Smuzhiyun #define CS35L36_VI_SPKMON_FILT		0x00004004
80*4882a593Smuzhiyun #define CS35L36_VI_SPKMON_GAIN		0x00004008
81*4882a593Smuzhiyun #define CS35L36_VI_SPKMON_IP_SEL	0x00004100
82*4882a593Smuzhiyun #define CS35L36_DTEMP_WARN_THLD		0x00004220
83*4882a593Smuzhiyun #define CS35L36_DTEMP_STATUS		0x00004300
84*4882a593Smuzhiyun #define CS35L36_VPVBST_FS_SEL		0x00004400
85*4882a593Smuzhiyun #define CS35L36_VPVBST_VP_CTRL		0x00004440
86*4882a593Smuzhiyun #define CS35L36_VPVBST_VBST_CTRL	0x00004444
87*4882a593Smuzhiyun #define CS35L36_ASP_TX_PIN_CTRL		0x00004800
88*4882a593Smuzhiyun #define CS35L36_ASP_RATE_CTRL		0x00004804
89*4882a593Smuzhiyun #define CS35L36_ASP_FORMAT		0x00004808
90*4882a593Smuzhiyun #define CS35L36_ASP_FRAME_CTRL		0x00004818
91*4882a593Smuzhiyun #define CS35L36_ASP_TX1_TX2_SLOT	0x0000481C
92*4882a593Smuzhiyun #define CS35L36_ASP_TX3_TX4_SLOT	0x00004820
93*4882a593Smuzhiyun #define CS35L36_ASP_TX5_TX6_SLOT	0x00004824
94*4882a593Smuzhiyun #define CS35L36_ASP_TX7_TX8_SLOT	0x00004828
95*4882a593Smuzhiyun #define CS35L36_ASP_RX1_SLOT		0x0000482C
96*4882a593Smuzhiyun #define CS35L36_ASP_RX_TX_EN		0x0000483C
97*4882a593Smuzhiyun #define CS35L36_ASP_RX1_SEL		0x00004C00
98*4882a593Smuzhiyun #define CS35L36_ASP_TX1_SEL		0x00004C20
99*4882a593Smuzhiyun #define CS35L36_ASP_TX2_SEL		0x00004C24
100*4882a593Smuzhiyun #define CS35L36_ASP_TX3_SEL		0x00004C28
101*4882a593Smuzhiyun #define CS35L36_ASP_TX4_SEL		0x00004C2C
102*4882a593Smuzhiyun #define CS35L36_ASP_TX5_SEL		0x00004C30
103*4882a593Smuzhiyun #define CS35L36_ASP_TX6_SEL		0x00004C34
104*4882a593Smuzhiyun #define CS35L36_SWIRE_P1_TX1_SEL	0x00004C40
105*4882a593Smuzhiyun #define CS35L36_SWIRE_P1_TX2_SEL	0x00004C44
106*4882a593Smuzhiyun #define CS35L36_SWIRE_P2_TX1_SEL	0x00004C60
107*4882a593Smuzhiyun #define CS35L36_SWIRE_P2_TX2_SEL	0x00004C64
108*4882a593Smuzhiyun #define CS35L36_SWIRE_P2_TX3_SEL	0x00004C68
109*4882a593Smuzhiyun #define CS35L36_SWIRE_DP1_FIFO_CFG	0x00005000
110*4882a593Smuzhiyun #define CS35L36_SWIRE_DP2_FIFO_CFG	0x00005004
111*4882a593Smuzhiyun #define CS35L36_SWIRE_DP3_FIFO_CFG	0x00005008
112*4882a593Smuzhiyun #define CS35L36_SWIRE_PCM_RX_DATA	0x0000500C
113*4882a593Smuzhiyun #define CS35L36_SWIRE_FS_SEL		0x00005010
114*4882a593Smuzhiyun #define CS35L36_SPARE_CP_BITS		0x00005C00
115*4882a593Smuzhiyun #define CS35L36_AMP_DIG_VOL_CTRL	0x00006000
116*4882a593Smuzhiyun #define CS35L36_VPBR_CFG		0x00006404
117*4882a593Smuzhiyun #define CS35L36_VBBR_CFG		0x00006408
118*4882a593Smuzhiyun #define CS35L36_VPBR_STATUS		0x0000640C
119*4882a593Smuzhiyun #define CS35L36_VBBR_STATUS		0x00006410
120*4882a593Smuzhiyun #define CS35L36_OVERTEMP_CFG		0x00006414
121*4882a593Smuzhiyun #define CS35L36_AMP_ERR_VOL		0x00006418
122*4882a593Smuzhiyun #define CS35L36_CLASSH_CFG		0x00006800
123*4882a593Smuzhiyun #define CS35L36_CLASSH_FET_DRV_CFG	0x00006804
124*4882a593Smuzhiyun #define CS35L36_NG_CFG			0x00006808
125*4882a593Smuzhiyun #define CS35L36_AMP_GAIN_CTRL		0x00006C04
126*4882a593Smuzhiyun #define CS35L36_PWM_MOD_IO_CTRL		0x0000706C
127*4882a593Smuzhiyun #define CS35L36_PWM_MOD_STATUS		0x00007070
128*4882a593Smuzhiyun #define CS35L36_DAC_MSM_CFG		0x00007400
129*4882a593Smuzhiyun #define CS35L36_AMP_SLOPE_CTRL		0x00007410
130*4882a593Smuzhiyun #define CS35L36_AMP_PDM_VOLUME		0x00007E04
131*4882a593Smuzhiyun #define CS35L36_AMP_PDM_RATE_CTRL	0x00007E08
132*4882a593Smuzhiyun #define CS35L36_PDM_CH_SEL		0x00007E10
133*4882a593Smuzhiyun #define CS35L36_AMP_NG_CTRL		0x00007E14
134*4882a593Smuzhiyun #define CS35L36_PDM_HIGHFILT_CTRL	0x00007E3C
135*4882a593Smuzhiyun #define CS35L36_INT1_STATUS		0x00D00000
136*4882a593Smuzhiyun #define CS35L36_INT2_STATUS		0x00D00004
137*4882a593Smuzhiyun #define CS35L36_INT3_STATUS		0x00D00008
138*4882a593Smuzhiyun #define CS35L36_INT4_STATUS		0x00D0000C
139*4882a593Smuzhiyun #define CS35L36_INT1_RAW_STATUS		0x00D00020
140*4882a593Smuzhiyun #define CS35L36_INT2_RAW_STATUS		0x00D00024
141*4882a593Smuzhiyun #define CS35L36_INT3_RAW_STATUS		0x00D00028
142*4882a593Smuzhiyun #define CS35L36_INT4_RAW_STATUS		0x00D0002C
143*4882a593Smuzhiyun #define CS35L36_INT1_MASK		0x00D00040
144*4882a593Smuzhiyun #define CS35L36_INT2_MASK		0x00D00044
145*4882a593Smuzhiyun #define CS35L36_INT3_MASK		0x00D00048
146*4882a593Smuzhiyun #define CS35L36_INT4_MASK		0x00D0004C
147*4882a593Smuzhiyun #define CS35L36_INT1_EDGE_LVL_CTRL	0x00D00060
148*4882a593Smuzhiyun #define CS35L36_INT3_EDGE_LVL_CTRL	0x00D00068
149*4882a593Smuzhiyun #define CS35L36_PAC_INT_STATUS		0x00D00200
150*4882a593Smuzhiyun #define CS35L36_PAC_INT_RAW_STATUS	0x00D00210
151*4882a593Smuzhiyun #define CS35L36_PAC_INT_FLUSH_CTRL	0x00D00218
152*4882a593Smuzhiyun #define CS35L36_PAC_INT0_CTRL		0x00D00220
153*4882a593Smuzhiyun #define CS35L36_PAC_INT1_CTRL		0x00D00224
154*4882a593Smuzhiyun #define CS35L36_PAC_INT2_CTRL		0x00D00228
155*4882a593Smuzhiyun #define CS35L36_PAC_INT3_CTRL		0x00D0022C
156*4882a593Smuzhiyun #define CS35L36_PAC_INT4_CTRL		0x00D00230
157*4882a593Smuzhiyun #define CS35L36_PAC_INT5_CTRL		0x00D00234
158*4882a593Smuzhiyun #define CS35L36_PAC_INT6_CTRL		0x00D00238
159*4882a593Smuzhiyun #define CS35L36_PAC_INT7_CTRL		0x00D0023C
160*4882a593Smuzhiyun #define CS35L36_PAC_PMEM_WORD0		0x00E02800
161*4882a593Smuzhiyun #define CS35L36_PAC_PMEM_WORD1		0x00E02804
162*4882a593Smuzhiyun #define CS35L36_PAC_PMEM_WORD1023	0x00E037FC
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun #define CS35L36_INTPAC_REG_COUNT	25
165*4882a593Smuzhiyun #define CS35L36_CHIP_ID			0x00035A36
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #define CS35L36_INT_OUTPUT_EN_MASK	0x01
168*4882a593Smuzhiyun #define CS35L36_INT_GPIO_SEL_MASK	0x02
169*4882a593Smuzhiyun #define CS35L36_INT_GPIO_SEL_SHIFT	1
170*4882a593Smuzhiyun #define CS35L36_INT_POL_SEL_MASK	0x04
171*4882a593Smuzhiyun #define CS35L36_INT_POL_SEL_SHIFT	2
172*4882a593Smuzhiyun #define CS35L36_INT_DRV_SEL_MASK	0x20
173*4882a593Smuzhiyun #define CS35L36_INT_DRV_SEL_SHIFT	5
174*4882a593Smuzhiyun #define CS35L36_IRQ_SRC_MASK		0x08
175*4882a593Smuzhiyun #define CS35L36_IRQ_SRC_SHIFT		3
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun #define CS35L36_SCLK_MSTR_MASK		0x40
178*4882a593Smuzhiyun #define CS35L36_SCLK_MSTR_SHIFT		6
179*4882a593Smuzhiyun #define CS35L36_LRCLK_MSTR_MASK		0x01
180*4882a593Smuzhiyun #define CS35L36_LRCLK_MSTR_SHIFT	0
181*4882a593Smuzhiyun #define CS35L36_SCLK_INV_MASK		0x100
182*4882a593Smuzhiyun #define CS35L36_SCLK_INV_SHIFT		8
183*4882a593Smuzhiyun #define CS35L36_LRCLK_INV_MASK		0x04
184*4882a593Smuzhiyun #define CS35L36_LRCLK_INV_SHIFT		2
185*4882a593Smuzhiyun #define CS35L36_SCLK_FRC_MASK		0x80
186*4882a593Smuzhiyun #define CS35L36_SCLK_FRC_SHIFT		7
187*4882a593Smuzhiyun #define CS35L36_LRCLK_FRC_MASK		0x02
188*4882a593Smuzhiyun #define CS35L36_LRCLK_FRC_SHIFT		1
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun #define CS35L36_PDM_MODE_MASK		0x01
191*4882a593Smuzhiyun #define CS35L36_PDM_MODE_SHIFT		0
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun #define CS35L36_ASP_FMT_MASK		0x07
194*4882a593Smuzhiyun #define CS35L36_ASP_FMT_SHIFT		0
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun #define CS35L36_ASP_RX_WIDTH_MASK	0xFF0000
197*4882a593Smuzhiyun #define CS35L36_ASP_RX_WIDTH_SHIFT	16
198*4882a593Smuzhiyun #define CS35L36_ASP_TX_WIDTH_MASK	0xFF
199*4882a593Smuzhiyun #define CS35L36_ASP_TX_WIDTH_SHIFT	0
200*4882a593Smuzhiyun #define CS35L36_ASP_WIDTH_16		0x10
201*4882a593Smuzhiyun #define CS35L36_ASP_WIDTH_24		0x18
202*4882a593Smuzhiyun #define CS35L36_ASP_WIDTH_32		0x20
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun #define CS35L36_ASP_RX1_SLOT_MASK	0x3F
205*4882a593Smuzhiyun #define CS35L36_ASP_RX1_EN_MASK		0x00010000
206*4882a593Smuzhiyun #define CS35L36_ASP_RX1_EN_SHIFT	16
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun #define CS35L36_ASP_TX1_SLOT_MASK	0x3F
209*4882a593Smuzhiyun #define CS35L36_ASP_TX2_SLOT_MASK	0x3F0000
210*4882a593Smuzhiyun #define CS35L36_ASP_TX2_SLOT_SHIFT	16
211*4882a593Smuzhiyun #define CS35L36_ASP_TX3_SLOT_MASK	0x3F
212*4882a593Smuzhiyun #define CS35L36_ASP_TX4_SLOT_MASK	0x3F0000
213*4882a593Smuzhiyun #define CS35L36_ASP_TX4_SLOT_SHIFT	16
214*4882a593Smuzhiyun #define CS35L36_ASP_TX5_SLOT_MASK	0x3F
215*4882a593Smuzhiyun #define CS35L36_ASP_TX6_SLOT_MASK	0x3F0000
216*4882a593Smuzhiyun #define CS35L36_ASP_TX6_SLOT_SHIFT	16
217*4882a593Smuzhiyun #define CS35L36_ASP_TX7_SLOT_MASK	0x3F
218*4882a593Smuzhiyun #define CS35L36_ASP_TX8_SLOT_MASK	0x3F0000
219*4882a593Smuzhiyun #define CS35L36_ASP_TX8_SLOT_SHIFT	16
220*4882a593Smuzhiyun #define CS35L36_ASP_TX_HIZ_MASK		0x200000
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun #define CS35L36_APS_TX_SEL_MASK		0x7F
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun #define CS35L36_ASP_TX1_EN_MASK		0x01
225*4882a593Smuzhiyun #define CS35L36_ASP_TX2_EN_MASK		0x02
226*4882a593Smuzhiyun #define CS35L36_ASP_TX2_EN_SHIFT	1
227*4882a593Smuzhiyun #define CS35L36_ASP_TX3_EN_MASK		0x04
228*4882a593Smuzhiyun #define CS35L36_ASP_TX3_EN_SHIFT	2
229*4882a593Smuzhiyun #define CS35L36_ASP_TX4_EN_MASK		0x08
230*4882a593Smuzhiyun #define CS35L36_ASP_TX4_EN_SHIFT	3
231*4882a593Smuzhiyun #define CS35L36_ASP_TX5_EN_MASK		0x10
232*4882a593Smuzhiyun #define CS35L36_ASP_TX5_EN_SHIFT	4
233*4882a593Smuzhiyun #define CS35L36_ASP_TX6_EN_MASK		0x20
234*4882a593Smuzhiyun #define CS35L36_ASP_TX6_EN_SHIFT	5
235*4882a593Smuzhiyun #define CS35L36_ASP_TX7_EN_MASK		0x40
236*4882a593Smuzhiyun #define CS35L36_ASP_TX7_EN_SHIFT	6
237*4882a593Smuzhiyun #define CS35L36_ASP_TX8_EN_MASK		0x80
238*4882a593Smuzhiyun #define CS35L36_ASP_TX8_EN_SHIFT	7
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun #define CS35L36_PLL_CLK_SEL_MASK	0x07
242*4882a593Smuzhiyun #define CS35L36_PLL_CLK_SEL_SHIFT	0
243*4882a593Smuzhiyun #define CS35L36_PLLSRC_SCLK		0
244*4882a593Smuzhiyun #define CS35L36_PLLSRC_LRCLK		1
245*4882a593Smuzhiyun #define CS35L36_PLLSRC_SELF		3
246*4882a593Smuzhiyun #define CS35L36_PLLSRC_PDMCLK		4
247*4882a593Smuzhiyun #define CS35L36_PLLSRC_MCLK		5
248*4882a593Smuzhiyun #define CS35L36_PLLSRC_SWIRE		7
249*4882a593Smuzhiyun #define CS35L36_REFCLK_FREQ_MASK	0x7E0
250*4882a593Smuzhiyun #define CS35L36_REFCLK_FREQ_SHIFT	5
251*4882a593Smuzhiyun #define CS35L36_PLL_OPENLOOP_MASK	0x800
252*4882a593Smuzhiyun #define CS35L36_PLL_OPENLOOP_SHIFT	11
253*4882a593Smuzhiyun #define CS35L36_PLL_REFCLK_EN_MASK	0x10
254*4882a593Smuzhiyun #define CS35L36_PLL_REFCLK_EN_SHIFT	4
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun #define CS35L36_GLOBAL_FS_MASK		0x1F
258*4882a593Smuzhiyun #define CS35L36_GLOBAL_FS_SHIFT		0
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun #define CS35L36_HPF_PCM_EN_MASK		0x800
261*4882a593Smuzhiyun #define CS35L36_HPF_PCM_EN_SHIFT	15
262*4882a593Smuzhiyun #define CS35L36_PCM_RX_SEL_MASK		0x7F
263*4882a593Smuzhiyun #define CS35L36_PCM_RX_SEL_SHIFT	0
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun #define CS35L36_PCM_RX_SEL_ZERO		0x00
266*4882a593Smuzhiyun #define CS35L36_PCM_RX_SEL_PCM		0x08
267*4882a593Smuzhiyun #define CS35L36_PCM_RX_SEL_SWIRE	0x10
268*4882a593Smuzhiyun #define CS35L36_PCM_RX_SEL_DIAG		0x04
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun #define CS35L36_GLOBAL_EN_MASK		0x01
271*4882a593Smuzhiyun #define CS35L36_GLOBAL_EN_SHIFT		0x00
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun #define CS35L36_AMP_PCM_INV_MASK	0x4000
274*4882a593Smuzhiyun #define CS35L36_AMP_PCM_INV_SHIFT	14
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun #define CS35L36_AMP_VOL_PCM_MASK	0x3FF8
277*4882a593Smuzhiyun #define CS35L36_AMP_VOL_PCM_SHIFT	3
278*4882a593Smuzhiyun #define CS35L36_DIGITAL_MUTE		0x04CF
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun #define CS35L36_AMP_RAMP_MASK		0x0007
281*4882a593Smuzhiyun #define CS35L36_AMP_RAMP_SHIFT		0
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun #define CS35L36_AMP_MUTE_MASK		0x0010
284*4882a593Smuzhiyun #define CS35L36_AMP_MUTE_SHIFT		4
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun #define CS35L36_GLOBAL_RESYNC_FS1_MASK	0x00000200
287*4882a593Smuzhiyun #define CS35L36_GLOBAL_RESYNC_FS2_MASK	0x00000400
288*4882a593Smuzhiyun #define CS35L36_SYNC_GLOBAL_OVR_MASK	0x00000002
289*4882a593Smuzhiyun #define CS35L36_SYNC_GLOBAL_OVR_SHIFT	1
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun #define CS35L36_REFCLK_IN_MASK		0x00100000
292*4882a593Smuzhiyun #define CS35L36_PLL_UNLOCK_MASK		0x00002000
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun #define CS35L36_ASP_RX_UDF_MASK		0x00000040
295*4882a593Smuzhiyun #define CS35L36_ASP_RX_OVF_MASK		0x00000080
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun #define CS35L36_IMON_POL_MASK		0x02
298*4882a593Smuzhiyun #define CS35L36_IMON_POL_SHIFT		1
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun #define CS35L36_VMON_POL_MASK		0x01
301*4882a593Smuzhiyun #define CS35L36_VMON_POL_SHIFT		0
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun #define CS35L36_PDN_DONE		0x40
304*4882a593Smuzhiyun #define CS35L36_PDN_DONE_SHIFT		6
305*4882a593Smuzhiyun #define CS35L36_PUP_DONE		0x80
306*4882a593Smuzhiyun #define CS35L36_PUP_DONE_SHIFT		7
307*4882a593Smuzhiyun #define CS35L36_GLOBAL_EN_ASSRT		0x20
308*4882a593Smuzhiyun #define CS35L36_PUP_DONE_IRQ_UNMASK	0x7F
309*4882a593Smuzhiyun #define CS35L36_PUP_DONE_IRQ_MASK	0xBF
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun #define CS35L36_FS1_WINDOW_MASK		0x000007FF
312*4882a593Smuzhiyun #define CS35L36_FS2_WINDOW_MASK		0x00FFF800
313*4882a593Smuzhiyun #define CS35L36_FS2_WINDOW_SHIFT	12
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun #define CS35L36_PLL_FFL_IGAIN_MASK	0x0F
316*4882a593Smuzhiyun #define CS35L36_PLL_IGAIN_MASK		0x3F0
317*4882a593Smuzhiyun #define CS35L36_PLL_IGAIN_SHIFT		4
318*4882a593Smuzhiyun #define CS35L36_PLL_IGAIN		0x04
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun #define CS35L36_BST_EN_MASK		0x30
321*4882a593Smuzhiyun #define CS35L36_BST_EN			0x02
322*4882a593Smuzhiyun #define CS35L36_BST_DIS_VP		0x01
323*4882a593Smuzhiyun #define CS35L36_BST_DIS_EXTN		0x00
324*4882a593Smuzhiyun #define CS35L36_BST_EN_SHIFT		4
325*4882a593Smuzhiyun #define CS35L36_BST_MAN_IPKCOMP_MASK	0x200
326*4882a593Smuzhiyun #define CS35L36_BST_MAN_IPKCOMP_SHIFT	9
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun #define CS35L36_BST_MAN_IPKCOMP_EN_MASK		0x100
329*4882a593Smuzhiyun #define CS35L36_BST_MAN_IPKCOMP_EN_SHIFT	8
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun #define CS35L36_BST_IPK_MASK		0x7F
332*4882a593Smuzhiyun #define CS35L36_BST_OVP_THLD_MASK	0x3F
333*4882a593Smuzhiyun #define CS35L36_BST_OVP_THLD_11V	0x10
334*4882a593Smuzhiyun #define CS35L36_BST_OVP_TRIM_MASK	0x00078000
335*4882a593Smuzhiyun #define CS35L36_BST_OVP_TRIM_SHIFT	15
336*4882a593Smuzhiyun #define CS35L36_BST_OVP_TRIM_11V	0x0C
337*4882a593Smuzhiyun #define CS35L36_BST_CTRL_LIM_MASK	0x04
338*4882a593Smuzhiyun #define CS35L36_BST_CTRL_LIM_SHIFT	2
339*4882a593Smuzhiyun #define CS35L36_BST_CTRL_10V_CLAMP	0x96
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun #define CS35L36_NG_AMP_EN_MASK		0x3F00
342*4882a593Smuzhiyun #define CS35L36_NG_DELAY_MASK		0x70
343*4882a593Smuzhiyun #define CS35L36_NG_DELAY_SHIFT		4
344*4882a593Smuzhiyun #define CS35L36_AMP_ZC_SHIFT		10
345*4882a593Smuzhiyun #define CS35L36_PDM_LDM_ENTER_SHIFT	3
346*4882a593Smuzhiyun #define CS35L36_PDM_LDM_EXIT_SHIFT	4
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun #define CS35L36_BSTCVRT_K1_MASK		0xFF
349*4882a593Smuzhiyun #define CS35L36_BSTCVRT_K2_MASK		0xFF00
350*4882a593Smuzhiyun #define CS35L36_BSTCVRT_K2_SHIFT	8
351*4882a593Smuzhiyun #define CS35L36_BSTCVRT_SLOPE_MASK	0xFF00
352*4882a593Smuzhiyun #define CS35L36_BSTCVRT_SLOPE_SHIFT	8
353*4882a593Smuzhiyun #define CS35L36_BSTCVRT_CCMFREQ_MASK	0x0F
354*4882a593Smuzhiyun #define CS35L36_BSTCVRT_LBSTVAL_MASK	0x03
355*4882a593Smuzhiyun #define CS35L35_BSTCVRT_CTL_MASK	0xFF
356*4882a593Smuzhiyun #define CS35L35_BSTCVRT_CTL_SEL_MASK	0x03
357*4882a593Smuzhiyun #define CS35L36_DCM_AUTO_MASK		0x01
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun #define CS35L36_INT1_MASK_DEFAULT	0xF9BA7FFF
360*4882a593Smuzhiyun #define CS35L36_INT1_MASK_RESET		0xFFFFFFFF
361*4882a593Smuzhiyun #define CS35L36_INT3_MASK_DEFAULT	0xFFFFEFFF
362*4882a593Smuzhiyun #define CS35L36_INT3_MASK_RESET		0xFFFFFFFF
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun #define CS35L36_AMP_SHORT_ERR		0x1000
366*4882a593Smuzhiyun #define CS35L36_BST_SHORT_ERR		0x40000
367*4882a593Smuzhiyun #define CS35L36_TEMP_WARN		0x2000000
368*4882a593Smuzhiyun #define CS35L36_TEMP_ERR		0x4000000
369*4882a593Smuzhiyun #define CS35L36_BST_OVP_ERR		0x10000
370*4882a593Smuzhiyun #define CS35L36_BST_DCM_UVP_ERR		0x20000
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun #define CS35L36_AMP_SHORT_ERR_RLS	0x02
373*4882a593Smuzhiyun #define CS35L36_BST_SHORT_ERR_RLS	0x04
374*4882a593Smuzhiyun #define CS35L36_BST_OVP_ERR_RLS		0x08
375*4882a593Smuzhiyun #define CS35L36_BST_UVP_ERR_RLS		0x10
376*4882a593Smuzhiyun #define CS35L36_TEMP_WARN_ERR_RLS	0x20
377*4882a593Smuzhiyun #define CS35L36_TEMP_ERR_RLS		0x40
378*4882a593Smuzhiyun #define CS35L36_TEMP_THLD_MASK		0x03
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun #define CS35L36_REV_B0			0xb0
381*4882a593Smuzhiyun #define CS35L36_REV_A0			0xa0
382*4882a593Smuzhiyun #define CS35L36_B0_PAC_PATCH		0x00DD0102
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun #define CS35L36_OTP_ECC_EN_MASK		0x400
385*4882a593Smuzhiyun #define CS35L36_OTP_ECC_EN_SHIFT	10
386*4882a593Smuzhiyun #define CS35L36_OTP_RUN_BOOT_MASK	0x01
387*4882a593Smuzhiyun #define CS35L36_OTP_BOOT_DONE		0x2000000
388*4882a593Smuzhiyun #define CS35L36_PAC_RESET_MASK		0x04
389*4882a593Smuzhiyun #define CS35L36_PAC_RESET_SHIFT		2
390*4882a593Smuzhiyun #define CS35L36_PAC_STALL_MASK		0x02
391*4882a593Smuzhiyun #define CS35L36_PAC_STALL_SHIFT		1
392*4882a593Smuzhiyun #define CS35L36_PAC_ENABLE_MASK		0x00000001
393*4882a593Smuzhiyun #define CS35L36_PAC_MEM_ACCESS		0x01
394*4882a593Smuzhiyun #define CS35L36_PAC_MEM_ACCESS_CLR	0
395*4882a593Smuzhiyun #define CS35L36_SOFT_RESET		0x5AAA
396*4882a593Smuzhiyun #define CS35L36_MCU_BOOT_COMPLETE	0x02
397*4882a593Smuzhiyun #define CS35L36_MCU_CONFIG_UNMASK	0x00FEFFFF
398*4882a593Smuzhiyun #define CS35L36_MCU_CONFIG_CLR		0x00010000
399*4882a593Smuzhiyun #define CS35L36_MCU_CONFIG_MASK		0x00FFFFFF
400*4882a593Smuzhiyun #define CS35L36_GPIO_INT_SEL_MASK	0x0000003B
401*4882a593Smuzhiyun #define CS35L36_GPIO_INT_SEL_UNMASK	0x0000003A
402*4882a593Smuzhiyun #define CS35L36_PAC_RESET		0x00000000
403*4882a593Smuzhiyun #define CS35L36_OTP_REV_MASK		0x00FF0000
404*4882a593Smuzhiyun #define CS35L36_OTP_REV_L37		0x00CC0000
405*4882a593Smuzhiyun #define CS35L36_12V_L37			37
406*4882a593Smuzhiyun #define CS35L36_10V_L36			36
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun #define CS35L36_VPBR_EN_MASK		0x00001000
409*4882a593Smuzhiyun #define CS35L36_VPBR_EN_SHIFT		12
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun #define CS35L36_VPBR_THLD_MASK		0x0000001F
412*4882a593Smuzhiyun #define CS35L36_VPBR_THLD_SHIFT		0
413*4882a593Smuzhiyun #define CS35L36_VPBR_MAX_ATTN_MASK	0x00000F00
414*4882a593Smuzhiyun #define CS35L36_VPBR_MAX_ATTN_SHIFT	8
415*4882a593Smuzhiyun #define CS35L36_VPBR_ATK_VOL_MASK	0x0000F000
416*4882a593Smuzhiyun #define CS35L36_VPBR_ATK_VOL_SHIFT	12
417*4882a593Smuzhiyun #define CS35L36_VPBR_ATK_RATE_MASK	0x00070000
418*4882a593Smuzhiyun #define CS35L36_VPBR_ATK_RATE_SHIFT	16
419*4882a593Smuzhiyun #define CS35L36_VPBR_WAIT_MASK		0x00180000
420*4882a593Smuzhiyun #define CS35L36_VPBR_WAIT_SHIFT		19
421*4882a593Smuzhiyun #define CS35L36_VPBR_REL_RATE_MASK	0x00E00000
422*4882a593Smuzhiyun #define CS35L36_VPBR_REL_RATE_SHIFT	21
423*4882a593Smuzhiyun #define CS35L36_VPBR_MUTE_EN_MASK	0x01000000
424*4882a593Smuzhiyun #define CS35L36_VPBR_MUTE_EN_SHIFT	24
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun #define CS35L36_OSC_FREQ_TRIM_MASK	0x070
427*4882a593Smuzhiyun #define CS35L36_OSC_TRIM_DONE		0x08
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun #define CS35L36_FS1_DEFAULT_VAL		16
430*4882a593Smuzhiyun #define CS35L36_FS2_DEFAULT_VAL		36
431*4882a593Smuzhiyun #define CS35L36_FS_NOM_6MHZ		6000000
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun #define CS35L36_TEST_UNLOCK1		0x00005555
434*4882a593Smuzhiyun #define CS35L36_TEST_UNLOCK2		0x0000AAAA
435*4882a593Smuzhiyun #define CS35L36_TEST_LOCK1		0x0000CCCC
436*4882a593Smuzhiyun #define CS35L36_TEST_LOCK2		0x00003333
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun #define CS35L36_PAC_PROG_MEM		512
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun #define CS35L36_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
441*4882a593Smuzhiyun #define CS35L36_TX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE \
442*4882a593Smuzhiyun 				| SNDRV_PCM_FMTBIT_S32_LE)
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun extern const int cs35l36_a0_pac_patch[CS35L36_PAC_PROG_MEM];
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun #endif
447